An SRAM storage circuit based on polarity reinforcement technology

Abstract

The present invention discloses an SRAM storage circuit based on a polarity reinforcement technology, which includes four PMOS transistors and ten NMOS transistors. The PMOS transistors P1 and P2 serve as pull-up transistors, and the PMOS transistors P3 and P4 are cross-coupled. The NMOS transistors N3, N4, N5, and N6 serve as pull-down transistors, and the NMOS transistors N5 and N6 are cross-coupled. The main storage nodes Q and QN are respectively connected to the bit lines BL and BLB through the NMOS transistors N7 and N8, and the redundant storage nodes S0 and S1 are respectively connected to the bit lines BL and BLB through the NMOS transistors N9 and N10. The bit line BL is electrically connected to the sources of the NMOS transistors N7 and N9, and the bit line BLB is electrically connected to the sources of the NMOS transistors N8 and N10. The storage circuit with this structure can improve the write speed of the storage cell, reduce the cell power consumption, and improve the ability of the cell to resist single-event upsets (SEUs).

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to a SRAM storage circuit based on a polarity strengthening technology. Background Art

[0002] With the progress of technology, static random access memory (SRAM) has been widely used in various aerospace electronic fields. Due to the increasing integration level, the probability of single event upset (SEU) caused by the single event effects (SET) on SRAM is getting higher and higher. Single event upset is a main reliability fault mechanism, which can cause electronic system failures by temporarily changing the stored value. When a charged particle hits a sensitive node of an integrated circuit, the induced charges along its path can be effectively collected and accumulated through the drift process. Once the transient voltage pulse generated by the accumulated charges is higher than the switching threshold of the circuit, the stored value in this sensitive node will be changed.

[0003] At present, anti-SEU has become an issue that cannot be ignored by scientific researchers, while the existing technologies lack corresponding solutions. Summary of the Invention

[0004] The purpose of the present invention is to provide a SRAM storage circuit based on a polarity strengthening technology. The storage circuit with this structure can improve the write speed of the storage unit, reduce the unit power consumption, and enhance the ability of the unit to resist single event upset (SEU).

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] A SRAM storage circuit based on a polarity strengthening technology, the circuit includes four PMOS transistors and ten NMOS transistors. The four PMOS transistors are sequentially denoted as P1 to P4, and the ten NMOS transistors are sequentially denoted as N1 to N10, wherein:

[0007] The gate of PMOS transistor P3 is connected to the drain of PMOS transistor P4, and at the same time, the gate of PMOS transistor P4 is connected to the drain of PMOS transistor P3, that is, P3 and P4 form a cross-coupled structure of MOS transistors;

[0008] NMOS transistors N5 and N6 are cross-coupled, and the main storage nodes Q and QN are respectively connected to the gates of NMOS transistors N2 and N1;

[0009] The drains of PMOS transistors P3 and P4 are connected to the main storage nodes Q and QN. Therefore, PMOS transistors P1, P3, P2, and P4 act as pull-up transistors for the main storage nodes Q and QN. The drains of NMOS transistors N3 and N4 are connected to the main storage nodes Q and QN. Therefore, NMOS transistors N3 and N4 act as pull-down transistors for the main storage nodes Q and QN.

[0010] The sources of NMOS transistors N1 and N2 are connected to the redundant storage nodes S0 and S1. Therefore, NMOS transistors N1 and N2 act as pull-up transistors for the redundant storage nodes S0 and S1. The drains of NMOS transistors N5 and N6 are connected to the redundant storage nodes S0 and S1. Therefore, NMOS transistors N5 and N6 act as pull-down transistors for the redundant storage nodes S0 and S1.

[0011] The main storage nodes Q and QN are respectively connected to the bit lines BL and BLB through NMOS transistors N7 and N8. The redundant storage nodes S0 and S1 are respectively connected to the bit lines BL and BLB through NMOS transistors N9 and N10, where:

[0012] NMOS transistors N7, N8, N9, and N10 are controlled by the word line WL.

[0013] The bit line BL is electrically connected to the sources of NMOS transistors N7 and N9. The bit line BLB is electrically connected to the sources of NMOS transistors N8 and N10.

[0014] The word line WL is electrically connected to the gates of NMOS transistors N7, N8, N9, and N10.

[0015] The drain of NMOS transistor N7 is electrically connected to the drain of NMOS transistor N3. The drain of NMOS transistor N8 is electrically connected to the drain of NMOS transistor N4. The drain of NMOS transistor N9 is electrically connected to the drain of NMOS transistor N6. The drain of NMOS transistor N10 is electrically connected to the drain of NMOS transistor N5.

[0016] The power supply VDD is electrically connected to the sources of PMOS transistors P1 and P2, and the drains of NMOS transistors N1 and N2.

[0017] The sources of NMOS transistors N3, N4, N5, and N6 are all grounded.

[0018] As can be seen from the technical solution provided by the present invention above, the above SRAM storage circuit can improve the SEU resistance ability of the unit, and can greatly improve the write speed of the unit and reduce the power consumption of the unit while sacrificing a small unit area. Description of the Drawings

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 Schematic diagram of the SRAM storage circuit structure based on the polarity reinforcement technology provided by the embodiment of the present invention;

[0021] Figure 2 Timing waveform diagram of the SRAM storage cell circuit provided by the embodiment of the present invention;

[0022] Figure 3 Transient waveform simulation diagram of the SRAM storage circuit provided by the embodiment of the present invention when different nodes are injected with double-exponential current source pulses at different times;

[0023] Figure 4 Comparison diagram of the number of failures in 2000 Monte Carlo simulations of the main storage node of the SRAM unit circuit in the prior art and the SRAM storage circuit provided by the embodiment of the present invention when injected with double-exponential current source pulses and restored to its initial state at the same time; Detailed implementation manners

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, which do not constitute a limitation to the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0025] As Figure 1 shown is the schematic diagram of the SRAM storage circuit structure based on the polarity reinforcement technology provided by the embodiment of the present invention. The circuit includes four PMOS transistors and ten NMOS transistors. The four PMOS transistors are sequentially denoted as P1 to P4, and the ten NMOS transistors are sequentially denoted as N1 to N10, where:

[0026] The gate of PMOS transistor P3 is connected to the drain of PMOS transistor P4, and at the same time, the gate of PMOS transistor P4 is connected to the drain of PMOS transistor P3, that is, P3 and P4 form a cross-coupled structure of MOS transistors;

[0027] NMOS transistors N5 and N6 are cross-coupled, and the main storage nodes Q and QN are respectively connected to the gates of NMOS transistors N2 and N1;

[0028] The drains of PMOS transistors P3 and P4 are connected to the main storage nodes Q and QN. Therefore, PMOS transistors P1, P3, P2, and P4 function as pull-up transistors for the main storage nodes Q and QN. The drains of NMOS transistors N3 and N4 are connected to the main storage nodes Q and QN. Therefore, NMOS transistors N3 and N4 function as pull-down transistors for the main storage nodes Q and QN.

[0029] The sources of NMOS transistors N1 and N2 are connected to the redundant storage nodes S0 and S1. Therefore, NMOS transistors N1 and N2 function as pull-up transistors for the redundant storage nodes S0 and S1. The drains of NMOS transistors N5 and N6 are connected to the redundant storage nodes S0 and S1. Therefore, NMOS transistors N5 and N6 function as pull-down transistors for the redundant storage nodes S0 and S1.

[0030] The main storage nodes Q and QN are respectively connected to the bit lines BL and BLB through NMOS transistors N7 and N8. The redundant storage nodes S0 and S1 are respectively connected to the bit lines BL and BLB through NMOS transistors N9 and N10, where:

[0031] NMOS transistors N7, N8, N9, and N10 are controlled by the word line WL.

[0032] The bit line BL is electrically connected to the sources of NMOS transistors N7 and N9. The bit line BLB is electrically connected to the sources of NMOS transistors N8 and N10.

[0033] The word line WL is electrically connected to the gates of NMOS transistors N7, N8, N9, and N10.

[0034] The drain of NMOS transistor N7 is electrically connected to the drain of NMOS transistor N3. The drain of NMOS transistor N8 is electrically connected to the drain of NMOS transistor N4. The drain of NMOS transistor N9 is electrically connected to the drain of NMOS transistor N6. The drain of NMOS transistor N10 is electrically connected to the drain of NMOS transistor N5.

[0035] The power supply VDD is electrically connected to the sources of PMOS transistors P1 and P2, and the drains of NMOS transistors N1 and N2.

[0036] The sources of NMOS transistors N3, N4, N5, and N6 are all grounded.

[0037] In a specific implementation, the specific connection relationships of the transistors are as follows:

[0038] The drain of PMOS transistor P1 is electrically connected to the source of PMOS transistor P3, and the gate of PMOS transistor P1 is electrically connected to the source of NMOS transistor N1, the gate of NMOS transistor N3, the drain of NMOS transistor N5, and the gate of NMOS transistor N6;

[0039] The drain of PMOS transistor P2 is electrically connected to the source of PMOS transistor P4, and the gate of PMOS transistor P2 is electrically connected to the source of NMOS transistor N2, the gate of NMOS transistor N4, the gate of NMOS transistor N5, and the drain of NMOS transistor N6;

[0040] The drain of PMOS transistor P3 is electrically connected to the drain of NMOS transistor N3, the gate of PMOS transistor P4, and the gate of NMOS transistor N2, and the gate of PMOS transistor P3 is electrically connected to the gate of NMOS transistor N1 and the drain of NMOS transistor N4;

[0041] The drain of PMOS transistor P4 is electrically connected to the drain of NMOS transistor N4, the gate of PMOS transistor P3, and the gate of NMOS transistor N1, and the gate of PMOS transistor P4 is electrically connected to the gate of NMOS transistor N2 and the drain of NMOS transistor N3;

[0042] The source of NMOS transistor N1 is electrically connected to the gate of PMOS transistor P1, the gate of NMOS transistor N3, the drain of NMOS transistor N5, and the gate of NMOS transistor N6, and the gate of NMOS transistor N1 is electrically connected to the gate of PMOS transistor P3 and the drain of NMOS transistor N4;

[0043] The source of NMOS transistor N2 is electrically connected to the gate of PMOS transistor P2, the gate of NMOS transistor N4, the gate of NMOS transistor N5, and the drain of NMOS transistor N6, and the gate of NMOS transistor N2 is electrically connected to the gate of PMOS transistor P3 and the drain of NMOS transistor N4;

[0044] The drain of NMOS transistor N3 is electrically connected to the gate of PMOS transistor P4 and the gate of NMOS transistor N2, and the gate of NMOS transistor N3 is electrically connected to the gate of PMOS transistor P1, the source of NMOS transistor N1, the drain of NMOS transistor N5, and the gate of NMOS transistor N6;

[0045] The drain of NMOS transistor N4 is electrically connected to the gates of PMOS transistor P3 and NMOS transistor N1, and the gate of NMOS transistor N4 is electrically connected to the gates of PMOS transistor P2, the source of NMOS transistor N2, the gate of NMOS transistor N5, and the drain of NMOS transistor N6;

[0046] The drain of NMOS transistor N5 is electrically connected to the source of NMOS transistor N1, the gate of PMOS transistor P1, the gates of NMOS transistors N3 and N6, and the gate of NMOS transistor N5 is electrically connected to the gates of PMOS transistor P2, the source of NMOS transistor N2, the gate of NMOS transistor N4, and the drain of NMOS transistor N6;

[0047] The drain of NMOS transistor N6 is electrically connected to the source of NMOS transistor N2, the gate of PMOS transistor P2, the gates of NMOS transistors N4 and N5, and the gate of NMOS transistor N6 is electrically connected to the gate of PMOS transistor P1, the source of NMOS transistor N1, the gate of NMOS transistor N4, and the drain of NMOS transistor N5.

[0048] Based on the said circuit:

[0049] In the hold stage, bit lines BL and BLB are both precharged to high level, word line WL is at low level, the circuit maintains the initial state internally, and the circuit does not work;

[0050] In the data read stage, bit lines BL and BLB are both precharged to high level, word line WL is at high level, transfer transistors N7, N8, N9, and N10 are turned on; if the data stored in the circuit is '0', then "Q = S1 = 0, QN = S0 = 1", and then bit line BL discharges to ground through discharge path 1, i.e., NMOS transistors N7 and N3, and discharge path 2, i.e., NMOS transistors N9 and N6, causing a voltage difference to occur on bit line BL, and then the data is read through the sense amplifier; if the data stored in the circuit is '1', then "Q = S1 = 1, QN = S0 = 0", and then bit line BLB discharges to ground through discharge path 3, i.e., NMOS transistors N8 and N4, and discharge path 4, i.e., NMOS transistors N10 and N5, causing a voltage difference to occur on bit line BLB, and then the data is read through the sense amplifier;

[0051] In the data write stage, word line WL is at high level. If bit line BL is at high level and bit line BLB is at low level, then '1' is written to storage nodes Q and S1 respectively through transfer transistors N7 and N9; if bit line BL is at low level and bit line BLB is at high level, then '1' is written to storage nodes QN and S0 respectively through transfer transistors N8 and N10.

[0052] During the data writing process, since data is written to the storage nodes Q / S1 and QN / S0 through the transfer transistors N7 and N9, N8 and N10, the storage nodes are more easily written with data, so that the writing speed will be greatly improved. At the same time, due to the improvement of the writing speed, the power consumption of the circuit is reduced.

[0053] In addition, the gate length of all transistors is 65 nm, where:

[0054] The gate widths of the PMOS transistors P1, P2, P3, and P4 are 300 nm;

[0055] The gate widths of the NMOS transistors N1 and N2 are 75 nm;

[0056] The gate widths of the NMOS transistors N5 and N6 are 300 nm;

[0057] The gate widths of the NMOS transistors N3, N4, N7, N8, N9, and N10 are 150 nm.

[0058] As Figure 2 shown is the timing waveform diagram of the SRAM storage cell circuit provided by the embodiment of the present invention. The specific simulation conditions are: Corner: TT; Temperature: 25 °C; VDD: 1.2V. It can be Figure 2 seen that within the entire 20 ns time, the functions of writing "1", writing "0", writing "1", and reading "1" are completed successively. Therefore, the RCPD-14T cell can complete the read and write functions required by the sram cell.

[0059] Table 1 below is a comparison table of the read and write times and power consumption simulations of the SRAM cell circuit of the prior art and the SRAM storage cell circuit provided by the embodiment of the present invention. The specific simulation conditions are: Corner: TT; Temperature: 25 °C; VDD: 1.2V.

[0060] Table 1

[0061] Unit Read Latency (ps) Write Latency (ps) DICE 58.8 31.12 Quatro 114 29.32 S4P8N 80.6 22.41 RHPD-12T 61.6 14.9 QUCCE-10T 95.8 31.74 RCPD-14T 64 20

[0062] It can be seen from Table 1 that under the same simulation conditions, the read speed of the RCPD-14T cell far exceeds that of cells such as Quatro, S4P8N, and QUCCE-10T; the write speed of the RCPD-14T cell far exceeds that of cells such as DICE, Quatro, S4P8N, and QUCCE-10T. The read and write speeds of the RCPD-14T cell can be comparable to those of the RHPD-12T.

[0063] As Figure 3The following figure shows the transient waveform simulation diagram of the SRAM storage circuit provided by the embodiment of the present invention when different nodes are injected with double-exponential current source pulses at different times. The specific simulation conditions are: VDD: 1.2V. As can be seen from Figure 3 : When Q and QN are simultaneously injected with double-exponential current source pulses, Q and QN can be fully restored. When Q, QN, and S1 are respectively injected with double-exponential current source pulses, the relevant storage nodes can be fully restored. This shows that the RCPD-14T cell has the characteristics that when the single node and the double nodes are injected with double-exponential current source pulses, the cell storage nodes will not be affected.

[0064] As Figure 4 shown in the figure below is the comparison diagram of the number of failures in 2000 Monte Carlo simulations of the SRAM cell circuit in the prior art and the SRAM storage circuit provided by the embodiment of the present invention when the main storage nodes are injected with double-exponential current source pulses at the same time and then restored to their initial states. The specific simulation conditions are: Corner: MC; Temperature: 25°C; VDD: 1.2V. As can be seen from Figure 4 : In the same simulation environment, when double-exponential current source pulses are injected into the main storage nodes of all cells Q and QN, in 2000 Monte Carlo simulations, the values of the main storage nodes of the DICE, Quatro, S4P8N, and QUCCE-10T cells are all damaged, while the main storage nodes of the RHPD-12T and RCPD-12T cells are restored 2000 times.

[0065] It should be noted that the content not described in detail in the embodiments of the present invention belongs to the prior art well-known to those skilled in the art.

[0066] In summary, the SRAM storage circuit provided by the embodiment of the present invention can improve the SEU resistance of the cell circuit, can greatly improve the write speed of the cell while sacrificing a small cell area, and reduces the power consumption of the cell.

[0067] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background art part of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art already known to those skilled in the art.

Claims

1. An SRAM storage circuit based on a polarity reinforcement technology, characterized in that, the circuit includes four PMOS transistors and ten NMOS transistors. The four PMOS transistors are sequentially denoted as P1 to P4, and the ten NMOS transistors are sequentially denoted as N1 to N10, where: the gate of PMOS transistor P3 is connected to the drain of PMOS transistor P4, and at the same time, the gate of PMOS transistor P4 is connected to the drain of PMOS transistor P3, that is, P3 and P4 form a cross-coupled structure of MOS transistors; NMOS transistors N5 and N6 are cross-coupled, and the main storage nodes Q and QN are respectively connected to the gates of NMOS transistors N2 and N1; PMOS transistor P3 is connected to the main storage node Q, and the drain of PMOS transistor P4 is connected to the main storage node QN. Therefore, PMOS transistors P1, P3, P2, and P4 act as pull-up transistors for the main storage nodes Q and QN; the drain of NMOS transistor N3 is connected to the main storage node Q, and the drain of NMOS transistor N4 is connected to the main storage node QN. Therefore, NMOS transistors N3 and N4 act as pull-down transistors for the main storage nodes Q and QN; the source of NMOS transistor N1 is connected to the redundant storage node S0, and the source of NMOS transistor N2 is connected to the redundant storage node S1. Therefore, NMOS transistors N1 and N2 act as pull-up transistors for the redundant storage nodes S0 and S1; the drain of NMOS transistor N5 is connected to the redundant storage node S0, and the drain of NMOS transistor N6 is connected to the redundant storage node S1. Therefore, NMOS transistors N5 and N6 act as pull-down transistors for the redundant storage nodes S0 and S1; the main storage node Q is connected to the bit line BL through NMOS transistor N7, the main storage node QN is connected to the bit line BLB through NMOS transistor N8, the redundant storage node S0 is connected to the bit line BL through NMOS transistor N9, and the redundant storage node S1 is connected to the bit line BLB through NMOS transistor N10, where: NMOS transistors N7, N8, N9, and N10 are controlled by the word line WL; the bit line BL is electrically connected to the sources of NMOS transistors N7 and N9, and the bit line BLB is electrically connected to the sources of NMOS transistors N8 and N10; the word line WL is electrically connected to the gates of NMOS transistors N7, N8, N9, and N10; the drain of NMOS transistor N7 is electrically connected to the drain of NMOS transistor N3, and the drain of NMOS transistor N8 is electrically connected to the drain of NMOS transistor N4; the drain of NMOS transistor N9 is electrically connected to the drain of NMOS transistor N6, and the drain of NMOS transistor N10 is electrically connected to the drain of NMOS transistor N5; the power supply VDD is electrically connected to the sources of PMOS transistors P1 and P2, and the drains of NMOS transistors N1 and N2; the sources of NMOS transistors N3, N4, N5, and N6 are all grounded; wherein, the specific connection relationship of each transistor is: The drain of PMOS transistor P1 is electrically connected to the source of PMOS transistor P3, and the gate of PMOS transistor P1 is electrically connected to the source of NMOS transistor N1, the gate of NMOS transistor N3, the drain of NMOS transistor N5, and the gate of NMOS transistor N6; The drain of PMOS transistor P2 is electrically connected to the source of PMOS transistor P4, and the gate of PMOS transistor P2 is electrically connected to the source of NMOS transistor N2, the gate of NMOS transistor N4, the gate of NMOS transistor N5, and the drain of NMOS transistor N6; The drain of PMOS transistor P3 is electrically connected to the drain of NMOS transistor N3, the gate of PMOS transistor P4, and the gate of NMOS transistor N2, and the gate of PMOS transistor P3 is electrically connected to the gate of NMOS transistor N1 and the drain of NMOS transistor N4; The drain of PMOS transistor P4 is electrically connected to the drain of NMOS transistor N4, the gate of PMOS transistor P3, and the gate of NMOS transistor N1, and the gate of PMOS transistor P4 is electrically connected to the gate of NMOS transistor N2 and the drain of NMOS transistor N3; The source of NMOS transistor N1 is electrically connected to the gate of PMOS transistor P1, the gate of NMOS transistor N3, the drain of NMOS transistor N5, and the gate of NMOS transistor N6, and the gate of NMOS transistor N1 is electrically connected to the gate of PMOS transistor P3 and the drain of NMOS transistor N4; The source of NMOS transistor N2 is electrically connected to the gate of PMOS transistor P2, the gate of NMOS transistor N4, the gate of NMOS transistor N5, and the drain of NMOS transistor N6, and the gate of NMOS transistor N2 is electrically connected to the gate of PMOS transistor P3 and the drain of NMOS transistor N4; The drain of NMOS transistor N3 is electrically connected to the gate of PMOS transistor P4 and the gate of NMOS transistor N2, and the gate of NMOS transistor N3 is electrically connected to the gate of PMOS transistor P1, the source of NMOS transistor N1, the drain of NMOS transistor N5, and the gate of NMOS transistor N6; The drain of NMOS transistor N4 is electrically connected to the gate of PMOS transistor P3 and the gate of NMOS transistor N1, and the gate of NMOS transistor N4 is electrically connected to the gate of PMOS transistor P2, the source of NMOS transistor N2, the gate of NMOS transistor N5, and the drain of NMOS transistor N6; The drain of NMOS transistor N5 is electrically connected to the source of NMOS transistor N1, the gate of PMOS transistor P1, the gate of NMOS transistor N3, and the gate of NMOS transistor N6, and the gate of NMOS transistor N5 is electrically connected to the gate of PMOS transistor P2, the source of NMOS transistor N2, the gate of NMOS transistor N4, and the drain of NMOS transistor N6; The drain of NMOS transistor N6 is electrically connected to the source of NMOS transistor N2, the gate of PMOS transistor P2, the gate of NMOS transistor N4, and the gate of NMOS transistor N5. And the gate of NMOS transistor N6 is electrically connected to the gate of PMOS transistor P1, the source of NMOS transistor N1, the gate of NMOS transistor N4, and the drain of NMOS transistor N5.

2. The SRAM memory circuit based on the polarity reinforcement technology according to claim 1, characterized in that, based on the said circuit: In the hold stage, bit lines BL and BLB are both precharged to high level, word line WL is at low level, the internal state of the circuit is maintained, and the circuit does not work. In the data read stage, bit lines BL and BLB are both precharged to high level, word line WL is at high level, and NMOS transistors N7, N8, N9 and N10 are turned on. If the data stored in the circuit is '0', then "Q = S1 = 0, QN = S0 = 1", and then bit line BL discharges to ground through discharge path 1, i.e., NMOS transistors N7 and N3, and discharge path 2, i.e., NMOS transistors N9 and N6, causing a voltage difference on bit line BL, and then the data is read through the sense amplifier. If the data stored in the circuit is '1', then "Q = S1 = 1, QN = S0 = 0", and then bit line BLB discharges to ground through discharge path 3, i.e., NMOS transistors N8 and N4, and discharge path 4, i.e., NMOS transistors N10 and N5, causing a voltage difference on bit line BLB, and then the data is read through the sense amplifier. In the data write stage, word line WL is at high level. If bit line BL is at high level and bit line BLB is at low level, then '1' is written to storage nodes Q and S1 respectively through NMOS transistors N7 and N9. If bit line BL is at low level and bit line BLB is at high level, then '1' is written to storage nodes QN and S0 respectively through NMOS transistors N8 and N10.

3. The SRAM memory circuit based on the polarity reinforcement technology according to claim 1, characterized in that, the gate length of all transistors is 65 nm, where: the gate widths of PMOS transistors P1, P2, P3, P4 are 300 nm; the gate widths of NMOS transistors N1, N2 are 75 nm; the gate widths of NMOS transistors N5, N6 are 300 nm; the gate widths of NMOS transistors N3, N4, N7, N8, N9, N10 are 150 nm.

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