Semiconductor device
By using multiple stacked metal wiring layers as test conductors in the test pad, the problem of long and complex test conductors is solved, thereby simplifying the wiring structure and improving connection efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2020-10-29
- Publication Date
- 2026-05-29
Smart Images
Figure CN114429917B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device. Background Technology
[0002] Semiconductor dies are manufactured from semiconductor wafers, and each semiconductor die contains an integrated circuit. These integrated circuits are formed on the semiconductor wafer through steps such as deposition, photolithography, etching, and ion implantation. After the integrated circuit fabrication on the wafer is completed, the semiconductor wafer is typically diced to separate the semiconductor dies. The wafer space left between the semiconductor dies is used for wafer dicing and is called the dicing channel.
[0003] Generally, the dicing area contains a test element group (TEG). The TEG includes a probing pad and test elements, and the test bond structure is fabricated simultaneously with the actual device or functional device on the semiconductor die. The quality of the actual device or functional device can be inspected by electrically contacting the test probe with the probing pad.
[0004] As the linewidth of the scribe lines on the chip decreases, the test element group continues to shrink, and the test pads inside also shrink. The test elements become more complex, and the wiring connecting the test pads and test elements becomes longer and longer, leading to connection difficulties. Summary of the Invention
[0005] This application addresses, at least to some extent, the aforementioned technical problems in the related art. To this end, this application proposes a semiconductor device to solve the problem of long and complex test leads.
[0006] To achieve the above objectives, a first aspect of this application provides a semiconductor device, comprising:
[0007] A semiconductor substrate having diced line regions formed thereon;
[0008] The first test pad and the test element are disposed in the cutting line area;
[0009] Test leads are used to connect the first test pad and the test element;
[0010] The first test pad includes multiple stacked metal wiring layers, with at least one metal wiring layer containing a first metal wiring and a second metal wiring, and the first metal wiring serving as the test conductor. Attached Figure Description
[0011] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:
[0012] Figure 1 A schematic diagram of test wire wiring in the prior art is shown;
[0013] Figure 2 A schematic diagram of the test wire wiring in one embodiment of this application is shown;
[0014] Figure 3 This illustration shows a schematic diagram of the metal wiring layer and test wire wiring within the test pad in one embodiment of this application. Figure 1 ;
[0015] Figure 4 This illustration shows a schematic diagram of the metal wiring layer and test wire wiring within the test pad in one embodiment of this application. Figure 2 ;
[0016] Figure 5 This illustration shows a schematic diagram of the metal wiring layer and test wire wiring within the test pad in one embodiment of this application. Figure 3 ;
[0017] Figure 6 This illustration shows a schematic diagram of the metal wiring layer and test wire wiring within the test pad in one embodiment of this application. Figure 4 . Detailed Implementation
[0018] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0019] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0020] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0021] Embodiments of this application provide a semiconductor device having a dicing line region, wherein the dicing line region is provided for performing a dicing process to form individual chips from a semiconductor wafer.
[0022] The semiconductor device includes a semiconductor substrate and a test element group. The semiconductor substrate has an isolation structure formed therein for isolating and surrounding the formation of source / drain regions. In this embodiment, the isolation structure may be a shallow trench isolation structure. Alternatively, the isolation structure may be a local silicon oxide feature.
[0023] In this embodiment, the semiconductor substrate may include semiconductor materials such as silicon, germanium, silicon-germanium, or III-V semiconductor compounds such as GaP, GaAs, and GaSb. In some embodiments, it may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.
[0024] The test element group is set in the cutting line area. The test element group includes a first test pad 11, a test element 12 and a test lead 13. The test lead 13 is used to connect the first test pad 11 and the test element 12 and to measure the electrical characteristics of the test element 12.
[0025] Current methods for measuring the electrical characteristics of test element 12 include... Figure 1 As shown, several test leads 13 are led out from the test element 12 and connected to multiple test pads 11. The test leads 13 are typically connected in a zigzag pattern, which obviously increases their length and makes their structure complex. To solve this problem, as... Figure 2 As shown, in this embodiment, some of the metal wires in the test pad are separated as test wires 13. In this way, the test wires 13 can connect the test pad and the test element 12 in a straight line, which shortens the length of the test wires 13 and simplifies the arrangement structure of the test wires 13.
[0026] like Figure 3As shown, specifically, the first test pad 11 includes a first metal wiring layer 110 and a second metal wiring layer 111 stacked together, wherein the first metal wiring layer 110 and the second metal wiring layer 111 are alternately arranged, and the number of layers of the first metal wiring layer 110 and the second metal wiring layer 111 are both 2. The first test pad 11 can be a 4-layer metal wiring structure, wherein the first metal wiring layer 110 can be located in the 1st and 3rd layers respectively, and the second metal wiring layer 111 can be located in the 2nd and 4th layers. The first metal wiring layer 110 has a first metal wiring and a second metal wiring 112 that are insulated from each other. The first metal wiring is used as a test wire 13, and the second metal wiring 112 is connected to other metal wiring layers through a via connector 14.
[0027] It is worth mentioning that the first test pad 11 can also be a multi-layer metal wiring structure with 5, 6, 7, etc. In this embodiment, the number of layers of the first test pad 11 is not limited, and those skilled in the art can choose flexibly according to their needs.
[0028] Continue to refer to Figure 3 The test leads 13 in two adjacent first metal wiring layers 110 are staggered. Of course, this embodiment is not limited to this, and the test leads 13 in two adjacent first metal wiring layers 110 can also be positioned correspondingly.
[0029] In other embodiments of the invention, such as Figure 4 As shown, the first test pad 11 may include a second metal wiring layer 111 and a first metal wiring layer 110 stacked continuously. The second metal wiring layer 111 may be located at the fourth layer position. The number of layers of the first metal wiring layer 110 is 3, and the number of layers of the second metal wiring layer 111 is 1. Each first metal wiring layer 110 has insulated first metal wiring and second metal wiring 112. All the first metal wirings in the first metal wiring layer 110 can be used as test wires 13. The second metal wiring 112 in each first metal wiring layer 110 is connected to the second metal wiring layer 111 through a through-hole connector 14. The test wires 13 in all the first metal wiring layers 110 are in corresponding positions.
[0030] It is worth mentioning that the first metal wiring and the second metal wiring 112 are formed alternately, that is, the test wire 13 and the second metal wiring 112 are formed alternately.
[0031] Unlike Figure 4 The arrangement shown may be used in other embodiments of the present invention, such as... Figure 5 As shown, the test wires 13 in adjacent first metal wiring layers 110 are staggered, and the test wires 13 in two cross-layer first metal wiring layers 110 are in corresponding positions.
[0032] Unlike Figure 5 The arrangement shown may be used in other embodiments of the present invention, such as... Figure 6 As shown, the test wires 13 in each first metal wiring layer 110 are staggered.
[0033] This embodiment does not limit the number of metal wiring layers, the location of the test wires 13, or the arrangement of the test wires 13. Those skilled in the art can choose flexibly as needed.
[0034] In addition, the semiconductor device in this embodiment may also include a second test pad (not shown in the figure) electrically connected to the test lead 13. Specifically, unlike the first test pad, the second test pad may be a test pad with a conventional structure. The head of the second test pad is connected to the test element 12 through the test lead 13, achieving the effect of using a mixture of new and old test pads.
[0035] The semiconductor device in this embodiment may be a volatile memory device such as a DRAM device or an SRAM device, or a non-volatile memory device such as a Flash device, a PRAM device, an MRAM device, or an RRAM device.
[0036] Furthermore, chips with the aforementioned semiconductor devices can be used in various electronic devices, specifically smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.
[0037] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0038] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A semiconductor device, characterized in that, include: A semiconductor substrate having diced line regions formed thereon; Multiple first test pads and test elements are arranged in a straight line in the cutting line area; Test leads are used to connect the first test pad and the test element; Each first test pad includes multiple alternating layers of first metal wiring and second metal wiring. First metal wiring and second metal wiring are formed insulated from each other within the first metal wiring layer. The first metal wiring serves as the test wire, extending straight from the first test pad to connect to the test element. The first metal wiring in two adjacent first metal wiring layers is staggered. The second metal wiring in each of the first metal wiring layers is electrically connected to the other metal wiring layers of the first test pad via via connectors; the first metal wiring and the second metal wiring are alternately formed within the same first metal wiring layer.
2. The semiconductor device according to claim 1, characterized in that, It also includes a second test pad that is electrically connected to the test lead.