A narrow-bandgap semiconductor device and a method for manufacturing the same

Abstract

The present invention provides a narrow-bandgap semiconductor device with a high on-off ratio and a manufacturing method thereof. The device has a support substrate, on which there are successively a narrow-bandgap semiconductor layer, a gate dielectric layer and a gate stack structure. There is an L-shaped self-aligned sidewall on both sides of the gate stack structure, and its horizontal part extends a certain length along the plane where the narrow-bandgap semiconductor layer is located to the source region and the drain region on the outside respectively with respect to the gate dielectric layer located thereunder. Further, a metal is deposited on the horizontal part outside the sidewall and the narrow-bandgap semiconductor layer, and the latter is used as the source and drain of the semiconductor device. The device forms the sidewall through a gate self-alignment process, which can reduce the electric field strength at the junction of the channel and the source-drain region, thereby increasing the width of the interband tunneling barrier at the drain end, so that the reverse tunneling of minority carriers at the drain end can be better suppressed when operating under a large bias voltage. Therefore, while maintaining the high performance of the narrow-bandgap semiconductor device, the on-off ratio can be increased, and the bipolarity can be significantly suppressed.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a carbon nanotube field effect transistor and a preparation method thereof. Background Art

[0002] Currently, the feature size of the critical patterns of advanced silicon-based integrated circuit devices has crossed the 10 nm mark. When transistors continue to develop towards 5 nm and even smaller node technologies, it can be foreseen that silicon-based semiconductor technology is facing challenges from aspects such as processing technology, device physical limits, and performance. Its continuous development must overcome huge obstacles in terms of power consumption, cost, etc., and the development space also shows a trend of becoming smaller and smaller. There is an urgent need to find new information devices to continue to promote the development of the future semiconductor industry.

[0003] In recent years, many new semiconductor materials have great development potential in the field of high-speed integrated circuits due to their ultra-high mobility. In particular, binary compound semiconductors such as indium antimonide and indium arsenide are widely used in high-speed radio frequency circuits, and new nanomaterials such as carbon nanotubes, graphene, and nanoribbons have unique advantages. However, for some two-dimensional materials such as InAs nanowires, graphene nanoribbons, black phosphorus and one-dimensional materials such as carbon nanotubes, these semiconductors with high mobility usually have a relatively small bandgap, and there is a common problem of excessive off-state leakage current, which has become the main bottleneck for their large-scale engineering applications and integrations. For example, the typical bandgap of carbon nanotubes is about 0.8 eV, while the bandgap of silicon is about 1.12 eV, and the former is significantly smaller than the latter.

[0004] For conventional undoped (No-doping) narrow-bandgap semiconductor devices, due to the narrow bandgap, when a large reverse bias is applied, the electric field at the drain end (or called the drain electrode end or drain) is too concentrated and strong, resulting in a significant compression of the tunneling barrier width between bands at the drain end in the off state, making the Schottky tunneling near the drain end severe, and the reverse tunneling current of minority carriers increases greatly, generating a large tunneling current. This causes a significant increase in the off-state current of the device under a large reverse bias, a decrease in the on-off ratio of the transistor, and the bipolarity becomes more obvious. These effects lead to a large static power consumption of narrow-bandgap semiconductor integrated circuits and are prone to logic errors during operation.

[0005] In addition, for some new ultra-thin narrow-bandgap semiconductor materials such as carbon nanotubes, during the transistor preparation process, traditional ion implantation and doping methods cannot be used to regulate the transistor type like silicon-based devices. Therefore, in subsequent process steps, ion implantation technologies such as lightly doped drain (LDD) cannot be used to regulate the peak value of the drain electric field strength and its spatial distribution, thereby reducing negative effects such as short-channel effects, junction leakage current, and parasitic current.

[0006] There are already some relevant published literatures on the solutions to this problem. For example, Peking University proposed a feedback gate structure, as Figure 1 shown, which includes: an insulating substrate (201), a narrow bandgap semiconductor bulk or thin film (202), a gate dielectric layer (203), a gate electrode (204), a gate mask layer (205), sidewalls (206), a drain electrode wetting interface layer (207), a source electrode (208), and a drain-feedback gate electrode (209). Among them, the sidewalls (206) are located on both sides of the gate electrode (204) and the gate mask layer (205) to form an electrical isolation structure. By connecting a feedback gate near the drain-biased end of the channel, the feedback gate is connected to the drain-end metal electrode to form an equipotential, so that a rectangular potential barrier that does not change with the drain bias voltage is clamped at the drain end, thus greatly suppressing Schottky tunneling, suppressing the off-state leakage current, and improving the on-off ratio. However, due to the small bandgap, when operating in the off state, the minority carrier tunneling at the drain end is very serious. In addition, there are also many deficiencies in this feedback gate in terms of process. Since it uses a non-self-aligned process, there are large alignment deviation problems, and it is not compatible with the current integrated circuit manufacturing process, making large-scale preparation impossible. In addition, the drain end occupies a large contact area and it is difficult to continuously scale down with the development of semiconductor technology nodes.

[0007] In addition, IBM reported an asymmetric contact structure, which widens the Schottky barrier into a triangular barrier by etching near the drain end, thereby increasing the on-off ratio. However, the drain-end barrier of this method still has a tendency to thin with the increase of the bias voltage. In addition, this method is also a non-self-aligned process, with alignment problems, and the structure preparation is complex and the controllability of wet etching is poor, challenging the device performance uniformity and stability, and it is not easy to be integrated.

[0008] Therefore, how to effectively suppress the bipolarity of narrow bandgap semiconductor devices, thereby improving the on-off ratio of semiconductor transistors, and how to be compatible with the general silicon-based integrated circuit manufacturing process and suitable for large-scale industrialization have become the core issues in the application of narrow bandgap semiconductor materials in integrated circuits and other application fields. Summary of the Invention

[0009] The purpose of the present invention is to provide a narrow bandgap semiconductor device with a high on-off ratio and its processing method. The semiconductor device forms a sidewall structure with a specific shape through a gate self-aligned process, thereby reducing the electric field strength at the junction of the channel and the source-drain region, increasing the width of the interband tunneling barrier at the drain end, enabling good suppression of the reverse tunneling of minority carriers at the drain end when operating under a large bias voltage, so that the on-off ratio can be increased while maintaining the high performance of the narrow bandgap semiconductor device, and significantly suppressing bipolarity.

[0010] The technical solution of the present invention is as follows:

[0011] The present invention provides a self-aligned narrow-bandgap semiconductor device with a high on-off ratio, which includes a narrow-bandgap semiconductor layer and a gate stack structure on a support substrate. On both sides of the gate stack structure, there are sidewalls with an L-shaped profile formed by a self-alignment process, which respectively define a source region and a drain region located outside the sidewalls. Specifically, it includes the following features:

[0012] There is a gate dielectric layer between the gate stack structure and the narrow-bandgap semiconductor layer. The sidewall has an L-shaped profile composed of a vertical part and a horizontal part. The horizontal part extends a certain length along the plane of the narrow-bandgap semiconductor layer to the source region and the drain region located outside respectively under it. A metal layer is covered on the outside of the vertical part of the sidewall, above the horizontal part, and on the narrow-bandgap semiconductor layer to form the source and the drain.

[0013] Preferably, the support structure is a semiconductor material, a hard insulating material, or a high-temperature resistant flexible insulating material. Among them, the semiconductor material is silicon, silicon-on-insulator (SOI), SiC, InAs, III-V group materials, or II-IV group materials. The insulating material is selected from silicon oxide, quartz, glass, and alumina. The high-temperature resistant flexible insulating material is selected from polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyimide.

[0014] Preferably, the typical bandgap of the narrow-bandgap semiconductor layer is less than 1 eV, and it is selected from one of semiconductor-type carbon nanotubes, graphene nanoribbons, molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (P), germanium (Ge), or a composite layer of any two of the above.

[0015] Preferably, the thickness range of the gate dielectric layer (104) is 1-10 nm, and it is selected from silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, or lanthanum aluminate.

[0016] Preferably, the thickness range of the source (110) and the drain (110’) is 5-100 nm.

[0017] Preferably, the source (110) and the drain (110’) are selected from titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), conductive metal silicide, or doped polysilicon, any one of the above materials, or a laminated combination of different types of the above materials.

[0018] Preferably, for PMOS devices, the source (110) and drain are selected from high work function metals such as platinum (Pt) and palladium (Pd); for NMOS devices, the source and drain are selected from scandium (Sc), yttrium (Y), and aluminum (Al).

[0019] Another method for fabricating a self-aligned narrow bandgap semiconductor device with a high switching ratio according to the present invention is characterized by comprising the following steps:

[0020] S1: Provide a support structure, and sequentially form a narrow bandgap semiconductor layer, a gate dielectric layer, and a gate stack structure on the support structure;

[0021] S2: Deposit a first dielectric layer and a second dielectric layer sequentially on the above structure;

[0022] S3: Perform anisotropic etching on the second dielectric layer and accurately stop on the first dielectric layer to form an outer sidewall on both sides of the gate stack structure;

[0023] S4: Use the etched second dielectric layer as a self-aligned mask to perform anisotropic etching on the first dielectric layer and the gate dielectric layer and stop on the narrow bandgap semiconductor layer to form an inner sidewall;

[0024] S5: Remove the outer sidewall to form an L-shaped inner sidewall composed of a vertical part and a horizontal part. The width of the vertical part is determined by the thickness of the first dielectric layer, and the horizontal length is determined by the thickness of the outer sidewall. The size is precisely controllable and is located on the gate dielectric layer (104);

[0025] S6: Deposit source-drain metal to form a source (110) and a drain (110') on the semiconductor layer (103) on both sides of the inner sidewall.

[0026] Preferably, the first dielectric layer has an L-shaped profile formed by a deposition technique with good step coverage, and the second dielectric layer is formed by atomic layer deposition or plasma-enhanced chemical vapor deposition.

[0027] Preferably, the typical bandgap of the narrow bandgap semiconductor layer (103) is less than 1 eV and is selected from one of semiconductor-type carbon nanotube films, graphene nanoribbons, molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (P), germanium (Ge), or a composite layer of any two of the above.

[0028] Preferably, the thickness range of the gate dielectric layer (104) is 1 - 10 nm and is selected from silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, or lanthanum aluminate.

[0029] Preferably, the narrow-bandgap semiconductor device is formed by a back-gate process. The gate stack structure formed in step S1 is a dummy gate structure. After the outer sidewalls are removed in step S5 and the source electrode (110) and the drain electrode (110') are further formed thereon, an interlayer dielectric layer (112) is formed thereon. Subsequently, chemical mechanical polishing (CMP) planarization is performed on the interlayer dielectric layer (112), stopping on the dummy gate structure, and then the dummy gate structure is removed and a HKMG gate is formed therein. The typical bandgap of the narrow-bandgap semiconductor layer (103) is less than 1 eV, and it is selected from one of semiconductor-type carbon nanotubes, graphene nanoribbons, molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (P), germanium (Ge), or a composite layer of any two of the above.

[0030] Preferably, the thickness range of the gate dielectric layer (104) is 1-10 nm, and it is selected from silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, or lanthanum aluminate.

[0031] Preferably, the thickness range of the source electrode (110) and the drain electrode (110') is 5-100 nm.

[0032] Preferably, the source electrode (110) and the drain electrode (110') are selected from titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), conductive metal silicide, or doped polysilicon, any one of the above materials, or a laminated combination of different types of the above materials.

[0033] Preferably, for PMOS devices, the source electrode (110) and the drain electrode (110') are selected from high work function metals such as platinum (Pt) and palladium (Pd); for NMOS devices, the source electrode and the drain electrode are selected from scandium (Sc), yttrium (Y), and aluminum (Al).

[0034] Another aspect of the present invention provides a method for fabricating a self-aligned narrow-bandgap semiconductor device with a high switching ratio, including the following steps:

[0035] S1: Provide a support structure, and sequentially form a narrow-bandgap semiconductor layer, a gate dielectric layer, and a gate stack structure on the support structure;

[0036] S2: Sequentially deposit a first dielectric layer and a second dielectric layer on the above structure;

[0037] S3: Perform anisotropic etching on the second dielectric layer and accurately stop on the first dielectric layer to form an outer sidewall on both sides of the gate stack structure;

[0038] S4: Using the etched second dielectric layer as a self-aligned mask, anisotropically etch the first dielectric layer and the gate dielectric layer, and stop on the narrow bandgap semiconductor layer to form inner sidewalls;

[0039] S5: Remove the outer sidewalls to form L-shaped inner sidewalls composed of a vertical part and a horizontal part. The width of the vertical part is determined by the thickness of the first dielectric layer, and the horizontal length is determined by the thickness of the outer sidewalls. The size is precisely controllable and located on the gate dielectric layer;

[0040] S6: Deposit source-drain metal to form source and drain electrodes on the semiconductor layers on both sides of the inner sidewalls.

[0041] Preferably, the first dielectric layer has an L-shaped profile formed by a deposition technique with good step coverage, and the second dielectric layer is formed by atomic layer deposition or plasma-enhanced chemical vapor deposition method.

[0042] Preferably, the typical bandgap of the narrow bandgap semiconductor layer (103) is less than 1 eV, and it is selected from one of semiconductor-type carbon nanotube films, graphene nanoribbons, molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (P), germanium (Ge), or a composite layer of any two of the above.

[0043] Preferably, the thickness range of the gate dielectric layer is 1 - 10 nm, and it is selected from silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, or lanthanum aluminate.

[0044] Preferably, the narrow bandgap semiconductor device is formed by a back-gate process. The gate stack structure formed in step S1 is a dummy gate structure. After forming the source and drain electrodes further after removing the outer sidewalls in step S5, an interlayer dielectric layer is formed thereon, and then the interlayer dielectric layer is subjected to CMP planarization, stopping on the dummy gate structure, and then the dummy gate structure is removed and a high-k / metal gate (HKMG) is formed therein.

[0045] The present invention provides a narrow-bandgap semiconductor device with a high on-off ratio and a manufacturing method thereof. By adjusting the thickness of the inner sidewall of the transistor gate electrode and precisely controlling the extension length of the sidewall in the active region, the electric field intensity coupled into the channel region by the drain electrode can be weakened, thereby increasing the width of the interband tunneling barrier at the drain end. The semiconductor transistor structure and manufacturing process proposed by the present invention are very simple and efficient. Without using any traditional ion implantation or doping processes, nor adopting complex multi-layer thin film structures or multiple work function adjustment steps and processes, it can more efficiently solve the static power consumption problem caused by off-state tunneling current, effectively suppress the bipolarity problem of the device due to the narrow bandgap of the material itself, improve the on-off ratio of the narrow-bandgap semiconductor transistor. In particular, its manufacturing method can be compatible with the general silicon-based integrated circuit manufacturing process, paving the way for large-scale mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] By describing the technical solutions of the present invention with reference to the following drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0047] Figure 1 Schematic diagram of a semiconductor transistor structure with a feedback gate for the prior art;

[0048] Figure 2 Schematic diagram of the gate stack structure after lithography;

[0049] Figure 3 Schematic diagram of the structure after gate etching;

[0050] Figure 4 Schematic diagram of the structure after depositing the inner sidewall;

[0051] Figure 5 Schematic diagram of the structure after depositing the outer sidewall;

[0052] Figure 6 Schematic diagram of the double-layer sidewall structure formed by anisotropic etching;

[0053] Figure 7 Schematic diagram of the double-layer sidewall structure after removing the gate dielectric;

[0054] Figure 8 Schematic diagram of the naturally formed specific L-shaped inner sidewall structure after removing the outer sidewall;

[0055] Figure 9 Schematic diagram of the metal contact electrode structure formed in the source-drain region;

[0056] Figure 10 Schematic diagram of the structure for forming the contact hole etch stop layer and the ILD dielectric layer;

[0057] Figure 11Schematic diagram of the structure after CMP planarization of the ILD dielectric layer;

[0058] Figure 12 Schematic diagram of the structure after dummy gate removal, high-k / metal gate filling, and CMP planarization. Detailed implementation manners

[0059] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, the same elements are denoted by the same reference numerals, and the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, a semiconductor structure obtained after several steps may be described in one drawing.

[0060] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "above" or "on top of" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the device is flipped, this layer or region will be "below" or "beneath" the other layer or another region.

[0061] If it is for describing the case of being directly above another layer or another region, the expression "A is directly on top of B" or "A is on top of B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0062] The following will Figures 2 - 12 describe the present invention in detail.

[0063] In an embodiment of the present invention, a self-aligned narrow-bandgap semiconductor device with a high switching ratio obtained according to the above method steps is described, and its specific structure is as Figure 11 shown. A support structure 101, on which there is successively a narrow-bandgap semiconductor layer (103), and on the narrow-bandgap semiconductor layer (103), there are sidewalls (108) respectively defining a source region, a drain region outside the sidewalls (108), and an active region between the sidewalls (108), and in the active region, there is a gate stack structure (105).

[0064] Among them, the above-mentioned support structure 101 can be a semiconductor material, a hard insulating material, or a high-temperature resistant flexible insulating material. The semiconductor material is silicon, silicon-on-insulator (SOI), SiC, InAs, III-V group materials, II-IV group materials, or other semiconductor materials. The insulating material is selected from silicon oxide, quartz, glass, and alumina. The high-temperature resistant flexible insulating material is selected from polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyimide. The typical bandgap of the narrow bandgap semiconductor layer 103 is less than 1 eV, and it is selected from one of semiconductor-type carbon nanotube films, graphene nanoribbons, molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (P), germanium (Ge), or a composite layer composed of any two of the above. In this embodiment, the support structure 101 uses a silicon substrate, the narrow bandgap semiconductor layer 103 is a carbon nanotube film, and there is also a dielectric layer 102 between the support structure 101 and the narrow bandgap semiconductor layer 103 for insulation between semiconductors. The above-mentioned dielectric layer 102 can be silicon oxide, silicon nitride, SiCN, and other known or unknown dielectric insulating materials, and this patent does not make special limitations. In addition, in other embodiments, according to the specific requirements of the narrow bandgap semiconductor layer 103, the dielectric layer 102 material may not be used, and the substrate 101 also needs to be changed accordingly.

[0065] There is a gate dielectric layer 104 between the above-mentioned gate stack structure and the narrow bandgap semiconductor layer 103. The above-mentioned sidewall 108 has a specific L-shaped structure composed of a vertical part and a horizontal part, that is, it is formed by one-time manufacturing. The horizontal part extends a certain length along the plane where the narrow bandgap semiconductor layer 103 is located towards the source region and the drain region on the outside, and this length is precisely adjustable during the manufacturing process and covers the gate dielectric layer 104. In this embodiment, since the inner sidewall 108 is formed by a self-alignment process, the extension length of the inner sidewall 108 in the active region can be precisely controlled, and the electric field strength coupled into the channel region by the drain end electrode can be weakened, thereby increasing the width of the drain end interband tunneling barrier. The thickness range of the gate dielectric layer 104 is 1-10 nm, and its material is selected from silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, lanthanum aluminate, or other high dielectric constant (K) materials. In this embodiment, the thickness of the gate dielectric layer 104 is preferably 7 nm.

[0066] As CMOS devices are scaled down to the 45nm technology node, it has become inevitable to replace the traditional silicon dioxide and silicon oxynitride gate dielectrics with high-K materials having a higher dielectric constant. The replacement of polysilicon gates with metal gates solves the incompatibility problem between polysilicon gates and high-K dielectrics, and fundamentally eliminates inherent effects such as gate depletion and boron penetration in polysilicon gates. In the popular silicon-based planar back-gate technology, the high-K / metal gate stack is formed after the silicide (including high-temperature processes) in the CMOS front-end (FEOL) process is completed, that is, after the ILD layer is planarized and the dummy gate electrode is removed, the high-K and metal gate materials are deposited. Currently, in silicon-based devices, two back-gate process flows have been developed, either depositing the high-K gate dielectric material before the dummy gate is patterned, or depositing the high-K gate dielectric and metal gate stack materials after removing the polysilicon or amorphous silicon dummy gate.

[0067] The gate stack structure 105 can be a single layer or a stack of multiple metals. The materials of the metal gate mainly include Ti, TiN, TaN, TiAl, TiAlC, Al, etc. The preparation of the metal gate material is mainly determined by the integration process of high-K / metal gate (HKMG). The work function of the gate metal needs to match the energy of the carriers in the channel, that is, the work function of the selected metal gate must meet the requirements of PMOS and NMOS respectively. Different from polysilicon gate materials, which can easily provide carriers with appropriate energy and type through doping, for metals, the work function is a characteristic of the material itself and cannot be changed by doping. In the process of implementing metal gates, the main challenge is to select a metal with a suitable work function to obtain good drive performance. The work function of the metal gate needs to match the energy of the carriers in the channel, that is, to be close to the conduction band or valence band edge of the silicon energy band. That is, in order to control the device with the lowest threshold voltage (and thus the lowest power), NMOS devices must use low-work-function metals, while PMOS devices must use high-work-function metals. That is to say, if you want to change the threshold voltage of the MOS transistor, it can be achieved by changing the work function between the gate metal and the semiconductor channel material. In order to obtain a suitable threshold voltage, it is usually required that the work function of the NMOS metal gate material is around 4.1eV, and the work function of the PMOS metal gate material is around 5.2eV.

[0068] In the present invention, different from the silicon-based back-gate process, in the current embodiment, the metal gate stack structure 105 is directly deposited on the gate dielectric layer (104) without involving any dummy gate electrode materials such as polysilicon or amorphous silicon. This front-gate metal gate process greatly simplifies the manufacturing process and process complexity compared to the back-gate metal gate process. However, in order to obtain a suitable threshold voltage, when processing NMOS and PMOS devices, the work function of the metal gate stack structure needs to be around 4.1eV and 5.2eV respectively.

[0069] A metal layer is covered on the horizontal portion of the inner sidewall 108 and the narrow-bandgap semiconductor layer 103, and the latter serves as the source electrode 110 and the drain electrode 110'. Among them, the thickness range of the source electrode 110 and the drain electrode 110' is 5-100 nm, and it is selected from any one of metals such as titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), etc., conductive metal silicides or doped polysilicon, or a laminated combination of different types of the above materials. In this embodiment, the semiconductor device is a PMOS device, and the source electrode 110 and the drain electrode 110' respectively adopt high work function metals of platinum (Pt) and palladium (Pd). In another embodiment, the semiconductor device is an NMOS device, and the above source electrode 110 and drain electrode 110' are selected from low work function metals such as scandium (Sc), yttrium (Y), aluminum (Al), etc.

[0070] The semiconductor transistor structure obtained in this embodiment can solve the static power consumption problem caused by the off-state tunneling current, can effectively suppress the bipolar problem of the device caused by the narrow bandgap of the material itself, and further improve the switching ratio of the narrow-bandgap semiconductor transistor.

[0071] In another embodiment of the present invention, a method for directly fabricating a self-aligned narrow-bandgap semiconductor device with a high switching ratio by using a front-gate metal gate process is described, and the specific steps are as Figures 2 - 11 shown. The front-gate metal gate process is relative to the silicon-based back-gate process. In the former, during the manufacturing process, the high-K / metal gate is deposited before the source and drain electrodes are formed, and no dummy gate formation and removal process is involved in the whole process, while the latter needs to first fabricate a dummy gate electrode and source and drain electrodes, then remove the dummy gate, and then fill the high-K / metal gate therein to form.

[0072] First, according to step S1, a support structure 101 is provided, and then a narrow-bandgap semiconductor layer 103 is formed thereon. The support structure 101 mainly plays a supporting role and can be a semiconductor material, a hard insulating material or a high-temperature resistant flexible insulating material. Among them, the semiconductor material is silicon, silicon-on-insulator (SOI), SiC, InAs, III-V group materials, II-IV group materials or other semiconductor materials, the insulating material is selected from silicon oxide, quartz, glass, aluminum oxide, and the high-temperature resistant flexible insulating material is selected from polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or polyimide.

[0073] Among them, the typical bandgap of the narrow-bandgap semiconductor layer 103 is less than 1 eV, and it is selected from a composite layer of one of semiconductor-type carbon nanotube films, graphene nanoribbons, molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (P), germanium (Ge), or any combination of the above two. In this embodiment, the support structure 101 is made of silicon material, and the narrow-bandgap semiconductor layer 103 is a carbon nanotube film, including a carbon nanotube array film with neatly arranged parallel carbon nanotubes, a self-assembled carbon nanotube film, a carbon nanotube network array, and / or a carbon nanotube composite film formed by any combination of the above multiple methods. In this embodiment, the narrow-bandgap semiconductor material is selected as a carbon nanotube aligned array film, which can be obtained by pulling a substrate into a carbon nanotube solution. The carbon nanotube solution is formed by dissolving carbon nanotubes in one or more halogenated hydrocarbons, and the halogenated hydrocarbons can be selected from organic solvents such as chloroform, dichloroethane, trichloroethane, chlorobenzene, dichlorobenzene, and bromobenzene.

[0074] In this embodiment, since a silicon semiconductor material is used as the substrate support structure, a dielectric layer 102 must be introduced between 101 and 103 to play an insulating role between the two semiconductors. The dielectric layer 102 can be silicon oxide, silicon nitride, SiCN, and other known or unknown dielectric insulating materials, and this patent does not make special limitations. Additionally, in other embodiments, according to the specific requirements of the narrow-bandgap semiconductor layer 103, the dielectric layer 102 material may not be used, and the substrate 101 will also be changed accordingly.

[0075] Furthermore, a gate dielectric layer 104 is deposited on the above-mentioned narrow-bandgap semiconductor layer 102 by atomic layer deposition (ALD). The thickness range of the gate dielectric layer 104 is 1 - 10 nm, and its material can be selected from silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, lanthanum aluminate, or other high-K dielectric materials. In this embodiment, the material of the gate dielectric layer 104 is selected as hafnium oxide, and its thickness is 7 nm.

[0076] Then, a gate stack layer 105 is continuously formed on the gate dielectric layer 104, which can be a single layer or a stack of multiple metals. The materials of the metal gate 105 mainly include Ti, TiN, TaN, TiAl, TiAlC, Al, etc., or any other suitable materials, which are mainly determined by the integration process and performance requirements of CMOS devices. Mainly two methods of atomic layer deposition (ALD) or physical vapor deposition (PVD) are used. ALD can provide very excellent step coverage and can obtain a uniform metal gate thickness, providing a basic guarantee for providing precisely controllable gate materials. The PVD method can obtain different work functions by adjusting reaction parameters and can obtain higher productivity than the former. In this embodiment, ALD is used for the deposition of the gate stack layer 105.

[0077] Further, a layer of lead metal layer can be deposited on the above-mentioned gate stack layer 105. Metal materials such as tungsten (W), aluminum (Al), nickel (Ni), cobalt (Co), ruthenium (Ru), etc. can be selected. In this embodiment, cobalt (Co) is used as the lead metal layer. Then, a hard mask layer 106 and a gate lithography pattern 107 are sequentially formed thereon, and the lithography pattern 107 is transferred to the underlying hard mask layer 106 by using a suitable etching technique. Generally, the hard mask layer 106 is composed of a stack of an optical planarization (OPL) layer and an anti-reflection coating (ARC), or can also be composed of a stack of a planarization (OPL) layer and a silicon-based insulating dielectric layer, or a stack of a single insulating dielectric layer, so as to be able to achieve high-fidelity lithography pattern transfer as much as possible and ensure good topography control. Among them, the optical planarization (OPL) layer can be inorganic amorphous carbon, or an organic material such as spin-on carbon or diamond-like carbon. Its function is to provide a smooth and flat surface for the underlying structure. In one embodiment, the optical planarization (OPL) layer can be formed by spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), evaporation, or chemical solution deposition. The thickness of the OPL is generally selected according to the specific etching size. The current trend is to use an increasingly small thickness, such as 10 nm to 100 nm. The silicon-based insulating dielectric layer can be silicon oxide, silicon nitride, or silicon oxynitride, and can be formed by spin coating, (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HPCVD), chemical solution deposition, atomic layer deposition (ALD), etc.

[0078] The anti-reflection coating (ARC) includes a silicon-containing anti-reflection coating material. In this embodiment, a silicon anti-reflection layer (SiARC) is used, which can minimize the light reflection during lithography. The anti-reflection coating (ARC) can be formed by spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), evaporation, or chemical solution deposition. The silicon anti-reflection layer can also be replaced by a silicon-based insulating dielectric layer such as silicon oxide, silicon nitride, or silicon oxynitride.

[0079] Subsequently, the hard mask pattern 106 is transferred to the underlying gate stack layer 105 by using a suitable etching technique and can be precisely stopped on the gate dielectric layer 104, such as Figure 3As shown. During this process, any suitable etching technique can be adopted, such as dry etching processes like reactive ion etching, pulsed plasma etching, atomic layer etching, etc. Generally, halogen-based, fluorine-based, and fluorocarbon-based gases are used, preferably a mixed gas of Cl2, HBr, or SF6, CH2F2, etc. The present invention does not make specific limitations in this regard. Eventually, a gate stack structure 105 with a steep topography is formed. For the gate dielectric layer 104, a certain degree of over-etching can be performed, but the underlying semiconductor layer 103 should not be significantly damaged.

[0080] According to step S2, a first dielectric layer 108 is deposited on the above-mentioned gate stack structure 105, as Figure 4 shown. This material is used to isolate the direct connection between the source / drain metal layer and the gate layer to avoid short-circuit problems. The material of the first dielectric layer 108 is silicon dioxide (SiO2), silicon nitride (Si3N4), or other low-k dielectric materials such as SiCN, etc. Preferably, a thickness between about 5 nm and 50 nm can be adopted. In this embodiment, the deposited thickness is 20 nm. In order to form a specific L-shaped sidewall profile, that is, the first dielectric layer 108 composed of a vertical part and a horizontal part, a deposition technique with good step coverage is required to meet the requirements. Preferably, atomic layer deposition technology is selected.

[0081] Further, a second dielectric layer 109 is formed on the above-mentioned first dielectric layer 108, as Figure 5 shown. The material of the second dielectric layer 109 is silicon dioxide (SiO2), silicon nitride (Si3N4), or other low-k dielectric materials such as SiCN, etc., but it is required to have a certain etching selectivity with respect to the first dielectric layer 108. The second dielectric layer 109 can be formed by atomic layer deposition (ALD), atomic layer chemical vapor deposition (ALCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable deposition process. It should be noted that the thickness of the second dielectric layer 109 can be greater than that of the first dielectric layer 108, and its thickness is generally in the range of 20 nm to 100 nm. By controlling the thickness of the second dielectric layer 109, the extension length of the sidewall towards the source / drain contact region can be precisely controlled, thereby weakening the electric field intensity coupled into the channel region by the drain end electrode, and thus increasing the width of the drain end interband tunneling barrier. In this embodiment, the first dielectric layer 108 can be composed of silicon dioxide, and the second dielectric layer 109 can be composed of silicon nitride, with thicknesses of 20 nm and 50 nm respectively.

[0082] Further according to step S3, an anisotropic etching is performed on the second dielectric layer 109 using a dry etching process. Generally, a mixed plasma of a carbon-fluorine-based gas such as CF4, CHF3, etc. and O2 is used for etching, and the etching stops on the first dielectric layer 108, thereby forming outer sidewalls on both sides of the above gate stack structure. This process can use any suitable etching technique, such as dry etching processes like reactive ion etching, pulsed plasma etching, atomic layer etching, etc. During implementation, the materials of the first sidewall 108 and the second sidewall 109 need to be carefully selected, and it is required that the latter has a high etching selectivity to the former to ensure that the latter can stop accurately on the former during the etching process without causing serious damage to the underlying gate dielectric layer 104.

[0083] Further according to step S4, an anisotropic etching is performed on the first dielectric layer 108 using the above outer sidewalls as a self-aligned mask, and the etching stops on the gate dielectric layer 104 to form a specific L-shaped inner sidewall. To reduce the possible damage to the semiconductor layer 103 during the etching of the first dielectric layer 108, the etching process needs to be precisely controlled, and it is required that the remaining thickness of the gate dielectric layer 104 after etching is more than one-third of the initial thickness, thereby forming a self-aligned double-layer sidewall on both sides of the gate stack structure, as Figure 6 shown.

[0084] Next, further using the double-layer sidewalls as a mask, a suitable dry etching or wet etching technique or an advanced technique that may emerge in the future is used to remove the remaining gate dielectric layer 104 in the source-drain regions, thereby forming L-shaped inner sidewalls with a specific shape on both sides of the gate stack structure, as Figure 7 shown. It should be noted that although the first dielectric layer 108 and the second dielectric layer 109 can use any existing thin film deposition technique such as atomic layer deposition (ALD), atomic layer chemical vapor deposition (ALCVD), plasma-enhanced chemical vapor deposition (PECVD), or other deposition techniques, it is necessary to ensure that the first dielectric layer 108 has good step coverage during the deposition process. Therefore, it is preferably prepared using the atomic layer deposition (ALD) technique. The requirements for the second dielectric layer 109 are relatively low, and it can be formed using various deposition techniques.

[0085] Subsequently, according to step S5, the outer sidewalls are removed, and finally only the inner sidewalls 108 are retained, thereby forming self-aligned inner sidewalls, as Figure 8As shown. Among them, the gate dielectric layer 104 is located between the semiconductor material layer and the inner spacer 108, and is only located between the channel region and the source region and between the channel region and the drain region in the horizontal direction; the horizontal part extends a certain length along the plane of the narrow-bandgap semiconductor layer 103 to the source region and the drain region on the outside respectively with the gate dielectric layer 104 located thereunder, and this length is precisely controllable during the manufacturing process; the source region and the drain region are symmetrically located on both sides of the inner spacer 108 and the gate, and the etched inner spacer 108 is entirely located above the plane of the narrow-bandgap semiconductor layer.

[0086] Furthermore, deposit metal on the structure of the inner spacer 108, and selectively remove the redundant metal layer on the surface of the inner spacer 108 and the metal layer that needs to be removed to achieve isolation between adjacent devices, only retaining the metal layers on the source-drain regions, on the horizontal surfaces of the inner spacer 108, on the outer sides in the vertical direction of the inner spacer 108, and on the top of the gate stack structure. Thus, contact metals can be formed on the source-drain regions and the top of the gate at one time. The inner spacer 108 extends a certain dimension in the horizontal direction to the source and drain regions, which can weaken the electric field intensity coupled into the channel region by the drain end electrode, thereby increasing the width of the drain end interband tunneling barrier, as Figure 9 shown. In the present invention, the source 110 and the drain 110' are formed symmetrically and self-aligned on both sides of the gate structure. By adjusting the thicknesses of the inner and outer spacers of the transistor gate electrode, the insulation performance between different devices and the extension length of the spacer in the active region can be precisely controlled to ensure device performance. In comparison, most other similar inventions control the pattern size through lithography, i.e., non-self-aligned processes, which cannot guarantee the alignment accuracy of the source and drain metals, cannot be symmetrically and precisely distributed on both sides of the gate, resulting in variations in device performance or various reliability problems.

[0087] Doping technology is the core of current silicon-based CMOS technology. Impurities provide carriers for the device channel, thus determining the properties of the device. This requires processes such as ion implantation or doping to form the source and drain regions, and then a self-aligned silicide process is used to form silicide or a silicide layer in the source and drain regions, which is formed through a silicidation reaction, that is, the reaction occurs within the silicon body. Over the decades, a total of various metals have been used in the preparation of silicides, mainly including materials such as Ti, Co, Ni and their alloys. Compared with traditional silicon-based semiconductor devices, in this patent, the working principle of the new narrow-bandgap device is completely different. During the manufacturing process, no traditional doping or ion implantation process is involved. This doping-free CMOS technology completely breaks through the concept of traditional silicon-based devices. The polarity of the new narrow-bandgap device is controlled by the work function of the contact electrode. A metal that meets the work function requirements is directly deposited on the surface of the semiconductor material in the source and drain regions, and forms good wetting with the semiconductor layer. At the same time, it also forms a good ohmic contact with the conduction band or valence band of the semiconductor layer. The N-type or P-type polarity of the device is adjusted through charge coupling or conduction between the semiconductor material and the metal. Obviously, the new narrow-bandgap device does not require doping of the semiconductor material layer, and a doping region will not be formed naturally on the surface or in the body of the semiconductor layer. This is essentially different in principle from the way of forming source and drain regions by doping or ion implantation in traditional silicon-based processes.

[0088] The thickness range of the metal deposited on the source 110 and drain 110’ regions is 5 - 100 nm, and it is selected from metals such as titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), etc., conductive metal silicides or doped polysilicon, or any one of these materials or a laminated combination of different types of the above materials. The general guiding principle is to select different metals according to whether an nFET or pFET type device is manufactured. A metal thin film is formed by source and drain metal sputtering instead of changing the type of the device through complex and cumbersome ion implantation and forming silicide or a silicide layer as in traditional silicon-based devices. For nFET, a metal system with a lower work function (WF) can be used, such as Sc or Al, while for pFET, a metal system with a higher work function (WF) can be used, such as Au or Pd. In one embodiment, the semiconductor layer of the new narrow-bandgap device is a carbon nanotube. The low work function metal is selected as Sc, and the high work function metal is selected as Pd. They can form good ohmic contacts with the carbon nanotubes, so that electrons or holes can be selectively and unobstructedly injected from the contact electrode into the semiconductor layer, thus realizing an N-type or P-type device.

[0089] In another embodiment, the semiconductor device is a PMOS device, and the source 110 and the drain 110' are made of platinum (Pt) with a high work function metal, and the thickness is 20 nm. In another embodiment, the semiconductor device is an NMOS device, and the source 110 and the drain 110' can be selected from yttrium (Y) and aluminum (Al).

[0090] Subsequently, the manufacturing of the contact hole structure can be carried out. Since extremely high-energy plasma bombardment is required during contact hole etching, it is necessary to avoid damaging the semiconductor layer 103 as much as possible during this process. Therefore, an etch stop layer 111 needs to be formed on the surface of the processed device in advance as the stop layer during the subsequent contact hole etching process, and at the same time, the damage to the sidewall can also be reduced, as Figure 9 shown. Otherwise, if the semiconductor material layer under the source-drain contact metal or the gate sidewall is directly etched during contact hole etching, it will directly damage the carrier injection ability of the source-drain contact region, or cause a short circuit between the source-drain contact metal and the gate metal, which will have a serious impact on the performance of the transistor.

[0091] Specifically, first, an etch stop layer 111 with a certain thickness is deposited on the wafer surface, and careful design is required to ensure that its thickness meets the requirements of the device. Preferably, the etch stop layer 111 can be silicon nitride, silicon carbide, silicon oxynitride, or other insulating materials. It is generally prepared by PECVD, LPCVD, or ALD deposition techniques, and the specific thickness depends on the needs of the device, generally ranging from 5 to 50 nm. In this embodiment, silicon nitride is used as the etch stop layer for contact holes.

[0092] Further, an interlayer dielectric layer (ILD) 112 is formed on this layer 111, and it can be deposited by PECVD, SACVD, LPCVD, or HDPCVD to form silicon oxide or a spin-on insulating dielectric SOD is spin-coated, as Figure 10 shown. The interlayer dielectric layer (ILD) material can be doped or undoped silicon oxide, low-k materials including but not limited to organic low-k materials (such as organic polymers containing aryl or polycyclic rings), inorganic low-k materials, such as amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicate glass, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), porous low-k materials (such as disiloxane (SSQ)-based porous low-k materials, porous silicon dioxide, porous SiOCH, carbon-doped silicon dioxide, fluorine-doped porous amorphous carbon, porous diamond, porous organic polymers). In this embodiment, the interlayer dielectric layer (ILD) is formed by depositing silicon oxide by PECVD.

[0093] Furthermore, a chemical mechanical polishing (CMP) method is further adopted to perform CMP planarization on the interlayer dielectric layer (ILD) 112. According to requirements, it is necessary to accurately stop above the high-K / metal gate structure and make contact with the metal gate material to meet the requirements for local interconnects, such as Figure 11 shown.

[0094] In addition to the front-gate metal gate process, in other embodiments, a similar silicon-based back-gate process can also be used to form narrow-bandgap semiconductor devices. That is, after forming the gate dielectric layer 104 in step S1, a dummy gate electrode layer is formed thereon, and then photolithography and etching are performed on the dummy gate electrode to form a dummy gate electrode structure. The material of the dummy gate electrode 104 can be polysilicon or amorphous silicon. In this embodiment, amorphous silicon is used as the dummy gate electrode material. In the above step S5, CMP planarization is performed on the above interlayer dielectric layer 112, stopping on the above dummy gate structure, and then the above dummy gate structure is further removed and a high-K / metal gate (HKMG) material is deposited therein, such as Figure 12 shown.

[0095] According to the manufacturing process of the above embodiment, by adjusting the thickness of the L-shaped inner sidewall 108 of the transistor gate electrode and precisely controlling the extension length of the outer sidewall 109 in the active region, the electric field strength coupled into the channel region by the drain end electrode is weakened, thereby increasing the width of the drain end interband tunneling barrier. Moreover, its processing method can be compatible with the general silicon-based integrated circuit manufacturing process, paving the way for large-scale mass production.

[0096] Although the present invention has been described in detail above with general descriptions and specific embodiments, based on the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of the present invention claimed.

Claims

1. A self-aligned narrow-bandgap semiconductor device with a high on-off ratio, comprising a narrow-bandgap semiconductor layer (103) and a gate stack structure (105) on a support structure (101), and having L-shaped sidewalls (108, 108') formed by a self-aligned process on both sides of the gate stack structure (105), which respectively define a source region and a drain region located outside the sidewalls (108, 108'), characterized in that: There is a gate dielectric layer (104) between the gate stack structure (105) and the narrow-bandgap semiconductor layer (103), the sidewalls (108, 108') are in direct contact with the side surfaces of the gate stack structure (105), the sidewalls (108, 108') have an L-shaped profile composed of a vertical part and a horizontal part, and the horizontal part extends a certain length along the plane of the narrow-bandgap semiconductor layer (103) to the source region and the drain region located outside respectively with respect to the gate dielectric layer (104) thereunder, and a metal layer is covered on the outside of the vertical part of the sidewalls (108, 108'), above the horizontal part and on the narrow-bandgap semiconductor layer (103) to form a source electrode (110) and a drain electrode (110').

2. The self-aligned narrow-bandgap semiconductor device with a high on / off ratio as claimed in claim 1, wherein The support structure (101) is a semiconductor material, a hard insulating material or a high-temperature resistant flexible insulating material, wherein the semiconductor material is silicon, silicon-on-insulator (SOI), SiC, InAs, III-V group materials or II-IV group materials, the insulating material is selected from silicon oxide, quartz, glass, aluminum oxide, and the high-temperature resistant flexible insulating material is selected from polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or polyimide.

3. The self-aligned narrow-bandgap semiconductor device with a high on-off ratio as described in claim 1, wherein The typical bandgap of the narrow-bandgap semiconductor layer (103) is less than 1 eV, and it is selected from one of semiconductor-type carbon nanotubes, graphene nanoribbons, molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (P), germanium (Ge) or a composite layer of any two of the above.

4. The self-aligned narrow-bandgap semiconductor device with a high on-off ratio as described in claim 1, wherein The thickness range of the gate dielectric layer (104) is 1-10 nm, and it is selected from silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide or lanthanum aluminate.

5. The self-aligned narrow-bandgap semiconductor device with a high on / off ratio as described in claim 1, characterized in that The thickness range of the source electrode (110) and the drain electrode (110') is 5-100 nm.

6. The self-aligned narrow-bandgap semiconductor device with a high on / off ratio as claimed in claim 1 or 5, wherein The source electrode (110) and the drain electrode (110') are selected from titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), conductive metal silicides or doped polysilicon, any one of the materials or a laminated combination of different types of the above materials.

7. The self-aligned narrow-bandgap semiconductor device with a high on-off ratio as claimed in claim 1 or 5, characterized in that, For PMOS devices, the source electrode (110) and the drain electrode (110') are selected from platinum (Pt), palladium (Pd); for NMOS devices, the source electrode and the drain electrode are selected from scandium (Sc), yttrium (Y), aluminum (Al).

8. A manufacturing method of a self-aligned narrow-bandgap semiconductor device with a high switching ratio, characterized in that, Including the following steps: S1: Provide a support structure (101), and sequentially form a narrow-bandgap semiconductor layer (103), a gate dielectric layer (104), and a gate stack structure (105) on the support structure (101); S2: Sequentially deposit a first dielectric layer and a second dielectric layer on the above structure; S3: Anisotropically etch the second dielectric layer and accurately stop on the first dielectric layer to form an outer sidewall on both sides of the gate stack structure (105); S4: Use the etched second dielectric layer as a self-aligned mask to anisotropically etch the first dielectric layer and the gate dielectric layer (104) and stop on the narrow-bandgap semiconductor layer (103) to form an inner sidewall; S5: Remove the outer sidewall to form an L-shaped inner sidewall composed of a vertical part and a horizontal part. The width of the vertical part is determined by the thickness of the first dielectric layer, and the horizontal length is determined by the thickness of the outer sidewall. The size is precisely controllable and is located on the gate dielectric layer (104); S6: Deposit source-drain metal to form a source electrode (110) and a drain electrode (110') on the semiconductor layer (103) on both sides of the inner sidewall.

9. The method for fabricating a self-aligned narrow-bandgap semiconductor device with a high on / off ratio as claimed in claim 8, wherein, The first dielectric layer has an L-shaped profile formed by a deposition technique with good step coverage. The second dielectric layer is formed by atomic layer deposition or plasma-enhanced chemical vapor deposition method.

10. The manufacturing method of the self-aligned narrow-bandgap semiconductor device with a high on / off ratio as claimed in claim 8, characterized in that, The typical bandgap of the narrow-bandgap semiconductor layer (103) is less than 1 eV and is selected from one of semiconductor-type carbon nanotube films, graphene nanoribbons, molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (P), germanium (Ge), or a composite layer of any two of the above.

11. The method for fabricating a self-aligned narrow-bandgap semiconductor device with a high on / off ratio as claimed in claim 8, wherein The thickness range of the gate dielectric layer (104) is 1-10 nm and is selected from silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, or lanthanum aluminate.

12. The manufacturing method of a self-aligned narrow-bandgap semiconductor device with a high on-off ratio as claimed in claim 8, wherein The narrow-bandgap semiconductor device is formed by a back-gate process. The gate stack structure formed in step S1 is a dummy gate structure. After forming the source electrode (110) and the drain electrode (110') further after removing the outer sidewall in step S5, and forming an interlayer dielectric layer (112) thereon, then perform CMP planarization on the interlayer dielectric layer (112), stop on the dummy gate structure, and then remove the dummy gate structure and form a high-k / metal gate (HKMG) therein.

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