Mask, mask manufacturing method, and mask assembly

Abstract

Disclosed herein is a mask, a mask assembly, and a method of manufacturing a mask. The mask includes a polymer film defining at least one cell region and at least one peripheral region therein, the at least one peripheral region surrounding the at least one cell region; a conductive layer disposed on the polymer film and including a metal; an inorganic layer disposed between the polymer film and the conductive layer and including a silicon-based inorganic material; and a plurality of holes penetrating the polymer film, the conductive layer, and the inorganic layer and superimposed on the at least one cell region in a plan view.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0145382, filed on November 3, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The invention relates to a mask with improved reliability, a method for manufacturing the mask, and a mask assembly including the mask. Background Technology

[0003] A display panel comprises pixels. Each pixel includes a driving element such as a transistor and a display element such as an organic light-emitting diode. The display element can be formed by setting electrodes and light-emitting patterns on a substrate.

[0004] A light-emitting pattern is formed on a specific area using a mask with defined holes. The light-emitting pattern can be formed on the area exposed by the holes. Because mass production of display panels requires the reuse of production facilities, research is needed to provide production facilities with improved reliability.

[0005] It will be understood that this background section is intended to provide some useful context for understanding the technology. However, this background section may also include ideas, concepts, or insights that were not known or understood by one of skill in the art prior to the corresponding valid date of submission of the subject matter disclosed herein. Summary of the Invention

[0006] The embodiments provide a mask with improved reliability and a mask assembly including the mask. The embodiments also provide a mask manufacturing method that can produce a mask with improved reliability without additional facility investment.

[0007] According to an embodiment, a mask may include: a polymer film defining at least one unit region and at least one peripheral region therein, the at least one peripheral region surrounding the at least one unit region; a conductive layer disposed on the surface of the polymer film, the conductive layer comprising a metal; an inorganic layer disposed between the polymer film and the conductive layer, the inorganic layer comprising a silicon-based inorganic material; and a plurality of holes penetrating the polymer film, the conductive layer and the inorganic layer, and superimposed on the at least one unit region in a plan view.

[0008] In this embodiment, the inorganic layer may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following.

[0009] In the embodiments, the polymer film may include at least one of polyimide (PI), polycarbonate (PC), polyethylene naphthalate (PEN), and polyethylene terephthalate (PET).

[0010] In embodiments, the conductive layer may include nickel (Ni), gold (Au), titanium (Ti), molybdenum (Mo), or titanium nitride (TiN). x At least one of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0011] In the embodiments, the thickness of the polymer film can be in the range of about 3 μm to about 50 μm.

[0012] In this embodiment, the thickness of the inorganic layer may be less than the thickness of the polymer film.

[0013] In an embodiment, the at least one unit region may include multiple unit regions. The multiple unit regions may be spaced apart from each other, and the at least one peripheral region may be disposed between adjacent unit regions among the multiple unit regions.

[0014] According to an embodiment, a mask assembly may include a mask frame defining at least one opening therein and at least one mask corresponding to the at least one opening disposed on the mask frame. The at least one mask may include: a polymer film defining at least one unit region and at least one peripheral region surrounding the at least one unit region; a conductive layer disposed on the surface of the polymer film, the conductive layer comprising a metal; an inorganic layer disposed between the polymer film and the conductive layer, the inorganic layer comprising a silicon-based inorganic material; and a plurality of holes penetrating the polymer film, the conductive layer, and the inorganic layer, and superimposed on the at least one unit region in a planar view.

[0015] In this embodiment, the inorganic layer may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following.

[0016] In an embodiment, the at least one unit region may include multiple unit regions. The multiple unit regions may be spaced apart from each other, the at least one peripheral region may be disposed between adjacent unit regions among the multiple unit regions, and in a plan view, the multiple unit regions may overlap with the at least one opening.

[0017] In an embodiment, the at least one opening may include multiple openings, the at least one mask may include multiple masks, and the multiple masks may be disposed on a mask frame corresponding to the multiple openings.

[0018] In an embodiment, a portion of the at least one mask may be incorporated into a mask frame to overlap with the at least one peripheral region in a planar view. The portion of the at least one mask incorporated into the mask frame may comprise a metal oxide.

[0019] According to an embodiment, a mask manufacturing method may include: forming an initial polymer film; forming an initial inorganic layer on the initial polymer film; forming an initial conductive layer on the initial inorganic layer; and forming a plurality of holes penetrating the initial polymer film, the initial inorganic layer, and the initial conductive layer. The initial inorganic layer may include a silicon-based inorganic material, and the initial conductive layer may include a metal.

[0020] In this embodiment, the initial inorganic layer can be formed by chemical vapor deposition (CVD).

[0021] In one embodiment, the formation of the plurality of holes may include irradiating a laser to simultaneously penetrate the initial polymer film, the initial inorganic layer, and the initial conductive layer.

[0022] In this embodiment, the wavelength range of the laser may include the wavelength range of ultraviolet light.

[0023] In one embodiment, the formation of the plurality of holes may include irradiating a laser to form the plurality of holes in a planar view with a pattern.

[0024] In an embodiment, the formation of the plurality of holes may include: forming a patterned photoresist on an initial conductive layer; forming a plurality of first initial holes penetrating the initial conductive layer by a first etching step of etching the initial conductive layer; removing the photoresist; forming a plurality of second initial holes penetrating the initial inorganic layer and superimposed on the plurality of first initial holes by a second etching step of etching the initial inorganic layer; and forming the plurality of holes penetrating the initial polymer film and superimposed on the plurality of second initial holes by a third etching step of etching the initial polymer film.

[0025] In an embodiment, the formation of the plurality of holes may include: forming a patterned photoresist on an initial conductive layer; forming a plurality of first initial holes penetrating the initial conductive layer by a first etching step of etching the initial conductive layer; removing the photoresist; and forming the plurality of holes penetrating the initial inorganic layer and the initial polymer film and superimposed on the plurality of first initial holes by a second etching step of simultaneously etching the initial inorganic layer and the initial polymer film.

[0026] In an embodiment, the first etching step may include a wet etching step or a dry etching step. The second and third etching steps may each include a dry etching step. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of the embodiments, and these drawings are incorporated in and form a part of this specification. The above and other aspects and features of this disclosure will become clearer from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0028] Figure 1 A schematic cross-sectional view illustrating a display panel according to an embodiment is shown.

[0029] Figure 2 A schematic cross-sectional view illustrating a deposition apparatus according to an embodiment is shown.

[0030] Figure 3A A perspective view illustrating a mask assembly according to an embodiment is shown.

[0031] Figure 3B It shows the following along Figure 3A A schematic cross-sectional view of the mask cut by line I-I'.

[0032] Figure 4 A schematic cross-sectional view illustrating the steps of a display panel manufacturing process according to an embodiment is shown.

[0033] Figure 5A A perspective view illustrating a mask assembly according to an embodiment is shown.

[0034] Figure 5B It shows the following along Figure 5A A schematic cross-sectional view of the mask assembly taken from line II-II'.

[0035] Figure 6 A flowchart illustrating a mask manufacturing method according to an embodiment is shown.

[0036] Figures 7A to 7D A schematic cross-sectional view illustrating a mask manufacturing method according to an embodiment is shown.

[0037] Figures 8A to 8E A schematic cross-sectional view illustrating a mask manufacturing method according to an embodiment is shown.

[0038] Figure 9A and Figure 9B A schematic cross-sectional view illustrating a mask manufacturing method according to an embodiment is shown.

[0039] Figures 10A to 10C A schematic cross-sectional view illustrating a method for manufacturing a mask assembly according to an embodiment is shown. Detailed Implementation

[0040] The disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0041] In the accompanying drawings, the size, thickness, scale, and dimensions of elements may be exaggerated for ease of description and clarity. The same reference numerals always denote the same elements.

[0042] In this description, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on," "connected to," or "bonded to" another element, the element may be directly on, directly connected to, or directly bonded to the other element, or there may be one or more intermediate elements between them. In a similar sense, when an element (or region, layer, portion, etc.) is described as "covering" another element, the element may directly cover the other element, or there may be one or more intermediate elements between them.

[0043] In the description, when an element is "directly on" another element, "directly connected to" another element, or "directly bonded to" another element, there is no intermediate element. For example, "directly on" can refer to setting two layers or two elements without any additional elements such as adhesive elements between them.

[0044] As used herein, expressions used in the singular, such as “a,” “one,” and “the,” are also intended to include the plural form, unless the context clearly indicates otherwise.

[0045] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items. For example, “A and / or B” can be understood to mean “A, B, or A and B”. The terms “and” and “or” can be used in the sense of combination or separation and can be understood as equivalent to “and / or”.

[0046] The term "at least one of..." is intended, for the purposes of its meaning and interpretation, to include the meaning of "selected from at least one of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B". When the term "at least one of..." follows a column of elements, it modifies the entire column of elements, rather than a single element in that column.

[0047] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the publicly disclosed teachings, a first element may be referred to as a second element. Similarly, without departing from the scope of the disclosure, a second element may be referred to as a first element.

[0048] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “above,” etc., are used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to those depicted in the drawings. For example, if the device shown in the drawings is flipped, a device located “below” or “under” another device may be positioned “above” that device. Therefore, the illustrative term “below” can include both upper and lower positions. The device may also be positioned in other directions, and thus the spatial relative terms can be interpreted differently depending on the orientation.

[0049] As used herein, the terms “about” or “approximately” include the stated value and refer to an acceptable deviation of the stated value from the error (i.e., the limitations of the measurement system) determined by a person skilled in the art considering the measurement in question and the error associated with the measurement of the stated quantity. For example, “about” may mean within one or more standard deviations, or within ±20%, ±10%, or ±5% of the stated value.

[0050] It should be understood that the terms “comprising,” “including,” “containing,” “having,” “having,” and variations thereof are intended to indicate the presence of the stated features, wholes, steps, operations, elements, components, or combinations thereof in the disclosure, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, or combinations thereof.

[0051] Unless otherwise defined or implied herein, all terms used (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined in the specification, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0052] The mask, mask assembly, and mask manufacturing method according to embodiments will now be described.

[0053] Figure 1A schematic cross-sectional view illustrating a display panel according to an embodiment is shown. In this embodiment, the display panel DP may be an organic light-emitting display panel. Figure 1 A schematic cross-section of one of the pixels is shown. In this description, a pixel may include at least one transistor and at least one light-emitting element. Figure 1 A cross-section of an embodiment in which transistors T1 and T2, in which pixels are disposed, and a light-emitting element DP-OL is shown.

[0054] The substrate layer BL may include a synthetic resin layer. Manufacturing the display panel DP may include forming a synthetic resin layer on a support substrate used for manufacturing the display panel DP, forming a conductive layer and an insulating layer on the synthetic resin layer, and removing the support substrate. When the support substrate is removed, the synthetic resin layer may correspond to the substrate layer BL.

[0055] The circuit element layer ML may include at least one insulating layer and at least one circuit element. The circuit element may include signal lines, pixel driver circuits, etc. The insulating layer, semiconductor layer, and conductive layer may be formed by coating and / or deposition processes, and the insulating layer, semiconductor layer, and conductive layer may be patterned by patterning processes to form the circuit element layer ML.

[0056] In an embodiment, the circuit element layer ML may include a barrier layer BRL, a buffer layer BFL, and first to seventh insulating layers 10, 20, 30, 40, 50, 60, and 70. The barrier layer BRL, buffer layer BFL, and first to seventh insulating layers 10 may include at least one inorganic layer and an organic layer. At least one of the fifth insulating layer 50, sixth insulating layer 60, and seventh insulating layer 70 may include an organic layer.

[0057] A barrier layer BRL and a buffer layer BFL can be disposed on a substrate layer BL. At least one of the barrier layer BRL and the buffer layer BFL may include an inorganic layer. A semiconductor pattern can be disposed on the barrier layer BRL and the buffer layer BFL. The barrier layer BRL and the buffer layer BFL can increase the adhesion between the substrate layer BL and the semiconductor pattern.

[0058] Figure 1 An arrangement of an embodiment constituting a first active layer A1, a second active layer A2, a first gate electrode G1, a second gate electrode G2, a first source S1, a second source S2, a first drain D1, and a second drain D2 is shown.

[0059] In this embodiment, the first active layer A1 and the second active layer A2 may comprise materials different from each other. The first active layer A1 may comprise a polycrystalline silicon semiconductor, and the second active layer A2 may comprise a metal-oxide-semiconductor. The first source S1 and the first drain D1 may each have a doping concentration greater than that of the first active layer A1, and may each serve as an electrode. The second source S2 and the second drain D2 may each be a reduced form of the metal-oxide-semiconductor and may each serve as an electrode.

[0060] In this embodiment, the first active layer A1 and the second active layer A2 may include the same semiconductor material, and the circuit element layer ML may have a simplified stacked structure.

[0061] The first gate electrode G1 and the second gate electrode G2 may be stacked with the first active layer A1 and the second active layer A2, respectively. The first gate electrode G1 and the second gate electrode G2 may each comprise multiple metal layers. The first gate electrode G1 and the second gate electrode G2 may each be used as masks in a semiconductor patterning doping process.

[0062] The upper electrode UE can be disposed on the second insulating layer 20 covering the first gate electrode G1. The upper electrode UE can be stacked with the first gate electrode G1. The upper electrode UE can include multiple metal layers. In an embodiment, the upper electrode UE can be omitted.

[0063] The display element layer EL may include a pixel defining layer PDL and a light-emitting element DP-OL. The light-emitting element DP-OL may be an organic light-emitting diode or a quantum dot light-emitting diode. The light-emitting element DP-OL may include a first electrode AE, a hole control layer HCL, a light-emitting layer EML, an electron control layer ECL, and a second electrode CE stacked sequentially.

[0064] The first electrode AE ​​can be disposed on the seventh insulating layer 70. The pixel defining layer PDL can have an opening PDL-OP that exposes at least a portion of the first electrode AE. The opening PDL-OP of the pixel defining layer PDL can define a light-emitting region PXA. A non-light-emitting region NPXA can surround the light-emitting region PXA.

[0065] The hole control layer (HCL) and the electronic control layer (ECL) can be commonly disposed within the emitting region (PXA) and the non-emitting region (NPXA). An aperture mask can be used to allow the HCL and ECL to be commonly formed on multiple pixels.

[0066] The light-emitting layer EML can be deposited in a different manner than the hole control layer HCL and the electronic control layer ECL, and each of the hole control layer HCL and the electronic control layer ECL can be formed as a thin film. The light-emitting layer EML can be formed differently depending on the type of pixel to be formed. A mask according to an embodiment can be used such that the light-emitting layer EML is patterned to have a shape corresponding to the shape of the opening PDL-OP of the pixel defining layer PDL.

[0067] However, the embodiments are not limited thereto, and in a manner similar to the formation of the light-emitting layer EML, the mask according to the embodiments can be used such that the hole control layer HCL and the electron control layer ECL are each patterned to have a shape corresponding to the shape of the opening PDL-OP of the pixel defining layer PDL.

[0068] The second electrode CE can be disposed on the electronic control layer ECL. The upper insulating layer ECP can be disposed on the second electrode CE. The upper insulating layer ECP can have a multilayer structure including at least one of inorganic and organic layers. The upper insulating layer ECP can include an insulating layer for encapsulating the display element layer EL and / or improving luminous efficiency.

[0069] Figure 2 A schematic cross-sectional view illustrating a deposition apparatus according to an embodiment is shown. The deposition apparatus DPD according to the embodiment can be used in... Figure 1 The diagram illustrates a deposition process in the fabrication of a display panel DP (such as for a light-emitting layer EML). The deposition apparatus DPD may include a chamber CHB and may include a deposition source S, a platform STG, a moving plate PP, and a mask assembly MA disposed within the chamber CHB. The mask assembly MA may include a mask frame MF and a mask MK.

[0070] The chamber CHB can provide an airtight space and establish vacuum deposition conditions. The chamber CHB may have a bottom surface, a top surface, and sidewalls. The bottom surface of the chamber CHB is parallel to the plane defined by a first direction axis DR1 and a second direction axis DR2. The normal direction of the bottom surface of the chamber CHB is parallel to a third direction axis DR3. In the following description, the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 are defined as representing the first direction, the second direction, and the third direction, respectively, wherein the first direction to the third direction are assigned the same reference numerals.

[0071] The chamber CHB may have at least one valve GT. The chamber CHB may be opened or closed by the valve GT. The target substrate SUB may be loaded into or unloaded from the chamber CHB through the valve GT.

[0072] The deposition source S includes a deposition material. The deposition material may include at least one of a metal, inorganic material, and organic material capable of sublimation or evaporation. Deposition vapor DM evaporated from the deposition source S can pass through a mask MK and can be deposited on a target substrate SUB. According to an embodiment, the deposition source S may include a luminescent material for fabricating a light-emitting element DP-OL. The luminescent material in the form of deposition vapor DM evaporated from the deposition source S can be deposited on the target substrate SUB.

[0073] The platform STG can be positioned on the deposition source S. The platform STG can support the mask assembly MA placed on the platform STG. The platform STG can be stacked with the mask frame MF of the mask assembly MA, but can also be separated from the opening OP of the mask frame MF. For example, the platform STG can be positioned outside the path of the deposition vapor DM supplied to the target substrate SUB.

[0074] In this embodiment, the mask assembly MA can be positioned above the deposition source S within the chamber CHB. The target substrate SUB can be positioned on the mask assembly MA. Deposition vapor DM, evaporated from the deposition source S, can be deposited onto the target substrate SUB in a pattern after passing through orifices HO defined in the mask MK. The mask MK and mask frame MF will be discussed in further detail below.

[0075] The movable plate PP can align the target substrate SUB onto the mask assembly MA. The movable plate PP can align the target substrate SUB by moving up, down, left, and / or right.

[0076] The movable plate PP can be equipped with an electrostatic induction object such as an electrostatic chuck ESC. The electrostatic chuck ESC can include a body portion formed of ceramic and electrodes embedded in the body portion. When a voltage is applied to the electrodes of the electrostatic chuck ESC, the electrostatic chuck ESC can induce an electrostatic force. The electrostatic chuck ESC inducing this electrostatic force can then be directed to a conductive layer included in the mask MK (see...). Figure 3B An attractive force induced by electrostatic force is applied to the CL (Cellular Clamp). The target substrate SUB can be fixed to the mask assembly MA by the electrostatic force induced by the electrostatic chuck ESC, and the target substrate SUB can be firmly attached to the mask MK. Therefore, mask MK sagging can be prevented, and the deposition process can have improved accuracy.

[0077] The target substrate SUB, on which the deposition material is deposited using a deposition apparatus DPD, can be separated from the mask assembly MA. Following the deposition process, the target substrate SUB can have a light-emitting pattern layer on its surface. The light-emitting pattern layer can be formed in the cell regions of the mask MK (see [link to image]). Figure 3A On the part corresponding to CA in the text.

[0078] A deposition process using a deposition apparatus (DPD) can form a display panel (DP) on a target substrate (SUB). The display panel DP can be separated and provided after being cut along a cut line on the target substrate (SUB). However, embodiments are not limited to this, and a single target substrate (SUB) can be formed as a single display panel DP depending on the size of the display panel DP to be manufactured.

[0079] Figure 3A A perspective view illustrating a mask assembly according to an embodiment is shown. Figure 3B It shows along Figure 3A A schematic cross-sectional view of the mask taken by line I-I'. The mask assembly MA includes at least one mask MK and a mask frame MF.

[0080] In this description, the top (or front) and bottom (or rear) surfaces of each component are parallel to the plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 represents the thickness direction of each component. The upper and lower sides, or upper and lower portions, of each component are distinguished from each other in the third direction DR3. The first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can therefore be converted to other directions. In this description, the phrase "when viewed in a plane (or in a plan view)" can mean "when viewed in the third direction DR3".

[0081] The mask frame MF can support at least one mask MK. Figure 3A An embodiment is shown in which a mask frame MF is disposed below the lower portion of the edge of at least one mask MK and supports the lower portion of the edge of at least one mask MK. However, the embodiment is not limited thereto, and the mask frame MF may be disposed on both the upper and lower portions of the edge of the mask MK to support at least one mask MK.

[0082] An opening OP may be defined within a mask frame MF. The mask frame MF may have at least one opening OP defined therein. The at least one opening OP may be a hole penetrating from the top surface of the mask frame MF to the bottom surface. The at least one opening OP may expose the bottom surface of at least one mask MK. In such a configuration, in a deposition apparatus (see...) Figure 2 In the DPD, the deposited material can pass through at least one mask MK after passing through at least one opening OP of the mask frame MF.

[0083] When viewed in a plan view, the mask frame MF can have a ring shape (or loop). Figure 3A An embodiment of a mask frame MF having a rectangular ring shape is shown, but there are no limitations on the shape of the mask frame MF. For example, the mask frame MF can have a circular ring shape, a polygonal ring shape, or any other suitable shape.

[0084] The mask frame MF can be made of metal. For example, the mask frame MF can be made of stainless steel (SUS), Invar alloy, nickel (Ni), or cobalt (Co), but there are no restrictions on the material of the mask frame MF.

[0085] At least one mask MK may be disposed on a mask frame MF. The mask assembly MA of an embodiment may include a single, integral mask MK disposed on a mask frame MF. However, the embodiment is not limited thereto, and as... Figure 5A As shown, multiple masks can be set on a mask frame MF.

[0086] When viewed in a plan view, the mask MK according to the embodiment may have at least one cell region CA and at least one peripheral region EA surrounding the at least one cell region CA. The mask MK may include apertures HO defined in the at least one cell region CA and penetrating the mask MK along a third direction DR3, which is the thickness direction of the mask MK. Apertures HO may be arranged to be spaced apart from each other in the at least one cell region CA. As an example, apertures HO are shown arranged along a first direction DR1 and a second direction DR2, but the embodiment is not limited thereto, and apertures HO may be defined with respect to the light-emitting layer of the display panel DP to be deposited (see...). Figure 1 The shape corresponds to the EML in the text.

[0087] According to an embodiment, the mask MK may have a flat plate shape extending along a first direction DR1 and a second direction DR2. In an embodiment, at least one unit region CA may include a plurality of unit regions CA, wherein the plurality of unit regions CA may be spaced apart from each other and at least one peripheral region EA is disposed between adjacent unit regions CA in the unit regions CA. For example, at least one peripheral region EA may surround each unit region CA and connect the unit regions CA to each other, and the mask MK may be formed as a single integral plate on which the unit regions CA are connected to each other.

[0088] The unit region CA can be arranged along one or both of the first direction DR1 and the second direction DR2. For example... Figure 3A As depicted in the embodiments shown, the cell region CA can be arranged in a matrix arrangement along the first direction DR1 and the second direction DR2, but the embodiments are not limited thereto, and the cell region CA can be arranged along one of the first direction DR1 and the second direction DR2.

[0089] The cell region CA can be superimposed on at least one opening OP of the mask frame MF. Figure 3ANine cell regions CA are shown, spaced apart from each other in the first direction DR1 and the second direction DR2 and superimposed on an opening OP. However, the embodiment is not limited to this, and more or fewer cell regions CA may be defined on the mask MK.

[0090] Reference Figure 3B The mask MK may include a polymer film PF, an inorganic layer IL, and a conductive layer CL. The conductive layer CL may be disposed on the surface of the polymer film PF, and the inorganic layer IL may be disposed between the polymer film PF and the conductive layer CL.

[0091] The aperture HO can penetrate the sequentially stacked conductive layer CL, inorganic layer IL, and polymer film PF on the third direction DR3. The aperture HO can be spaced apart from each other at a certain interval along one or both of the first direction DR1 and the second direction DR2.

[0092] The pores HO that penetrate each of the conductive layer CL, the inorganic layer IL, and the polymer film PF can each have a planar area that can vary based on location. For example, the pores HO can all have a planar area that decreases from the conductive layer CL to the polymer film PF.

[0093] A polymer film PF can be formed by coating or depositing a polymer resin. The polymer film PF may include at least one of polyimide (PI), polycarbonate (PC), polyethylene naphthalate (PEN), and polyethylene terephthalate (PET).

[0094] Because the mask MK comprises a polymer film PF, the mask MK can be formed as a rod extending in one direction or a plate extending in two directions, namely a first direction DR1 and a second direction DR2. Because the mask MK comprises a polymer film PF, the mask MK can be easily formed to have a large size and low weight. For example, it is possible to manufacture large-area masks suitable for forming multiple display panels at once or for forming a large-size display panel. Therefore, when the display panel manufacturing process uses a deposition apparatus including the mask MK of the embodiment (see...),... Figure 2 When using DPD (Display Panel Device) technology, the display panel manufacturing process can reduce process time and cost.

[0095] The polymer film PF can have a thickness ranging from about 3 μm to about 50 μm. When the polymer film PF has a thickness of less than about 3 μm, the mask MK will have poor durability. When the polymer film PF has a thickness of more than about 50 μm, the overall thickness of the mask MK will reduce the accuracy of the deposition process.

[0096] The conductive layer CL may include a metal or a metal oxide. The conductive layer CL may include unrestricted materials, as long as the material can be coated or deposited and can be used with an electrostatic chuck (see [link to electrostatic chuck]). Figure 2 Electrostatic forces are generated when the ESC (electrostatic discharge layer) is bonded together. For example, the conductive layer CL can include nickel (Ni), gold (Au), titanium (Ti), molybdenum (Mo), and titanium nitride (TiN). x At least one of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0097] Reference Figure 2 and Figure 3B The electrostatic force generated between the conductive layer CL and the electrostatic chuck ESC located in the deposition apparatus DPD allows the target substrate SUB to contact the mask MK and prevents the mask MK from sagging. Because mask MK sagging is prevented, the appearance of shadows caused by the mask MK can be suppressed, enabling a precise deposition process.

[0098] The conductive layer CL can have a thickness smaller than that of the polymer film PF. For example, the conductive layer CL can have a thickness of approximately 3 nm to approximately 5 μm. When the conductive layer CL is too thin, the mask MK will receive insufficient electrostatic force induced by an electrostatically inductive object such as an electrostatic chuck (ESC), and therefore the mask MK will not be able to adhere tightly to the target substrate SUB. When the conductive layer CL is too thick, the overall thickness of the mask MK will reduce the accuracy of the deposition process.

[0099] An inorganic layer IL can be disposed between the polymer film PF and the conductive layer CL, and can bond the polymer film PF and the conductive layer CL together. Each of the adhesive forces between the inorganic layer IL and the polymer film PF and between the inorganic layer IL and the conductive layer CL can be greater than the adhesive force between the polymer film PF and the conductive layer CL. Therefore, compared to a conductive layer disposed on the polymer film of a mask, the conductive layer CL of the mask MK disposed on the inorganic layer IL of the mask MK in this embodiment is more difficult to peel off.

[0100] The inorganic layer IL may comprise an inorganic material having a stronger adhesion to each of the polymer film PF and the conductive layer CL than the adhesion between the polymer film PF and the conductive layer CL. In an embodiment, the inorganic layer IL may comprise a silicon-based inorganic material. The silicon-based inorganic material may comprise any material that can be formed by chemical vapor deposition. For example, the inorganic layer IL may comprise silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following.

[0101] The inorganic layer IL can have a thickness smaller than that of the polymer film PF. When the inorganic layer IL is too thin, the polymer film PF and the conductive layer CL will have low adhesion between them. When the inorganic layer IL is too thick, the overall thickness of the mask MK will reduce the accuracy of the deposition process.

[0102] According to embodiments, the mask MK may require ultrasonic cleaning or repeated cleaning, which removes contaminants such as post-deposit materials after the mask MK has been manufactured or after it has been used in the deposition process. When the mask MK does not include the inorganic layer IL, ultrasonic cleaning or repeated cleaning may peel the conductive layer CL from the polymer film PF. Conversely, according to embodiments, since the mask MK includes the inorganic layer IL, delamination of the conductive layer CL can be avoided after ultrasonic cleaning or repeated cleaning. Therefore, the mask MK can be free from contamination and can be reused in the deposition process. Thus, the mask MK can have increased lifespan and reliability, and the production cost and material quantity of the mask MK required for the deposition process can be reduced.

[0103] Figure 4 An enlarged schematic cross-sectional view is shown, illustrating the process of targeting a substrate (see embodiment) according to an embodiment. Figure 2 The SUB in the middle is placed Figure 3A The steps for forming the light-emitting elements of the display panel are shown in the mask assembly MA. A description of each component of the mask MK can be found in the reference. Figure 3A and Figure 3B The description discussed is the same. The target substrate SUB can be used with the deposited luminescent layer (see...). Figure 1 The EML (in the middle) previously displayed panel (see Figure 1 This corresponds to a portion of the DP in the table.

[0104] A deposition process can be performed on the target substrate SUB that is in contact with the mask MK. The configuration of the contact with the mask MK can be varied depending on the stacking structure of the display panel to be manufactured. For example, in the light-emitting layer forming the display panel (see... Figure 1 In the EML step, the polymer film PF of the mask MK can contact the hole control layer HCL disposed on the pixel defining layer PDL.

[0105] The hole HO can be confined within the mask MK. Figure 4 A schematic cross-sectional view of one of the holes HO in the embodiment is shown.

[0106] The light-emitting layer of the display panel (see...) Figure 1 The EML (Emitting Microlayer) can be deposited according to a pattern. Deposited vapor DM can pass through the apertures HO of the mask MK and can be deposited in the openings PDL-OP of the pixel-defined layer PDL, resulting in the formation of an emissive layer. The emissive layer formed through one of the apertures HO (see...) Figure 1 The EML in the image can be used with the display panel (see...). Figure 1 The pixels included in DP are corresponding to the pixels.

[0107] The aperture HO can have a planar area that decreases from the conductive layer CL to the polymer film PF adjacent to the target substrate SUB. Deposited vapor DM can pass through the inclined surface forming the aperture HO and can be deposited on the target substrate SUB, so the light-emitting layer formed by the deposition of deposited vapor DM can have an overall uniform thickness.

[0108] Figure 5A A perspective view illustrating a mask assembly according to an embodiment is shown. Figure 5B It shows along with Figure 5A A schematic cross-sectional view of mask assembly MA-a taken from line II-II' corresponding to mask MK2 among the multiple masks shown. Figure 5A and Figure 5B The mask assembly MA-a shown may include, according to Figure 3A The mask components MA shown in the embodiments are substantially the same, but the number of masks included in a mask component varies. Figure 5A The accompanying diagram shows the reference numerals for some of the masks in masks MK1, MK2, and MK3. The above description also applies to... Figure 5A and Figure 5B Description of the mask MK1, MK2 or MK3 shown and the mask frame MF.

[0109] The mask frame MF can be a quadrilateral with four sides, each side extending along a first direction DR1 or a second direction DR2. At least one opening can be defined in a mask frame MF. In embodiments, at least one opening can include multiple openings. The openings can be arranged spaced apart from each other. The openings can be arranged along one or both of the first direction DR1 and the second direction DR2. Figure 5A As shown, the openings can be arranged in a matrix arrangement along the first direction DR1 and the second direction DR2.

[0110] Each opening can be a hole penetrating from the top surface of the mask frame MF to the bottom surface. The openings can be stacked corresponding to at least one unit region CA of masks MK1, MK2 and MK3, and can correspondingly expose the bottom surfaces of masks MK1, MK2 and MK3.

[0111] When viewed in a plan view, each opening may have a quadrilateral shape. However, the embodiments are not limited to this, and the shape of the opening may vary depending on the shape of the masks MK1, MK2, and MK3 corresponding to the opening arrangement.

[0112] Figure 5A A mask frame MF with nine openings is shown. However, the embodiment is not limited to this, and the number of openings in the mask frame MF can be varied depending on the size of the target substrate to be deposited.

[0113] A single mask assembly MA-a may include masks MK1, MK2, and MK3. Masks MK1, MK2, and MK3 may be respectively disposed on the mask frame MF corresponding to openings in the mask frame MF. For ease of description, in Figure 5A In the diagram, a mask MK1 is shown as if spaced apart from the mask frame MF and shown as corresponding to an opening OP1 in the opening. Another mask MK2 corresponds to another opening in the opening (see...). Figure 5B (Corresponds to OP2 in the text).

[0114] When viewed in a plan view, each of masks MK1, MK2, and MK3 may have at least one unit region CA and at least one peripheral region EA surrounding said at least one unit region CA. The at least one unit region CA defined in each of masks MK1, MK2, and MK3 may be stacked corresponding to an opening in the mask frame MF. Each of masks MK1, MK2, and MK3 may include, within its at least one unit region CA, a hole HO that penetrates mask MK1, MK2, or MK3 and is spaced apart from each other.

[0115] When viewed in a plan view, each of masks MK1, MK2, and MK3 can have a quadrilateral shape. However, there are no restrictions on the shape of masks MK1, MK2, or MK3.

[0116] The masks MK1, MK2, and MK3 included in the mask assembly MA-a may have the same area, or in another embodiment, at least one of the masks may have an area different from the areas of the other masks. The area of ​​the openings in the mask frame MF can be varied based on the areas of the masks MK1, MK2, and MK3. The areas of the masks MK1, MK2, and MK3, and the area of ​​the openings in the mask frame MF, can be varied based on the area of ​​the deposition target.

[0117] Masks MK1, MK2 and MK3 can be arranged in one or both of the first direction DR1 and the second direction DR2 to correspond to the openings of the mask frame MF. Figure 5A Nine masks MK1, MK2, and MK3 are shown, corresponding to the nine openings. However, the embodiment is not limited to this, and the number of masks MK1, MK2, and MK3 can be varied depending on the size of the target substrate to be deposited and the number of openings defined in the mask frame MF.

[0118] Reference Figure 5A and Figure 5BEach of masks MK1, MK2, and MK3 can be integrated into a mask frame MF. Each of masks MK1, MK2, and MK3 may include an integration portion BP at its integration point into the mask frame MF. When viewed in a plan view, the integration portion BP may be positioned within the peripheral region EA overlapping the mask frame MF. When viewed in a plan view, Figure 3A The mask MK and mask frame MF shown can also be combined with each other, and the part of the mask MK combined with the mask frame MF can be superimposed on the peripheral area EA.

[0119] Reference Figure 5B The bonding portion BP can be the part of the mask MK2 and the mask frame MF welded together. For example, the bonding portion BP can be formed when a welding rod disposed on the mask MK2 melts to combine with a portion of the molten mask frame MF. The bonding portion BP can include metal oxides. The bonding method between the mask MK and the mask frame MF will be discussed in further detail below.

[0120] The bonding portion BP can extend along a first direction DR1 or a second direction DR2 in the peripheral region EA of the mask MK2, and the mask frame MF can be bonded to the mask MK2. However, the embodiment is not limited to this, and the bonding portion BP can extend along the peripheral region EA of the cell region CA surrounding the mask MK2 in the first direction DR1 and the second direction DR2, and when viewed in a plan view, the bonding portion BP can have a quadrilateral ring shape.

[0121] The mask manufacturing method according to the embodiments will now be discussed. The same reference numerals are assigned to the same components discussed above, and their detailed description will be omitted when explaining the mask manufacturing method according to the embodiments.

[0122] Figure 6 A flowchart illustrating a mask manufacturing method according to an embodiment is shown. (Refer to...) Figure 6 The mask manufacturing method may include a step S10 of forming an initial polymer film, a step S20 of forming an initial inorganic layer on the initial polymer film, a step S30 of forming an initial conductive layer on the initial inorganic layer, and a step S40 of forming a plurality of holes penetrating the initial polymer film, the initial inorganic layer, and the initial conductive layer. In this description, the term "initial" may refer to the state prior to the formation of holes in the components included in the mask MK.

[0123] Figures 7A to 7D A schematic cross-sectional view illustrating a mask manufacturing method according to an embodiment is shown. Figures 8A to 8E A schematic cross-sectional view illustrating a mask manufacturing method according to an embodiment is shown. Figure 9A and Figure 9BA schematic cross-sectional view illustrating a mask manufacturing method according to an embodiment is shown.

[0124] Figure 7A A cross-sectional view is shown illustrating the steps of sequentially stacking an initial polymer film PF', an initial inorganic layer IL', and an initial conductive layer CL'. The initial polymer film PF' can be formed by coating a polymer resin onto a glass layer GL'. The initial polymer film PF' can be formed on the glass layer GL' in a plate shape. The polymer resin may include at least one selected from polyimide, polycarbonate, polyethylene naphthalate, and polyethylene terephthalate.

[0125] An initial inorganic layer IL' can be formed or deposited on an initial polymer film PF'. The initial inorganic layer IL' can be formed to cover the surface of the initial polymer film PF'. The initial inorganic layer IL' can be formed by a deposition process such as chemical vapor deposition (CVD), and the formation of the initial inorganic layer IL' includes the deposition of a silicon-based inorganic material. For example, the silicon-based inorganic material can include at least one of silicon oxide and silicon nitride.

[0126] An initial conductive layer CL' can be formed or deposited on the initial inorganic layer IL'. The initial conductive layer CL' can be formed to cover the surface of the initial inorganic layer IL'. The initial conductive layer CL' can be formed from a metal-containing deposition material by deposition processes such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD). For example, the initial conductive layer CL' can include nickel (Ni), gold (Au), titanium (Ti), molybdenum (Mo), titanium nitride (TiN). x At least one of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0127] A mask can be fabricated by forming a hole HO that penetrates the sequentially stacked initial polymer film PF', initial inorganic layer IL', and initial conductive layer CL' (see [link to documentation]). Figure 7C (MK in the image). Holes HO can be formed by laser irradiation or etching.

[0128] Figure 7B A schematic cross-sectional view is shown illustrating the step of irradiating a laser LS1 to form a hole HO. With the initial polymer film PF', the initial inorganic layer IL', and the initial conductive layer CL' stacked sequentially, the laser LS1 can be irradiated onto the location where the hole HO is desired to form the hole HO. The laser LS1 can simultaneously penetrate the initial polymer film PF', the initial inorganic layer IL', and the initial conductive layer CL'.

[0129] Compared to processes using lasers to process alloys, the process of using a laser LS1 to process the initial polymer film PF' to form the aperture HO can reduce working time and the amount of dust generated during processing. This reduces or prevents dust generated during processing from adhering to the aperture processing surface. Therefore, the mask manufacturing method of the embodiment can provide a mask that reduces manufacturing time and improves reliability.

[0130] The wavelength range of the laser LS1 can include the wavelength range of ultraviolet light. For example, the laser LS1 can have a wavelength equal to or less than about 400 nm. However, the wavelength range of ultraviolet light is not limited to the example above. When the laser LS1 has too short a wavelength or too strong an intensity, it will damage the stacked structure irradiated by the laser LS1. When the laser LS1 has too long a wavelength or too weak an intensity, it will be difficult to form a hole HO that completely penetrates the stacked structure.

[0131] When viewed in a plan view, the holes HO can be formed in a regular arrangement. For example, in a plan view, the holes HO can be formed in a pattern. The holes HO can be arranged along a first direction DR1 and a second direction DR2, and Figure 7B A schematic cross-sectional view illustrating the steps of forming a hole HO arranged along the first direction DR1 is shown by way of example.

[0132] Holes HO can be formed by irradiation with a single laser beam LS1. However, the embodiments are not limited to this, and multiple laser beams can be irradiated simultaneously to form multiple holes HO at the same time.

[0133] Figure 7C A cross-sectional view of a mask MK formed on a glass layer GL' is shown. Apertures HO can be arranged at intervals along a first direction DR1 and a second direction DR2, and the pattern formed by the apertures HO can correspond to the pattern of the deposited layer to be deposited using the mask MK.

[0134] Figure 7D A cross-section of the mask MK, ultimately formed by separating the glass layer GL' and the mask MK from each other, is shown. The mask MK can be fabricated in which a polymer film PF, an inorganic layer IL, and a conductive layer CL are sequentially stacked, with an aperture HO penetrating the polymer film PF, the inorganic layer IL, and the conductive layer CL. The fabricated mask MK can be ultrasonically cleaned to remove contaminants generated during the manufacturing process. The inorganic layer IL, disposed between the polymer film PF and the conductive layer CL, prevents the conductive layer CL from delaminating due to ultrasonic cleaning.

[0135] Figures 8A to 8E A schematic cross-sectional view of a mask manufacturing method according to an embodiment is shown, illustrating the step of forming holes using an etching process. The same reference numerals are assigned to the same components discussed above, and in reference... Figures 8A to 8E Detailed descriptions of the mask manufacturing method according to the embodiments will be omitted when explaining the method.

[0136] Reference Figures 8A to 8E The aperture HO can be formed by an etching process, which correspondingly etches the initial conductive layer CL', the initial inorganic layer IL', and the initial polymer film PF'. In an embodiment, step S40 of forming the aperture HO may include a first etching step, a second etching step, and a third etching step.

[0137] Reference Figure 8A In such Figure 7A As shown in the state where the initial conductive layer CL', the initial inorganic layer IL', and the initial polymer film PF' are stacked sequentially, a pre-patterned photoresist PR' can be applied to the initial conductive layer CL'. The photoresist PR' may include a photosensitive material.

[0138] A pattern mask PM can be applied to the photoresist PR' to pattern the photoresist PR'. The pattern mask PM can be illuminated with light LL to pattern the photoresist PR' to correspond to the pattern of the pattern mask PM. The patterned photoresist PR can be used as an etching mask in the step of etching the initial conductive layer CL'.

[0139] Reference Figure 8B A patterned photoresist PR can be provided with an etchant ET1 coated thereon to form a first initial hole HO-a penetrating the initial conductive layer CL'. The first etching step in which the initial conductive layer CL' is etched can be a wet etching step using etchant ET1, but the embodiments are not limited thereto, and the first etching step can be a dry etching step using plasma gas.

[0140] The initial conductive layer CL' can be patterned to correspond to the patterned photoresist PR. The patterned photoresist PR can partially expose the initial conductive layer CL', and the etchant ET1 can etch the exposed portion of the initial conductive layer CL'. The etching process of the initial conductive layer CL' can form a first initial via HO-a that penetrates the initial conductive layer CL'.

[0141] Reference Figure 8C After forming the conductive layer CL in which the first initial aperture HO-a is formed, the patterned photoresist PR can be removed. The conductive layer CL in which the first initial aperture HO-a is formed can be used as an etching mask in the step of etching the initial inorganic layer IL' and the initial polymer film PF'.

[0142] The conductive layer CL, to which the first initial aperture HO-a is formed, can be supplied with a first plasma gas ET2 to form a second initial aperture HO-b penetrating the initial inorganic layer IL'. The second etching step, in which the initial inorganic layer IL' is etched, can be a dry etching step using the first plasma gas ET2.

[0143] The initial inorganic layer IL' can be patterned to correspond to the pattern of the conductive layer CL in which the first initial via HO-a is formed. The conductive layer CL with the first initial via HO-a can partially expose the top surface of the initial inorganic layer IL', and the first plasma gas ET2 can etch the exposed portion of the initial inorganic layer IL'. The etching process of the initial inorganic layer IL' can form a second initial via HO-b superimposed on the first initial via HO-a. Therefore, the second initial via HO-b can be formed to penetrate both the conductive layer CL and the inorganic layer IL.

[0144] Reference Figure 8D The conductive layer CL and inorganic layer IL, in which the second initial aperture HO-b is formed, can be used as an etching mask in the step of etching the initial polymer film PF'. The conductive layer CL can be provided with a second plasma gas ET3 sprayed thereon to form aperture HO penetrating the initial polymer film PF'. Aperture HO can be formed to overlap with the first initial aperture HO-a and the second initial aperture HO-b, and can correspond to the aperture HO defined in the mask MK that penetrates the aforementioned polymer film PF, inorganic layer IL and conductive layer CL.

[0145] The third etching step, in which the initial polymer film PF' is etched, can be a dry etching step using a second plasma gas ET3. The second plasma gas ET3 used to etch the initial polymer film PF' can be different from the first plasma gas ET2 used to etch the initial inorganic layer IL'.

[0146] The conductive layer CL and the inorganic layer IL can partially expose the top surface of the initial polymer film PF', and the second plasma gas ET3 can etch the exposed portion of the initial polymer film PF'. The etching process of the initial polymer film PF' can form a hole HO corresponding to the pattern of the conductive layer CL and the inorganic layer IL in which the second initial hole HO-b is formed.

[0147] Figure 8E A schematic cross-sectional view of a mask MK in which holes are formed by an etching step is shown. Holes HO can be arranged at intervals along a first direction DR1 and a second direction DR2, corresponding to the patterned photoresist PR pattern. After forming the holes HO by the etching process, the glass layer GL' can be removed, thus finally producing a mask MK. Figure 7D The mask MK shown in the image.

[0148] Figure 9A and Figure 9B A schematic cross-sectional view is shown illustrating the step in which an etching process is used to form a hole. (Refer to...) Figure 9A and Figure 9B The hole HO can be formed by a first etching step in which the initial conductive layer CL' is etched and a fourth etching step in which the initial inorganic layer IL' and the initial polymer film PF' are etched simultaneously.

[0149] Reference Figure 8A and Figure 8B The same principles discussed apply to the first etching step in which the initial conductive layer CL' is etched. After the conductive layer CL is formed, the patterned photoresist PR can be removed. (See reference...) Figure 9A The conductive layer CL, in which the first initial hole HO-a is formed, can be used as an etching mask in the fourth etching step of etching the initial inorganic layer IL' and the initial polymer film PF'.

[0150] The conductive layer CL, on which the first initial hole HO-a is formed, can be supplied with a third plasma gas ET4 injected thereon to form a hole HO that penetrates the initial inorganic layer IL' and the initial polymer film PF'. The hole HO can be formed to overlap with the first initial hole HO-a and can correspond to the hole HO defined in the mask MK that penetrates the polymer film PF, the inorganic layer IL and the conductive layer CL discussed above.

[0151] The fourth etching step, which etches the initial inorganic layer IL' and the initial polymer film PF', can be a dry etching step using the third plasma gas ET4. The same third plasma gas ET4 can be used to simultaneously etch the initial inorganic layer IL' and the initial polymer film PF'.

[0152] The initial inorganic layer IL' and the initial polymer film PF' can be patterned to correspond to the pattern of the conductive layer CL in which the first initial hole HO-a is formed. The conductive layer CL in which the first initial hole HO-a is formed can partially expose the top surface of the initial inorganic layer IL', and the third plasma gas ET4 can etch the exposed portion of the initial inorganic layer IL' and the initial polymer film PF' disposed beneath it. The hole HO superimposed on the first initial hole HO-a can be formed by a process that simultaneously etches the initial inorganic layer IL' and the initial polymer film PF'.

[0153] Whether a material is etched, and to what extent, depends on the type of plasma gas, exposure time, density, and temperature. For example... Figure 8C and Figure 8D As shown, the initial inorganic layer IL' and the initial polymer film PF' can be precisely etched using different plasma gases. However, the embodiments are not limited to this, as... Figure 9A As shown, the same plasma gas can be used to simultaneously etch the initial inorganic layer IL' and the initial polymer film PF'. Simultaneous etching can reduce manufacturing costs and the number of process steps.

[0154] Figure 9B A schematic cross-sectional view of a mask MK is shown, in which vias HO are formed by simultaneously etching an initial conductive layer CL' and an initial inorganic layer IL' and an initial polymer film PF'. The vias HO can be arranged at intervals along a first direction DR1 and a second direction DR2, corresponding to a patterned photoresist PR. After forming the vias HO by the etching process, the glass layer GL' can be removed to finally fabricate a material such as... Figure 7D The mask MK is shown.

[0155] Figures 10A to 10C A schematic cross-sectional view illustrating a method for manufacturing a mask assembly according to an embodiment is shown. The same reference numerals are assigned to the same components discussed above, and in reference... Figures 10A to 10C Detailed descriptions of the mask assembly manufacturing method in the embodiments will be omitted. For ease of description, Figures 10A to 10C The dashed line representing the outer region EA of the mask MK is shown. When viewed in a plan view, the outer region EA is superimposed on the mask frame MF.

[0156] The mask assembly MA of this embodiment can be formed by combining the mask MK with the mask frame MF. (See reference...) Figure 10A The fabricated mask MK can be configured to allow its conductive layer CL to lie on the top surface of the mask frame MF. The mask MK can be disposed on the mask frame MF to allow the aperture HO defined in the mask MK to overlap with the opening OP of the mask frame MF.

[0157] Although not shown, tension can be applied to the mask MK before it is set on the mask frame MF. A clamp included in the tensioning device can provide tension to the mask MK in one or both directions, namely a first direction DR1 and a second direction DR2, away from the center of the mask MK.

[0158] Reference Figure 10B The welding electrode WB can be disposed in the peripheral region EA of the mask MK, which overlaps with the mask frame MF. The welding electrode WB can be a strip extending in one direction. For example, the welding electrode WB can be disposed around the cell region CA of the mask MK and overlapped with the peripheral region EA of the mask MK. However, the embodiments are not limited to this.

[0159] Welding electrodes (WB) can include metals. For example, welding electrodes (WB) can include stainless steel (SUS), Invar alloy, nickel (Ni), or cobalt (Co).

[0160] The welding electrode WB can be irradiated and melted using a laser LS2. The mask frame MF can have a partially molten portion on its top surface where it contacts the mask MK, and the molten welding electrode WB can be bonded to the partially molten portion of the mask frame MF. The molten welding electrode WB can bond the mask MK and the mask frame MF together.

[0161] Reference Figure 10C During the welding process, the molten welding electrode WB can penetrate the polymer film PF, inorganic layer IL, and conductive layer CL of the mask MK, and can contact and bond with a partially molten portion of the mask frame MF, thereby forming a bonding portion BP of the mask MK to the mask frame MF. The bonding portion BP may include a metal oxide. (See reference...) Figure 5B The description of the discussion can also be applied to the combined part of BP.

[0162] Because the mask according to the embodiment comprises a polymer film, the mask can be easily configured to have a small weight and large size and can be suitable for depositing large-area target substrates. Because the mask of the embodiment includes a conductive layer, mask sagging can be prevented. Because the mask of the embodiment includes an inorganic layer for attaching the polymer film to the conductive layer, delamination of the conductive layer due to repeated cleaning processes can be prevented. Therefore, the mask of the embodiment and the mask assembly including the mask can improve lifespan and reliability. The mask manufacturing method according to the embodiment can provide a mask with improved lifespan and reliability without the installation of additional facilities.

[0163] When cleaning the masks used in the deposition process for manufacturing display panels, it is possible to avoid delamination between the mask components.

[0164] Embodiments have been disclosed herein, and although terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, unless otherwise specifically stated, features, characteristics, and / or elements described in connection with the embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the disclosure set forth in the appended claims.

Claims

1. A mask, the mask comprising: A polymer film, wherein at least one unit region and at least one peripheral region are defined in the polymer film, the at least one peripheral region surrounding the at least one unit region; A conductive layer is disposed on the polymer film, the conductive layer comprising at least one of nickel, gold, titanium, molybdenum, titanium nitride, indium tin oxide, and indium zinc oxide; An inorganic layer is disposed between the polymer film and the conductive layer, wherein the inorganic layer comprises at least one of silicon oxide and silicon nitride; as well as Multiple pores penetrate the polymer film, the conductive layer, and the inorganic layer, and are superimposed on the at least one unit region in a planar view. Each of the plurality of pores has a planar area decreasing from the conductive layer to the polymer film. The mask is configured such that the conductive layer contacts a mask frame that supports the mask. The polymer film comprises at least one of polyimide, polycarbonate, polyethylene naphthalate, and polyethylene terephthalate. The thickness of the polymer film is in the range of 3 μm to 50 μm.

2. The mask according to claim 1, wherein, The thickness of the inorganic layer is less than the thickness of the polymer film.

3. The mask according to claim 1, wherein, The at least one unit region includes multiple unit regions. The plurality of unit regions are spaced apart from each other, and The at least one peripheral region is disposed between adjacent unit regions among the plurality of unit regions.

4. A mask assembly, the mask assembly comprising: A mask frame, wherein at least one opening is defined in the mask frame; as well as At least one mask, corresponding to the at least one opening in the mask frame, is disposed on the mask frame. Wherein, the at least one mask includes: A polymer film, wherein at least one unit region and at least one peripheral region are defined in the polymer film, the at least one peripheral region surrounding the at least one unit region; A conductive layer is disposed on the polymer film, the conductive layer comprising at least one of nickel, gold, titanium, molybdenum, titanium nitride, indium tin oxide, and indium zinc oxide; An inorganic layer, disposed between the polymer film and the conductive layer, the inorganic layer comprising at least one of silicon oxide and silicon nitride; and Multiple pores penetrate the polymer film, the conductive layer, and the inorganic layer, and are superimposed on the at least one unit region in a planar view. Each of the plurality of pores has a planar area decreasing from the conductive layer to the polymer film. The conductive layer contacts the mask frame. The polymer film comprises at least one of polyimide, polycarbonate, polyethylene naphthalate, and polyethylene terephthalate. The thickness of the polymer film is in the range of 3 μm to 50 μm.

5. The mask assembly according to claim 4, wherein, The at least one unit region includes multiple unit regions. The multiple unit regions are spaced apart from each other. The at least one peripheral region is disposed between adjacent unit regions among the plurality of unit regions, and In the plan view, the plurality of unit regions overlap with the at least one opening.

6. The mask assembly according to claim 4, wherein, The at least one opening includes multiple openings. The at least one mask includes multiple masks, and The plurality of masks are disposed on the mask frame corresponding to the plurality of openings.

7. The mask assembly according to claim 4, wherein, A portion of the at least one mask is incorporated into the mask frame to overlap with the at least one peripheral region in a plan view, and The at least one mask incorporated into the portion of the mask frame comprises a metal oxide.

8. A method for manufacturing a mask, wherein the mask is a mask according to any one of claims 1 to 3, the method comprising: Formation of the initial polymer film; An initial inorganic layer is formed on the initial polymer film; An initial conductive layer is formed on the initial inorganic layer; as well as Multiple pores are formed that penetrate the initial polymer film, the initial inorganic layer, and the initial conductive layer.

9. The mask manufacturing method according to claim 8, wherein, The initial inorganic layer is formed by chemical vapor deposition.

10. The mask manufacturing method according to claim 8, wherein, The formation of the plurality of pores includes irradiating a laser to simultaneously penetrate the initial polymer film, the initial inorganic layer, and the initial conductive layer.

11. The mask manufacturing method according to claim 10, wherein, The wavelength range of the laser includes the wavelength range of ultraviolet light.

12. The mask manufacturing method according to claim 10, wherein, The formation of the plurality of holes includes irradiating the laser to form the plurality of holes in a patterned planar view.

13. The mask manufacturing method according to claim 8, wherein, The formation of the plurality of holes includes: A patterned photoresist is formed on the initial conductive layer; A plurality of first initial holes penetrating the initial conductive layer are formed by a first etching step of etching the initial conductive layer; Remove the photoresist; A second etching step, which involves etching the initial inorganic layer, forms a plurality of second initial holes that penetrate the initial inorganic layer and overlap with the plurality of first initial holes; and The plurality of holes are formed by a third etching step of etching the initial polymer film, which penetrates the initial polymer film and overlaps with the plurality of second initial holes.

14. The mask manufacturing method according to claim 8, wherein, The formation of the plurality of holes includes: A patterned photoresist is formed on the initial conductive layer; A plurality of first initial holes penetrating the initial conductive layer are formed by a first etching step of etching the initial conductive layer; Remove the photoresist; and The plurality of holes are formed by a second etching step that simultaneously etches the initial inorganic layer and the initial polymer film, and are superimposed on the plurality of first initial holes.

15. The mask manufacturing method according to claim 13, wherein, The first etching step includes a wet etching step or a dry etching step, and Each of the second and third etching steps includes a dry etching step.

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