radar sensor

Abstract

A radar sensor having at least one transmitting antenna and having at least one receiving antenna and having a radar SoC, the radar SoC comprising a radar generation circuit portion and a microcontroller circuit portion for the operation of the radar sensor and the processing of received radar data, characterized in that the radar SoC has an inter-processor communication interface and at least one further radar SoC having an inter-processor communication interface is provided, which communicates with the radar SoC via the inter-processor communication interface, wherein in the further radar SoC only the microcontroller circuit portion is functionally used for processing radar data, whereas the radar generation circuit portion is not functionally used.

Description

Technical Field

[0001] The present invention relates to a radar sensor having at least one transmitting antenna and at least one receiving antenna and having a radar SoC (System-on-a-Chip), comprising a radar generation circuit section and a microcontroller circuit section for operating the radar sensor and processing received radar data. Background Technology

[0002] Radar sensors are used to enable comfort features (such as so-called adaptive cruise control, which adjusts vehicle speed based on distance to the vehicle ahead) or safety features (such as emergency braking assist). The main advantage of such radar sensors is that they involve the direct measurement of physical parameters, rather than interpreting images recorded, for example, by means of a camera.

[0003] A radar sensor transmits a high-frequency radar beam through an antenna or antenna structure and receives the beam reflected at an object. The detected object can be stationary or moving. Using the received radar beam, the distance and direction (angle) to the object can be calculated. Furthermore, the relative velocity between the object and the radar sensor can be calculated. Typical radar sensors operate in the frequency range between 76 and 81 GHz.

[0004] In current radar sensors, two modules are essentially used: one for generating the radar signal and the other for processing the received signal. The so-called MMIC (Microwave Monolithic Integrated Circuit) consists of the radar generation circuitry and the microcontroller circuitry, which has dedicated hardware for processing the radar data, such as an FFT accelerator or a DSP. The software necessary for operating the radar sensor and processing the radar data is implemented in the microcontroller circuitry. This part is also known as the sensing technology part. Additionally, as an option, further software can be implemented, such as incorporating data from other sensors to enable better object detection, a process known as sensor fusion. Another option is software provided by the vehicle manufacturer, for example, when these radar sensors are used in vehicles, for vehicle management purposes.

[0005] This radar sensor is implemented as a highly integrated module in RFCMOS technology. In particular, it allows for the integration of microcontroller circuitry into the radar generation circuitry, i.e., the MMIC, or implementation on a single chip. This type of module is called a radar SoC.

[0006] A significant advantage of high integration lies in low-cost modules, as it eliminates the overhead of using a secondary chip. This reduces so-called packaging costs, testing costs, board area, and the overhead on printed circuit boards (PRBs) for wiring the high-speed interface between the radar generation circuitry (MMIC) and the microcontroller circuitry (μC). However, radar SoCs are limited in their content. Silicon area or package size is limited due to the necessary high-frequency characteristics; in particular, a large amount of content in the digital section can interfere with sensitive high-frequency components. Furthermore, power consumption is a limiting parameter. For this reason, especially in terms of computing power, an upper limit is given by physical boundary conditions. Summary of the Invention

[0007] Therefore, this invention is based on the objective of providing the possibility of implementing large digital components in radar SoCs.

[0008] According to the solution configuration of the present invention, the radar SoC has an inter-processor communication interface (Interprozessor-Kommunikationsschnittstelle), and at least one additional radar SoC having an inter-processor communication interface is provided, the at least one additional radar SoC communicating with the first radar SoC through the inter-processor communication interface, wherein, in the additional radar SoC, only the microcontroller circuit portion is used functionally to process radar data, however, the radar generation circuit portion is not used functionally.

[0009] The solution according to the invention improves computing power without incurring significant overhead in developing additional chips. According to the invention, the radar SoC is extended with an additional digital interface that enables communication with other radar SoCs. This interface is hereinafter referred to as the inter-processor communication interface. At least two radar SoCs are then integrated into a radar sensor, their microcontroller circuitry communicating with each other via the inter-processor communication interface. In the additional radar SoC, only the microcontroller circuitry is functionally used to process radar data; however, the radar generation circuitry is not functionally used. This functional omission means, on the one hand, saving additional components, such as those necessary for voltage supply in the high-frequency section. Furthermore, high-frequency testing can be omitted, or components that do not meet the required specifications in the high-frequency section can be used without problems in the digital section, i.e., the microcontroller circuitry.

[0010] This makes it possible to increase computing power without having to develop additional chips at high cost. It also eliminates the drawback of limited computing power for implementing optional software. In other words, it's conceivable to develop larger SoCs at high cost. However, in addition to the higher cost of the chip, additional overhead will accumulate, especially for ensuring high-frequency characteristics and the reliability of soldered connections. This will increase the manufacturing cost of such radar SoCs, which is particularly disadvantageous when the number of units is small. The same applies when separate, dedicated microcontrollers are used. In this case, a considerable development overhead must be provided for the expected low number of units, especially in terms of the computer architecture to be developed, and therefore also in terms of the software to be developed for running the system, drivers, etc.

[0011] According to an advantageous configuration, not only is one additional radar SoC with an inter-processor communication interface provided, but also more than one additional radar SoC with an inter-processor communication interface is provided, and the more than one additional radar SoC communicates with each other through the inter-processor communication interface.

[0012] In one configuration, radar SoCs are connected in series, and each radar SoC inserted between two radar SoCs implements a switch function, transmitting data to / from the adjacent radar SoC. This series connection allows the computational overhead to be distributed across multiple microcontroller circuit sections of the radar SoC.

[0013] In another aspect of the invention, the radar SoCs communicate with each other via a bus system through their inter-processor communication interfaces. The solution also includes a cascaded connection of multiple radar SoCs.

[0014] In another advantageous configuration, radar SoCs communicate with each other in a star configuration via their inter-processor communication interface.

[0015] Here, a star-shaped layout can be configured with a central switch.

[0016] This also allows for flexible configuration of the computational load. For example, additional computational overhead for optional software can be allocated to a separate radar SoC, while the core tasks, i.e., sensing tasks, can be redistributed to other radar SoCs. Purely in principle, the following variations are conceivable:

[0017] - Distribute all computational overhead to all radar SoCs, including radar data processing;

[0018] - Distribute along the functional action chain (Wirkkette): Process radar data in a radar SoC equipped with a high-frequency component, and process additional processing steps in another radar SoC, so as to also reduce the computational overhead of communication.

[0019] - The allocation can be configured based on the software supply: for example, optional software from the OEM can be implemented on its own radar SoC.

[0020] Based on the division of software functions, the necessary or appropriate data rate for the communication interface is determined. The envisioned interface is:

[0021] -SPI, this interface is typically used for transfer rates up to 40Mbps;

[0022] -LVDS, this interface is typically used for transmission rates of >=400Mbps;

[0023] - Ethernet, this interface is used for data transfer rates between 100Mbps and 1000Mbps; and

[0024] -PCIe, this interface is used for data transfer rates of >=2.5Gbps.

[0025] Furthermore, according to another aspect of the present invention, the inter-processor communication interface is configured as a wireless communication interface (WLAN).

[0026] To facilitate connectivity with external devices, the radar SoC can be configured with external communication interfaces in an advantageous configuration. In this way, connections to these external communication interfaces can also be allocated through the radar SoC. This increases the maximum number of external communication interfaces without requiring a single radar SoC to provide significant additional computational overhead. It also increases the number of possible cooperative control devices, such as those used for sensor data fusion. Attached Figure Description

[0027] Embodiments of the invention are shown in the accompanying drawings and described in more detail in the following description.

[0028] Figure 1 shows the circuitry of a radar sensor as known from the prior art;

[0029] Figure 2 illustrates a radar SoC known from the prior art;

[0030] Figure 3 An embodiment of a radar sensor according to the present invention is shown;

[0031] Figure 4 Another embodiment of a radar SoC of a radar sensor according to the present invention is shown;

[0032] Figure 5 Another embodiment of a radar SoC of a radar sensor according to the present invention is shown;

[0033] Figure 6 Another embodiment of a radar SoC of a radar sensor according to the present invention is shown. Detailed Implementation

[0034] Figure 1 schematically illustrates the circuitry of a radar sensor known from the prior art. This circuitry includes a radar generation circuitry section 10 and a microcontroller circuitry section 20, the radar generation circuitry section also referred to as a microwave monolithic integrated circuit (MMIC). The radar generation circuitry section 10 includes a receiver 11, a transceiver 12, a baseband, an ADC circuitry section 15, and a synthesizer 17. A first antenna 1 is coupled to the receiver 11, and a second antenna 2 is coupled to the transceiver 12. The radar generation circuitry section 10 is used for radar generation, and the microcontroller circuitry section 20 is used for calculating the signals output by the radar generation circuitry section 10, these signals hereinafter referred to as radar data.

[0035] The microcontroller circuit section 20 includes a circuit section 21 for performing Fast Fourier Transform (FFT), a storage module 22, and various computer cores 24. An interface 27 is used for communication with external devices. Radar data is provided from the baseband and ADC circuit section 15 of the radar generation circuit section 10 to the circuit section 21, where the FFT is implemented. The microcontroller 20 contains dedicated hardware for processing the radar data, namely the circuit section 21 or other (not shown) circuit sections, such as a DSP. The software necessary for the operation of the radar sensor and the processing of radar data is implemented in the microcontroller circuit section 20. The radar generation circuit section 10 is also referred to as the sensing technology section. The microcontroller circuit section 20 is also simply referred to as a microcontroller (MC). As an option, additional software can be implemented in the microcontroller circuit section 20, such as processing data from other sensors and incorporating it into the result to achieve better object detection. This is also known as sensor fusion. Furthermore, additional options and software sections, such as those provided by vehicle manufacturers, can be implemented for vehicle management, etc. Vehicle use is an important application area for this type of sensor.

[0036] The radar sensor known from the prior art, as shown in Figure 1, has two individual circuit sections implemented as a single chip. With the new RFCMOS technology, due to further high integration, the two circuit sections (i.e., radar generation circuit section 10 and microcontroller circuit section 20) can be combined into a single chip, commonly referred to as a radar SoC or simply SoC. Here, the acronym SoC stands for "System-On-a-Chip". A significant advantage of higher integration is lower-cost modules, as the overhead of additional chips is eliminated. This overhead includes packaging costs, testing costs; furthermore, additional board space must be allocated, and additional wiring overhead is incurred for the high-speed interface between the radar generation circuit section and the microcontroller circuit section. This radar SoC is shown in Figure 2 and is indicated by reference numeral 100. In this illustration, the same components are indicated by the same reference numerals as in Figure 1, and their description is referenced above.

[0037] This radar SoC 100 is particularly advantageous in terms of lower cost because it eliminates the need for a second chip. However, limitations in computing power restrict the implementation of optional software. That is, purely in principle, it is possible to develop a larger SoC with higher overhead. Then, in addition to the higher cost of the chip, additional overhead is required to ensure, in particular, the reliability of high-frequency characteristics and soldered connections. This overhead is unacceptable in many cases, especially when the number of such SoCs is small. The same situation, with necessary modifications, also applies when only a separate SoC with a microcontroller circuit section is provided, i.e., without a radar generation circuit section. For this reason, according to the present invention, the radar SoC is provided with an inter-processor communication interface 40, which enables the radar SoC to communicate with other radar SoCs of the same type, such as those in... Figure 3 As shown in the diagram. Figure 3In the upper part of the accompanying drawings, radar SoC 101 is shown, where the same elements are again indicated by the same reference numerals as in Figures 2 and 1, thus referring to a detailed explanation of these figures in its description. The lower image portion shows a second radar SoC 201, which also has an inter-processor communication interface 40 that allows the second radar SoC to communicate with radar SoC 101. In the second radar SoC 201, circuit elements 11, 15, 12, and 17 belonging to the radar generation section are drawn only with dashed lines to indicate that these parts are not functionally used in the second radar SoC. This saves additional components, such as those originally necessary for the voltage supply of the high-frequency section. Furthermore, it saves on testing of the high-frequency section during chip manufacturing, or allows the use of parts that do not meet high-frequency specifications but can be easily used in the microcontroller circuitry. Therefore, in Figure 3 In the illustrated radar SoC arrangement, the first radar SoC 101 controls antennas 1 and 2, transmits and receives radar signals, and processes radar data in the microcontroller circuitry. Further data processing is performed in the second radar SoC 201, which communicates with the first radar SoC 101 via an inter-processor communication interface 40. While further processing of the radar data can occur here, additional software programs can also be used, such as those incorporating data from other sensors to achieve better object detection. This enables sensor fusion.

[0038] In addition to Figure 3 In addition to the configuration shown, more than one additional radar SoC, namely a third radar SoC 301 or other radar SoCs (not shown), can be configured. These radar SoCs can communicate with each other through an inter-processor communication interface. Furthermore, communication between radar SoCs 101, 201, 301 and possible other radar SoCs can be configured via bus 400.

[0039] exist Figure 4 In the arrangement shown, communication occurs via an inter-processor communication interface, such as through multiple point-to-point connections and a switch function within the chip. Figure 4 In the arrangement shown, radar SoC 201 transmits data that should be transferred between radar SoC 101 and radar SoC 301 from one interface to another.

[0040] exist Figure 5 In the arrangement shown, the transmission is performed via bus 400.

[0041] Another configuration is in Figure 6As shown in the diagram, radar SoCs 101, 201, and 301 are arranged in a star configuration. Communication is conducted through a central switch 500. This switch can also be omitted.

[0042] The computational load can be flexibly configured in all the variations shown. Additional computing power can be allocated, i.e., handling additional optional software through separate radar SoCs 201 and 301. However, the primary tasks, i.e., sensing technology tasks, can also be allocated to radar SoC 101 to a certain extent. The following variations are possible:

[0043] - Distribute the entire computational overhead across all radar SoCs, including radar data processing.

[0044] - The distribution proceeds along the functional chain, including: processing radar data in a radar SoC equipped with a high-frequency component, which is labeled 101 in the illustration. Further processing steps are performed in other radar SoCs to reduce communication overhead. In the illustrations shown, these are radar SoCs 201 and 301.

[0045] - Allocation depends on software supply: Optional software from the OEM is processed on its own radar SoC, such as the radar SoC301.

[0046] Depending on the software functionality, the necessary or appropriate data rates for communication interfaces differ. Available interfaces are:

[0047] -SPI, which is typically used for data transfer rates up to 40Mbps;

[0048] -LVDS, which is typically used for data transfer rates of >=400Mbps;

[0049] - Ethernet, which is typically used in the range of 100Mbps to 1000Mbps; and

[0050] -PCIe, which is typically used for data transfer rates of >=2.5Gbps.

[0051] This list is merely illustrative and is neither complete nor definitive. Furthermore, wireless communication via wireless networks (WLANs) can also be envisioned.

[0052] External communication interface connections can also be allocated through the radar SoC. This increases the maximum number of external communication interfaces without requiring a separate radar SoC to handle the increased computational overhead. It also increases the number of possible cooperative control devices, such as other sensors used for sensor data fusion.

Claims

1. A radar sensor having at least one transmitting antenna (2) and at least one receiving antenna (1) and having a radar SoC (100, 101, 201, 301), the radar SoC including a radar generation circuit section (10) and a microcontroller circuit section (20) for operation of the radar sensor and processing of received radar data, Its features are, The radar SoC (100, 101, 201, 301) has an inter-processor communication interface (40), and at least one other radar SoC (100, 101, 201, 301) having an inter-processor communication interface (40) is provided, the at least one other radar SoC communicating with the radar SoC (100, 101, 201, 301) through the inter-processor communication interface (40), wherein, in the other radar SoC (100, 101, 201, 301), only the microcontroller circuit section (21, 22, 24, 27) is used functionally to process radar data, however, the radar generation circuit section (11, 12, 15, 17) is not used functionally.

2. The radar sensor according to claim 1, characterized in that, More than one additional radar SoC (100, 101, 201, 301) is provided, which communicate with each other through the inter-processor communication interface (40).

3. The radar sensor according to claim 2, characterized in that, The radar SoCs (100, 101, 201, 301) are connected in series, and the radar SoCs connected between two radar SoCs (100, 101, 201, 301) respectively implement the switching function, which transmits data from / to the adjacent radar SoC (100, 101, 201, 301).

4. The radar sensor according to claim 2, characterized in that, The radar SoCs (100, 101, 201, 301) communicate with each other via a bus system (400) through their inter-processor communication interface (40).

5. The radar sensor according to claim 2, characterized in that, The radar SoCs (100, 101, 201, 301) communicate with each other in a star configuration via their inter-processor communication interface (40).

6. The radar sensor according to claim 5, wherein the star-shaped arrangement has a central switch (500).

7. The radar sensor according to any one of the preceding claims, characterized in that, The inter-processor communication interface (40) is one of the following interfaces: SPI, LVDS, Ethernet PCIe.

8. The radar sensor according to any one of claims 1 to 6, characterized in that, The inter-processor communication interface (40) is a wireless communication interface.

9. The radar sensor according to any one of the preceding claims, characterized in that, The radar SoC (100, 101, 201, 301) has an external communication interface for communicating with external devices.

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