Array substrate and manufacturing method thereof, and display device

Abstract

The present disclosure provides an array substrate and a manufacturing method thereof, and a display device, and relates to the field of display technology. The array substrate includes a plurality of data lines and a plurality of sub-pixels, and at least one sub-pixel includes: a first insulating layer, located on one side of a first substrate; a gate, located between the first substrate and the first insulating layer; an active layer, located on the side of the first insulating layer away from the gate; a pixel electrode; a first electrode, located on the side of the active layer and the pixel electrode away from the first substrate, connected to the active layer and in contact with the pixel electrode; a second electrode, connected to the active layer and a data line; a second insulating layer, located on the side of the pixel electrode, the first and second electrodes away from the first substrate and having a first opening, the first opening overlapping the orthographic projection of the pixel electrode and the first electrode on the first substrate; a connecting electrode, contacting the pixel electrode and the first electrode through the first opening; and a common electrode, located on the side of the second insulating layer away from the pixel electrode and spaced apart from the connecting electrode.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display device. Background Art

[0002] With the rapid development of display technology, people's requirements for the resolution of liquid crystal display devices such as televisions are getting higher and higher, and 8K resolution liquid crystal display devices have gradually become a research hotspot.

[0003] As the resolution of liquid crystal display devices increases, the number of sub-pixels in the liquid crystal display devices increases, and the size of a single sub-pixel decreases. Summary of the invention

[0004] According to one aspect of an embodiment of the present disclosure, an array substrate is provided, comprising a first substrate, a plurality of data lines, and a plurality of sub-pixels connected to the plurality of data lines, wherein at least one of the plurality of sub-pixels comprises: a first insulating layer located on one side of the first substrate; a gate located between the first substrate and the first insulating layer; an active layer located on a side of the first insulating layer away from the gate; a pixel electrode located on a side of the first insulating layer away from the first substrate; a first electrode located on a side of the active layer and the pixel electrode away from the first substrate, the first electrode being connected to the active layer and in contact with the pixel electrode; and a second electrode The first electrode is spaced apart and connected to the active layer and one of the multiple data lines; a second insulating layer is located on a side of the pixel electrode, the first electrode and the second electrode away from the first substrate, and has a first opening, the orthographic projection of the first opening on the first substrate overlaps with the orthographic projection of the pixel electrode on the first substrate, and overlaps with the orthographic projection of the first electrode on the first substrate; a connecting electrode is in contact with the pixel electrode and the first electrode through the first opening; and a common electrode is located on a side of the second insulating layer away from the pixel electrode and spaced apart from the connecting electrode.

[0005] In some embodiments, common electrodes of some of the sub-pixels are connected to each other, and common electrodes of the remaining sub-pixels are spaced apart from each other.

[0006] In some embodiments, the multiple sub-pixels include multiple columns of sub-pixels, the partial sub-pixels include at least one column of sub-pixels among the multiple columns of sub-pixels, each column of sub-pixels in the at least one column of sub-pixels includes two adjacent sub-pixels, and two common electrodes of the two adjacent sub-pixels are connected through a common electrode connector.

[0007] In some embodiments, the plurality of sub-pixels include a plurality of rows of sub-pixels, and two gates of two adjacent sub-pixels in each row of the plurality of rows of sub-pixels are connected by a gate connector, and the gate connector partially overlaps the common electrode connector and the data line.

[0008] In some embodiments, the data line extends along a first direction, and the data line includes: a first data line portion that does not overlap with the gate connector; and a second data line portion adjacent to the first data line portion that partially overlaps with the gate connector, wherein a length of the second data line portion in a second direction perpendicular to the first direction is greater than a length of the first data line portion in the second direction.

[0009] In some embodiments, an angle between an extension direction of the gate connector and the first direction is greater than or equal to 45 degrees and less than 90 degrees.

[0010] In some embodiments, a ratio of a length of the second data line portion in the second direction to a length of the first data line portion in the second direction is greater than 1 and less than or equal to 1.4.

[0011] In some embodiments, the multiple columns of sub-pixels include multiple columns of first sub-pixels configured to emit light of a first color, multiple columns of second sub-pixels configured to emit light of a second color, and multiple columns of third sub-pixels configured to emit light of a third color, two adjacent columns of third sub-pixels in the multiple columns of third sub-pixels are separated by a column of first sub-pixels in the multiple columns of first sub-pixels and a column of second sub-pixels in the multiple columns of second sub-pixels, and the first color, the second color, and the third color are different from each other; and the at least one column of sub-pixels includes two or more columns of third sub-pixels in the multiple columns of third sub-pixels.

[0012] In some embodiments, two adjacent columns of the two or more columns of third sub-pixels are separated by a column of the third sub-pixels other than the two or more columns of third sub-pixels.

[0013] In some embodiments, the two common electrodes are integrally provided with the common electrode connector.

[0014] In some embodiments, the multiple sub-pixels include multiple rows of sub-pixels; and the array substrate also includes multiple common voltage lines connected to the multiple rows of sub-pixels, each of the multiple common voltage lines is configured to apply a common voltage to the common electrode of a corresponding row of sub-pixels in the multiple rows of sub-pixels.

[0015] In some embodiments, the array substrate also includes: a first alignment layer, located on a side of the common electrode away from the first base substrate; the second insulating layer of each sub-pixel in each row of sub-pixels in the multiple rows of sub-pixels has a second opening; and the common electrode of each sub-pixel in each row of sub-pixels is in contact with a common voltage line among the multiple common voltage lines corresponding to each row of sub-pixels and the first base substrate through the second opening.

[0016] In some embodiments, the common voltage line includes a first common voltage line portion, a second common voltage line portion and a third common voltage line portion, the third common voltage line portion is located between the first common voltage line portion and the second common voltage line portion, and is adjacent to the first common voltage line portion and the second common voltage line portion, respectively, the length of the second common voltage line portion in a first direction perpendicular to a second direction in which the common voltage line extends is greater than the length of the first common voltage line portion in the first direction, and the length of the first common voltage line portion in the first direction is greater than the length of the third common voltage line portion in the first direction; and the common electrode of each sub-pixel in each row of sub-pixels contacts the second common voltage line portion through the second opening.

[0017] In some embodiments, the plurality of common voltage lines and the gate are located at the same layer.

[0018] In some embodiments, the common electrode and the connection electrode are located in the same layer.

[0019] In some embodiments, the common electrode includes: a first electrode portion having a slit, located on a side of the connecting electrode away from the gate; and a second electrode portion adjacent to the first electrode portion, not having a slit, located on a side of the connecting electrode away from the data line.

[0020] According to another aspect of the embodiments of the present disclosure, a display device is provided, comprising: the array substrate described in any one of the above embodiments.

[0021] In some embodiments, the display device also includes a color filter substrate arranged opposite to the array substrate, and the color filter substrate includes: a second base substrate; a black matrix and a filter layer, located on a side of the second base substrate close to the array substrate, the filter layer includes a plurality of filter units, and adjacent filter units in the plurality of filter units are separated by the black matrix; a planarization layer, located on a side of the black matrix and the filter layer close to the array substrate; and a plurality of spacers, located between the planarization layer and the array substrate, the orthographic projection of each of the plurality of spacers on the second base substrate being located within the orthographic projection of the black matrix on the second base substrate.

[0022] In some embodiments, the plurality of sub-pixels include a plurality of columns of first sub-pixels configured to emit light of a first color, a plurality of columns of second sub-pixels configured to emit light of a second color, and a plurality of columns of third sub-pixels configured to emit light of a third color, two adjacent columns of second sub-pixels in the plurality of columns of second sub-pixels are separated by a column of first sub-pixels in the plurality of columns of first sub-pixels and a column of third sub-pixels in the plurality of columns of third sub-pixels, and the first color, the second color, and the third color are different from each other; and the plurality of spacers include a plurality of columns of spacers corresponding to the plurality of columns of second sub-pixels, the orthographic projection of each spacer in each column of the plurality of columns of spacers on the first substrate is a first projection, the orthographic projection of the gate of a second sub-pixel in a column of second sub-pixels corresponding to each column of spacers in the plurality of columns of second sub-pixels on the first substrate is a second projection, the orthographic projection of the active layer of the second sub-pixel on the first substrate is a third projection, the orthographic projection of the data line connected to the second sub-pixel on the first substrate is a fourth projection, and the first projection is located within the second projection and on a side of the third projection away from the fourth projection.

[0023] In some embodiments, the second color is red.

[0024] In some embodiments, the area not covered by the black matrix of each first subpixel in the multiple columns of first subpixels, each second subpixel in the multiple columns of second subpixels, and each third subpixel in the multiple columns of third subpixels is a light-emitting area, and the area of ​​the light-emitting area of ​​each second subpixel is smaller than the area of ​​the light-emitting area of ​​each first subpixel and the area of ​​the light-emitting area of ​​each third subpixel.

[0025] In some embodiments, the second sub-pixel also includes a plurality of blocking portions, and the orthographic projection of each of the plurality of blocking portions on the first substrate is located within the orthographic projection of the black matrix on the first substrate, and the plurality of blocking portions include: a first blocking portion, located on a side of a spacer among the plurality of spacers corresponding to the second sub-pixel close to the pixel electrode; and a second blocking portion, located on a side of the first blocking portion away from the spacer, and a height of the second blocking portion is greater than a height of the first blocking portion.

[0026] In some embodiments, the area of ​​the second sub-pixel not covered by the black matrix is ​​a light-emitting area; the first blocking portion and the second blocking portion are located on a first side of the light-emitting area; and the multiple blocking portions also include a third blocking portion, which is located on a second side of the light-emitting area opposite to the first side.

[0027] In some embodiments, the first blocking portion includes a first layer, a second layer, a third layer, a fourth layer and a fifth layer arranged in sequence on the one side of the first base substrate; at least one of the second blocking portion and the third blocking portion includes a sixth layer, a seventh layer, an eighth layer, a ninth layer, a tenth layer and an eleventh layer arranged in sequence on the one side of the first base substrate; and the first layer, the seventh layer and the first insulating layer are located on the same layer, the second layer, the eighth layer and the pixel electrode are located on the same layer, the third layer, the ninth layer and the first electrode are located on the same layer, the fourth layer, the tenth layer and the second insulating layer are located on the same layer, the fifth layer, the eleventh layer and the common electrode are located on the same layer, and the sixth layer and the gate are located on the same layer.

[0028] According to another aspect of the embodiments of the present disclosure, a method for manufacturing an array substrate is provided, comprising forming a plurality of data lines and a plurality of sub-pixels on one side of a first substrate, wherein forming at least one of the plurality of sub-pixels comprises: forming a gate on the one side of the first substrate; forming a first insulating layer on a side of the gate away from the first substrate; forming an active layer on a side of the first insulating layer away from the gate; forming a pixel electrode on a side of the first insulating layer away from the first substrate; forming a first electrode and a second electrode, wherein: the first electrode is located on a side of the active layer and the pixel electrode away from the first substrate, connected to the active layer, and in contact with the pixel electrode, and the second electrode is in contact with the active layer; The pixel electrode, the first electrode and the second electrode are spaced apart from each other and connected to the active layer and one of the plurality of data lines; a second insulating layer is formed on a side of the pixel electrode, the first electrode and the second electrode away from the first substrate, the second insulating layer having a first opening, the orthographic projection of the first opening on the first substrate overlaps with a portion of the orthographic projection of the pixel electrode on the first substrate, and overlaps with a portion of the orthographic projection of the first electrode on the first substrate; and a connecting electrode and a common electrode spaced apart from the connecting electrode are formed, the connecting electrode contacts the pixel electrode and the first electrode through the first opening, and the common electrode is located on a side of the second insulating layer away from the pixel electrode.

[0029] In some embodiments, forming the second insulating layer includes: forming an insulating material layer covering the pixel electrode, the first electrode and the second electrode; forming a mask having a third opening on a side of the insulating material layer away from the first substrate; and patterning the insulating material layer using the mask to obtain the second insulating layer.

[0030] In the array substrate provided by the embodiment of the present disclosure, on the one hand, the distance between the pixel electrode and the common electrode is reduced, the storage capacitance of the sub-pixel is increased, and the vertical crosstalk of the array substrate is reduced. On the other hand, the first electrode is in contact with the pixel electrode, and both the first electrode and the pixel electrode are in contact with the connecting electrode in the first opening, which increases the contact area between the first electrode and the pixel electrode and reduces the resistance between the first electrode and the pixel electrode, which is conducive to improving the driving ability of the sub-pixel and improving the display effect of the array substrate.

[0031] Other features, aspects and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings constitute a part of this specification, and illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0033] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0034] Figure 1A is a schematic structural diagram showing an array substrate according to an embodiment of the present disclosure;

[0035] Figure 1B It is shown Figure 1A A partial enlarged schematic diagram of the array substrate shown;

[0036] Figure 2A It is along Figure 1B A schematic cross-sectional view taken along line AA' is shown;

[0037] Figure 2B It is along Figure 1B A schematic cross-sectional view taken along line BB' is shown;

[0038] Figure 2C It is along Figure 1A A schematic cross-sectional view taken along the line C-C' is shown;

[0039] Figure 3 is a schematic structural diagram showing a display device according to an embodiment of the present disclosure;

[0040] Figure 4 It is along Figure 1B A schematic cross-sectional view taken along line D-D' is shown;

[0041] Figure 5 is a schematic flow chart showing a method for manufacturing a sub-pixel according to an embodiment of the present disclosure;

[0042] Figure 6-Figure 8is a schematic diagram showing the structure of a shift register unit according to some embodiments of the present disclosure.

[0043] It should be understood that the size of each part shown in the accompanying drawings is not necessarily drawn according to the actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0044] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0045] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprises" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0046] In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be an intermediate component between the specific component and the first component or the second component. When a specific component is described as being connected to other components, the specific component may be directly connected to the other components without an intermediate component, or may not be directly connected to the other components but have an intermediate component.

[0047] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries, such as general dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.

[0048] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0049] The inventors noticed that as the size of sub-pixels becomes smaller and smaller, the storage capacitors in the sub-pixels also become smaller and smaller, making the sub-pixels susceptible to interference from the leakage current of the thin film transistors in the sub-pixels and the capacitive coupling between the sub-pixels and the data lines, thereby generating vertical crosstalk.

[0050] Figure 1A FIG. 4 is a schematic diagram showing the layout of an array substrate according to an embodiment of the present disclosure.

[0051] like Figure 1A As shown, the array substrate TA includes a first base substrate 100, a plurality of data lines DL, and a plurality of sub-pixels 10 connected to the plurality of data lines DL. For example, the sub-pixels 10 connected to the same data line DL among the plurality of sub-pixels 10 are located on the same side of the data line DL, that is, the sub-pixels 10 in the same column are connected to the same data line DL.

[0052] Figure 1B It is shown Figure 1A A partial enlarged schematic diagram of the array substrate is shown. Figure 2A It is along Figure 1B A schematic cross-sectional view taken along line AA' is shown; Figure 2B It is along Figure 1B The cross-sectional schematic diagram shown is taken along line BB'.

[0053] Combine the following Figure 1B , Figure 2A and Figure 2B The structure of the sub-pixel 10 according to some embodiments of the present disclosure is introduced. The structure of at least one of the multiple sub-pixels 10 of the array substrate TA may be the structure of the sub-pixel 10 described below. In some embodiments, the structure of each sub-pixel 10 of the array substrate TA may be the structure of the sub-pixel 10 described below.

[0054] See also Figure 1B , Figure 2A and Figure 2B The sub-pixel 10 includes a gate 101 , a first insulating layer 102 , an active layer 103 , a pixel electrode 104 , a first electrode 105 , a second electrode 106 , a second insulating layer 107 , a connecting electrode 108 and a common electrode 109 .

[0055] The gate 101 is located on one side of the first substrate 100. Figure 2A Here, the gate 101 is shown as being located on the upper side of the first substrate 100. The first substrate 100 may be, for example, a glass substrate, etc. The material of the gate 101 may include, for example, metals such as aluminum and copper.

[0056] The first insulating layer 102 is located on one side of the first substrate 100, and the gate 101 is located between the first substrate 100 and the first insulating layer 102. Figure 2A It should be understood that the first insulating layer 102 also covers a portion of the first substrate 100, such as Figure 2B As shown in some implementations, the material of the first insulating layer 102 may include silicon oxide, silicon nitride (eg, SiN x ) or silicon oxides, etc.

[0057] The active layer 103 is located on a side of the first insulating layer 102 away from the gate 101. Figure 2A For example, the material of the active layer 103 may include semiconductor materials such as amorphous silicon, low temperature polysilicon, oxide semiconductor, etc. In some embodiments, the material of the active layer 103 may include a P-type semiconductor material.

[0058] The pixel electrode 104 is located on a side of the first insulating layer 102 away from the first substrate 100. Figure 2B In addition, for example, the pixel electrode 104 is spaced apart from the active layer 103, as shown in FIG. Figure 1B As shown. As some implementations, the material of the pixel electrode 104 may include a transparent material such as indium tin oxide (ITO). It should be understood that in the present disclosure, component A is spaced apart from component B, which means that component A and component B are insulated.

[0059] The first electrode 105 is located on a side of the active layer 103 and the pixel electrode 104 away from the first substrate 100. Figure 2A and Figure 2B See Figure 2A , the first electrode 105 is connected to the active layer 103. For example, the first electrode 105 may be in contact with the active layer 103. Figure 2B , the first electrode 105 is in contact with the pixel electrode 104 .

[0060] The second electrode 106 is spaced apart from the first electrode 105. Figure 1B and Figure 2A As shown. The second electrode 106 is connected to the active layer 103. For example, the second electrode 106 contacts the active layer 103. In addition, the second electrode 106 is also connected to one data line DL among the plurality of data lines DL. For example, the second electrode 106 can be integrally provided with the connected data line DL. Here, one of the first electrode 105 and the second electrode 106 is a source electrode, and the other is a drain electrode. For example, the first electrode 105 is a drain electrode, and the second electrode 106 is a source electrode.

[0061] The second insulating layer 107 covers the pixel electrode 104, the first electrode 105 and the second electrode 106. Figure 2A and Figure 2B See Figure 1B and Figure 2B , the second insulating layer 107 has a first opening V1. The orthographic projection of the first opening V1 on the first base substrate 100 overlaps with the orthographic projection portion of the pixel electrode 104 on the first base substrate 100, and overlaps with the orthographic projection portion of the first electrode 105 on the first base substrate 100. In other words, the first opening V1 exposes a portion of the pixel electrode 104, and exposes a portion of the first electrode 105. That is, a portion of the orthographic projection of the first opening V1 on the first base substrate 100 (for example, referred to as the first portion) overlaps with the orthographic projection of the pixel electrode 104 on the first base substrate 100, and does not overlap with the orthographic projection of the first electrode 105 on the first base substrate 100; another portion of the orthographic projection of the first opening V1 on the first base substrate 100 (for example, referred to as the second portion) overlaps with the orthographic projection of the first electrode 105 on the first base substrate 100. It should be understood that although Figure 1B The area of ​​the first part of the orthographic projection of the first opening V1 on the first substrate 100 is shown to be larger than the area of ​​the second part, but this is not restrictive. For example, the area of ​​the first part of the orthographic projection of the first opening V1 on the first substrate 100 may also be smaller than or equal to the area of ​​the second part. As some implementations, the material of the first insulating layer 102 may include silicon oxide, silicon nitride (e.g., SiN x ) or silicon oxides, etc.

[0062] The connecting electrode 108 contacts the pixel electrode 104 and the first electrode 105 through the first opening V1. Figure 2B In other words, the connection electrode 108 is at least partially located in the first opening V1 and contacts the exposed portion of the pixel electrode 104 and the exposed portion of the first electrode 105. As some implementations, the material of the connection electrode 108 may include a transparent material such as ITO.

[0063] The common electrode 109 is located on a side of the second insulating layer 107 away from the pixel electrode 104 and is spaced apart from the connecting electrode 108. Figure 1B and Figure 2B As some implementations, the material of the connecting electrode 108 may include transparent materials such as indium tin oxide.

[0064] In some embodiments, the common electrode 109 and the connecting electrode 108 are located in the same layer. It should be noted that in the embodiments of the present disclosure, multiple components are located in the same layer means that the multiple components are formed by patterning the same material layer. For example, the materials of the common electrode 109 and the connecting electrode 108 both include indium tin oxide. In some embodiments, the common electrode 109 and the connecting electrode 108 spaced apart from each other can be formed by patterning the same indium tin oxide material layer.

[0065] In the above embodiment, on the one hand, the distance between the pixel electrode 104 and the common electrode 109 is reduced, which increases the storage capacitance of the sub-pixel 10 and reduces the vertical crosstalk of the array substrate. On the other hand, the first electrode 105 is in contact with the pixel electrode 104, and both the first electrode 105 and the pixel electrode 104 are in contact with the connecting electrode 108 in the first opening V1, which increases the contact area between the first electrode 105 and the pixel electrode 104 and reduces the resistance between the first electrode 105 and the pixel electrode 104, which is beneficial to improving the driving capability of the sub-pixel 10 and improving the display effect of the array substrate.

[0066] In some embodiments, the array substrate of the above-mentioned embodiment can be manufactured by using existing mask plates, without increasing the number of additional mask plates, which facilitates process implementation.

[0067] In some embodiments, see Figure 1A , the common electrode 109 of the sub-pixel 10 may include a first common electrode portion 109A and a second common electrode portion 109B adjacent to the first common electrode portion 109A. The first common electrode portion 109A is located on a side of the connection electrode 108 away from the gate 101, such as the upper side; the second common electrode portion 109B is located on a side of the connection electrode 108 away from the data line DL connected to the sub-pixel 10, such as the left side. Here, the second common electrode portion 109B can be regarded as protruding outward relative to the first common electrode portion 109A. The first common electrode portion 109A has a slit SL, while the second common electrode portion 109B does not have a slit. In this way, the luminous efficiency of the sub-pixel 10 can be improved, and the capacitance between the pixel electrode 104 and the common electrode 109 can be further increased, thereby further reducing the vertical crosstalk of the array substrate.

[0068] In some embodiments, the common electrodes 109 of some of the sub-pixels 10 are connected to each other, and the common electrodes 109 of the remaining sub-pixels 10 are spaced apart from each other. In this way, it is beneficial to improve the uniformity of the common voltage applied to the common electrode 109, so as to improve the display uniformity of the array substrate.

[0069] In some embodiments, the plurality of sub-pixels 10 include a plurality of columns of sub-pixels. At least one column of sub-pixels in the plurality of columns of sub-pixels includes two adjacent sub-pixels, and two common electrodes 109 of the two adjacent sub-pixels are connected to each other. That is, the above-mentioned part of the sub-pixels 10 may include at least one column of sub-pixels in the plurality of columns of sub-pixels. In the at least one column of sub-pixels, two common electrodes 109 of two adjacent sub-pixels 10 in each column of sub-pixels are connected through a common electrode connector CCL.

[0070] For example, see Figure 1A , the multiple columns of sub-pixels may include multiple columns of first sub-pixels P1 configured to emit light of a first color, multiple columns of second sub-pixels P2 configured to emit light of a second color, and multiple columns of third sub-pixels P3 configured to emit light of a third color. Here, two adjacent columns of third sub-pixels P3 in the multiple columns of third sub-pixels P3 are separated by a column of first sub-pixels P1 in the multiple columns of first sub-pixels P1 and a column of second sub-pixels P2 in the multiple columns of second sub-pixels P2. For example, the multiple columns of sub-pixels are repeatedly arranged in the order of the first column of sub-pixels P1, the second column of sub-pixels P2, and the third sub-pixels P3. The first color, the second color, and the third color are different from each other. In some embodiments, one of the first color, the second color, and the third color is red, and the other two are green and blue. For example, the second color is red, one of the first color and the third color is blue, and the other is green.

[0071] In some embodiments, the common electrodes 109 of each column of the third sub-pixels P3 in two or more columns are connected to each other, while the common electrodes 109 of the sub-pixels in other columns are spaced apart from each other. For example, the third sub-pixels P3 may be blue sub-pixels or green sub-pixels. Figure 1A In each column of the third sub-pixel P3, the two common electrodes 109 of two adjacent sub-pixels 10 are connected by a common electrode connector CCL. In some embodiments, the two adjacent common electrodes 109 are integrally provided with the common electrode connector CCL. For example, the common electrode connector CCL may be formed simultaneously during the process of forming the common electrode 109. For example, the common electrode 109 may be formed integrally with the common electrode connector CCL by patterning the same material layer.

[0072] In some embodiments, in two or more columns of third sub-pixels P3 in which the common electrodes 109 of each column of third sub-pixels P3 are connected to each other, two adjacent columns of third sub-pixels P3 are separated by one column of third sub-pixels P3 in multiple columns of third sub-pixels P3. Here, one column of third sub-pixels P3 in multiple columns of third sub-pixels P3 is a column of third sub-pixels P3 other than two or more columns of third sub-pixels P3 in which the common electrodes 109 are connected to each other. That is, the common electrodes 109 in the column of third sub-pixels P3 are separated from each other. For example, multiple columns of third sub-pixels P3 include a first column of third sub-pixels P3, a second column of third sub-pixels P3, and a third column of third sub-pixels P3 arranged from left to right. The common electrodes 109 of each column of third sub-pixels P3 in the first column of third sub-pixels P3 and the third column of third sub-pixels P3 are connected to each other, while the common electrodes 109 of the second column of third sub-pixels P3 are separated from each other. In this way, the display uniformity of the array substrate can be improved, and excessive coupling capacitance between too many common electrode connectors CCL and other metal layers can be avoided, thereby further improving the display effect of the array substrate.

[0073] In some embodiments, see Figure 1A , the plurality of sub-pixels 10 include a plurality of rows of sub-pixels, such as a row of R1 sub-pixels, a row of R2 sub-pixels, etc. It should be understood that Figure 1A Only two rows of sub-pixels are schematically shown. Two gates 101 of two adjacent sub-pixels 10 in each row of sub-pixels in the plurality of rows of sub-pixels are connected via a gate connector GCL. Here, the orthographic projection of the gate connector GCL on the first substrate 100 partially overlaps with the orthographic projection of the common electrode connector CCL on the first substrate 100, and partially overlaps with the orthographic projection of the data line DL on the first substrate 100.

[0074] The inventors also noticed that the data line DL and the gate connection member GCL may be broken at the overlapping position, which may affect the display effect of the array substrate. Based on this, the embodiment of the present disclosure also proposes the following solution.

[0075] In some embodiments, the data lines DL extend along a first direction (eg, a column direction). Figure 1B , the data line DL may include a first data line portion DL11 and a second data line portion DL12 adjacent to the first data line portion DL11. Here, the first data line portion DL11 does not overlap with the gate connection member GCL, and the second data line portion DL12 partially overlaps with the gate connection member GCL. In addition, the length L2 of the second data line portion DL12 in a second direction (e.g., a row direction) perpendicular to the first direction is greater than the length L1 of the first data line portion DL11 in the second direction. In this way, the area where the data line DL overlaps with the gate connection member GCL can be increased, thereby reducing the possibility of the data line DL breaking at the position where it overlaps with the gate connection member GCL.

[0076] It should be understood that in the present disclosure, component A and component B are adjacent to each other, which can be understood as component A is adjacent to and connected to component B. In some embodiments, component A and component B can be integrally provided. In this case, component A and component B are different parts of the same component.

[0077] As some implementations, the ratio of the length L2 of the second data line portion DL12 in the second direction to the length L1 of the first data line portion DL11 in the second direction is greater than 1 and less than or equal to 1.4, for example, 1.2, 1.3, etc. As some implementations, L2 is 1 micron to 2 microns larger than L1, for example, 1 micron, 1.5 microns, 1.18 microns, 2 microns, etc. In this way, the possibility of the data line DL being broken at the position overlapping with the gate connector GCL can be reduced, and the coupling capacitance between the overly wide data line DL and the surrounding metal can be prevented from being too large.

[0078] In other embodiments, the extension direction of the gate connector GCL is not perpendicular to and parallel to the first extension direction of the data line DL. For example, the angle between the extension direction of the gate connector GCL and the first extension direction of the data line DL is greater than or equal to 45 degrees and less than 90 degrees, such as 60 degrees, 80 degrees, etc. In this way, the area where the gate connector GCL overlaps with the data line DL can be increased, thereby reducing the possibility of the data line DL being broken at the position where it overlaps with the gate connector GCL.

[0079] In some other embodiments, the length L2 of the second data line portion DL12 in the second direction perpendicular to the first direction in which the data line DL extends is greater than the length L1 of the first data line portion DL11 in the second direction, and the extending direction of the gate connector GCL is not perpendicular to and parallel to the first direction in which the data line DL extends. In this way, the possibility of the data line DL being broken at the position overlapping with the gate connector GCL can be further reduced.

[0080] In some embodiments, see Figure 1A , the array substrate further includes a plurality of common voltage lines 11 connected to the plurality of rows of sub-pixels. Each of the plurality of common voltage lines 11 is configured to apply a common voltage to a common electrode of a corresponding row of sub-pixels in the plurality of rows of sub-pixels. For example, the number of the plurality of common voltage lines 11 is the same as the number of rows of sub-pixels, and one common voltage line 11 corresponds to a row of sub-pixels. In this case, each common voltage line 11 applies a common voltage to a common electrode of a corresponding row of sub-pixels.

[0081] In some embodiments, an orthographic projection of the common voltage line 11 on the first base substrate 100 does not overlap with an orthographic projection of the pixel electrode 104 on the first base substrate 100 .

[0082] The inventors also noticed that the connection mode between the common voltage line 11 and the common electrode 109 will affect the thickness uniformity of the alignment layer, thereby affecting the display uniformity of the array substrate. Accordingly, the embodiments of the present disclosure also provide the following solutions.

[0083] Figure 2C It is along Figure 1A The schematic cross-sectional view taken along line CC' is shown.

[0084] like Figure 2C As shown, in some embodiments, the array substrate TA further includes a first alignment layer 12. The first alignment layer 12 is located on a side of the common electrode 109 away from the first base substrate 100. As some implementations, the material of the first alignment layer 12 may include polyimide (PI).

[0085] The second insulating layer 107 of each sub-pixel 10 in each row of sub-pixels in the plurality of rows of sub-pixels has a second opening V2. Figure 1A The common electrode 109 of each sub-pixel 10 in each row of sub-pixels contacts one common voltage line 11 corresponding to each row of sub-pixels and the first substrate 100 through the second opening V2. In some embodiments, the common voltage lines 11 and the gate 101 are located in the same layer.

[0086] It should be understood that for a row of sub-pixels, the second opening V2 of each sub-pixel 10 exposes a portion of the common electrode line 11 corresponding to the row of sub-pixels and exposes a portion of the first base substrate 100. Figure 2C The common electrode 109 is partially located in the second opening V2 and contacts the exposed portion of the common electrode line 11 and the exposed portion of the first base substrate 100 .

[0087] In the above embodiment, the common electrode 109 contacts both the common voltage line 11 and the first base substrate 100 through the second opening V2. Compared with the common electrode 109 contacting only the common voltage line 11 through the second opening V2 (i.e., the second opening V2 only exposes a portion of the common voltage line 11), such a structure facilitates the liquid used to form the first alignment layer 12 to flow into the second opening V2, so that the flow of the liquid is more uniform, thereby making the thickness of the first alignment layer 12 more uniform, thereby improving the display uniformity of the array substrate.

[0088] The inventors have noticed that in some cases, the position of the second opening V2 may deviate from the desired position. In this case, the common electrode 109 may only contact the first base substrate 100 through the second opening V2, but cannot contact the corresponding common voltage line 11. In view of this, the following solution is proposed in the embodiment of the present disclosure.

[0089] In some embodiments, see Figure 1A , the common voltage line 11 connected to each row of sub-pixels 10 includes a first common voltage line portion 111, a second common voltage line portion 112, and a third common voltage line portion 113. The third common voltage line portion 113 is located between the first common voltage line portion 111 and the second common voltage line portion 112, and is adjacent to the first common voltage line portion 111 and the second common voltage line portion 112, respectively. The length L4 of the second common voltage line portion 112 in the first direction perpendicular to the second direction in which the common voltage line 11 extends is greater than the length L3 of the first common voltage line portion 111 in the first direction, and the length L3 of the first common voltage line portion 111 in the first direction is greater than the length L5 of the third common voltage line portion 113 in the first direction. The common electrode 109 of each sub-pixel 10 in each row of sub-pixels contacts the second common voltage line portion 112 through the second opening V2.

[0090] In this way, the wider second common voltage line portion 112 is more conducive to ensuring that the common electrode 109 is in contact with the first base substrate 100. In addition, since the third common voltage line portion 113 is relatively narrower than the first common voltage line portion 111 and the second common voltage line portion 112, it is more conducive to ensuring that the common electrode 109 is in contact with the first base substrate 100. In this way, such a structure is more conducive to the common electrode 109 being in contact with both the first base substrate 100 and the common voltage line 11.

[0091] In some embodiments, the common voltage line 11 further includes a fourth common voltage line portion 114 overlapping the data line DL, and the fourth common voltage line portion 112 is adjacent to the second common voltage line portion 112. The length L6 of the fourth common voltage line portion 114 in the first direction is less than the length L4 of the second common voltage line portion 112 in the first direction. In this way, the coupling capacitance between the common voltage line 11 and the data line DL can be reduced.

[0092] The present disclosure also provides a display device, which may include an array substrate of any of the above embodiments. In some embodiments, the display device may be, for example, a display panel, a mobile terminal, a television, a monitor, a laptop, a digital photo frame, a navigator, an electronic paper, or any other product or component with a display function. For example, the size of the display device may be 55 inches, 65 inches, 75 inches, etc., and the resolution may be 4K, 8K, or higher.

[0093] Figure 3 is a schematic structural diagram showing a display device according to an embodiment of the present disclosure.

[0094] like Figure 3As shown, the display device includes an array substrate TA and a color filter substrate TB arranged opposite to the array substrate TA. The color filter substrate TB includes a second base substrate 200, a black matrix 201, a filter layer 202, a planarization layer 203 and a plurality of spacers 204. It should be understood that liquid crystal is arranged between the array substrate TA and the color filter substrate TB.

[0095] The second base substrate 200 may be, for example, a glass substrate. The black matrix 201 and the filter layer 202 are both located on a side of the second base substrate 200 close to the array substrate TA. Figure 1A The black matrix 201 is shown in dotted lines. It should be understood that the area of ​​the sub-pixel 10 not covered by the black matrix 201 is the light-emitting area.

[0096] The filter layer 202 includes a plurality of filter units, such as a red filter unit R, a green filter unit G, and a blue filter unit B. Adjacent filter units in the plurality of filter units are separated by a black matrix 201. For example, the red filter unit R and the green filter unit G are separated by the black matrix 201, and the green filter unit G and the blue filter unit B are separated by the black matrix 201.

[0097] The planarization layer 203 is located on a side of the black matrix 201 and the filter layer 202 close to the array substrate TA. For example, the material of the planarization layer 203 includes resin, photoresist, and the like.

[0098] A plurality of spacers 204 are located between the planarization layer 203 and the array substrate TA. The orthographic projection of each of the plurality of spacers 204 on the second base substrate 200 is located within the orthographic projection of the black matrix 201 on the second base substrate 100. For example, the material of the spacers 204 may include resin or photoresist.

[0099] The inventors have noticed that the plurality of spacers 204 may move under the action of external force, thereby causing damage to the array substrate TA, for example, the first alignment layer 12 of the array substrate TA may be damaged, thereby affecting the display effect of the display device. Since the orthographic projection of the spacer 204 on the second base substrate 100 is located within the orthographic projection of the black matrix 201 on the second base substrate 100, even if the spacer 204 moves, as long as it is covered by the black matrix 201, it will not have an adverse effect on the display effect of the display device. Therefore, such a structure is conducive to reducing the adverse effect of the movement of the spacer 204 on the display effect of the display device.

[0100] In some embodiments, the area of ​​each first subpixel in the multiple columns of first subpixels P1, each second subpixel in the multiple columns of second subpixels P2, and each third subpixel in the multiple columns of third subpixels P3 that is not covered by the black matrix 201 is a light-emitting area. The area of ​​the light-emitting area of ​​each second subpixel is smaller than the area of ​​the light-emitting area of ​​each first subpixel and the area of ​​the light-emitting area of ​​each third subpixel.

[0101] In some embodiments, the color filter substrate TB further includes a second alignment layer 205 located on the side of the planarization layer 203 close to the array substrate TA and on the surface of the spacer 204. As some implementations, the material of the second alignment layer 205 may include polyimide (PI).

[0102] In some embodiments, the plurality of sub-pixels 10 include a plurality of columns of first sub-pixels P1 configured to emit light of a first color, a plurality of columns of second sub-pixels P2 configured to emit light of a second color, and a plurality of columns of third sub-pixels P3 configured to emit light of a third color. Two adjacent columns of second sub-pixels P2 in the plurality of columns of second sub-pixels P2 are separated by a column of first sub-pixels P1 in the plurality of columns of first sub-pixels P1 and a column of third sub-pixels P3 in the plurality of columns of third sub-pixels P3. The plurality of spacers 204 include a plurality of columns of spacers corresponding to the plurality of columns of second sub-pixels P2. For example, the number of columns of the plurality of columns of second sub-pixels P2 is the same as the number of columns of the plurality of columns of spacers, that is, one column of second sub-pixels P2 corresponds to one column of spacers.

[0103] For the sake of convenience of explanation, the orthographic projection of each spacer 204 in each column of spacers in the multiple columns of spacers on the first base substrate 100 is defined as a first projection, the orthographic projection of a gate 101 of a second sub-pixel P2 in a column of second sub-pixels P2 corresponding to each column of spacers in the multiple columns of second sub-pixels P2 on the first base substrate 100 is defined as a second projection, the orthographic projection of the active layer 103 of the second sub-pixel P2 on the first base substrate 100 is defined as a third projection, and the orthographic projection of the data line DL connected to the second sub-pixel P2 on the first base substrate 100 is defined as a fourth projection.

[0104] See also Figure 1A and Figure 1B In some embodiments, the first projection of the spacer 204 is located within the second projection of the gate 101 and is located on the side of the third projection of the active layer 103 away from the fourth projection of the data line DL. In such a structure, the spacer 204 has a small adverse effect on the light emission of the sub-pixel 10.

[0105] It should be noted that in Figure 1A and Figure 1B , the first projection of the spacer 204 is shown to be consistent with the spacer 204. Similarly, Figure 1A and Figure 1BThe other components shown can also be understood as the orthographic projections of the other components on the first substrate 100 . Figure 1A and Figure 1B The first projection of the spacer 204 shown may be understood as an orthographic projection of the surface of the spacer 204 close to the planarization layer 203 on the first base substrate 100 .

[0106] It should also be noted that although Figure 1A and Figure 1B The shape of the first projection of the spacer 204 is shown to be an octagon, but this is not restrictive, and the shape of the first projection of the spacer 204 may also be a circle or other polygons.

[0107] In some embodiments, the second color is red, that is, the second sub-pixel P2 is a red sub-pixel. The brightness of the red sub-pixel is lower than that of the blue sub-pixel and the green sub-pixel. The positions of the multiple columns of spacers are set to correspond to the multiple columns of red sub-pixels, which can minimize the adverse effects of the multiple spacers 204 on the display effect of the display device.

[0108] In some embodiments, see Figure 1A and Figure 1B , each second sub-pixel P2 in each column of the second sub-pixel further includes a plurality of blocking portions 110 configured to block the movement of the spacer 204, and the orthographic projection of each blocking portion 110 on the first substrate 100 is located within the orthographic projection of the black matrix 201 on the first substrate 100. The plurality of blocking portions 110 include a first blocking portion 110A and a second blocking portion 110B. The first blocking portion 110A is located on a side of a spacer 204 corresponding to the second sub-pixel P2 among the plurality of spacers 204 close to the pixel electrode 104, and the second blocking portion 110B is located on a side of the first blocking portion 110A away from the spacer 204. In addition, the height of the second blocking portion 110B is greater than the height of the first blocking portion 110A. It should be understood that in the present disclosure, the height of a certain component can be understood as the length of the component extending in a direction perpendicular to the surface of the first substrate 100.

[0109] In the above embodiment, the first blocking portion 110A with a smaller height can block the spacer 204 from moving. Even if the spacer 204 crosses the first blocking portion 110A, the first blocking portion 110A also plays a buffering role, reducing the moving speed of the spacer 204, so that the second blocking portion 110B with a larger height can more effectively block the spacer 204 from moving. In this way, the spacer 204 can be more effectively blocked from moving to the light-emitting area of ​​the second sub-pixel P2, thereby preventing the spacer 204 from adversely affecting the second sub-pixel P2.

[0110] In some embodiments, see Figure 1A, the plurality of blocking portions 110 of the second sub-pixel P2 further include a third blocking portion 110C. The first blocking portion 110A and the second blocking portion 110B are located at a first side of the light-emitting region of the second sub-pixel P2. The third blocking portion 110C is located at a second side of the light-emitting region of the second sub-pixel P2 opposite to the first side. The third blocking portion 110C can block the spacer 204 in the adjacent second sub-pixel P2 located in the same column as the second sub-pixel P2 from moving to the light-emitting region of the second sub-pixel P2, thereby further preventing the spacer 204 from affecting the second sub-pixel P2.

[0111] In some embodiments, the plurality of blocking portions 110 may be formed during the process of forming other layers of the array substrate. Figure 4 , Figure 2A and Figure 2B Make an introduction.

[0112] Figure 4 It is along Figure 1B The cross-sectional schematic diagram shown is taken along line D-D'.

[0113] like Figure 4 As shown, the first blocking portion 110A includes a first layer LY1, a second layer LY2, a third layer LY3, a fourth layer LY4 and a fifth layer LY5 which are sequentially arranged on one side of the first base substrate 100, and at least one of the second blocking portion 110B and the third blocking portion 110C includes a sixth layer LY6, a seventh layer LY7, an eighth layer LY8, a ninth layer LY9, a tenth layer LY10 and an eleventh layer LY11 which are sequentially arranged on one side of the first base substrate 100.

[0114] The first layer LY1, the seventh layer LY7 and Figure 2B The first insulating layer 102 is shown in the same layer, the second layer LY2, the eighth layer LY8 and Figure 2B The pixel electrodes 104 shown are located in the same layer, the third layer LY3, the ninth layer LY9 and Figure 2B The first electrode 105 shown is located in the same layer as the fourth layer LY4, the tenth layer LY10 and Figure 2B The second insulating layer 107 shown is located on the same layer as the fifth layer LY5, the eleventh layer LY11 and Figure 2B The common electrode 109 shown is located on the same layer as the sixth layer LY6. Figure 2A The gate electrode 101 is shown to be located on the same layer.

[0115] The present disclosure also provides a method for manufacturing an array substrate, comprising forming a plurality of data lines and a plurality of sub-pixels on one side of a first base substrate. Figure 5 A process of forming at least one of the plurality of sub-pixels is described.

[0116] Figure 5is a schematic flow chart showing a method for manufacturing a sub-pixel according to an embodiment of the present disclosure.

[0117] In step 502, a gate is formed on one side of a first substrate.

[0118] In step 504, a first insulating layer is formed on a side of the gate away from the first substrate.

[0119] In step 506 , an active layer is formed on a side of the first insulating layer away from the gate.

[0120] In step 508 , a pixel electrode is formed on a side of the first insulating layer away from the first substrate.

[0121] In step 510, a first electrode and a second electrode are formed. For example, the first electrode and the second electrode can be formed by the same patterning process.

[0122] The first electrode is located on a side of the active layer and the pixel electrode away from the first substrate, and is connected to the active layer. In addition, the first electrode is in contact with the pixel electrode.

[0123] The second electrode is spaced apart from the first electrode and connected to the active layer and one of the plurality of data lines.

[0124] In step 512, a second insulating layer is formed on a side of the pixel electrode, the first electrode, and the second electrode away from the first substrate. The second insulating layer has a first opening, and the orthographic projection of the first opening on the first substrate overlaps with the orthographic projection of the pixel electrode on the first substrate, and overlaps with the orthographic projection of the first electrode on the first substrate.

[0125] In step 514, a connection electrode and a common electrode spaced apart from the connection electrode are formed. For example, the common electrode and the connection electrode may be formed by the same patterning process.

[0126] Here, the connection electrode contacts the pixel electrode and the first electrode through the first opening, and the common electrode is located on a side of the second insulating layer away from the pixel electrode.

[0127] In the array substrate formed by the above embodiment, on the one hand, the distance between the pixel electrode and the common electrode is reduced, the storage capacitance of the sub-pixel is increased, and the vertical crosstalk of the array substrate is reduced. On the other hand, the first electrode is in direct contact with the pixel electrode, and both the first electrode and the pixel electrode are in contact with the connecting electrode in the first opening, which increases the contact area between the first electrode and the pixel electrode and reduces the resistance between the first electrode and the pixel electrode, which is beneficial to improving the driving ability of the sub-pixel and improving the display effect of the array substrate.

[0128] In some implementations, the second insulating layer may be formed in the following manner: First, an insulating material layer covering the pixel electrode, the first electrode, and the second electrode is formed; then, a mask having a third opening is formed on a side of the insulating material layer away from the first substrate; and then, the insulating material layer is patterned using the mask to obtain a second insulating layer having a second opening.

[0129] The mask with the third opening can be manufactured using existing mask plates without increasing the number of mask plates, thus facilitating process implementation.

[0130] When the display panel is driven to display, gate scanning signals can be written to the gate lines row by row according to the picture to be displayed, and data voltage signals can be written to the data lines at the same time, so that the sub-pixels in the display panel are lit up row by row.

[0131] The gate scan signal is provided by the gate drive circuit, and the data voltage signal is provided by the source drive circuit. In some embodiments, the gate drive circuit can be integrated into the gate drive chip, and the source drive circuit can be integrated into the source drive chip. In other embodiments, in order to reduce the number of chips and achieve narrow borders or no borders, the gate drive circuit can be integrated on the array substrate. The gate drive circuit includes a plurality of cascaded shift register units integrated on the array substrate, and the plurality of shift register units are connected to a plurality of gate lines in a one-to-one correspondence. Each shift register unit is used to provide a gate scan signal for the gate line connected thereto.

[0132] In order to more clearly explain how the shift register unit implements the output of the gate scanning signal, some examples of the shift register unit are described below.

[0133] Figure 6-Figure 8 is a schematic diagram showing the structure of a shift register unit according to some embodiments of the present disclosure.

[0134] In some embodiments, Figure 6 As shown, the shift register unit includes an input subcircuit 1, an output subcircuit 2, a pull-up reset subcircuit 3 and an output reset subcircuit 4. The input subcircuit 1 charges the pull-up node PU in response to the input signal input by the signal input terminal INPUT. The output subcircuit 2 outputs the clock signal input by the clock signal terminal CLK through the signal output terminal OUTPUT in response to the potential of the pull-up node PU. The pull-up reset subcircuit 3 resets the pull-up node PU in response to the pull-up reset signal output by the pull-up reset signal terminal RESET_PU, for example, resets the potential of the pull-up node PU to a low level. The output reset subcircuit 4 resets the signal output terminal OUTPUT in response to the output reset signal, for example, resets the potential of the signal output terminal OUTPUT to a low level.

[0135] In some embodiments, Figure 6 As shown, the input subcircuit 1 includes a first transistor M1, the pull-up reset subcircuit 3 includes a second transistor M2, the output subcircuit 2 includes a third transistor M3 and a storage capacitor C, and the output reset subcircuit 4 includes a fourth transistor M4. The gate and source of the first transistor M1 are connected to the signal input terminal INPUT, and the drain of the first transistor M1 is connected to the pull-up node PU. The gate of the second transistor M2 is connected to the pull-up reset signal terminal RESET_PU, the source of the second transistor M2 is connected to the pull-up node PU, and the drain of the second transistor M2 is connected to the low-level signal terminal VSS. The gate of the third transistor M3 is connected to the pull-up node PU, the source of the third transistor M3 is connected to the clock signal terminal CLK, and the drain of the third transistor M3 is connected to the signal output terminal OUTPUT. The first end of the storage capacitor C is connected to the pull-up node PU, and the second end of the storage capacitor C is connected to the signal output terminal OUTPUT. The gate of the fourth transistor M4 is connected to the output reset signal terminal RESET_OUTPUT, the source of the fourth transistor M4 is connected to the signal output terminal OUTPUT, and the drain of the fourth transistor M4 is connected to the low-level signal terminal VSS.

[0136] The following introduces Figure 6 The working process of the shift register unit is shown.

[0137] In the input stage, a high-level signal is written into the signal input terminal INPUT, and the first transistor M1 is turned on. The high-level signal pulls up the potential of the pull-up node PU and charges the storage capacitor C.

[0138] In the output stage, since the potential of the pull-up node PU is pulled high in the input stage, the third transistor M3 is turned on, and the high level signal input by the clock signal terminal CLK is output to the gate line connected to the shift register unit through the signal output terminal OUTPUT.

[0139] In the reset phase, a high-level signal is input to the output reset signal terminal RESET_OUTPUT, the fourth transistor M4 is turned on, and the low-level signal input through the low-level signal terminal VSS pulls down the potential of the output of the signal output terminal OUTPUT. A high-level signal is input to the pull-up reset signal terminal RESET_PU, the second transistor M2 is turned on, and the low-level signal input through the low-level signal terminal VSS pulls down the potential of the pull-up node PU. In this way, the reset of the pull-up node PU and the signal output terminal OUTPUT is completed.

[0140] It should be noted that, in some embodiments, the output reset subcircuit 4 may not be provided in the shift register unit. In the reset stage, after the pull-up node PU is reset, the potential of the pull-up node PU is at a low level, at which time the third transistor M3 is turned off, and the signal output terminal OUTPUT no longer outputs the high-level signal input by the clock signal terminal CLK, thereby resetting the signal output terminal OUTPUT.

[0141] In some embodiments, the signal output terminal OUTPUT of a certain stage of shift register units in the gate driving circuit including the above-mentioned shift register units is connected to the pull-up reset signal terminal RESET_PU of the previous stage of shift register units and the signal input terminal INPUT of the next stage of shift register units.

[0142] In other embodiments, Figure 7 As shown, in addition to the above-mentioned input subcircuit, output subcircuit, and pull-up reset subcircuit, the shift register unit also includes a first pull-down control subcircuit, a second pull-down control subcircuit, a first pull-down subcircuit, a second pull-down subcircuit, a first noise reduction subcircuit, a second noise reduction subcircuit, a discharge subcircuit, a first auxiliary subcircuit, and a second auxiliary subcircuit. The discharge subcircuit responds to the signal input by the signal terminal STV0 and discharges the pull-up node PU through the low-level signal input by the low-level signal terminal VGL. The first pull-down control subcircuit and the second pull-down control subcircuit have the same structure and function, and work in time sharing. Similarly, the first pull-down subcircuit and the second pull-down subcircuit have the same structure and function, the first auxiliary subcircuit and the second auxiliary subcircuit have the same structure and function, and the first noise reduction subcircuit and the second noise reduction subcircuit have the same structure and function. The input subcircuit, the output subcircuit, and the pull-up reset subcircuit have the same structure and function as described above, and will not be repeated here.

[0143] The first auxiliary subcircuit and the second auxiliary subcircuit both respond to the input signal input by the signal input terminal INPUT, and respectively pull down the potential of the first pull-down node PD1 and the second pull-down node PD2 through the low-level signal. The first pull-down control subcircuit controls the potential of the first pull-down node PD1 in response to the first power supply voltage input by the first power supply voltage signal terminal VDDO; the second pull-down control subcircuit controls the potential of the second pull-down node PD2 in response to the second power supply voltage input by the second power supply voltage signal terminal VDDE. The first pull-down subcircuit responds to the potential of the pull-up node PU, and pulls down the potential of the first pull-down node PD1 and the first pull-down control node PD_CN1 through the low-level signal input by the low-level signal terminal VGL. The second pull-down subcircuit responds to the potential of the pull-up node PU, and pulls down the potential of the second pull-down node PD2 and the second pull-down control node PD_CN2 through the level signal input by the low-level signal terminal VGL. The first noise reduction sub-circuit responds to the potential of the first pull-down node PD1 and reduces the noise of the signal outputted by the pull-up node PU and the signal output terminal OUTPUT through the low level signal inputted by the low level signal terminal VGL.

[0144] In some embodiments, Figure 7 As shown, the first pull-down control subcircuit and the second pull-down control subcircuit both include a fifth transistor and a ninth transistor. The fifth transistor in the first pull-down control subcircuit and the second control subcircuit is represented by M5 and M5', respectively, and the ninth transistor is represented by M9 and M9', respectively. The first pull-down subcircuit and the second pull-down subcircuit both include a sixth transistor and an eighth transistor. The sixth transistor in the first pull-down subcircuit and the second pull-down subcircuit is represented by M6 and M6', respectively, and the eighth transistor is represented by M8 and M8', respectively. The first noise reduction subcircuit and the second noise reduction subcircuit both include a tenth transistor and an eleventh transistor. The tenth transistor in the first noise reduction subcircuit and the second noise reduction subcircuit is represented by M10 and M10', respectively, and the eleventh transistor is represented by M11 and M11', respectively. The discharge subcircuit includes a seventh transistor M7. The first auxiliary subcircuit and the second auxiliary subcircuit both include a sixth transistor, represented by M16 and M16', respectively.

[0145] See also Figure 7, the gate and source of the first transistor M1 are connected to the signal input terminal INPUT, and the drain of the first transistor M1 is connected to the pull-up node PU. The gate of the second transistor M2 is connected to the pull-up reset signal terminal RESET_PU, the source of the second transistor M2 is connected to the pull-up node PU, and the drain of the second transistor M2 is connected to the low-level signal terminal VGL. The gate of the third transistor M3 is connected to the pull-up node PU, the source of the third transistor M3 is connected to the clock signal terminal CLK, and the drain of the third transistor M3 is connected to the signal output terminal OUTPUT. The first end of the storage capacitor C is connected to the pull-up node PU, and the second end of the storage capacitor C is connected to the signal output terminal OUTPUT. The gate and source of the ninth transistor M9 are both connected to the first power supply voltage terminal VDDO, and the drain of the ninth transistor M9 is connected to the first pull-down control node PD_CN1. The gate of the fifth transistor M5 is connected to the first pull-down control node PD_CN1, the source of the fifth transistor M5 is connected to the first power supply voltage terminal VDDO, and the drain of the fifth transistor M5 is connected to the first pull-down node PD1. The gate and source of the ninth transistor M9' are both connected to the second power supply voltage terminal VDDE, and the drain of the ninth transistor M9' is connected to the second pull-down control node PD_CN2; the gate of the fifth transistor M5' is connected to the second pull-down control node PD_CN2, the source of the fifth transistor M5' is connected to the second power supply voltage terminal VDDE, and the drain of the fifth transistor M5' is connected to the second pull-down node PD2. The gate of the sixth transistor M6 is connected to the pull-up node PU, the source of the sixth transistor M6 is connected to the first pull-down node PD1, and the drain of the sixth transistor M6 is connected to the low-level signal terminal VGL. The gate of the eighth transistor M8 is connected to the pull-up node PU, the source of the eighth transistor M8 is connected to the first pull-down control node PD_CN1, and the drain of the eighth transistor M8 is connected to the low-level signal terminal VGL. The gate of the sixth transistor M6' is connected to the pull-up node PU, the source of the sixth transistor M6' is connected to the second pull-down node PD2, and the drain of the sixth transistor M6' is connected to the low-level signal terminal VGL. The gate of the eighth transistor M8' is connected to the pull-up node PU, the source of the eighth transistor M8' is connected to the second pull-down control node PD_CN2, and the drain of the eighth transistor M8' is connected to the low-level signal terminal VGL. The gate of the tenth transistor M10 is connected to the first pull-down node PD1, the source of the tenth transistor M10 is connected to the pull-up node PU, and the drain of the tenth transistor M10 is connected to the low-level signal terminal VGL. The gate of the eleventh transistor M11 is connected to the first pull-down node PD1, the source of the eleventh transistor M11 is connected to the signal output terminal OUTPUT, and the drain of the eleventh transistor M11 is connected to the low-level signal terminal VGL. The gate of the tenth transistor M10' is connected to the second pull-down node PD2, the source of the tenth transistor M10' is connected to the pull-up node PU, and the drain of the tenth transistor M10' is connected to the low-level signal terminal VGL.The gate of the eleventh transistor M11' is connected to the second pull-down node PD2, the source of the eleventh transistor M11' is connected to the signal output terminal OUTPUT, and the drain of the eleventh transistor M11' is connected to the low-level signal terminal VGL. The gate of the seventh transistor M7 is connected to the signal terminal STV0, the source of the seventh transistor M7 is connected to the pull-up node PU, and the drain of the seventh transistor M7 is connected to the low-level signal terminal VGL. The gate of the sixteenth transistor M16 is connected to the signal input terminal INPUT, the source of the sixteenth transistor M16 is connected to the first pull-down node PD1, and the drain of the sixteenth transistor M16 is connected to the low-level signal terminal VGL. The gate of the sixteenth transistor M16' is connected to the signal input terminal INPUT, the source of the sixteenth transistor M16' is connected to the second pull-down node PD2, and the drain of the sixteenth transistor M16' is connected to the low-level signal terminal VGL.

[0146] The fifth transistor M5 and the ninth transistor M9 form a first pull-down control subcircuit, the fifth transistor M5' and the ninth transistor M9' form a second pull-down control subcircuit, and the first pull-down control subcircuit and the second pull-down control subcircuit work in time sharing, that is, work in turns. The first noise reduction subcircuit composed of the tenth transistor M10 and the eleventh transistor M11 is controlled by the first pull-down control subcircuit, and the second noise reduction subcircuit composed of the tenth transistor M10' and the eleventh transistor M11M11' is controlled by the second pull-down control subcircuit, so the first noise reduction subcircuit and the second noise reduction subcircuit also work in time sharing.

[0147] The first pull-down control subcircuit and the second pull-down control subcircuit have the same working principle, and the first noise reduction subcircuit and the second noise reduction subcircuit have the same working principle. The following only describes the working principle of the shift register unit when the first pull-down control subcircuit and the first noise reduction subcircuit are working.

[0148] In the discharge phase, that is, before a frame is displayed, a high level signal is input to the signal terminal STV0, and the seventh transistor M7 is turned on. The pull-up node PU is discharged by the low level signal input from the low level signal terminal VGL to prevent the residual charge on the pull-up node PU from causing display abnormality.

[0149] In the input stage, a high-level signal is input to the signal input terminal INPUT, and the first transistor M1 is turned on. The potential of the pull-up node PU is pulled high by the high-level signal, and the storage capacitor C is charged.

[0150] In the output stage, since the potential of the pull-up node PU is pulled high in the input stage, the third transistor M3 is turned on. The high level signal input by the clock signal terminal CLK is output to the corresponding gate line through the signal output terminal OUTPUT.

[0151] In the reset stage, a high-level signal is input to the pull-up reset signal terminal RESET_PU, and the second transistor M2 is turned on. The low-level signal input through the low-level signal terminal VGL pulls down the potential of the pull-up node PU to reset the pull-up node PU. Since the potential of the pull-up node PU is pulled down, the third transistor M3 is turned off, and the signal output terminal OUTPUT and the cascade signal output terminal OUT_C ​​no longer output high-level signals. At the same time, the first pull-down control node PD_CN1 and the first pull-down node PD1 are both high-level signals, and the tenth transistor M10 and the eleventh transistor M11 are turned on, thereby reducing the noise of the pull-up node PU and the signal output terminal OUTPUT, until the next frame begins, the potential of the pull-up node PU is pulled up again.

[0152] In some embodiments, Figure 8 As shown, in order to reduce the load of the signal output terminal OUTPUT, a cascade subcircuit is also provided in the shift register. The cascade subcircuit responds to the potential of the pull-up node PU, and outputs the clock signal input by the clock signal terminal CLK through the cascade signal output terminal OUT_C. The cascade signal output terminal OUT_C ​​is the same as the signal output by the signal output terminal OUTPUT. For example, the cascade signal output terminal OUT_C ​​outputs a high-level signal to the pull-up reset signal terminal RESET_PU of the upper-level shift register unit, and the signal input terminal INPUT of the next-level shift register unit. The cascade subcircuit includes a thirteenth transistor M13, the gate of the thirteenth transistor M13 is connected to the pull-up node PU, the source of the thirteenth transistor M13 is connected to the clock signal terminal CLK, and the drain of the thirteenth transistor M13 is connected to the cascade signal terminal OUT_C. In addition, a twelfth transistor is also provided in both the first noise reduction subcircuit and the second noise reduction subcircuit, represented by M12 and M12', respectively, for noise reduction of the signal output by the cascade signal output terminal OUT_C. The gate of the twelfth transistor M12 is connected to the first pull-down node PD1, the source of the twelfth transistor M12 is connected to the cascade signal output terminal OUT_C, and the drain of the twelfth transistor M12 is connected to the low-level signal terminal LVGL. The gate of the twelfth transistor M12' is connected to the second pull-down node PD2, the source of the twelfth transistor M12' is connected to the cascade signal output terminal OUT_C, and the drain of the twelfth transistor M12' is connected to the low-level signal terminal LVGL.

[0153] The separate provision of the cascade sub-circuit can reduce the load of the signal output terminal OUTPUT, so as to avoid affecting the gate scanning signal outputted by the signal output terminal OUTPUT.

[0154] For the gate drive circuit using the above shift register unit, Figure 8As shown, the cascade signal output terminal OUT_C ​​of the shift register unit at this stage is connected to the pull-up reset signal terminal RESET_PU of the shift register at the previous stage, and the signal input terminal INPUT of the shift register unit at the next stage. It should be understood that the cascade sub-circuit may not be provided in the above-mentioned shift register unit. In this case, the signal output terminal OUTPUT of the shift register unit at this stage is connected to the pull-up reset signal terminal RESET_PU of the shift register at the previous stage, and the signal input terminal INPUT of the shift register unit at the next stage.

[0155] In addition, Figure 7 In comparison, Figure 8 In the embodiment, the drains of the eleventh transistors M11 and M11' are connected to the low level signal terminal VGL, and the drains of other transistors that need to be connected to the low level signal terminal are all connected to the low level signal terminal LVGL.

[0156] So far, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution disclosed here.

[0157] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An array substrate, comprising a first base substrate, a plurality of data lines, and a plurality of sub-pixels connected to the plurality of data lines, at least one of the plurality of sub-pixels comprising: A first insulating layer, located on one side of the first substrate; A gate, located between the first substrate and the first insulating layer; An active layer, located on a side of the first insulating layer away from the gate; A pixel electrode, located on a side of the first insulating layer away from the first substrate; a first electrode, located on a side of the active layer and the pixel electrode away from the first substrate, the first electrode being connected to the active layer and in contact with the pixel electrode; a second electrode spaced apart from the first electrode and connected to the active layer and one of the plurality of data lines; a second insulating layer, located on a side of the pixel electrode, the first electrode and the second electrode away from the first base substrate, and having a first opening, wherein an orthographic projection of the first opening on the first base substrate overlaps with an orthographic projection of the pixel electrode on the first base substrate, and overlaps with an orthographic projection of the first electrode on the first base substrate; a connecting electrode, contacting the pixel electrode and the first electrode through the first opening; and a common electrode, located on a side of the second insulating layer away from the pixel electrode and spaced apart from the connecting electrode; The plurality of sub-pixels include a plurality of rows of sub-pixels, and the array substrate further includes a plurality of common voltage lines connected to the plurality of rows of sub-pixels, each common voltage line being configured to apply a common voltage to a common electrode of a corresponding row of sub-pixels in the plurality of rows of sub-pixels; The common voltage line includes a first common voltage line portion, a second common voltage line portion, and a third common voltage line portion, the third common voltage line portion is located between the first common voltage line portion and the second common voltage line portion, and is adjacent to the first common voltage line portion and the second common voltage line portion, respectively, a length of the second common voltage line portion in a first direction perpendicular to a second direction in which the common voltage line extends is greater than a length of the first common voltage line portion in the first direction, and a length of the first common voltage line portion in the first direction is greater than a length of the third common voltage line portion in the first direction; The common electrode of each sub-pixel in each row of sub-pixels contacts the second common voltage line portion of a corresponding common voltage line through the second opening of the second insulating layer.

2. The array substrate according to claim 1, wherein: Common electrodes of some of the sub-pixels are connected to each other, and common electrodes of the remaining sub-pixels are spaced apart from each other.

3. The array substrate according to claim 2, wherein: The multiple sub-pixels include multiple columns of sub-pixels, the partial sub-pixels include at least one column of sub-pixels in the multiple columns of sub-pixels, each column of sub-pixels in the at least one column of sub-pixels includes two adjacent sub-pixels, and two common electrodes of the two adjacent sub-pixels are connected through a common electrode connector.

4. The array substrate according to claim 3, wherein: The plurality of sub-pixels include a plurality of rows of sub-pixels, two gates of two adjacent sub-pixels in each row of the plurality of rows of sub-pixels are connected via a gate connector, and the gate connector partially overlaps the common electrode connector and the data line.

5. The array substrate according to claim 4, wherein: The data line extends along a first direction, and the data line includes: a first data line portion that does not overlap the gate connection member; and A second data line portion adjacent to the first data line portion partially overlaps the gate connector, wherein a length of the second data line portion in a second direction perpendicular to the first direction is greater than a length of the first data line portion in the second direction.

6. The array substrate according to claim 4, wherein: An angle between an extension direction of the gate connector and the first direction is greater than or equal to 45 degrees and less than 90 degrees.

7. The array substrate according to claim 5, wherein: A ratio of a length of the second data line portion in the second direction to a length of the first data line portion in the second direction is greater than 1 and less than or equal to 1.

4.

8. The array substrate according to claim 3, wherein: The plurality of columns of sub-pixels include a plurality of columns of first sub-pixels configured to emit light of a first color, a plurality of columns of second sub-pixels configured to emit light of a second color, and a plurality of columns of third sub-pixels configured to emit light of a third color, two adjacent columns of the plurality of columns of third sub-pixels are separated by a column of first sub-pixels in the plurality of columns of first sub-pixels and a column of second sub-pixels in the plurality of columns of second sub-pixels, and the first color, the second color, and the third color are different from each other; The at least one column of sub-pixels includes two or more columns of third sub-pixels among the multiple columns of third sub-pixels.

9. The array substrate according to claim 8, wherein: Two adjacent columns of the two or more columns of third sub-pixels are separated by one column of the plurality of columns of third sub-pixels other than the two or more columns of third sub-pixels.

10. The array substrate according to claim 3, wherein: The two common electrodes are integrally arranged with the common electrode connector.

11. The array substrate according to any one of claims 1 to 10, further comprising: The first alignment layer is located at a side of the common electrode away from the first substrate.

12. The array substrate according to any one of claims 1 to 10, wherein: The common electrode of each sub-pixel in each row of sub-pixels contacts the first base substrate through the second opening.

13. The array substrate according to any one of claims 1 to 10, wherein: The plurality of common voltage lines and the gate are located at the same layer.

14. The array substrate according to any one of claims 1 to 10, wherein: The common electrode and the connecting electrode are located in the same layer.

15. The array substrate according to any one of claims 1 to 10, wherein: The common electrode comprises: A first electrode portion having a slit and located at a side of the connection electrode away from the gate; and The second electrode portion adjacent to the first electrode portion has no slit and is located at a side of the connecting electrode away from the data line.

16. A display device, comprising: An array substrate as described in any one of claims 1 to 15.

17. The display device according to claim 16, further comprising a color filter substrate disposed opposite to the array substrate, the color filter substrate comprising: a second substrate base plate; A black matrix and a filter layer are located on a side of the second base substrate close to the array substrate, the filter layer includes a plurality of filter units, and adjacent filter units in the plurality of filter units are separated by the black matrix; A planarization layer, located on a side of the black matrix and the filter layer close to the array substrate; and A plurality of spacers are located between the planarization layer and the array substrate, and an orthographic projection of each of the plurality of spacers on the second base substrate is located within an orthographic projection of the black matrix on the second base substrate.

18. The display device according to claim 17, wherein: The plurality of sub-pixels include a plurality of columns of first sub-pixels configured to emit light of a first color, a plurality of columns of second sub-pixels configured to emit light of a second color, and a plurality of columns of third sub-pixels configured to emit light of a third color, two adjacent columns of second sub-pixels in the plurality of columns of second sub-pixels are separated by a column of first sub-pixels in the plurality of columns of first sub-pixels and a column of third sub-pixels in the plurality of columns of third sub-pixels, and the first color, the second color, and the third color are different from each other; as well as The multiple spacers include multiple columns of spacers corresponding to the multiple columns of second sub-pixels, the orthographic projection of each spacer in each column of the multiple columns of spacers on the first substrate is a first projection, the orthographic projection of the gate of a second sub-pixel in a column of second sub-pixels corresponding to each column of spacers in the multiple columns of second sub-pixels on the first substrate is a second projection, the orthographic projection of the active layer of the second sub-pixel on the first substrate is a third projection, the orthographic projection of the data line connected to the second sub-pixel on the first substrate is a fourth projection, and the first projection is located within the second projection and on a side of the third projection away from the fourth projection.

19. The display device according to claim 18, wherein: The second color is red.

20. The display device according to claim 18, wherein: The area not covered by the black matrix of each first subpixel in the multiple columns of first subpixels, each second subpixel in the multiple columns of second subpixels, and each third subpixel in the multiple columns of third subpixels is a light-emitting area, and the area of ​​the light-emitting area of ​​each second subpixel is smaller than the area of ​​the light-emitting area of ​​each first subpixel and the area of ​​the light-emitting area of ​​each third subpixel.

21. The display device according to claim 18, wherein: The second sub-pixel further includes a plurality of blocking parts, wherein the orthographic projection of each of the plurality of blocking parts on the first substrate is located within the orthographic projection of the black matrix on the first substrate, and the plurality of blocking parts include: A first blocking portion is located at a side of a spacer corresponding to the second sub-pixel among the plurality of spacers and close to the pixel electrode; and The second blocking portion is located at a side of the first blocking portion away from the spacer, and the height of the second blocking portion is greater than the height of the first blocking portion.

22. The display device according to claim 21, wherein: The area of ​​the second sub-pixel not covered by the black matrix is ​​a light-emitting area; The first blocking portion and the second blocking portion are located at a first side of the light emitting area; as well as The plurality of blocking portions further includes a third blocking portion located at a second side of the light emitting region opposite to the first side.

23. The display device according to claim 22, wherein: The first blocking portion includes a first layer, a second layer, a third layer, a fourth layer and a fifth layer sequentially arranged on the one side of the first base substrate; At least one of the second barrier portion and the third barrier portion includes a sixth layer, a seventh layer, an eighth layer, a ninth layer, a tenth layer and an eleventh layer sequentially disposed on the one side of the first base substrate; as well as The first layer, the seventh layer and the first insulating layer are located on the same layer, the second layer, the eighth layer and the pixel electrode are located on the same layer, the third layer, the ninth layer and the first electrode are located on the same layer, the fourth layer, the tenth layer and the second insulating layer are located on the same layer, the fifth layer, the eleventh layer and the common electrode are located on the same layer, and the sixth layer and the gate are located on the same layer.

24. A method for manufacturing an array substrate, comprising forming a plurality of data lines and a plurality of sub-pixels on one side of a first base substrate, wherein forming at least one of the plurality of sub-pixels comprises: forming a gate on the one side of the first substrate; forming a first insulating layer on a side of the gate away from the first substrate; forming an active layer on a side of the first insulating layer away from the gate; forming a pixel electrode on a side of the first insulating layer away from the first base substrate; A first electrode and a second electrode are formed, wherein: The first electrode is located on a side of the active layer and the pixel electrode away from the first substrate, connected to the active layer, and in contact with the pixel electrode. The second electrode is spaced apart from the first electrode and connected to the active layer and one of the plurality of data lines; forming a second insulating layer on a side of the pixel electrode, the first electrode and the second electrode away from the first base substrate, the second insulating layer having a first opening, an orthographic projection of the first opening on the first base substrate overlapping with an orthographic projection of the pixel electrode on the first base substrate, and overlapping with an orthographic projection of the first electrode on the first base substrate; and forming a connecting electrode and a common electrode spaced apart from the connecting electrode, wherein the connecting electrode contacts the pixel electrode and the first electrode through the first opening, and the common electrode is located on a side of the second insulating layer away from the pixel electrode; Wherein, the plurality of sub-pixels include a plurality of rows of sub-pixels, and the method further includes forming a plurality of common voltage lines connected to the plurality of rows of sub-pixels, each common voltage line being configured to apply a common voltage to a common electrode of a corresponding row of sub-pixels in the plurality of rows of sub-pixels; The common voltage line includes a first common voltage line portion, a second common voltage line portion, and a third common voltage line portion, the third common voltage line portion is located between the first common voltage line portion and the second common voltage line portion, and is adjacent to the first common voltage line portion and the second common voltage line portion, respectively, a length of the second common voltage line portion in a first direction perpendicular to a second direction in which the common voltage line extends is greater than a length of the first common voltage line portion in the first direction, and a length of the first common voltage line portion in the first direction is greater than a length of the third common voltage line portion in the first direction; The common electrode of each sub-pixel in each row of sub-pixels contacts the second common voltage line portion of a corresponding common voltage line through the second opening of the second insulating layer.

25. The method according to claim 24, wherein: Forming the second insulating layer includes: forming an insulating material layer covering the pixel electrode, the first electrode and the second electrode; forming a mask having a third opening on a side of the insulating material layer away from the first substrate; and The insulating material layer is patterned using the mask to obtain the second insulating layer.

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