An integrated computing device, chip, board, apparatus, and computing method

Abstract

The present disclosure discloses an integrated computing device, a machine learning operation device, a neural network chip, a board card, an electronic device and a method. The integrated computing device can be included in a combined processing device, which can also include an interface device and other processing devices. The integrated computing device interacts with other processing devices to jointly complete a user-specified computing operation. The combined processing device can also include a storage device connected to the integrated computing device and the other processing devices, respectively, for storing data of the integrated computing device and the other processing devices. The scheme of the present disclosure can start and / or stop the circuit according to the preset rule, avoiding the problem of excessive instantaneous current caused by simultaneous starting.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of computer technology. More particularly, the present disclosure relates to an integrated computing device, a machine learning operation device, a neural network chip, a board card, an electronic device and a method. BACKGROUND

[0002] Existing artificial intelligence operations often involve a large amount of data operations, such as convolution operations, image processing, etc. With the increase of data volume, the operation amount and storage amount involved in data operations such as matrix operations will increase sharply due to the increase of data scale.

[0003] Therefore, in some operation processing circuits, multiple hardware architectures are used to flexibly select suitable processing circuits according to actual needs. For example, multiple circuits are simultaneously present in a chip for parallel processing of data. However, when such a chip is started, if all circuits are started at the same time, it is easy to cause excessive instantaneous current, resulting in excessive instantaneous power consumption, thereby causing some failure phenomena on the hardware; or even unknown errors are triggered, causing the chip to run abnormally. SUMMARY

[0004] In order to at least solve one or more technical problems as mentioned above, the present disclosure proposes, in various aspects, a technical solution that each circuit is started and / or closed in turn according to a preset rule, thereby avoiding the problem of excessive instantaneous current caused by simultaneous starting.

[0005] In a first aspect, the present disclosure provides an integrated computing device comprising a first circuit and a plurality of second circuits, wherein when starting and / or closing the integrated computing device, the first circuit is configured to: send control information to all or part of the plurality of second circuits according to a predetermined rule to indicate that the second circuits are started and / or closed in turn in a sequence; and the second circuit is configured to: in response to receiving the control information, start and / or close the second circuit in turn in the sequence.

[0006] In a second aspect, the present disclosure provides a machine learning operation device, wherein the machine learning operation device comprises one or more integrated computing devices according to any embodiment of the first aspect of the present disclosure.

[0007] In a third aspect, the present disclosure provides a neural network chip, comprising a machine learning operation device according to any embodiment of the second aspect of the present disclosure.

[0008] In a fourth aspect, the present disclosure provides a board card, comprising a neural network chip according to any embodiment of the third aspect of the present disclosure.

[0009] In a fifth aspect, this disclosure provides an electronic device that includes a board as described in any embodiment of the fourth aspect of this disclosure.

[0010] In a sixth aspect, this disclosure provides a method for an integrated computing device, the integrated computing device including a first circuit and a plurality of second circuits, wherein, when the integrated computing device is started and / or turned off, the first circuit sends control information to all or part of the plurality of second circuits according to a predetermined rule to instruct the second circuits to be started and / or turned off sequentially; and the second circuits, in response to receiving the control information, start and / or turn off the second circuits sequentially in the order stated.

[0011] By utilizing the integrated computing device, machine learning computing device, neural network chip, circuit board, electronic device, and method for integrating the computing device as described above, the disclosed solution sequentially starts and / or shuts down all or part of the circuits according to preset rules, avoiding the potential hazards caused by excessive instantaneous current. In some embodiments, the information controlling the start-up and / or shutdown can be indicated using the data status of data transmitted between circuits, thereby reducing signal and line overhead. In other embodiments, the information controlling the start-up and / or shutdown can be indicated using a dedicated enable signal, thereby simplifying the control method. Attached Figure Description

[0012] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0013] Figure 1 A general architecture diagram of an integrated computing device 100 according to an embodiment of this disclosure is shown;

[0014] Figure 2 An exemplary schematic block diagram of a circuit startup scheme according to an embodiment of this disclosure is shown;

[0015] Figure 3 An exemplary schematic block diagram of a circuit startup scheme according to another embodiment of this disclosure is shown;

[0016] Figure 4 An exemplary schematic block diagram of a circuit shutdown scheme according to an embodiment of this disclosure is shown;

[0017] Figure 5 An exemplary schematic block diagram of a circuit startup scheme according to yet another embodiment of this disclosure is shown;

[0018] Figure 6An exemplary topology of a second circuit according to an embodiment of this disclosure is shown;

[0019] Figure 7 Another exemplary topology of the second circuit according to an embodiment of this disclosure is shown;

[0020] Figure 8 An exemplary flowchart of a method 800 for integrating a computing device according to an embodiment of this disclosure is shown;

[0021] Figure 9 A structural diagram of a combined processing apparatus according to an embodiment of the present disclosure is shown; and

[0022] Figure 10 A schematic diagram of the structure of a board card according to an embodiment of this disclosure is shown. Detailed Implementation

[0023] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0024] It should be understood that the terms "first" and "second," etc., in the claims, specification, and drawings of this disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0025] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0026] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0027] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0028] Figure 1 A general architecture diagram of an integrated computing device 100 according to an embodiment of this disclosure is shown. Figure 1 As shown, the integrated computing device 100 disclosed herein can be used to perform deep learning computations, and may include a storage circuit 10, a control circuit 11 and a computing circuit 12, which are interconnected to transmit various data and instructions.

[0029] The control circuit 11 is used to coordinate and control the operation of the arithmetic circuit 12 and the storage circuit 10. The control circuit 11 may include, for example, an instruction fetch unit (IFU) 111 and an instruction decode unit (IDU) 112.

[0030] In various arithmetic operations, such as calculations, the control circuit 11 can be configured to acquire and parse calculation instructions to obtain arithmetic instructions, and then send the arithmetic instructions to the arithmetic circuit 12 and the storage circuit 10. The calculation instructions can be a form of hardware instruction and include one or more opcodes, each opcode representing one or more specific operations to be executed by the arithmetic circuit 114. These operations can include different types depending on the application scenario, such as arithmetic operations like addition or multiplication, logical operations, comparison operations, or table lookup operations, or any combination of the aforementioned operations. Correspondingly, the arithmetic instructions can be one or more microinstructions executed internally by the arithmetic circuit after parsing the calculation instructions.

[0031] Furthermore, depending on the application scenario, the arithmetic instruction obtained after parsing the calculation instruction can be an arithmetic instruction decoded by the control circuit 11 or an arithmetic instruction not decoded by the control circuit 11. When the arithmetic instruction is an arithmetic instruction not decoded by the control circuit 11, the arithmetic circuit 12 may include a corresponding decoding circuit to perform the decoding of the arithmetic instruction, so as to obtain, for example, multiple microinstructions.

[0032] The operational circuit 12 may include a first circuit 121 and a plurality of second circuits 122. The first circuit and the second circuits, as well as the plurality of second circuits, can communicate with each other through various connections.

[0033] The first circuit can be configured as the master circuit, and multiple second circuits can be configured as slave circuits, allowing the first and second circuits to cooperate and achieve parallel computation. In this configuration, the first circuit can, for example, perform pre-processing on input data, transmit data and computation instructions to one or more second circuits, and receive intermediate results from the second circuits and perform subsequent processing to obtain the final computation result of the computation instructions. The second circuits can, for example, perform intermediate operations in parallel based on the data and computation instructions transmitted from the first circuit to obtain multiple intermediate results, and transmit these intermediate results back to the first circuit.

[0034] In different application scenarios, the connection between multiple second circuits can be either a hard connection through hard wiring or a logical connection configured according to, for example, microinstructions, to form various topologies of second circuit arrays. Several examples of second circuit topologies will be given later with reference to the accompanying drawings.

[0035] By configuring the arithmetic circuit 12 into a master-slave structure (e.g., a master-multiple-slave structure, or a multi-master-multiple-slave structure, which is not limited in this disclosure), for the calculation instructions of forward operation, the data can be split according to the calculation instructions, so that the part with a large amount of calculation can be operated in parallel by multiple second circuits, thereby improving the calculation speed, saving calculation time, and reducing power consumption.

[0036] To support computational functions, the first and second circuits may include various computing circuits, such as vector operation units and matrix operation units. The vector operation unit is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit is responsible for the core computations of deep learning algorithms, such as matrix multiplication and convolution.

[0037] Storage circuit 10 is used to store or move relevant data. In deep learning, storage circuitry can be used to store computational data such as neurons and weights, or to store computation results. Storage circuitry may include, for example, one or any combination of cache 102, register 104, and direct memory access (DMA) module 106. Direct memory access module DMA 106 can be used to interact with off-chip memory (not shown).

[0038] The foregoing describes an exemplary integrated computing device according to embodiments of the present disclosure, in which the first circuit and the second circuit may belong to different modules of the same processor or chip, or to different processors, and the present disclosure is not limited in this respect.

[0039] To support increasingly large-scale computing processing, integrated computing devices include more and more circuits. During the startup process, activating multiple circuits simultaneously can easily cause excessive instantaneous current, potentially leading to hardware errors and triggering unknown faults, resulting in malfunctions. Therefore, this disclosure proposes a scheme to sequentially activate and / or sequentially deactivate circuits in the integrated computing device according to preset rules, thereby avoiding the hazards caused by excessive instantaneous current due to simultaneous startup.

[0040] In some embodiments, the first circuit described above can be configured to send control information to all or part of a plurality of second circuits according to a predetermined rule, to instruct the second circuits to start and / or shut down sequentially. Accordingly, the second circuits can be configured to perform start and / or shutdown operations sequentially in a specified order in response to receiving the control information.

[0041] Depending on the scale of the computation and the task allocation, the entire second circuit may be required to participate in the computation, or only a portion of the second circuit may be needed. In some embodiments, when only a portion of the second circuit is required, the aforementioned sequential startup scheme can be activated only if the predicted startup current exceeds a preset threshold, thereby shortening the startup time safely.

[0042] Information transmitted between circuits can generally be divided into two categories: data and control.

[0043] In some embodiments disclosed herein, the control information used to indicate the start-up and / or shutdown of the second circuit can be implicitly indicated, for example, through the data status of data transmitted between the circuits. In schemes employing implicit indication, at least two indication mechanisms can be provided based on the scope of responsibility of the first circuit.

[0044] In one implementation, the first circuit is responsible for all control information for starting and / or shutting down the second circuit. In this implementation, the first circuit can be configured to set corresponding data states for the second circuit to be started and / or shut down, thereby triggering the operation of the corresponding second circuit through these data states. Accordingly, the second circuit can be configured to perform start-up and / or shutdown in response to the received data states.

[0045] In another implementation, the first circuit is responsible for controlling only one second circuit, which can be the first second circuit in a connection of multiple second circuits. In this implementation, the first circuit can be configured to set the corresponding data state for the first second circuit to be started and / or stopped, thereby triggering the operation of the first second circuit through the data state. Control information for starting and / or stopping the remaining second circuits can be triggered and propagated by the first second circuit.

[0046] Accordingly, during startup, the second circuit can be configured to start in response to a received data status indication; set the corresponding data status for the next second circuit; and pass the set data status to the next second circuit. Through this method of setting control information from the preceding circuit to the following circuit, each second circuit can be started sequentially.

[0047] During the shutdown process, the second circuit can be configured to perform corresponding data processing in response to a received data status indication to shut down; set a corresponding data status for the previous second circuit; pass the set data status forward to the previous second circuit; and shut down the current second circuit.

[0048] Note that the terms "before" and "after" mentioned in this disclosure are relative to the direction from the first circuit to the second circuit. In essence, they refer to the current circuit on the transmission link setting control information for the next circuit on the transmission link.

[0049] In both implementations that use implicit indication, control information is indicated by the data status of the transmitted data, and there may be multiple ways for data to be transmitted between circuits.

[0050] Taking the first and second circuits configured as a master-slave structure as an example, there are three scenarios for data transmission: (1) the master circuit broadcasts data to the slave circuit; (2) the master circuit distributes data to the slave circuit; and (3) the slave circuit sends the calculation result to the master circuit. Here, broadcasting means that the data is the same for all receivers, that is, each slave circuit receives the same data. Distribution means that the data can be different for all receivers, for example, each slave circuit receives different data.

[0051] In the field of deep learning, input neurons are typically broadcast data, while weights are typically distributed data. For example, in convolution operations, the master circuit broadcasts neurons to the slave circuits, which is the case described in (1) above. If the slave circuit has a corresponding storage unit, it can retrieve the weights from its own storage unit and perform convolution operations with the received neurons to obtain the result. Otherwise, the master circuit also needs to send weight data to the slave circuits, which is the case described in (2) above. Each slave circuit sends the result back to the master circuit, which is the case described in (3) above.

[0052] In the implementation of implicit indication, control information can be indicated by the data status of broadcast data or by the data status of distributed data, and this disclosure is not limited in this respect.

[0053] Figure 2 An exemplary schematic block diagram of a circuit startup scheme according to an embodiment of this disclosure is shown. Figure 2 The circuit startup process according to an embodiment of this disclosure is illustrated using a first circuit and four second circuits connected in a chain or series as an example. Figure 2 As shown, the first circuit 20 broadcasts data, such as neuron N, to four second circuits 21-1, 21-2, 21-3, and 21-4. The first circuit 20 prepares the neuron N to be transmitted and sets the corresponding data state, such as setting it to active. Then, the first circuit 20 transmits neuron N and its associated data state to the second circuit 21-1. To clearly show the startup sequence of each circuit, the actions of each cycle are described below in chronological order.

[0054] In the first cycle, the second circuit 21-1, in response to receiving the above-mentioned valid data state, starts the circuit, receives the neuron N, and passes the neuron N and the associated data state to the next circuit.

[0055] In the second cycle, in response to receiving the aforementioned valid data state from the second circuit 21-1, the second circuit 21-2 starts the circuit, receives the neuron N, and passes the neuron N and the associated data state to the next circuit.

[0056] In the third cycle, in response to receiving the aforementioned valid data state from the second circuit 21-2, the second circuit 21-3 starts the circuit, receives the neuron N, and passes the neuron N and the associated data state to the next circuit.

[0057] In the fourth cycle, in response to receiving the aforementioned valid data state from the second circuit 21-3, the second circuit 21-4 activates and receives the neuron N. At this point, all four second circuits have been activated sequentially.

[0058] In the above description, the data state set by the first circuit can be used by all second circuits. Those skilled in the art will understand that the broadcast-style data transmission also applies to situations where the current second circuit on the transmission link sets data state / control information for the next second circuit on the transmission link. This situation, where the current second circuit on the transmission link sets control information for the next second circuit, will be described below in conjunction with the distribution-style data transmission.

[0059] Figure 3An exemplary schematic block diagram of a circuit startup scheme according to another embodiment of this disclosure is shown. Figure 3 In this example, a first circuit and four second circuits connected in a chain or series are used to illustrate the circuit startup process according to an embodiment of this disclosure. Figure 3 As shown, the first circuit 20 distributes data to four second circuits 21-1, 21-2, 21-3, and 21-4, for example, the corresponding data are A, B, C, and D, respectively. The first circuit 20 prepares the data A, B, C, and D to be transmitted, and optionally also sets the corresponding data status for data A in the second circuit 21-1, for example, by setting it to valid. Then, the first circuit 20 transmits data A, B, C, and D, along with the related data status, to the second circuit 21-1. To clearly show the startup sequence of each circuit, the actions of each cycle are described below in chronological order.

[0060] In the first cycle, the second circuit 21-1, in response to receiving the aforementioned valid data state, starts the circuit and retrieves the required data A. Then, it sets the corresponding data state for the subsequent second circuit and transmits data B, C, and D, along with the related data state, to the subsequent second circuit.

[0061] In the second cycle, in response to receiving the aforementioned valid data state from the preceding second circuit 21-1, the second circuit 21-2 starts the circuit and retrieves the required data B. Then, it sets the corresponding data state for the subsequent second circuit and transmits data C and D, along with the associated data state, to the subsequent second circuit.

[0062] In the third cycle, in response to receiving the aforementioned valid data state from the second circuit 21-2, the second circuit 21-3 starts the circuit and retrieves the required data C. Then, it sets the corresponding data state for the next second circuit and transmits the data D and related data state to the next second circuit.

[0063] In the fourth cycle, in response to receiving the aforementioned valid data status from the second circuit 21-3, the second circuit 21-4 starts up and retrieves the required data D. At this point, all four second circuits have been started sequentially.

[0064] In the above description, the data state set by the first circuit is only used for the first second circuit 21-1, and subsequent second circuits are set by the second circuit preceding it on the connection link. Those skilled in the art will understand that the data transmission of the above distribution method is also applicable to the situation where the first circuit sets the corresponding data state for all second circuits to be started, which will not be described in detail here.

[0065] from Figure 2 and Figure 3As can be seen from the description, in broadcast mode, the data transmission bandwidth occupied by circuits is the same. In distribution mode, the data transmission bandwidth occupied by circuits decreases from large to small, with the earlier circuits experiencing greater bandwidth pressure.

[0066] Figure 4 An exemplary schematic block diagram of a circuit shutdown scheme according to one embodiment of this disclosure is shown. Figure 4 In this example, a first circuit and four second circuits connected in a chain or series are used to illustrate the circuit shutdown process according to an embodiment of this disclosure. Figure 4 As shown, the four second circuits 21-1, 21-2, 21-3, and 21-4 each complete their respective calculations and return the results to the first circuit. To clearly show the shutdown sequence of each circuit, the actions of each cycle are described below in chronological order.

[0067] In the first cycle, the second circuit 21-4 shuts down in response to the received data status indication, performs corresponding data processing, sets the corresponding data status for the preceding second circuit, and passes the data status forward to the preceding second circuit. Then, the second circuit 21-4 shuts down.

[0068] In the second cycle, the second circuit 21-3, in response to receiving a data status indication to shut down from the second circuit 21-4, performs corresponding data processing; sets the corresponding data status for the preceding second circuit; and passes the data status forward to the preceding second circuit. Then, the second circuit 21-3 shuts down.

[0069] In the third cycle, the second circuit 21-2, in response to receiving a data status indication to shut down from the second circuit 21-3, performs corresponding data processing; sets the corresponding data status for the preceding second circuit; and passes the data status forward to the preceding second circuit. Then, the second circuit 21-2 shuts down.

[0070] In the fourth cycle, the second circuit 21-1, in response to receiving a data status indication to shut down from the second circuit 21-2, performs corresponding data processing; sets the corresponding data status for the preceding second circuit; and passes this data status forward to the preceding second circuit. Then, the second circuit 21-1 shuts down. At this point, all four second circuits have been sequentially activated.

[0071] Data processing in each of the second circuits may include data processing within the current circuit itself, and / or fusion processing of its own data with data transmitted from the next second circuit. Fusion processing may include, for example, addition or concatenation, and this disclosure is not limited in this respect. Figure 4 The example shows an instance where the results of the calculations of the individual second circuits are directly concatenated and passed forward.

[0072] In other embodiments disclosed herein, the control information described above for indicating the activation and / or deactivation of the second circuit can be explicitly indicated, for example, by a dedicated enable signal. Similarly, in these embodiments, at least two enable signal indication mechanisms can be provided based on the scope of responsibility of the first circuit.

[0073] In one implementation, the first circuit is responsible for controlling all control information for the second circuits to be started and / or shut down. This approach can also be called "global enable / control". In this implementation, the first circuit can be configured to set corresponding enable signals for the second circuits to be started and / or shut down, thereby triggering the operation of the corresponding second circuits through the enable signals. Accordingly, the second circuits can be configured to perform start-up and / or shutdown in response to the received enable signals.

[0074] In another implementation, the first circuit is responsible for controlling only one second circuit, which can be the first second circuit in a connection of multiple second circuits. This approach can also be called "partial enable / control". In this implementation, the first circuit can be configured to set a corresponding enable signal for the first second circuit to be started and / or stopped, thereby triggering the operation of the first second circuit through the enable signal. Enable signals for starting and / or stopping the remaining second circuits can be triggered and propagated by the first second circuit.

[0075] Accordingly, during startup, the first second circuit can be configured to start the current second circuit in response to receiving an enable signal from the first circuit indicating startup. This second circuit is further configured to generate startup confirmation information for the current second circuit and pass this confirmation information to the next second circuit. For a non-first second circuit in the connection, it can be configured to start the current second circuit in response to receiving an enable signal indicating startup and receiving startup confirmation information from the previous second circuit. Similarly, this second circuit is further configured to generate startup confirmation information for the current second circuit and pass this confirmation information to the next second circuit. It is understood that for the last second circuit, startup confirmation information does not need to be generated after startup.

[0076] Similarly, during the shutdown process, the first (in the context of shutdown, "first" actually refers to the last end of the connection) second circuit can be configured to perform corresponding data processing in response to receiving an enable signal from the first circuit indicating shutdown. This second circuit is further configured to generate shutdown confirmation information for the current second circuit, pass this confirmation information forward to the preceding second circuit, and then shut down the current second circuit. For a non-first (in this case, non-last end) second circuit in the connection, it can be configured to perform corresponding data processing in response to receiving an enable signal indicating shutdown and receiving shutdown confirmation information from the next second circuit. Likewise, this second circuit is further configured to generate shutdown confirmation information for the current second circuit, pass this confirmation information forward to the preceding second circuit, and then shut down the current second circuit.

[0077] Similar to the preceding examples, data processing in each of the second circuits may include data processing within the current circuit itself, and / or fusion processing of its own data with data transmitted from the subsequent second circuit. Fusion processing may include, for example, addition or concatenation, and this disclosure is not limited in this respect.

[0078] In some embodiments, the aforementioned closing confirmation information may be sent together with the calculation result information of the second circuit. Depending on the data processing method allocated to the second circuit, the calculation result information may include at least one of the following: the calculation result of the current second circuit; the calculation result received from the subsequent second circuit; and the fusion result of the calculation result of the current second circuit and the calculation result of the subsequent second circuit.

[0079] Figure 5 An exemplary schematic block diagram of a circuit startup scheme according to yet another embodiment of this disclosure is shown. Figure 5 In this example, a first circuit and four second circuits connected in a chain or series are used to illustrate the circuit startup process according to an embodiment of this disclosure. Figure 5 As shown, regardless of the specific data path between the first circuit and the second circuit (represented by data interconnect 22 in the figure), there is at least one path for transmitting control signals between the first circuit 20 and the four second circuits 21-1, 21-2, 21-3 and 21-4, such as... Figure 5 As shown by the dashed line. In this example, the first circuit 20 prepares an enable signal (en), which will be transmitted along the path shown by the dashed line.

[0080] In one implementation, the enable signal may include, for example, four bits, each corresponding to one of the four second circuits. By setting the value of each bit, the activation and / or deactivation of these four second circuits can be controlled.

[0081] In another implementation, the startup and / or shutdown of the current second circuit can be determined based on the startup / shutdown state of the previous second circuit connected to it. To clearly show the startup sequence of each circuit, the actions of each cycle are described below in chronological order.

[0082] In the first cycle, the second circuit 21-1 starts the circuit in response to receiving an enable signal indicating that it has started. At this time, the second circuit 21-1 can also receive data passed to itself through the data path. Then, the second circuit 21-1 sets the enable signal indicating that it has started to be valid (e.g., set it to "1") and passes it to the next second circuit through the dashed path.

[0083] In the second cycle, the second circuit 21-2 starts in response to receiving an enable signal indicating its activation, and also upon receiving an enable signal from the preceding second circuit 21-1 indicating its activation. At this time, the second circuit 21-2 can receive data passed to itself via the data path. Then, the second circuit 21-2 sets the enable signal indicating its activation to active (e.g., to "1") and passes it to the next second circuit via the dashed path.

[0084] In the third cycle, the second circuit 21-3 starts in response to receiving an enable signal indicating its activation, and also upon receiving an enable signal from the preceding second circuit 21-2 indicating its activation. At this time, the second circuit 21-3 can receive data passed to itself via the data path. Then, the second circuit 21-3 sets the enable signal indicating its activation to active (e.g., to "1") and passes it to the next second circuit via the dashed path.

[0085] In the fourth cycle, the second circuit 21-4 starts in response to receiving an enable signal indicating its activation, and also starts upon receiving an enable signal from the preceding second circuit 21-3 indicating its activation. At this point, the second circuit 21-4 can receive data transmitted to it via the data path. Thus, all four second circuits have been activated sequentially.

[0086] The shutdown process is similar to the previous one, and will not be described in detail here.

[0087] Optionally or additionally, in some embodiments, the multiple second circuits included in the integrated computing device may be grouped, with each group of second circuits including at least one second circuit. In these embodiments, the sequential activation and / or sequential deactivation of the multiple second circuits may include at least one of the following: within a single group of second circuits, each second circuit is sequentially activated and / or sequentially deactivated; and / or between multiple groups of second circuits, each group of second circuits is sequentially activated and / or sequentially deactivated.

[0088] The following describes an example of grouping second circuits using specific topological connections between multiple second circuits.

[0089] Figure 6 An exemplary topology of a second circuit according to an embodiment of this disclosure is shown. Figure 6 As shown, multiple second circuits 61 are arranged in an array, comprising M rows and N columns. Within each row, the second circuits are connected sequentially; within each column, they are also connected sequentially, meaning each second circuit is connected to its adjacent second circuit. A first circuit 60 connects K of these multiple second circuits. These K second circuits are: the N second circuits in the first row, the N second circuits in the Mth row, and the M second circuits in the first column. It should be noted that these K second circuits connected to the first circuit can directly receive data and / or control signals from the first circuit.

[0090] In this array-like distribution, the second circuits can be grouped according to their row and column connections. For example, second circuits in the same row can be grouped into one second circuit group, or second circuits in the same column can be grouped into another second circuit group.

[0091] In some embodiments, within each second circuit group, the second circuits can be sequentially started and / or shut down according to their connection relationships, thereby avoiding simultaneous startup that would result in high current. In this case, the second circuit groups can be started simultaneously or sequentially. Since the number of circuits starting simultaneously is reduced through grouping, even if the groups start simultaneously, the instantaneous current is significantly reduced compared to all starting simultaneously. Depending on the connection relationship between the first and second circuits, the first starting / shutting second circuit within each circuit group can be different. Correspondingly, the startup / shutting order within the circuit group can also take various forms; for example, control information can be transmitted symmetrically from the first, last, or middle second circuit to both sides, or from any position to both sides. This disclosure embodiment is not limited in this respect. For example, in... Figure 6 In the example shown, when grouped by column, the first second circuit to start / stop in each column can be either the topmost or the bottommost second circuit. When grouped by row, the first second circuit to start in each row is the leftmost second circuit.

[0092] Optionally or additionally, among multiple second circuit groups, each second circuit group can be started and / or shut down sequentially. For example, M circuit groups (by row) can be started / shut down sequentially; or N circuit groups (by column) can be started / shut down sequentially. Similarly, circuit groups can be started simultaneously or sequentially.

[0093] Figure 7Another exemplary topology of the second circuit according to an embodiment of this disclosure is shown. Figure 7 As shown, the first circuit 70 and multiple second circuits 71 can be connected via a tree interconnect 72. The tree interconnect 72 may include a root node, multiple subtree nodes, and multiple leaf nodes. The root node is connected to the first circuit 70, and the multiple leaf nodes are respectively connected to one of the multiple second circuits 71. Based on this tree interconnect structure, the second circuit group may include the second circuits connected to the leaf nodes belonging to the same subtree node.

[0094] In this tree-like interconnection structure, the second circuit can be divided according to the subtree node to which it belongs. For example, second circuits connected to leaf nodes belonging to the same subtree node can be grouped into a second circuit group. Depending on the level of the subtree node, there can be many different ways to divide the circuit.

[0095] Figure 7 The diagram illustrates a binary tree structure for tree interconnection. As those skilled in the art will understand, it can also be a ternary tree, a quadtree, or other types of tree interconnection.

[0096] for Figure 7 For example, during startup, circuits in any two subtree nodes belonging to the same top-level subtree can be turned on simultaneously. For instance, the activation of each pair of second circuits can be controlled based on an enable signal or data state. Similarly, during shutdown, circuits in any two subtree nodes belonging to the same top-level subtree can be turned off simultaneously. For instance, based on the enable signal, in the first cycle, the two circuits of the first subtree node at the top level can forward the calculation result and then turn off; in the second cycle, the two circuits of the second subtree node at the top level can forward the calculation result and then turn off. And so on.

[0097] Although Figure 6 and Figure 7 Several specific topological connection structures are shown, and several examples of sequential start / stop are given based on these connection structures. However, those skilled in the art will understand that these connection structures can be changed, and the order of start / stop can also be changed. As long as the number of circuits that start / stop simultaneously is reduced, the purpose of the embodiments disclosed herein can be achieved.

[0098] Figure 8 An exemplary flowchart of a method 800 for integrating a computing device according to an embodiment of this disclosure is shown. As previously described, the method can be used to control a plurality of second circuits in the integrated computing device to be turned on and / or off sequentially, thereby avoiding potentially large instantaneous currents.

[0099] like Figure 8As shown, in step S810, the first circuit sends control information to all or part of the plurality of second circuits according to a predetermined rule, instructing these second circuits to start and / or shut down sequentially.

[0100] Next, in step S820, in response to receiving the above control information, the second circuit sequentially starts and / or sequentially shuts down the second circuit.

[0101] As mentioned earlier, control information can be implicitly indicated through the data status of data transmitted between circuits. Alternatively, control information can also be explicitly indicated directly through a dedicated enable signal.

[0102] When using the implicit instruction method, the first circuit can set the data status for all second circuits and globally control the start / stop sequence of the second circuits; alternatively, the first circuit can control only some of the second circuits and locally control the start / stop sequence of the second circuits. For example, in the case of grouping the second circuits, only one second circuit in each group can be controlled, and the other second circuits in the group can be controlled by this second circuit.

[0103] In some embodiments, when the first circuit sets a corresponding data state for the first second circuit to be started and / or shut down, during the startup process, the second circuit may start the current second circuit in response to a received data state indication; then set a corresponding data state for the next second circuit and pass that data state forward to the next second circuit. Similarly, during the shutdown process, the second circuit performs corresponding data processing in response to a received data state indication to shut down, sets a corresponding data state for the previous second circuit; passes that data state forward to the previous second circuit and then shuts down the current second circuit.

[0104] Similarly, when using an enable signal to explicitly indicate, the first circuit can set an enable signal for all second circuits to globally control the start / stop sequence of the second circuits; alternatively, the first circuit can control only some of the second circuits to locally control the start / stop sequence of the second circuits. For example, in the case of grouping the second circuits, only one second circuit in each group can be controlled, and the other second circuits in the group can be controlled by this second circuit.

[0105] In some embodiments employing partial enable, during startup, the second circuit may, in response to a received enable signal indicating startup and receiving startup confirmation information from the preceding second circuit, start the current second circuit; generate startup confirmation information for the current second circuit; and pass the startup confirmation information backward to the next second circuit. Similarly, during shutdown, the second circuit may, in response to a received enable signal indicating shutdown and receiving shutdown confirmation information from the next second circuit, perform corresponding data processing; generate shutdown confirmation information for the current second circuit; pass the shutdown confirmation information forward to the preceding second circuit; and shut down the current second circuit. In some embodiments, the shutdown confirmation information may be sent along with computation result information.

[0106] The method for integrating a computing device according to embodiments of the present disclosure has been described above with reference to flowchart illustrations. It should be noted that although the operations of the method of the invention are described in a specific order in the drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Rather, the steps depicted in the flowcharts may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0107] Those skilled in the art will understand that the various features and details described above in conjunction with the device block diagram are equally applicable. Figure 8 For the sake of brevity, the method will not be repeated here.

[0108] This disclosure also provides a machine learning computing device, comprising one or more of the previously described integrated computing devices, for acquiring data to be processed and control information from other processing devices, executing specified machine learning operations, and transmitting the execution results to peripheral devices via I / O interfaces. Peripheral devices include, for example, cameras, monitors, mice, keyboards, network cards, Wi-Fi interfaces, and servers. When more than one integrated computing device is included, the computing devices can be linked and transmit data through a specific structure, such as interconnecting and transmitting data via a PCIe bus, to support larger-scale machine learning operations. In this case, they can share the same control system or have their own independent control systems; they can share memory or each accelerator can have its own memory. Furthermore, their interconnection method can be any interconnection topology. This machine learning computing device has high compatibility and can be connected to various types of servers via a PCIe interface.

[0109] Figure 9 This is a structural diagram illustrating a combined processing apparatus 900 according to an embodiment of this disclosure. Figure 9As shown, the combined processing device 900 includes a computing processing device 902, an interface device 904, other processing devices 906, and a storage device 908. Depending on the application scenario, the computing processing device may include one or more computing devices 910, which can be configured to... Figure 1 The integrated computing device shown is used to perform the operations described herein in conjunction with the accompanying drawings.

[0110] In various embodiments, the computing processing apparatus disclosed herein can be configured to perform user-specified operations. In an exemplary application, the computing processing apparatus can be implemented as a multi-core artificial intelligence processor. Similarly, one or more computing devices included within the computing processing apparatus can be implemented as an artificial intelligence processor core or a portion of the hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as artificial intelligence processor cores or portions of the hardware structure of artificial intelligence processor cores, the computing processing apparatus disclosed herein can be considered to have a homogeneous multi-core architecture.

[0111] In exemplary operation, the computing processing device disclosed herein can interact with other processing devices through an interface device to jointly complete user-specified operations. Depending on the implementation, the other processing devices disclosed herein may include one or more types of processors such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and an artificial intelligence processor, both general-purpose and / or special-purpose processors. These processors may include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, the computing processing device disclosed herein can be considered to have a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, they can be considered to form a heterogeneous multi-core structure.

[0112] In one or more embodiments, the other processing device may serve as an interface between the computing processing device disclosed herein (which may be specifically embodied in artificial intelligence, such as neural network operations) and external data and control, performing basic controls including but not limited to data transfer, starting and / or stopping the computing device. In another embodiment, the other processing device may also cooperate with the computing processing device to jointly complete computational tasks.

[0113] In one or more embodiments, the interface device can be used to transfer data and control commands between a computing processing device and other processing devices. For example, the computing processing device can obtain input data from other processing devices via the interface device and write it to on-chip storage (or memory) of the computing processing device. Further, the computing processing device can obtain control commands from other processing devices via the interface device and write them to on-chip control cache of the computing processing device. Alternatively or optionally, the interface device can also read data from the storage device of the computing processing device and transmit it to other processing devices.

[0114] Additionally or optionally, the combined processing apparatus disclosed herein may further include a storage device. As shown in the figures, the storage device is connected to both the computing processing device and the other processing device. In one or more embodiments, the storage device may be used to store data from the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage of the computing processing device or other processing device.

[0115] In some embodiments, this disclosure also discloses a chip (e.g. Figure 10 The chip shown is 1002. In one implementation, the chip is a system-on-a-chip (SoC) and integrates one or more such... Figure 9 The combined processing unit shown is illustrated. This chip can be connected to external interface devices (such as...). Figure 10 The external interface device 1006 shown is connected to other related components. These related components may be, for example, a camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. In some applications, the chip may integrate other processing units (e.g., video codecs) and / or interface modules (e.g., DRAM interfaces). In some embodiments, this disclosure also discloses a chip package structure that includes the aforementioned chip. In some embodiments, this disclosure also discloses a board that includes the aforementioned chip package structure. The following will be combined with... Figure 10 This board is described in detail.

[0116] Figure 10 This is a schematic diagram illustrating the structure of a board 1000 according to an embodiment of this disclosure. For example... Figure 10As shown, the board includes a storage device 1004 for storing data, which includes one or more storage cells 1010. This storage device can be connected and transmit data with the controller 1008 and the aforementioned chip 1002 via, for example, a bus. Furthermore, the board also includes an external interface device 1006, configured for data relay or switching between the chip (or a chip in a chip package) and an external device 1012 (e.g., a server or computer). For example, data to be processed can be transferred from the external device to the chip via the external interface device. Alternatively, the calculation results of the chip can be transmitted back to the external device via the external interface device. Depending on the application scenario, the external interface device can have different interface forms; for example, it can adopt a standard PCIe interface.

[0117] In one or more embodiments, the controller in the disclosed board can be configured to regulate the state of the chip. Therefore, in one application scenario, the controller may include a microcontroller (MCU) for regulating the operating state of the chip.

[0118] Based on the above combination Figure 9 and Figure 10 Based on the description, those skilled in the art will understand that this disclosure also discloses an electronic device or apparatus that may include one or more of the aforementioned boards, one or more of the aforementioned chips, and / or one or more of the aforementioned combined processing apparatus.

[0119] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablets, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing, such as cloud computing, edge computing, and terminal applications. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present disclosure can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0120] It should be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions disclosed herein are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this document, those skilled in the art will understand that some steps can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions disclosed herein. In addition, depending on the solution, the description of some embodiments in this disclosure may have different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

[0121] In terms of specific implementation, based on the disclosure and teachings of this document, those skilled in the art will understand that several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or apparatus embodiments described above, this document divides them based on logical functions, but in actual implementation, there may be other division methods. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationships between different units or components, the connections discussed above in conjunction with the accompanying drawings can be direct or indirect couplings between units or components. In some scenarios, the aforementioned direct or indirect couplings involve communication connections utilizing interfaces, where the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0122] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this disclosure. Additionally, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically independently.

[0123] In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage device (CMSDD). Therefore, when the disclosed solution is embodied in a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, server, or network device) to execute some or all of the steps of the method described in the embodiments of this disclosure. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0124] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0125] The foregoing can be better understood in accordance with the following terms:

[0126] Clause 1. An integrated computing device, comprising a first circuit and a plurality of second circuits, wherein, when the integrated computing device is started and / or stopped,

[0127] The first circuit is configured to send control information to all or part of the plurality of second circuits according to a predetermined rule, instructing the second circuits to start and / or shut down sequentially; and

[0128] The second circuit is configured to: in response to receiving the control information, sequentially start and / or sequentially shut down the second circuit in the order stated.

[0129] Clause 2. The integrated computing device according to Clause 1, wherein the control information is indicated by the data status of data transmitted between the circuits.

[0130] Clause 3. The integrated computing device as described in Clause 2, wherein,

[0131] The first circuit is further configured to: set corresponding data states for the second circuit to be started and / or stopped; and

[0132] The second circuit is further configured to perform startup and / or shutdown in response to the received data status.

[0133] Clause 4. The integrated computing device according to Clause 2, wherein,

[0134] The first circuit is further configured to: set corresponding data states for the first second circuit to be started and / or turned off; and

[0135] The second circuit is further configured as follows:

[0136] In response to the received data status indication, the current second circuit is started;

[0137] Set the corresponding data state for the subsequent second circuit; and

[0138] The data state is then passed back to the next second circuit; and / or

[0139] The second circuit is further configured as follows:

[0140] In response to the received data status indication that the system is closed, perform the corresponding data processing.

[0141] Set the corresponding data status for the preceding and second circuits;

[0142] The data state is passed forward to the preceding second circuit; and

[0143] Shut down the current second circuit.

[0144] Clause 5. An integrated computing device according to any one of Clauses 2-4, wherein, when the integrated computing device is started, the transmitted data is the same or different for each of the second circuits.

[0145] Clause 6. The integrated computing device according to Clause 1, wherein the control information is indicated via an enable signal.

[0146] Clause 7. The integrated computing device as described in Clause 6, wherein,

[0147] The first circuit is further configured to: set a corresponding enable signal for the second circuit to be started and / or turned off; and

[0148] The second circuit is further configured to perform startup and / or shutdown in response to a received enable signal.

[0149] Clause 8. The integrated computing device as described in Clause 6, wherein,

[0150] The first circuit is further configured to: set an enable signal for starting and / or turning off the second circuit; and

[0151] The second circuit is further configured as follows:

[0152] In response to the received enable signal indicating startup and upon receiving startup confirmation information from the previous second circuit, the current second circuit is started;

[0153] Generate the start confirmation information for the current second circuit; and

[0154] The startup confirmation information is then passed to the next second circuit; and / or

[0155] The second circuit is further configured as follows:

[0156] In response to the received enable signal indicating shutdown and the receipt of shutdown confirmation information from the subsequent second circuit, perform the corresponding data processing;

[0157] Generate a confirmation message for the current second circuit to be closed;

[0158] The closing confirmation information is passed forward to the preceding second circuit; and

[0159] Shut down the current second circuit.

[0160] Clause 9. The integrated computing device as described in Clause 8, wherein the shutdown confirmation information is sent together with the computation result information.

[0161] Clause 10. The integrated computing device according to Clause 9, wherein the computation result information includes at least one of the following:

[0162] The current calculation result of the second circuit;

[0163] The calculation results received from the second circuit; and

[0164] The result of the fusion of the current second circuit's calculation result and the subsequent second circuit's calculation result.

[0165] Clause 11. The integrated computing device according to any one of Clauses 1-10, wherein the plurality of second circuits are divided into several groups of second circuits, each group of second circuits includes at least one second circuit, and the plurality of second circuits are sequentially started and / or sequentially shut down including:

[0166] Within a single second circuit group, each second circuit is sequentially started and / or sequentially shut down; and / or

[0167] Among the multiple second circuit groups, each second circuit group is started and / or shut down sequentially.

[0168] Clause 12. The integrated computing device according to Clause 11, wherein the plurality of second circuits are arranged in an array, each group of second circuits includes second circuits in the same row or column of the array, and the first circuit is serially connected to one of the second circuits in each group of second circuits.

[0169] Clause 13. The integrated computing device according to Clause 11, wherein the plurality of second circuits are connected to the first circuit via a tree interconnection, the tree interconnection including a root node, a plurality of subtree nodes and a plurality of leaf nodes, the root node being connected to the first circuit, and the plurality of leaf nodes being respectively connected to one of the plurality of second circuits; the second circuit group includes second circuits connected to leaf nodes belonging to the same subtree node.

[0170] Clause 14. A machine learning computing device, wherein the machine learning computing device comprises one or more integrated computing devices as described in any one of Clauses 1-13.

[0171] Clause 15. A neural network chip, characterized in that the neural network chip includes a machine learning computing device as described in Clause 14.

[0172] Clause 16. A board, characterized in that the board includes a neural network chip as described in Clause 15.

[0173] Clause 17. An electronic device, characterized in that the electronic device includes a board as described in Clause 16.

[0174] Clause 18. A method for integrating a computing device, the integrated computing device comprising a first circuit and a plurality of second circuits, wherein, when the integrated computing device is started and / or turned off,

[0175] The first circuit sends control information to all or part of the plurality of second circuits according to a predetermined rule, instructing the second circuits to start and / or shut down sequentially; and

[0176] In response to receiving the control information, the second circuit sequentially starts and / or sequentially shuts down the second circuit in the specified order.

[0177] Clause 19. The method according to Clause 18, wherein the control information is indicated by the data status of data transmitted between the circuits.

[0178] Clause 20. The method according to Clause 19, wherein the method further comprises:

[0179] The first circuit sets the corresponding data state for the second circuit to be started and / or turned off.

[0180] Clause 21. The method according to Clause 19, wherein the method further comprises:

[0181] The first circuit sets the corresponding data state for the first second circuit to be started and / or turned off; and

[0182] The second circuit starts in response to a received data status indication, including: starting the current second circuit; setting a corresponding data status for the subsequent second circuit; and passing the data status to the subsequent second circuit; and / or

[0183] The second circuit responds to the received data status indication to close by performing corresponding data processing; setting a corresponding data status for the previous second circuit; passing the data status forward to the previous second circuit; and closing the current second circuit.

[0184] Clause 22. The method according to Clause 18, wherein the control information is indicated via an enable signal.

[0185] Clause 23. The method according to Clause 22, wherein the method further comprises:

[0186] The first circuit sets a corresponding enable signal for the second circuit to be started and / or stopped; and

[0187] The second circuit responds to the received enable signal by performing startup and / or shutdown accordingly.

[0188] Clause 24. The method according to Clause 22, wherein the method further comprises:

[0189] The first circuit is configured with an enable signal to start and / or stop the second circuit; and

[0190] The second circuit, in response to a received enable signal indicating startup and receiving startup confirmation information from the previous second circuit, starts the current second circuit; generates startup confirmation information for the current second circuit; and passes the startup confirmation information to the next second circuit; and / or

[0191] The second circuit responds to the received enable signal indicating shutdown and receives shutdown confirmation information from the next second circuit, performs corresponding data processing; generates shutdown confirmation information for the current second circuit; passes the shutdown confirmation information forward to the previous second circuit; and shuts down the current second circuit.

[0192] Clause 25. The method according to Clause 24, wherein the closing confirmation information is sent together with the calculation result information.

[0193] Clause 26. The method according to any one of Clauses 18-25, wherein the plurality of second circuits are divided into several groups of second circuits, each group of second circuits includes at least one second circuit, and the plurality of second circuits are sequentially activated and / or sequentially deactivated, comprising:

[0194] Within a single second circuit group, each second circuit is sequentially started and / or sequentially shut down; and / or

[0195] Among the multiple second circuit groups, each second circuit group is started and / or shut down sequentially.

Claims

1. An integrated computing device, comprising a first circuit and a plurality of second circuits, wherein, When the integrated computing device is started and / or shut down The first circuit is configured to send control information to all or part of the plurality of second circuits according to a predetermined rule, instructing the second circuits to start and / or shut down sequentially; and The second circuit is configured to: in response to receiving the control information, sequentially start and / or sequentially shut down the second circuit in the order stated; The control information is indicated by the data status of the data transmitted between the circuits. The first circuit is further configured to set a corresponding data status for the second circuit to be started and / or stopped. The second circuit is further configured to start and / or stop the circuit in response to the received data status. The data transmitted between the circuits includes any one of the following: input neurons, weights, or the result of the convolution operation between neurons and weights. The data status is the state in which the data is set to whether it is valid.

2. The integrated computing device according to claim 1, wherein, The first circuit is further configured to: set corresponding data states for the first second circuit to be started and / or turned off; and The second circuit is further configured as follows: In response to the received data status indication, the current second circuit is started; Set the corresponding data states for the subsequent second circuit; and The data state is then passed back to the next second circuit; and / or The second circuit is further configured as follows: In response to the received data status indication that the system is closed, perform the corresponding data processing. Set the corresponding data status for the preceding and second circuits; The data state is passed forward to the preceding second circuit; and Shut down the current second circuit.

3. The integrated computing device according to claim 1, wherein, When the integrated computing device is started, the transmitted data may be the same or different for each of the second circuits.

4. The integrated computing device according to claim 1, wherein the plurality of second circuits are divided into several groups of second circuits, each group of second circuits includes at least one second circuit, and the plurality of second circuits are sequentially started and / or sequentially shut down, comprising: Within a single second circuit group, each second circuit is started and / or shut down sequentially; and / or Among the multiple second circuit groups, each second circuit group is started and / or shut down sequentially.

5. The integrated computing device according to claim 4, wherein, The plurality of second circuits are arranged in an array, and each second circuit group includes second circuits in the same row or column of the array, and the first circuit is connected in series with one of the second circuits in each second circuit group.

6. The integrated computing device according to claim 4, wherein, The plurality of second circuits are connected to the first circuit via a tree interconnection, the tree interconnection including a root node, a plurality of subtree nodes and a plurality of leaf nodes, the root node being connected to the first circuit, and the plurality of leaf nodes being connected to one of the plurality of second circuits respectively; the second circuit group includes the second circuits connected to the leaf nodes belonging to the same subtree node.

7. A machine learning computing device, wherein the machine learning computing device comprises one or more integrated computing devices as described in any one of claims 1-6.

8. A neural network chip, characterized in that, The neural network chip includes the machine learning computing device as described in claim 7.

9. A circuit board, characterized in that, The board includes the neural network chip as described in claim 8.

10. An electronic device, characterized in that, The electronic device includes the board as described in claim 9.

11. A method for integrating a computing device, the integrated computing device comprising a first circuit and a plurality of second circuits, wherein, When the integrated computing device is started and / or shut down The first circuit sends control information to all or part of the plurality of second circuits according to a predetermined rule, instructing the second circuits to start and / or shut down sequentially; and In response to receiving the control information, the second circuit sequentially starts and / or sequentially shuts down the second circuit in the specified order; The control information is indicated by the data status of the data transmitted between the circuits. The first circuit sets the corresponding data status for the second circuit to be started and / or stopped. The second circuit is configured to start and / or stop in response to the received data status. The data transmitted between the circuits includes any one of the following: input neurons, weights, or the result of the convolution operation between neurons and weights. The data status is the state in which the data is set to whether it is valid.

12. The method of claim 11, wherein, The method further includes: The first circuit sets the corresponding data state for the first second circuit to be started and / or turned off; and The second circuit starts in response to a received data status indication, including: starting the current second circuit; setting a corresponding data status for the subsequent second circuit; and passing the data status to the subsequent second circuit; and / or The second circuit responds to the received data status indication to close by performing corresponding data processing; setting a corresponding data status for the previous second circuit; passing the data status forward to the previous second circuit; and closing the current second circuit.

13. The method of claim 11, wherein the plurality of second circuits are divided into several groups of second circuits, each group of second circuits includes at least one second circuit, and the plurality of second circuits are sequentially started and / or sequentially shut down, comprising: Within a single second circuit group, each second circuit is started and / or shut down sequentially; and / or Among the multiple second circuit groups, each second circuit group is started and / or shut down sequentially.

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