A verification IP integration method and system based on chip verification

Abstract

The present invention provides a verification IP integration method and system based on chip verification. The method includes: in response to configuration information set by a user, performing rendering through a template engine to create a verification IP configuration file; instantiating verification IP components supporting protocols according to a UVM environment template file and the configuration information, and passing the configuration file to the verification IP components; compiling the verification IP source code, instantiating corresponding verification IP interfaces through the compiled verification IP interface files, and passing the instantiated verification IP interfaces to the verification IP components. On the basis of generating a set of general frameworks, the present invention, by obtaining the configuration information set by the user, realizes the automatic integration of VIP related to the verification platform under different projects and different requirements, shortens the time for verification engineers to read the corresponding VIP specification documents, and the automatic integration provides a general and unified integration solution, which is convenient for unified maintenance at different levels of verification and enhances its reusability.

Description

Technical Field

[0001] The present invention relates to the technical field of chip functional verification, and in particular to a verification IP integration method and system based on chip verification. Background Art

[0002] With the rapid development of integrated circuits, the functions of chips are becoming increasingly complex, the design complexity of chips is getting higher and higher, and the scale of on-chip devices is getting larger and larger, which brings great challenges to the front-end verification of chips. Chip verification engineers need to fully verify the functions of chips in terms of functional correctness and completeness. Through continuous development and industry practice, the most mainstream verification methodology at present is UVM (Universal Verification Methodology), and the verification language is SV (System Verilog, a hardware design and verification language). Verification environments and platforms based on SV and UVM are being applied more and more widely in the front-end verification of chips.

[0003] Often, the progress of chip projects is very tight. Facing increasingly complex functions, the chip verification tasks are getting heavier and heavier. How to improve verification efficiency and shorten verification time within a tight project cycle becomes extremely important for chip project development. At present, the design method based on IP reuse has been widely applied in the design of SoC (System on Chip). The on-chip bus and peripheral bus designs are crucial for SoC. For this reason, many on-chip bus standards have emerged in the industry. Among them, the AMBA on-chip bus launched by ARM has been favored by a large number of IP (Internet Protocol) developers and SoC system integrators and has become a mainstream industrial standard on-chip protocol. For these standard protocol IPs, verification engineers need to develop corresponding verification components VIP (Verification IP) and integrate these VIPs into the verification environment. VIP provides reliable and standard IP verification components for chip verification engineers, reducing the time for chip verification engineers to develop VIPs. However, integrating these VIPs into the UVM verification environment and performing path self-testing and verification is also a time-consuming and laborious task.

[0004] Currently, the AMBA bus protocol is basically the mainstream industrial standard on-chip protocol in ASIC design verification. In the test environment, the corresponding VIP has emerged and is widely used in major chip companies, providing a mature, reliable and highly portable verification IP solution for chip verification. The traditional verification automation generation platform only generates a set of general frameworks and does not integrate the corresponding VIP into the verification platform for specific projects. Verification engineers need to read the corresponding VIP specification documents to integrate the VIP into the verification platform, complete the connection between the DUT (Design Under Test) and the VIP, and perform relevant path tests. Undoubtedly, it will take more time to understand the use of the VIP and greatly increase the possibility of human errors. Summary of the Invention

[0005] The present invention provides a method and system for integrating verification IP based on chip verification, which is used to solve the problem that the existing verification platform cannot complete specific project tests through the VIP framework.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] The first aspect of the present invention provides a method for integrating verification IP based on chip verification, and the method includes the following steps:

[0008] Responding to the configuration information set by the user, rendering through the template engine to create a verification IP configuration file;

[0009] According to the UVM environment template file and the configuration information, instantiating the verification IP components supporting the protocol, and passing the configuration file to the verification IP components;

[0010] Compiling the verification IP source code, instantiating the corresponding verification IP interfaces through the compiled verification IP interface files, and passing the instantiated verification IP interfaces to the verification IP components.

[0011] Further, the configuration information includes the project name, the path and file name where the top-level file of the design under test is stored, the top-level module name of the design under test, and the parameters required for integrating the verification IP;

[0012] The required parameters include the protocol type, master-slave mode, address bit width, data bit width, and integration quantity.

[0013] Further, after generating the verification IP components, the method further includes the step of:

[0014] Establishing the connection relationship between the verification IP and the design under test DUT in the verification platform.

[0015] Further, the specific process of establishing the connection relationship between the verification IP and the design under test DUT is:

[0016] According to the DUT top-level file path and top-level module name defined by the user, the interface information of the DUT top-level module is obtained through regular matching;

[0017] According to the interface information, the signals of the interface module in the verification platform are defined, and the signals with the same names as the DUT interface signals in the verification platform interface module are connected;

[0018] According to the protocol type preset in the configuration information, the definition of the standard signal names of the current protocol type is determined, the top-level interface signals in the DUT are matched, the verification platform interface module connected to the matched signals is obtained, the connected verification platform interface module is deleted, and replaced with the verification IP interface.

[0019] Furthermore, after establishing the connection relationship between the verification IP and the design under test (DUT), the method further includes the steps of:

[0020] Conduct a path test on the DUT for the test sequence provided by the verification IP.

[0021] Furthermore, the path test includes read-write tests and slave response tests.

[0022] Furthermore, the path test is specifically:

[0023] Obtain the master-slave mode preset by the user;

[0024] If it is the master mode, obtain the read-write test sequence corresponding to the protocol type. When the user calls the read-write sequence, specify the address information, and obtain the read data for the read sequence and specify the write data for the write sequence;

[0025] If it is the slave mode, obtain the response test sequence corresponding to the protocol type. When the user calls the response sequence, specify the response time and response status.

[0026] The second aspect of the present invention provides a verification IP integration system based on chip verification. The system includes a VIP integration module, and the VIP integration module includes:

[0027] A configuration file generation unit, in response to the configuration information set by the user, performs rendering through a template engine to create a verification IP configuration file;

[0028] A protocol instantiation unit, according to the UVM environment template file and configuration information, instantiates the verification IP components that support the protocol, and passes the configuration file to the verification IP components;

[0029] An integrated VIP unit is used to compile the verification IP source code, instantiate the corresponding verification IP interfaces through the compiled verification IP interface files, and pass the instantiated verification IP interfaces to the verification IP components.

[0030] Further, the system further includes a connection module, which establishes a connection relationship between the verification IP and the design under test (DUT) in the verification platform.

[0031] Further, the system further includes a test module, which performs path tests on the DUT for the test sequences provided by the verification IP.

[0032] The control device of the network service in the second aspect of the present invention can implement the methods in the first aspect and the implementation manners of the first aspect, and achieve the same effects.

[0033] The effects provided in the invention content are only the effects of the embodiments, rather than all the effects of the invention. One of the technical solutions in the above technical solutions has the following advantages or beneficial effects:

[0034] 1. Compared with the traditional verification automation generation platform, on the basis of generating a set of general frameworks, the present invention greatly shortens the time for verification engineers to read the corresponding VIP specification documents by obtaining the configuration information set by users, and enables verification engineers to focus more on the protocol itself and functional verification, rather than the use and integration of VIP. Secondly, the automated integration provides a general and unified integration solution, which is convenient for unified maintenance at different levels of verification and enhances its reusability.

[0035] 2. The embodiments of the present invention realize the automatic connection between the DUT and the VIP and the automatic generation of relevant path tests. It reduces the cumbersome and repetitive wiring operations of verification engineers, reduces the human errors caused by carelessness of verification engineers during wiring work, and improves work efficiency at the same time; the automatic integration of path tests provides a basic test sequence for verification engineers, which is convenient for verification engineers to quickly construct test cases in the early stage and quickly detect whether the DUT meets the corresponding protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0037] Figure 1 It is a schematic flowchart of the method embodiment of the present invention;

[0038] Figure 2 It is a schematic structural diagram of an embodiment of the system of the present invention. Specific Embodiments

[0039] To clearly illustrate the technical features of this solution, the present invention will be elaborated in detail below through specific embodiments and in conjunction with its accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, the components and settings of specific examples are described below. In addition, the present invention may repeat reference numerals and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. It should be noted that the components illustrated in the drawings are not necessarily drawn to scale. The present invention omits the description of well-known components and processing technologies and processes to avoid unnecessarily limiting the present invention.

[0040] As Figure 1 shown, a verification IP integration method based on chip verification provided by an embodiment of the present invention includes the following steps:

[0041] S1. In response to the configuration information set by the user, render through a template engine to create a verification IP configuration file;

[0042] S2. According to the UVM environment template file and the configuration information, instantiate the verification IP components supporting the protocol, and pass the configuration file to the verification IP components;

[0043] S3. Compile the verification IP source code, instantiate the corresponding verification IP interfaces through the compiled verification IP interface files, and pass the instantiated verification IP interfaces to the verification IP components.

[0044] Examples of the configuration information set in step S1 are as follows:

[0045]

[0046]

[0047] "Among them, projName is used to represent the folder name where the verification platform is stored after generation, that is, the project name; dut represents the path and file name where the top-level file of the design under test is stored, and dutName represents the top-level module name of the top-level module of the design under test. The combination of the two can obtain the top-level module interface of the design under test, thereby further completing the automatic connection function between the VIP and the DUT, and between the verification platform and the DUT; topName is used to indicate the prefix of the component name generated by the verification platform; backup is the backup option for the same project name. If 'yes' is selected, the verification platform with the same project name will be backed up and stored in a bak folder; svt_vip are the basic parameters required for VIP integration. The verification automation platform will parse the configuration of the VIP in sequence according to the previous serial numbers and integrate it into the environment. The first parameter is the selection of the AMBA protocol of the VIP to be integrated, supporting three protocols: APB, AHB, and AXI. This parameter determines the type of VIP component generated by the final verification platform. The second parameter represents the selection of the master-slave mode of the VIP to be integrated. Slv means that the VIP to be integrated works in Slave mode, and mst means that the VIP to be integrated works in Master mode. This parameter determines the working mode selected by the VIP component generated in the final verification platform, specifically reflected in the configuration selection of the VIP component in the verification platform. The third parameter represents the address bit width of the VIP to be integrated. This parameter determines the address bit width selected by the VIP component generated in the final verification platform, specifically reflected in the configuration selection of the VIP component in the verification platform. The fourth parameter represents the data bit width of the VIP to be integrated. This parameter determines the data bit width selected by the VIP component generated in the final verification platform, specifically reflected in the configuration selection of the VIP component in the verification platform. The last parameter represents the number of VIPs to be integrated. This parameter determines the number of this VIP component generated in the final verification platform."

[0048] In step S1, the creation of the configuration file is completed by rendering through the template engine according to the user's custom configuration, creating the corresponding protocol configuration class, selecting the master-slave mode, selecting the data bit width and the address bit width, and selecting the number of VIPs to be integrated.

[0049] In step S2, based on the UVM environment (uvm_environment) template file, the instantiation of the VIP components corresponding to the protocol is completed, and the configuration file is passed to the corresponding VIP components through the uvm_config_db function provided by UVM. According to the configuration information in the Makefile template file, the compilation of the VIP source code corresponding to the protocol is added, that is, the VIP source code is compiled in sequence through the vcs command.

[0050] In step S3, according to the configuration information in the top-level template file of the verification platform, corresponding VIP interface instantiations are added through the compiled VIP interface file, and they are passed to the VIP component in the Environment through the uvm_config_db function provided by UVM.

[0051] In one implementation of the method embodiment of the present invention, after generating the verification IP component, the method further includes the steps:

[0052] S4. In the verification platform, establish the connection relationship between the verification IP and the design under test (DUT).

[0053] The specific process of establishing the connection relationship between the verification IP and the DUT is as follows:

[0054] S41. According to the DUT top-level file path and top-level module name defined by the user, obtain the interface information of the DUT top-level module through regular matching. The interface information specifically includes the name, bit width, and input / output type of the signal.

[0055] S42. According to the interface information, define the signals of the interface module in the verification platform, and connect the signals with the same name in the DUT interface signals to the signals with the same name in the verification platform interface module.

[0056] S43. According to the protocol type preset in the configuration information, determine the definition of the standard signal name of the current protocol type, match the top-level interface signals in the DUT, obtain the verification platform interface module connected to the matched signals, delete the connected verification platform interface module, and replace it with the verification IP interface.

[0057] In one implementation of the method embodiment of the present invention, after establishing the connection relationship between the verification IP and the DUT, the method further includes the steps:

[0058] S5. Perform a path test on the DUT for the test sequence provided by the verification IP.

[0059] The path test includes read / write tests and slave response tests.

[0060] In the path test, set the test sequences under each VIP attribute in the sequence template file, and selectively provide the corresponding test sequences to the user in the sequence file according to different configurations of the user. Specifically:

[0061] S51. Obtain the master-slave mode preset by the user.

[0062] S52. If it is the master mode, obtain the read / write test sequence corresponding to the protocol type. When the user calls the read / write sequence, specify the address information, obtain the read data for the read sequence, and specify the write data for the write sequence.

[0063] S53. If it is the slave mode, obtain the response test sequence corresponding to the protocol type. When the user calls the response sequence, specify the response time and response status.

[0064] An embodiment of the present invention also provides a verification IP integration system based on chip verification. The system includes a VIP integration module 1, and the VIP integration module 1 includes a configuration file generation unit 11, a protocol instantiation unit 12, and an integrated VIP unit 13.

[0065] The configuration file generation unit 11 responds to the configuration information set by the user, performs rendering through a template engine, and creates a verification IP configuration file. The protocol instantiation unit 12 instantiates the verification IP components supporting the protocol according to the UVM environment template file and the configuration information, and passes the configuration file to the verification IP components. The integrated VIP unit 13 is used to compile the verification IP source code, instantiate the corresponding verification IP interfaces through the compiled verification IP interface files, and pass the instantiated verification IP interfaces to the verification IP components.

[0066] In one implementation manner of the system embodiment of the present invention, the system further includes a connection module 2, and the connection module 2 establishes a connection relationship between the verification IP and the design under test (DUT) in the verification platform.

[0067] In one implementation manner of the system embodiment of the present invention, the system further includes a test module, and the test module performs a path test on the DUT for the test sequence provided by the verification IP.

[0068] Although the specific implementation manners of the present invention are described above in conjunction with the accompanying drawings, it is not a limitation to the protection scope of the present invention. Those skilled in the art should understand that based on the technical solutions of the present invention, various modifications or deformations that can be made by those skilled in the art without creative efforts are still within the protection scope of the present invention.

Claims

1. A method for integrating verification IP based on chip verification, characterized in that, The method includes the following steps: In response to the configuration information set by the user, render through a template engine to create a verification IP configuration file; The configuration information includes the project name, the path and file name where the top-level file of the design to be verified is stored, the top-level module name of the design to be verified, and the parameters required for integrating the verification IP; the required parameters include protocol type, master-slave mode, address bit width, data bit width, and integration quantity; For the creation of the configuration file, render through the template engine according to the user's custom configuration to complete the creation of the corresponding protocol configuration class, complete the selection of the master-slave mode, complete the selection of the data bit width and the address bit width, and complete the selection of the number of VIPs to be integrated; According to the UVM environment template file and the configuration information, instantiate the verification IP components that support the protocol, and pass the configuration file to the verification IP components; Compile the verification IP source code, instantiate the corresponding verification IP interfaces through the compiled verification IP interface files, and pass the instantiated verification IP interfaces to the verification IP components.

2. The method for integrating verification IP based on chip verification according to claim 1, characterized in that, After generating the verification IP components, the method further includes the steps: In the verification platform, establish the connection relationship between the verification IP and the design under test (DUT).

3. The method for integrating verification IP based on chip verification according to claim 2, characterized in that, The specific process of establishing the connection relationship between the verification IP and the DUT is as follows: According to the DUT top-level file path and top-level module name defined by the user, obtain the interface information of the DUT top-level module through regular expression matching; According to the interface information, define the signals of the interface module in the verification platform, and connect the signals with the same names in the DUT interface signals and the verification platform interface module; According to the protocol type preset in the configuration information, determine the definition of the standard signal names of the current protocol type, match the top-level interface signals in the DUT, obtain the verification platform interface module connected to the matched signals, delete the connected verification platform interface module, and replace it with the verification IP interface.

4. The method for integrating verification IP based on chip verification according to claim 2, characterized in that, After establishing the connection relationship between the verification IP and the DUT, the method further includes the steps: Perform a path test on the DUT for the test sequences provided by the verification IP.

5. The method for integrating verification IP based on chip verification according to claim 4, characterized in that, The path test includes read-write tests and slave response tests.

6. The method for integrating verification IP based on chip verification according to claim 5, characterized in that, The specific path test is as follows: Obtain the master-slave mode preset by the user; If it is the master mode, obtain the read-write test sequences of the corresponding protocol type. When the user calls the read-write sequences, specify the address information, and for the read sequences, obtain the read data, and for the write sequences, specify the write data; If it is the slave mode, obtain the response test sequences of the corresponding protocol type. When the user calls the response sequences, specify the response time and response status.

7. A system for integrating verification IP based on chip verification, characterized in that, The system includes a VIP integration module, and the VIP integration module includes: A configuration file generation unit, which in response to the configuration information set by the user, renders through a template engine to create a verification IP configuration file; The configuration information includes the project name, the path and file name where the top-level file of the design to be verified is stored, the top-level module name of the design to be verified, and the parameters required for integrating the verification IP; the required parameters include protocol type, master-slave mode, address bit width, data bit width, and integration quantity; Creation of a configuration file, which is rendered through a template engine according to the user's custom configuration, to complete the creation of the corresponding protocol configuration class, the selection of the master-slave mode, the selection of the data bit width and the address bit width, and the selection of the number of VIPs to be integrated; Protocol instantiation unit, which instantiates the verification IP components supporting the protocol according to the UVM environment template file and the configuration information, and passes the configuration file to the verification IP components; Integrated VIP unit, which is used to compile the verification IP source code, instantiate the corresponding verification IP interfaces through the compiled verification IP interface files, and pass the instantiated verification IP interfaces to the verification IP components.

8. The system for integrating verification IP based on chip verification according to claim 7, characterized in that, The system further includes a connection module, which establishes a connection relationship between the verification IP and the design under test (DUT) in the verification platform.

9. The system for integrating verification IP based on chip verification according to claim 8, characterized in that, The system further includes a test module, which performs a path test on the DUT for the test sequence provided by the verification IP.

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