A 14T radiation-hardened SRAM memory circuit based on polarity strengthening technology

Abstract

The present invention discloses a 14T radiation-hardened SRAM memory circuit based on polarity strengthening technology, which includes six NMOS transistors and eight PMOS transistors. The six NMOS transistors are sequentially denoted as N1 to N6, and the eight PMOS transistors are sequentially denoted as P1 to P8. The PMOS transistors P3 and P4 are cross-coupled, and the PMOS transistors P1 and P2 serve as pull-up transistors, while the NMOS transistors N1, N2, N3, N4 and the PMOS transistors P5 and P6 serve as pull-down transistors. Two main storage nodes Q and QN are respectively connected to the bit lines BL and BLB through the NMOS transistors N5 and N6, and two redundant storage nodes S0 and S1 are respectively connected to the bit lines BL and BLB through the PMOS transistors P7 and P8. This circuit can improve the write speed of the storage cell, reduce the cell power consumption, and enhance the single-event upset (SEU) resistance ability of the cell.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to a 14T radiation-hardened SRAM memory circuit based on polarity strengthening technology. Background Art

[0002] In a space environment, high-energy protons, neutrons, α particles, heavy ions, etc. will hit microelectronic circuits, resulting in single-event effects. Particle impacts may cause temporary damage to the circuit (such as a flip of the logic state), or may also cause permanent damage to the circuit and equipment. For non-permanent types, which can also be called soft errors, the flip of the logic state is also called the single-event upset effect.

[0003] For timing units such as latches and flip-flops, high-energy particles in a radiation environment bombard sensitive nodes of the circuit, depositing a large amount of charge on the incident trajectory. These charges are collected by the circuit, causing the storage state of the unit to reverse, forming the single-event upset effect (abbreviated as SEU). With the development of integrated circuits, whether it is spacecraft in a space environment or ground microelectronic devices, the demand for radiation-hardened integrated circuits is increasing. According to Moore's law, the feature size of integrated circuits will inevitably become smaller and smaller, and the negative effects caused by charge sharing are becoming increasingly prominent. Therefore, in order to meet the requirements of spacecraft and others for radiation-hardened integrated circuits, it is very necessary to explore and analyze the physical mechanism and influencing factors of the charge sharing effect, and the prior art lacks corresponding solutions. Summary of the Invention

[0004] The purpose of the present invention is to provide a 14T radiation-hardened SRAM memory circuit based on polarity strengthening technology, which can improve the write speed of the storage unit, reduce the unit power consumption, and improve the single-event upset (SEU) resistance ability of the unit.

[0005] The purpose of the present invention is achieved by the following technical solutions:

[0006] A 14T radiation-hardened SRAM memory circuit based on polarity strengthening technology, the circuit includes six NMOS transistors and eight PMOS transistors. The six NMOS transistors are sequentially denoted as N1 to N6, and the eight PMOS transistors are sequentially denoted as P1 to P8, where:

[0007] Two main storage nodes Q and QN are respectively connected to bit lines BL and BLB through NMOS transistors N5 and N6, and two redundant storage nodes S0 and S1 are respectively connected to bit lines BL and BLB through PMOS transistors P8 and P7, where:

[0008] The NMOS transistors N5 and N6 are controlled by the word line WLB, and the PMOS transistors P7 and P8 are controlled by the word line WL;

[0009] The bit line BL is electrically connected to the sources of the NMOS transistor N5 and the PMOS transistor P7, and the bit line BLB is electrically connected to the sources of the NMOS transistor N6 and the PMOS transistor P8;

[0010] The word line WL is electrically connected to the gates of the PMOS transistors P7 and P8, and the word line WLB is electrically connected to the gates of the NMOS transistors N5 and N6;

[0011] The drain of the NMOS transistor N5 is electrically connected to the gate of the NMOS transistor N1, and the drain of the NMOS transistor N6 is electrically connected to the gate of the NMOS transistor N2; the drain of the PMOS transistor P8 is electrically connected to the drain of the PMOS transistor P3, and the drain of the PMOS transistor P7 is electrically connected to the drain of the PMOS transistor P4;

[0012] The gate of the PMOS transistor P3 is connected to the drain of the PMOS transistor P4, and at the same time, the gate of the PMOS transistor P4 is connected to the drain of the PMOS transistor P3, that is, the PMOS transistors P3 and P4 form a cross-coupled structure of MOS transistors;

[0013] The redundant storage nodes S0 and S1 are respectively connected to the gates of the PMOS transistors P1 and P2. The sources of the PMOS transistors P1 and P2 are connected to the circuit power supply VDD, and the drains of the PMOS transistors P1 and P2 are connected to the main storage nodes Q and QN; therefore, the PMOS transistors P1 and P2 act as pull-up transistors for the main storage nodes Q and QN;

[0014] The sources of the NMOS transistors N1 and N2 are connected to the redundant storage nodes S0 and S1, and the drains of the NMOS transistors N1 and N2 are connected to the circuit ground signal VSS; therefore, the NMOS transistors N1 and N2 act as pull-down transistors for the redundant storage nodes S0 and S1;

[0015] Similarly, the sources of the NMOS transistors N3 and N4 are connected to the main storage nodes Q and QN, and the drains of the NMOS transistors N3 and N4 are connected to the circuit ground signal VSS; therefore, the NMOS transistors N3 and N4 act as pull-down transistors for the main storage nodes Q and QN;

[0016] The power supply VDD is electrically connected to the sources of the PMOS transistors P1 and P2, and the power supply VDD is also electrically connected to the sources of the PMOS transistors P3 and P4;

[0017] The drains of the NMOS transistors N3 and N4 and the drains of the NMOS transistors N1 and N2 are all grounded.

[0018] As can be seen from the technical solution provided by the present invention above, the above circuit can significantly improve the write speed of the cell, reduce the power consumption of the cell, and improve the ability of the cell to resist single event upset (SEU) while sacrificing a relatively small cell area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1 FIG. is a schematic structural diagram of a 14T radiation-hardened SRAM memory circuit based on a polarity reinforcement technology provided by an embodiment of the present invention;

[0021] Figure 2 FIG. is a timing waveform diagram of the circuit provided by an embodiment of the present invention;

[0022] Figure 3 FIG. is a transient waveform simulation diagram of the circuit provided by an embodiment of the present invention when different nodes are injected with double-exponential current source pulses at different times. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments, which do not constitute a limitation to the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the protection scope of the present invention.

[0024] As Figure 1 shown is a schematic structural diagram of a 14T radiation-hardened SRAM memory circuit based on a polarity reinforcement technology provided by an embodiment of the present invention. The circuit mainly includes six NMOS transistors and eight PMOS transistors. The six NMOS transistors are sequentially denoted as N1 to N6, and the eight PMOS transistors are sequentially denoted as P1 to P8, where:

[0025] Two main storage nodes Q and QN are respectively connected to bit lines BL and BLB through NMOS transistors N5 and N6, and two redundant storage nodes S0 and S1 are respectively connected to bit lines BL and BLB through PMOS transistors P8 and P7, where:

[0026] NMOS transistors N5 and N6 are controlled by word line WLB, and PMOS transistors P7 and P8 are controlled by word line WL;

[0027] The bit line BL is electrically connected to the sources of the NMOS transistor N5 and the PMOS transistor P8, and the bit line BLB is electrically connected to the sources of the NMOS transistor N6 and the PMOS transistor P7;

[0028] The word line WL is electrically connected to the gates of the PMOS transistors P7 and P8, and the word line WLB is electrically connected to the gates of the NMOS transistors N5 and N6;

[0029] The drain of the NMOS transistor N5 is electrically connected to the gate of the NMOS transistor N1, and the drain of the NMOS transistor N6 is electrically connected to the gate of the NMOS transistor N2; the drain of the PMOS transistor P8 is electrically connected to the drain of the PMOS transistor P3, and the drain of the PMOS transistor P7 is electrically connected to the drain of the PMOS transistor P4;

[0030] The gate of the PMOS transistor P3 is connected to the drain of the PMOS transistor P4, and at the same time the gate of the PMOS transistor P4 is connected to the drain of the PMOS transistor P3, that is, the PMOS transistors P3 and P4 form a cross-coupled structure of MOS transistors;

[0031] The redundant storage nodes S0 and S1 are respectively connected to the gates of the PMOS transistors P1 and P2. The sources of the PMOS transistors P1 and P2 are connected to the circuit power supply VDD, and the drains of the PMOS transistors P1 and P2 are connected to the main storage nodes Q and QN; therefore, the PMOS transistors P1 and P2 act as pull-up transistors for the main storage nodes Q and QN;

[0032] The sources of the NMOS transistors N1 and N2 are connected to the redundant storage nodes S0 and S1, and the drains of the NMOS transistors N1 and N2 are connected to the circuit ground signal VSS; therefore, the NMOS transistors N1 and N2 act as pull-down transistors for the redundant storage nodes S0 and S1;

[0033] Similarly, the sources of the NMOS transistors N3 and N4 are connected to the main storage nodes Q and QN, and the drains of the NMOS transistors N3 and N4 are connected to the circuit ground signal VSS; therefore, the NMOS transistors N3 and N4 act as pull-down transistors for the main storage nodes Q and QN;

[0034] The power supply VDD is electrically connected to the sources of the PMOS transistors P1 and P2, and the power supply VDD is also electrically connected to the sources of the PMOS transistors P3 and P4;

[0035] The drains of the NMOS transistors N3 and N4 and the drains of the NMOS transistors N1 and N2 are all grounded.

[0036] For a circuit based on the above structure, if it is necessary to retain a signal, the word lines WL and WLB are respectively set to 0 and 1, and the PMOS transistors P1, P2 and the NMOS transistors N5, N6 are in the off state. The connections between the main storage nodes Q, QN and the redundant storage nodes S0, S1 and the bit lines BL, BLB are disconnected. The information stored in the Q node is opposite to that in the QN node, so that one of the NMOS transistors N3, N4 is turned on. Due to the cross-coupled circuit structure of the above NMOS transistors N3, N4, the pull-down transistor corresponding to the node storing the high level in the main storage nodes Q, QN is turned off, and the pull-down transistor corresponding to the node storing the low level is turned on, so as to retain the stored signals of the Q, QN nodes. At the same time, the stored information of S0 and QN, S1 and Q nodes remains the same signal;

[0037] The principle of realizing radiation resistance is that the information level stored in the Q node is opposite to that stored in the S0 node. If the Q node stores a high level, the corresponding S0 node stores a low level. The transistors P5, N1 and P4 are turned on to form a ground path for the S0 node and a power supply path for the S1 node at the same time. At the same time, the transistor P1 is turned on by the internal low-level signal of the S0 node, so as to turn on the power supply path of the Q node. When the Q node is bombarded by an external irradiation current, the voltage mutation of the Q node can be pulled back to the normal level, realizing the radiation resistance design.

[0038] If it is necessary to read information, the control bit lines BL, BLB are kept at a high level before the word lines WL, WLB are turned on, so that the bit lines are in a precharged state. The corresponding word lines WL, WLB turn on the gate transistors, turn on the discharge path of the storage node, and read the internal data of the main storage nodes Q, QN into the bit lines BL, BLB through the gate transistors (i.e., NMOS transistors N5, N6), realizing the reading of the stored information;

[0039] If it is necessary to write information, the control bit lines BL, BLB are respectively in the written information value and the reverse signal of the written information value. The word lines WL and WLB control the gate transistors, that is, the PMOS transistors P1, P2 and the NMOS transistors N5, N6 are turned on, and the electrical signals in the bit lines BL, BLB are written to realize the writing of the stored information.

[0040] In the specific implementation, as Figure 1 shown, the specific connection relationships of the transistors are as follows:

[0041] The drain of the PMOS transistor P1 is electrically connected to the gate of the PMOS transistor P6, the drain of the NMOS transistor N5, the gate of the NMOS transistor N1, the gate of the NMOS transistor N4 and the source of the NMOS transistor N3; the gate of the PMOS transistor P1 is electrically connected to the drain of the PMOS transistor P3, the source of the PMOS transistor P5 and the gate of the PMOS transistor P4;

[0042] The drain of PMOS transistor P2 is electrically connected to the gate of PMOS transistor P5, the gate of NMOS transistor N2, the drain of NMOS transistor N6, the source of NMOS transistor N4, and the gate of NMOS transistor N3; the gate of PMOS transistor P2 is electrically connected to the gate of PMOS transistor P3, the drain of PMOS transistor P4, and the source of PMOS transistor P6;

[0043] The drain of PMOS transistor P3 is electrically connected to the source of PMOS transistor P5, the gate of PMOS transistor P4, and the drain of PMOS transistor P8; the gate of PMOS transistor P3 is electrically connected to the drain of PMOS transistor P4, the source of PMOS transistor P6, and the drain of PMOS transistor P8;

[0044] The drain of PMOS transistor P4 is electrically connected to the gate of PMOS transistor P3, the drain of PMOS transistor P7, and the source of PMOS transistor P6; the gate of PMOS transistor P4 is electrically connected to the drain of PMOS transistor P3, the drain of PMOS transistor P8, and the source of PMOS transistor P5;

[0045] The source of PMOS transistor P5 is electrically connected to the drain of PMOS transistor P3, the drain of PMOS transistor P8, and the gate of PMOS transistor P4; the drain of PMOS transistor P5 is electrically connected to the source of NMOS transistor N1; the gate of PMOS transistor P5 is electrically connected to the drain of PMOS transistor P2, the gate of NMOS transistor N2, the drain of NMOS transistor N6, the source of NMOS transistor N4, and the gate of NMOS transistor N3;

[0046] The source of PMOS transistor P6 is electrically connected to the drain of PMOS transistor P4, the gate of PMOS transistor P3, and the drain of PMOS transistor P7; the drain of PMOS transistor P6 is electrically connected to the source of NMOS transistor N2; the gate of PMOS transistor P6 is electrically connected to the drain of PMOS transistor P1, the drain of NMOS transistor N5, the gate of NMOS transistor N1, the gate of NMOS transistor N4, and the source of NMOS transistor N3;

[0047] The source of PMOS transistor P8 is electrically connected to bit line BL; the drain of PMOS transistor P8 is electrically connected to the drain of PMOS transistor P3, the gate of PMOS transistor P4, and the source of PMOS transistor P5; the gate of PMOS transistor P8 is electrically connected to word line WL;

[0048] The source of PMOS transistor P7 is electrically connected to bit line BLB; the drain of PMOS transistor P7 is electrically connected to the drain of PMOS transistor P4, the gate of PMOS transistor P3, and the source of PMOS transistor P6; the gate of PMOS transistor P7 is electrically connected to word line WL;

[0049] The source of NMOS transistor N1 is electrically connected to the drain of PMOS transistor P5; the gate of NMOS transistor N1 is electrically connected to the drain of NMOS transistor N5, the drain of PMOS transistor P1, the gate of PMOS transistor P6, the gate of NMOS transistor N4, and the source of NMOS transistor N3;

[0050] The source of NMOS transistor N2 is electrically connected to the drain of PMOS transistor P6; the gate of NMOS transistor N2 is electrically connected to the drain of PMOS transistor P2, the gate of PMOS transistor P5, the drain of NMOS transistor N6, the gate of NMOS transistor N3, and the source of NMOS transistor N4;

[0051] The source of NMOS transistor N3 is electrically connected to the drain of PMOS transistor P1, the gate of PMOS transistor P6, the gate of NMOS transistor N1, the drain of NMOS transistor N5, and the gate of NMOS transistor N4; the gate of NMOS transistor N3 is electrically connected to the drain of PMOS transistor P2, the gate of PMOS transistor P5, the gate of NMOS transistor N2, the drain of NMOS transistor N6, and the source of NMOS transistor N4;

[0052] The source of NMOS transistor N4 is electrically connected to the drain of PMOS transistor P2, the gate of PMOS transistor P5, the gate of NMOS transistor N2, the drain of NMOS transistor N6, and the source of NMOS transistor N4; the gate of NMOS transistor N4 is electrically connected to the drain of PMOS transistor P1, the gate of PMOS transistor P6, the gate of NMOS transistor N1, the drain of NMOS transistor N5, and the gate of NMOS transistor N4;

[0053] The source of NMOS transistor N5 is electrically connected to bit line BL; the drain of NMOS transistor N5 is electrically connected to the drain of PMOS transistor P1, the gate of PMOS transistor P6, the gate of NMOS transistor N1, the source of NMOS transistor N3, and the gate of NMOS transistor N4; the gate of NMOS transistor N5 is electrically connected to word line WLB;

[0054] The source of NMOS transistor N6 is electrically connected to bit line BLB; the drain of NMOS transistor N6 is electrically connected to the drain of PMOS transistor P2, the gate of PMOS transistor P5, the gates of NMOS transistors N2, N3, and the source of NMOS transistor N4; the gate of NMOS transistor N6 is electrically connected to word line WLB.

[0055] In addition, the gate length of all transistors is 65 nm, where:

[0056] The gate widths of PMOS transistors P1, P2, P3, and P4 are 450 nm; the gate widths of PMOS transistors P5 and P6 are 200 nm; the gate widths of PMOS transistors P7 and P8 are 140 nm;

[0057] The gate widths of NMOS transistors N1, N2, N3, and N4 are 75 nm; the gate widths of NMOS transistors N5 and N6 are 140 nm.

[0058] As Figure 2 shown is the timing waveform diagram of the circuit provided by the embodiment of the present invention. The specific simulation conditions are: Corner: TT; Temperature: 27 °C; VDD: 1.2V. It can be seen from Figure 2 that before the word line WL is turned on, the bit lines BL and BLB remain at a high level to keep the bit line precharge signal; after the word line WL is turned on, the bit lines BL and BLB become high and low levels alternating respectively. It can be directly seen from the waveform that the signals of the word lines WL and WLB are reverse signals. At the same time, it is observed that the stored information of the Q and S1 nodes is consistent, and the stored information of the QN and S0 nodes is consistent.

[0059] As Figure 3 shown is the transient waveform simulation diagram of the circuit provided by the embodiment of the present invention when different nodes are injected with double-exponential current source pulses at different times. The specific simulation conditions are: VDD: 1.2V. It can be seen from Figure 3 that the read / write operation settings are consistent with Figure 2 the settings. At 10 ns and 20 ns, double-exponential current source pulses are used to inject into the main storage nodes Q and QN respectively. It is observed that at 10 ns, a negative charge bombardment is carried out on the Q node, and the Q and QN nodes quickly return to the original stored data, and the level is also at the level before the bombardment; the same operation is carried out at 20 ns, and it can still resist the interference of the bombardment current. And during the two bombardment processes, the stored information of the redundant storage nodes S0 and S1 does not leak or flip. Then it can be concluded that the circuit described in the embodiment of the present invention can meet the requirements of anti-radiation design.

[0060] It should be noted that the content not described in detail in the embodiment of the present invention belongs to the prior art well-known to those skilled in the art.

[0061] As described above, it is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background art part of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or an indication in any form that this information constitutes the prior art known to those skilled in the art.

Claims

1. A 14T radiation-hardened SRAM memory circuit based on polarity reinforcement technology, characterized in that, the circuit includes six NMOS transistors and eight PMOS transistors. The six NMOS transistors are sequentially denoted as N1 to N6, and the eight PMOS transistors are sequentially denoted as P1 to P8, where: The main storage node Q is connected to the bit line BL through the NMOS transistor N5, the main storage node QN is connected to the bit line BLB through the NMOS transistor N6, the redundant storage node S0 is connected to the bit line BL through the PMOS transistor P8, and the redundant storage node S1 is connected to the bit line BLB through the PMOS transistor P7, where: The NMOS transistors N5 and N6 are controlled by the word line WLB, and the PMOS transistors P7 and P8 are controlled by the word line WL; The bit line BL is electrically connected to the sources of the NMOS transistor N5 and the PMOS transistor P7, and the bit line BLB is electrically connected to the sources of the NMOS transistor N6 and the PMOS transistor P8; The word line WL is electrically connected to the gates of the PMOS transistors P7 and P8, and the word line WLB is electrically connected to the gates of the NMOS transistors N5 and N6; The drain of the NMOS transistor N5 is electrically connected to the gate of the NMOS transistor N1, and the drain of the NMOS transistor N6 is electrically connected to the gate of the NMOS transistor N2; the drain of the PMOS transistor P8 is electrically connected to the drain of the PMOS transistor P3, and the drain of the PMOS transistor P7 is electrically connected to the drain of the PMOS transistor P4; The gate of the PMOS transistor P3 is connected to the drain of the PMOS transistor P4, and at the same time, the gate of the PMOS transistor P4 is connected to the drain of the PMOS transistor P3, that is, the PMOS transistors P3 and P4 form a cross-coupled structure of MOS transistors; The redundant storage nodes S0 and S1 are respectively connected to the gates of the PMOS transistors P1 and P2. The sources of the PMOS transistors P1 and P2 are connected to the circuit power supply VDD, and the drains of the PMOS transistors P1 and P2 are connected to the main storage nodes Q and QN; therefore, the PMOS transistors P1 and P2 act as pull-up transistors for the main storage nodes Q and QN; The source of the NMOS transistor N1 is connected to the redundant storage node S0, the source of the NMOS transistor N2 is connected to the redundant storage node S1, and the drains of the NMOS transistors N1 and N2 are connected to the circuit ground signal VSS; therefore, the NMOS transistors N1 and N2 act as pull-down transistors for the redundant storage nodes S0 and S1; Similarly, the source of the NMOS transistor N3 is connected to the main storage node Q, the source of the NMOS transistor N4 is connected to the main storage node QN, and the drains of the NMOS transistors N3 and N4 are connected to the circuit ground signal VSS; therefore, the NMOS transistors N3 and N4 act as pull-down transistors for the main storage nodes Q and QN; The power supply VDD is electrically connected to the sources of the PMOS transistors P1 and P2, and the power supply VDD is also electrically connected to the sources of the PMOS transistors P3 and P4; The drains of the NMOS transistors N3 and N4 and the drains of the NMOS transistors N1 and N2 are all grounded; Among them, the specific connection relationships of the transistors are as follows: The drain of PMOS transistor P1 is electrically connected to the gate of PMOS transistor P6, the drain of NMOS transistor N5, the gate of NMOS transistor N1, the gate of NMOS transistor N4, and the source of NMOS transistor N3; the gate of PMOS transistor P1 is electrically connected to the drain of PMOS transistor P3, the source of PMOS transistor P5, and the gate of PMOS transistor P4; The drain of PMOS transistor P2 is electrically connected to the gate of PMOS transistor P5, the gate of NMOS transistor N2, the drain of NMOS transistor N6, the source of NMOS transistor N4, and the gate of NMOS transistor N3; the gate of PMOS transistor P2 is electrically connected to the gate of PMOS transistor P3, the drain of PMOS transistor P4, and the source of PMOS transistor P6; The drain of PMOS transistor P3 is electrically connected to the source of PMOS transistor P5, the gate of PMOS transistor P4, and the drain of PMOS transistor P8; the gate of PMOS transistor P3 is electrically connected to the drain of PMOS transistor P4, the source of PMOS transistor P6, and the drain of PMOS transistor P7; The drain of PMOS transistor P4 is electrically connected to the gate of PMOS transistor P3, the drain of PMOS transistor P7, and the source of PMOS transistor P6; the gate of PMOS transistor P4 is electrically connected to the drain of PMOS transistor P3, the drain of PMOS transistor P8, and the source of PMOS transistor P5; The source of PMOS transistor P5 is electrically connected to the drain of PMOS transistor P3, the drain of PMOS transistor P7, and the gate of PMOS transistor P4; the drain of PMOS transistor P5 is electrically connected to the source of NMOS transistor N1; the gate of PMOS transistor P5 is electrically connected to the drain of PMOS transistor P2, the gate of NMOS transistor N2, the drain of NMOS transistor N6, the source of NMOS transistor N4, and the gate of NMOS transistor N3; The source of PMOS transistor P6 is electrically connected to the drain of PMOS transistor P4, the gate of PMOS transistor P3, and the drain of PMOS transistor P7; the drain of PMOS transistor P6 is electrically connected to the source of NMOS transistor N2; the gate of PMOS transistor P6 is electrically connected to the drain of PMOS transistor P1, the drain of NMOS transistor N5, the gate of NMOS transistor N1, the gate of NMOS transistor N4, and the source of NMOS transistor N3; The source of PMOS transistor P8 is electrically connected to bit line BLB; the drain of PMOS transistor P8 is electrically connected to the drain of PMOS transistor P3, the gate of PMOS transistor P4, and the source of PMOS transistor P5; the gate of PMOS transistor P7 is electrically connected to word line WL; The source of the PMOS transistor P7 is electrically connected to the bit line BL; the drain of the PMOS transistor P7 is electrically connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P3, and the source of the PMOS transistor P6; the gate of the PMOS transistor P8 is electrically connected to the word line WL; The source of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P5; the gate of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N5, the drain of the PMOS transistor P1, the gate of the PMOS transistor P6, the gate of the NMOS transistor N4, and the source of the NMOS transistor N3; The source of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P6; the gate of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P2, the gate of the PMOS transistor P5, the drain of the NMOS transistor N6, the gate of the NMOS transistor N3, and the source of the NMOS transistor N4; The source of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P1, the gate of the PMOS transistor P6, the gate of the NMOS transistor N1, the drain of the NMOS transistor N5, and the gate of the NMOS transistor N4; the gate of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P2, the gate of the PMOS transistor P5, the gate of the NMOS transistor N2, the drain of the NMOS transistor N6, and the source of the NMOS transistor N4; The source of the NMOS transistor N4 is electrically connected to the drain of the PMOS transistor P2, the gate of the PMOS transistor P5, the gate of the NMOS transistor N2, the drain of the NMOS transistor N6, and the source of the NMOS transistor N4; the gate of the NMOS transistor N4 is electrically connected to the drain of the PMOS transistor P1, the gate of the PMOS transistor P6, the gate of the NMOS transistor N1, the drain of the NMOS transistor N5, and the gate of the NMOS transistor N4; The source of the NMOS transistor N5 is electrically connected to the bit line BL; the drain of the NMOS transistor N5 is electrically connected to the drain of the PMOS transistor P1, the gate of the PMOS transistor P6, the gate of the NMOS transistor N1, the source of the NMOS transistor N3, and the gate of the NMOS transistor N4; the gate of the NMOS transistor N5 is electrically connected to the word line WLB; The source of the NMOS transistor N6 is electrically connected to the bit line BLB; the drain of the NMOS transistor N6 is electrically connected to the drain of the PMOS transistor P2, the gate of the PMOS transistor P5, the gate of the NMOS transistor N2, the gate of the NMOS transistor N3, and the source of the NMOS transistor N4; the gate of the NMOS transistor N6 is electrically connected to the word line WLB.

2. The 14T radiation-hardened SRAM memory circuit based on the polarity hardening technology according to claim 1, characterized in that, based on the circuit: If it is necessary to maintain the signal, the word lines WL and WLB are respectively set to 0 and 1, and the PMOS transistors P1, P2 and the NMOS transistors N5, N6 are in the off state; the connections between the main storage nodes Q, QN and the redundant storage nodes S0, S1 and the bit lines BL, BLB are disconnected. The information stored in the Q node is opposite to that in the QN node, so that one of the NMOS transistors N3, N4 is turned on. Since the NMOS transistors N3, N4 have a cross-coupled circuit structure, the pull-down transistor corresponding to the node storing the high level in the main storage nodes Q, QN is turned off, and the pull-down transistor corresponding to the node storing the low level is turned on, so as to maintain the storage signals of the Q, QN nodes. At the same time, the storage information of the S0 and QN nodes, and the S1 and Q nodes remains the same signal; If it is necessary to read information, the control bit lines BL, BLB are maintained at a high level before the word lines WL, WLB are turned on, so that the bit lines are in a pre-charged state. The corresponding word lines WL, WLB turn on the gate transistors, and open the discharge path of the storage nodes, and the internal data of the main storage nodes Q, QN is read into the bit lines BL, BLB through the gate transistors, that is, the NMOS transistors N5, N6, to realize the reading of the storage information; If it is necessary to write information, the control bit lines BL, BLB are respectively in the write information value and the reverse signal of the write information value. The word lines WL and WLB control the gate transistors, that is, the PMOS transistors P1, P2 and the NMOS transistors N5, N6 to be turned on, and the electrical signals in the bit lines BL, BLB are written to realize the writing of the storage information.

3. The 14T radiation-hardened SRAM memory circuit based on the polarity hardening technology according to claim 1, characterized in that, the gate lengths of all transistors are 65nm, where: the gate widths of the PMOS transistors P1, P2, P3, P4 are 450nm; the gate widths of the PMOS transistors P5, P6 are 200nm; the gate widths of the PMOS transistors P8, P7 are 140nm; the gate widths of the NMOS transistors N1, N2, N3, N4 are 75nm; the gate widths of the NMOS transistors N5, N6 are 140nm.

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