Precharge method, device, control circuit, memory, storage system and equipment

Abstract

Embodiments of the present application disclose a pre-charging method, device, control circuit, memory, storage system and equipment, and belong to the technical field of memory. The pre-charging method is used for pre-charging a non-selected memory string, and the method comprises the following steps: applying a pre-charging voltage to a target input end of the non-selected memory string; and turning on a channel of a memory cell between the target input end and a target memory cell in the non-selected memory string, wherein the memory cell between the target input end and the target memory cell comprises a programmed memory cell, and the target memory cell is a memory cell connected with a selected word line in the non-selected memory string. The pre-charging method can attract the electrons in the channel of the target memory cell to the target input end more fully, thereby realizing more sufficient pre-charging of the non-selected memory string, and further reducing the programming interference on the target memory cell to a greater extent.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of memory, in particular to a pre-charge method, device, control circuit, memory, storage system and equipment. BACKGROUND

[0002] With the development of memory technology, there are more and more types of memories, and the three-dimensional NAND (3D NAND) memory is one of them. The 3D NAND memory includes a plurality of memory blocks, a memory block includes a plurality of memory strings arranged in an array, and a memory string includes a plurality of memory cells connected in series.

[0003] In a memory block, before writing data to a selected memory cell, the non-selected memory string in the memory block needs to be pre-charged to attract the electrons in the channel of the target memory cell in the non-selected memory string to a certain input terminal of the non-selected memory string, so as to reduce the programming interference received by the target memory cell, wherein the target memory cell is the memory cell connected with the selected word line in the non-selected memory string.

[0004] The related art pre-charges the non-selected memory string in the following manner: a pre-charge voltage is applied to a certain input terminal of the non-selected memory string, and a small voltage (such as 0V) is applied to the gate of each memory cell in the non-selected memory string, which is easy to cause insufficient pre-charging and make the programming interference received by the target memory cell stronger. SUMMARY

[0005] Embodiments of the present application provide a pre-charge method, device, control circuit, memory, storage system and equipment, which can be used to reduce the programming interference received by the target memory cell to a greater extent. The technical solution is as follows:

[0006] In one aspect, the present application provides a pre-charge method, which is used to pre-charge a non-selected memory string before writing data to a selected memory cell, and the method comprises:

[0007] applying a pre-charge voltage to a target input terminal of the non-selected memory string, the target input terminal being an input terminal connected with a bit line or an input terminal connected with a source line of the non-selected memory string;

[0008] conducting the channel of the memory cell between the target input terminal and the target memory cell in the non-selected memory string, the memory cell between the target input terminal and the target memory cell including a programmed memory cell, and the target memory cell being a memory cell connected with a selected word line in the non-selected memory string.

[0009] In a possible implementation, the method further includes:

[0010] applying a first voltage to the gate of the programmed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell.

[0011] In a possible implementation, the memory cells between the target input terminal and the target memory cell further include unprogrammed memory cells; and the method further includes:

[0012] applying a first voltage to the gate of the programmed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell.

[0013] applying a second voltage to the gate of the unprogrammed memory cell, the second voltage being greater than a threshold voltage of the unprogrammed memory cell and less than the first voltage.

[0014] In a possible implementation, the programming direction is a direction close to the target input terminal, and the programmed memory cells are all unerased memory cells.

[0015] In a possible implementation, the programming direction is a direction away from the target input terminal, and the programmed memory cells are all re-written memory cells, or the programmed memory cells are all unerased memory cells, or the programmed memory cells are re-written memory cells and unerased memory cells.

[0016] In a possible implementation, the method further includes:

[0017] conducting the channel of the memory cells in the unselected memory string that are not between the target input terminal and the target memory cell.

[0018] In a possible implementation, the turn-off time of applying the first voltage to the gate of the programmed memory cell is earlier than the turn-off time of applying the pre-charge voltage to the target input terminal.

[0019] In a possible implementation, the number of the programmed memory cells is a plurality, and the turn-off time of applying the first voltage to the gate of the programmed memory cell that is far from the target input terminal is not later than the turn-off time of applying the first voltage to the gate of the programmed memory cell that is close to the target input terminal.

[0020] In a possible implementation, the input end connected with the bit line and the input end connected with the source line are connected through a selection tube stack and a storage unit stack, and the target input end is the input end connected with the bit line, and the storage unit between the target input end and the target storage unit is a storage unit between the target input end and the target storage unit.

[0021] In another aspect, a pre-charge apparatus is provided for pre-charging a non-selected storage string before writing data to a selected storage unit, the apparatus comprising:

[0022] a voltage application module configured to apply a pre-charge voltage to a target input end of the non-selected storage string, the target input end being an input end connected with a bit line or an input end connected with a source line of the non-selected storage string;

[0023] a conduction module configured to conduct a channel of a storage unit between the target input end and a target storage unit in the non-selected storage string, the storage unit between the target input end and the target storage unit comprising a programmed storage unit, and the target storage unit being a storage unit connected with a selected word line in the non-selected storage string.

[0024] In a possible implementation, the conduction module is configured to apply a first voltage to a gate of the storage unit between the target input end and the target storage unit, the first voltage being greater than a threshold voltage of the programmed storage unit.

[0025] In a possible implementation, the storage unit between the target input end and the target storage unit further comprises an unprogrammed storage unit, the conduction module is configured to apply a first voltage to a gate of the programmed storage unit, the first voltage being greater than a threshold voltage of the programmed storage unit, and apply a second voltage to a gate of the unprogrammed storage unit, the second voltage being greater than a threshold voltage of the unprogrammed storage unit and less than the first voltage.

[0026] In a possible implementation, the programming direction is a direction close to the target input end, and the programmed storage units are all unerased storage units.

[0027] In a possible implementation, the programming direction is a direction away from the target input end, and the programmed storage units are all re-written storage units, or the programmed storage units are all unerased storage units, or the programmed storage units are re-written storage units and unerased storage units.

[0028] In a possible implementation, the turn-on module is further configured to turn on a channel of a storage cell in the non-selected storage string that is not located between the target input terminal and the target storage cell.

[0029] In a possible implementation, a turn-off time of applying the first voltage to the gate of the programmed storage cell is earlier than a turn-off time of applying the pre-charge voltage to the target input terminal.

[0030] In a possible implementation, the number of the programmed storage cells is a plurality, and a turn-off time of applying the first voltage to the gate of a programmed storage cell that is far from the target input terminal is not later than a turn-off time of applying the first voltage to the gate of a programmed storage cell that is close to the target input terminal.

[0031] In a possible implementation, the input terminal connected with the bit line and the input terminal connected with the source line comprise a selection tube stack and a storage cell stack, the selection tube stack and the storage cell stack are connected through a doped region, the target input terminal is the input terminal connected with the bit line, and the storage cell located between the target input terminal and the target storage cell comprises a storage cell between the doped region and the target storage cell.

[0032] In another aspect, a control circuit is provided, the control circuit comprising programmable logic circuitry and / or program instructions, the control circuit being configured to pre-charge a non-selected storage string according to the following steps before writing data to a selected storage cell:

[0033] applying a pre-charge voltage to a target input terminal of the non-selected storage string, the target input terminal being an input terminal of the non-selected storage string connected with a bit line or an input terminal connected with a source line;

[0034] turning on a channel of a storage cell in the non-selected storage string that is located between the target input terminal and a target storage cell, the storage cell located between the target input terminal and the target storage cell comprising a programmed storage cell, and the target storage cell being a storage cell of the non-selected storage string connected with a selected word line.

[0035] In a possible implementation, the control circuit is configured to apply a first voltage to a gate of the storage cell located between the target input terminal and the target storage cell, the first voltage being greater than a threshold voltage of the programmed storage cell.

[0036] In a possible implementation, the memory cells between the target input terminal and the target memory cell further include unprogrammed memory cells; and the control circuit is configured to apply a first voltage to the gates of the programmed memory cells, the first voltage being greater than a threshold voltage of the programmed memory cells; and apply a second voltage to the gates of the unprogramed memory cells, the second voltage being greater than a threshold voltage of the unprogrammed memory cells and less than the first voltage.

[0037] In a possible implementation, the programming direction is a direction close to the target input terminal, and the programmed memory cells are all unerased memory cells.

[0038] In a possible implementation, the programming direction is a direction away from the target input terminal, and the programmed memory cells are all re-written data memory cells, or the programmed memory cells are all unerased memory cells, or the programmed memory cells are re-written data memory cells and unerased memory cells.

[0039] In a possible implementation, the control circuit is further configured to turn on the channel of the memory cells in the non-selected memory string that are not between the target input terminal and the target memory cell.

[0040] In a possible implementation, the turn-off time of applying the first voltage to the gates of the programmed memory cells is earlier than the turn-off time of applying the pre-charge voltage to the target input terminal.

[0041] In a possible implementation, the number of the programmed memory cells is a plurality, and the turn-off time of applying the first voltage to the gates of the programmed memory cells far from the target input terminal is not later than the turn-off time of applying the first voltage to the gates of the programmed memory cells close to the target input terminal.

[0042] In a possible implementation, the input terminal connected with the bit line and the input terminal connected with the source line include a selection tube stack and a memory cell stack connected through a doped region, the target input terminal is the input terminal connected with the bit line, and the memory cells between the target input terminal and the target memory cell include the memory cells between the doped region and the target memory cell.

[0043] In another aspect, a memory is provided, including: a memory array and a control circuit communicatively connected with the memory array;

[0044] The memory array includes a non-selected memory string, and the control circuit is configured to pre-charge the non-selected memory string according to the following steps before writing data to a selected memory cell:

[0045] applying a pre-charge voltage to a target input end of the non-selected memory string, the target input end being an input end of the non-selected memory string connected to a bit line or an input end connected to a source line;

[0046] turning on a channel of a memory cell between the target input end and a target memory cell of the non-selected memory string, the memory cell between the target input end and the target memory cell including a programmed memory cell, the target memory cell being a memory cell of the non-selected memory string connected to a selected word line.

[0047] In a possible implementation, the control circuit is configured to apply a first voltage to a gate of the memory cell between the target input end and the target memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell.

[0048] In a possible implementation, the memory cell between the target input end and the target memory cell further includes an unprogrammed memory cell; the control circuit is configured to apply a first voltage to a gate of the programmed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell; and apply a second voltage to a gate of the unprogrammed memory cell, the second voltage being greater than a threshold voltage of the unprogrammed memory cell and less than the first voltage.

[0049] In a possible implementation, the programming direction is a direction close to the target input end, and the programmed memory cells are all unerased memory cells.

[0050] In a possible implementation, the programming direction is a direction away from the target input end, and the programmed memory cells are all re-written data memory cells, or the programmed memory cells are all unerased memory cells, or the programmed memory cells are re-written data memory cells and unerased memory cells.

[0051] In a possible implementation, the control circuit is further configured to turn on a channel of a memory cell of the non-selected memory string that is not between the target input end and the target memory cell.

[0052] In a possible implementation, a turn-off time of applying the first voltage to the gate of the programmed memory cell is earlier than a turn-off time of applying the pre-charge voltage to the target input end.

[0053] In a possible implementation, the number of the programmed storage units is multiple, and a cutoff time of applying the first voltage to the gate of the programmed storage unit far from the target input terminal is not later than a cutoff time of applying the first voltage to the gate of the programmed storage unit close to the target input terminal.

[0054] In a possible implementation, the input terminal connected with the bit line and the input terminal connected with the source line comprise a selection tube stack and a storage unit stack connected through a doped region, the target input terminal is the input terminal connected with the bit line, and the storage unit between the target input terminal and the target storage unit comprises a storage unit between the doped region and the target storage unit.

[0055] In another aspect, a storage system is provided, the storage system comprising a memory and a controller coupled to the memory, the controller configured to control the memory;

[0056] The memory comprises a storage array and a control circuit communicatively connected with the storage array; the storage array comprises a non-selected storage string, and the control circuit is configured to pre-charge the non-selected storage string according to the following steps before writing data to a selected storage unit:

[0057] applying a pre-charge voltage to a target input terminal of the non-selected storage string, the target input terminal being an input terminal connected with a bit line or an input terminal connected with a source line of the non-selected storage string;

[0058] turning on a channel of a storage unit between the target input terminal and a target storage unit in the non-selected storage string, the storage unit between the target input terminal and the target storage unit comprising a programmed storage unit, and the target storage unit being a storage unit connected with a selected word line in the non-selected storage string.

[0059] In a possible implementation, the control circuit is configured to apply a first voltage to a gate of the storage unit between the target input terminal and the target storage unit, the first voltage being greater than a threshold voltage of the programmed storage unit.

[0060] In a possible implementation, the storage unit between the target input terminal and the target storage unit further comprises an unprogrammed storage unit; the control circuit is configured to apply a first voltage to a gate of the programmed storage unit, the first voltage being greater than a threshold voltage of the programmed storage unit; and apply a second voltage to a gate of the unprogrammed storage unit, the second voltage being greater than a threshold voltage of the unprogrammed storage unit and less than the first voltage.

[0061] In a possible implementation, the programming direction is a direction close to the target input terminal, and the programmed storage units are all unerased storage units.

[0062] In a possible implementation, the programming direction is a direction away from the target input terminal, and the programmed storage units are all re-written data storage units, or the programmed storage units are all unerased storage units, or the programmed storage units are re-written data storage units and unerased storage units.

[0063] In a possible implementation, the control circuit is further configured to turn on the channel of the storage unit in the non-selected storage string that is not located between the target input terminal and the target storage unit.

[0064] In a possible implementation, the turn-off time of applying the first voltage to the gate of the programmed storage unit is earlier than the turn-off time of applying the pre-charge voltage to the target input terminal.

[0065] In a possible implementation, the number of the programmed storage units is a plurality, and the turn-off time of applying the first voltage to the gate of the programmed storage unit far away from the target input terminal is not later than the turn-off time of applying the first voltage to the gate of the programmed storage unit close to the target input terminal.

[0066] In a possible implementation, the input terminal connected with the bit line and the input terminal connected with the source line include a selection tube stack and a storage unit stack connected through a doped region, the target input terminal is the input terminal connected with the bit line, and the storage unit located between the target input terminal and the target storage unit includes a storage unit between the doped region and the target storage unit.

[0067] In another aspect, an electronic device is provided, the electronic device including a processor and a storage system, the processor being configured to read and write data from the storage system;

[0068] The storage system includes a memory and a controller coupled to the memory, the controller being configured to control the memory;

[0069] The memory includes a storage array and a control circuit communicatively connected to the storage array; the storage array includes a non-selected storage string, and the control circuit is configured to pre-charge the non-selected storage string according to the following steps before writing data to a selected storage unit:

[0070] applying a pre-charge voltage to a target input terminal of the non-selected memory string, the target input terminal being an input terminal of the non-selected memory string connected to a bit line or an input terminal connected to a source line;

[0071] turning on a channel of a memory cell between the target input terminal and a target memory cell of the non-selected memory string, the memory cell between the target input terminal and the target memory cell including a programmed memory cell, the target memory cell being a memory cell of the non-selected memory string connected to a selected word line.

[0072] In a possible implementation, the control circuit is configured to apply a first voltage to a gate of the memory cell between the target input terminal and the target memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell.

[0073] In a possible implementation, the memory cell between the target input terminal and the target memory cell further includes an unprogrammed memory cell; the control circuit is configured to apply a first voltage to a gate of the programmed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell; and apply a second voltage to a gate of the unprogrammed memory cell, the second voltage being greater than a threshold voltage of the unprogrammed memory cell and less than the first voltage.

[0074] In a possible implementation, the programming direction is a direction close to the target input terminal, and the programmed memory cells are all unerased memory cells.

[0075] In a possible implementation, the programming direction is a direction away from the target input terminal, and the programmed memory cells are all re-written data memory cells, or the programmed memory cells are all unerased memory cells, or the programmed memory cells are re-written data memory cells and unerased memory cells.

[0076] In a possible implementation, the control circuit is further configured to turn on a channel of a memory cell of the non-selected memory string that is not between the target input terminal and the target memory cell.

[0077] In a possible implementation, a turn-off time of applying the first voltage to the gate of the programmed memory cell is earlier than a turn-off time of applying the pre-charge voltage to the target input terminal.

[0078] In a possible implementation, the number of the programmed memory cells is a plurality, and a turn-off time of applying the first voltage to a gate of a programmed memory cell far from the target input terminal is not later than a turn-off time of applying the first voltage to a gate of a programmed memory cell close to the target input terminal.

[0079] In a possible implementation, the input end connected with the bit line and the input end connected with the source line comprise a selection tube stack and a storage unit stack, the selection tube stack and the storage unit stack are connected through a doped region, the target input end is the input end connected with the bit line, and the storage unit between the target input end and the target storage unit comprises a storage unit between the doped region and the target storage unit.

[0080] The technical scheme provided by the embodiment of the present application at least brings the following beneficial effects:

[0081] The technical scheme provided by the embodiment of the present application can avoid the phenomenon that the non-conducting channel blocks the movement of the electrons in the channel of the target storage unit to the target input end after the pre-charge voltage is applied to the target input end, so that the electrons in the channel of the target storage unit can be more fully attracted to the target input end, thereby realizing more sufficient pre-charging of the non-selected storage string, and further greatly reducing the programming interference suffered by the target storage unit. BRIEF DESCRIPTION OF DRAWINGS

[0082] In order to more clearly illustrate the technical scheme in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0083] Figure 1 is a structural schematic diagram of a storage block provided by the embodiment of the present application;

[0084] Figure 2 is a structural schematic diagram of a storage block provided by the embodiment of the present application;

[0085] Figure 3 is a structural schematic diagram of a storage block provided by the embodiment of the present application;

[0086] Figure 4 is a schematic diagram of a storage string provided by the embodiment of the present application;

[0087] Figure 5 is a schematic diagram of the state of the channel of a non-selected storage string provided by the embodiment of the present application;

[0088] Figure 6 is a flowchart of a pre-charging method provided by the embodiment of the present application;

[0089] Figure 7is a schematic diagram of a storage string provided by an embodiment of the present application;

[0090] Figure 8 is a schematic diagram of a voltage application case provided by an embodiment of the present application;

[0091] Figure 9 is a schematic diagram of a storage string provided by an embodiment of the present application;

[0092] Figure 10 is a schematic diagram of a voltage application case provided by an embodiment of the present application;

[0093] Figure 11 is a schematic diagram of a cross section of a storage string provided by an embodiment of the present application;

[0094] Figure 12 is a schematic diagram of a pre-charge device provided by an embodiment of the present application;

[0095] Figure 13 is a schematic diagram of a storage system provided by an embodiment of the present application;

[0096] Figure 14 is a schematic diagram of a storage system provided by an embodiment of the present application;

[0097] Figure 15 is a schematic diagram of a structure of a memory card provided by an embodiment of the present application;

[0098] Figure 16 is a schematic diagram of a structure of a solid state drive provided by an embodiment of the present application;

[0099] Figure 17 is a schematic diagram of a structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0100] In order to make the objects, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the drawings.

[0101] It should be noted that the terms "first", "second", and the like in the present application are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all the embodiments consistent with the present application. Rather, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0102] The pre-charge method provided in this application embodiment is applied to a memory. Exemplarily, the memory is a flash memory, such as a 3D NAND memory. The memory includes a memory array, which includes one or more memory blocks. A memory block includes multiple memory strings arranged in an array, and a memory string includes multiple memory cells connected in series.

[0103] Figure 1 This is a schematic diagram of the structure of a storage block in a memory provided in an embodiment of this application. For example... Figure 1 As shown, the memory block includes multiple memory strings: memory strings CS11 to CS1m and memory strings CS21 to CS2m. Here, m is an integer not less than 1. Memory strings CS11 to CS1m and CS21 to CS2m run along a bearing surface parallel to the substrate (i.e., Figure 1 The directional array is arranged in a plane formed by the +X and +Y directions. For example, Figure 1 The +X direction can also be called the row direction, and the +Y direction can also be called the column direction.

[0104] Each memory string comprises multiple (e.g., 32 or 64) memory cells (MCs) connected in series, with these multiple memory cells arranged in a direction perpendicular to the substrate's bearing surface (i.e., Figure 1 The cells are arranged in the +Z direction. Memory cells with the same height relative to the substrate bearing surface in different memory strings are located in the same layer.

[0105] In exemplary embodiments, the storage units involved in this application can be single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), or quad-level cells (QLC), etc. For SLC, each storage unit can store 1 bit of data; for MLC, each storage unit can store 2 bits of data; for TLC, each storage unit can store 3 bits of data; and for QLC, each storage unit can store 4 bits of data. For example, SLC can store two values ​​represented by 0 and 1; MLC can store four values ​​represented by 00, 01, 10 and 11; TLC can store eight values ​​represented by 000, 001, 010, 011, 100, 101, 110 and 111; QLC can store 16 values ​​represented by 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 and 1111.

[0106] As shown in Figure 1 each memory string includes at least one bottom select gate (BSG), memory cells MC1 to MCn, and at least one top select gate (TSG). The top select gate is also referred to as a top select gate or a drain select transistor, and the bottom select gate is also referred to as a bottom select gate or a source select transistor. n is an integer not less than 1.

[0107] As shown in Figure 1 between the at least one bottom select gate and the memory cell MC1 of each memory string, and between the at least one top select gate and the memory cell MCn, there is also a dummy cell (DC). The dummy cell is connected to the dummy cell in other memory strings through a dummy word line (DWL). The plurality of dummy cells at the same layer in the plurality of memory strings share the same dummy word line. Each dummy word line includes the gates of the plurality of dummy cells at the same layer and a gate line for coupling the gates. It can also be understood that the gate line is connected and coupled with the gates of the plurality of dummy cells to form a dummy word line.

[0108] In some embodiments, the dummy cell between the bottom select gate and the memory cell MC1 can reduce the electric field between the bottom select gate and the memory cell MC1, and the dummy cell between the top select gate and the memory cell MCn can reduce the electric field between the top select gate and the memory cell MCn. When the number of dummy cells increases, the size of the memory block and the operation reliability of the memory block increase, and when the number of dummy cells decreases, the size of the memory block and the operation reliability of the memory block decrease.

[0109] The bottom select gates of the memory strings arranged in the row direction can be connected to a source select line (SSL) extending in the row direction. As shown in Figure 1 The bottom select gates of the memory strings CS11 to CS1m arranged in the first row are connected to the source select line SSL1. The bottom select gates of the memory strings CS21 to CS2m arranged in the second row are connected to the source select line SSL2. Each source select line includes the gates of the plurality of bottom select gates at the same layer and a gate line for coupling the gates. It can also be understood that the gate line is coupled with the gates of the plurality of bottom select gates to form a source select line. In some embodiments, the bottom select gates of the memory strings CS11 to CS1m and the memory strings CS21 to CS2m can be commonly connected to a single source select line.

[0110] The select transistors of the memory strings arranged in the row direction can be connected to the drain select line (DSL) extending in the row direction. For example... Figure 1 As shown, the top-select transistors of memory strings CS11 to CS1m arranged in the first row are connected to the drain select line DSL1. The top-select transistors of memory strings CS21 to CS2m arranged in the second row are connected to the drain select line DSL2. Each drain select line includes the gates of multiple top-select transistors on the same layer and a gate line for coupling the gates. It can also be understood that the gate line is coupled to the gates of multiple top-select transistors to form a drain select line.

[0111] Each memory string has two input terminals: one directly or indirectly connected to the bit line (BL), and the other directly or indirectly connected to the source line (SL). In other words, each memory string has two input terminals: one connected to the bit line and one connected to the source line. Figure 1 In the example, memory strings CS11 and CS21 arranged in the first column are connected to bit line BL1, and memory strings CS1m and CS2m arranged in the m-th column are connected to bit line BLm. Exemplarily, each memory string has an input terminal connected to the same source line, also known as a common source line (CSL).

[0112] from Figure 1 As can be seen, the storage block includes m BLs (BL0 to BLm) arranged along the +X direction, multiple DSLs (DSL1, DSL2, etc.) arranged along the +Y direction, and multiple SSLs (SSL1, SSL2, etc.) arranged along the +Y direction. Each DSL is connected to m TSGs arranged along the +X direction, each BL is connected to multiple storage strings arranged along the +Y direction, and each SSL is connected to m BSGs arranged along the +X direction.

[0113] Continue to refer to Figure 1 In each memory string, memory cells MC1 to MCn are connected in series, and these cells are connected to word lines WL1 to WLn, respectively. Memory cells in each memory string within a memory block share a set of word lines with memory cells in other memory strings. For example... Figure 1The n WLs (WL0 to WLn) arranged in the +Z direction in the memory cell array 100 are connected to the memory cells in the same layer (i.e., having the same height relative to the bearing surface of the substrate). Each word line (WL) includes the gates of the memory cells in the same layer and a gate line for coupling the gates. In other words, the gate line is coupled to the gates of the memory cells to form a word line.

[0114] In some embodiments, the memory cells in the memory string can be floating gate type field effect transistors or charge trap type field effect transistors, etc. capable of storing data. The TSG and the BSG can be field effect transistors incapable of storing data or field effect transistors capable of storing data.

[0115] The memory cell includes a source, a drain, a gate, and a storage layer. The storage layer is used to store electrons, and the number of stored electrons determines the data stored in the memory cell. For the case where the memory cell is a floating gate type field effect transistor, the storage layer in the memory cell is a floating gate (FG) made of a conductor material. For the case where the memory cell is a charge trap type field effect transistor, the storage layer in the memory cell is a charge trapping layer made of an insulating material such as silicon nitride.

[0116] When data is written into the memory cell, a programming voltage can be applied to the gate of the memory cell to cause the electrons in the channel of the memory cell to tunnel to the storage layer. The number of electrons tunneling to the storage layer can be controlled by controlling the magnitude of the programming voltage, thereby controlling the magnitude of the threshold voltage Vth of the memory cell. Generally, the higher the amount of charge stored in the storage layer, the higher the threshold voltage Vth of the memory cell. It can be understood that when the threshold voltage Vth of the memory cell is different, the voltage required to be applied to the gate of the memory cell to control the conduction of the channel of the memory cell is different. Therefore, the magnitude of the threshold voltage Vth of the memory cell can reflect the content of the data stored therein. It should be noted that the storage layer can refer to a floating gate or a charge trapping layer, which is not limited in the embodiments of the present application.

[0117] Data is read in the form of a page (Page). The Page is a virtual concept and is not a physical concept. For example, for SLC, each memory cell stores 1 bit of data. When reading the data stored in a layer of memory cells at the physical level, 1 Page of data is read. For MLC, each memory cell stores 2 bits of data. When reading the data stored in a layer of memory cells at the physical level, 2 Pages of data are read.

[0118] When reading the data stored in the memory cell, different levels of read voltages can be applied to the gate of the memory cell in order from low to high. After each level of read voltage is applied, it can be detected whether the channel of the memory cell is turned on. In this way, the threshold voltage Vth of the memory cell can be detected, and the data stored in the memory cell can be read.

[0119] Because it is not easy to directly measure the threshold voltage of the memory cell, and the output current of the memory cell is related to the gate voltage and the threshold voltage, the threshold voltage of the memory cell is determined by measuring the current.

[0120] Taking SLC as an example, the threshold voltage distribution in the erased state is defined as “1”, and the threshold voltage distribution in the programmed state is defined as “0”. The voltage Vpass (greater than the maximum threshold voltage in the programmed state) is applied to the gate of the memory cell that is not selected, and the voltage Vread (less than the minimum threshold voltage in the programmed state and greater than the maximum threshold voltage in the erased state) is applied to the gate of the memory cell that is selected. If the current can be detected on the bit line, it means that the channel of the selected memory cell is turned on, and the selected memory cell is in the erased state “1”; if no current is detected on the bit line, it means that the channel of the selected memory cell is not turned on, and the selected memory cell is in the programmed state “0”.

[0121] Exemplarily, the channels of the memory cells in the memory string can be connected in sequence and form a column structure perpendicular to the substrate, which is the channel of the memory string. For ease of description, hereinafter, the channel corresponding to one memory string is referred to as the channel of the memory string, and the channel corresponding to one memory cell is referred to as the channel of the memory cell.

[0122] Figure 2 is a structural schematic diagram of a memory provided by an embodiment of the present application. As shown in Figure 2 The memory 200 includes a storage array 210 and a control circuit 220 communicatively connected to the storage array 210.

[0123] The storage array 210 includes one or more memory blocks, each memory block includes a plurality of array-arranged memory strings, and each memory string includes a plurality of memory cells connected in series between an input end connected to a bit line and an input end connected to a source line. Each memory string further includes a TSG located on the side of the input end connected to the bit line and a BSG located on the side of the input end connected to the source line.

[0124] The control circuit 220 is configured to drive the memory array 210. The control circuit 220 can be configured to pre-charge unselected memory strings in a memory block in the memory array 210 according to the pre-charge method provided by embodiments of the present application. In exemplary embodiments, the control circuit 220 can also be configured to perform erase, program, read, verify, or other operations on memory cells in the memory strings.

[0125] It should be understood by those skilled in the art that the memory 200 described above is only an example, and other existing or future possible memories can also be applicable to the present application and should be included in the protection scope of the present application.

[0126] As shown in the example, Figure 3 The control circuit 220 includes an address decoder 221, a voltage generator 222, a read and write circuit 223, and a data input / output circuit 224. The memory 200 also includes a control logic 230. The control logic 230 can be connected to the address decoder 221, the voltage generator 222, the read and write circuit 223, and the data input / output circuit 224.

[0127] The address decoder 221 can be connected to the memory array 210 through row lines. The row lines can include drain select lines, word lines, source select lines, and common source lines, etc. Among them, the word lines can include word lines connected to memory cells and pseudo word lines connected to dummy cells.

[0128] The address decoder 221 can be configured to operate in response to the control of the control logic 230. The address decoder 221 can receive an address from the control logic 230. The address decoder 221 can be configured to decode the received address to obtain a block address, and then select at least one memory block in the memory array 210 according to the block address. The address decoder 221 can also be configured to decode the received address to obtain a row address, and then apply the voltage provided by the voltage generator 222 to at least one word line according to the row address. The address decoder 221 can also be configured to decode the received address to obtain a column address, which can be passed to the read and write circuit 223. For example, the address decoder 221 can include components such as a row decoder, a column decoder, and an address buffer.

[0129] The voltage generator 222 is configured to generate a plurality of voltages. The voltage generator 222 can operate in response to the control of the control logic 230. In an exemplary embodiment, the voltage generator 222 can generate various voltages required by the memory array 210, such as erase voltages, program voltages, pass voltages, read voltages, etc., by using external power supply voltages or internal power supply voltages. The voltages generated by the voltage generator 222 can be supplied to the memory array 210 through the address decoder 221.

[0130] The read and write circuit 223 can include a page buffer. The page buffer can be connected to the memory array 210 by a bit line. The page buffer can operate in response to control by the control logic 230. The page buffer can transfer data with the data input / output circuit 224.

[0131] The data input / output circuit 224 can be connected to the page buffer in the read and write circuit 223 by a data line. The data input / output circuit 224 can operate in response to control by the control logic 230. The data input / output circuit 224 can include a plurality of input / output buffers (not shown) that receive data being input.

[0132] The control logic 230 can be configured to control operation of the memory array 210, such as programming operations, erase operations, read operations, verify operations, etc. The control logic 230 can operate in response to externally transmitted commands.

[0133] Exemplarily, the plurality of word lines in one memory block can be divided into first stack word lines and second stack word lines, the first stack word lines are a plurality of adjacent word lines close to the BL, and the second stack word lines are a plurality of adjacent word lines close to the SL. The division manner of the first stack word lines and the second stack word lines in the plurality of word lines in one memory block is not limited in the embodiments of the present application. Exemplarily, the division manner is equal division or non-equal division.

[0134] For one memory block, before programming in the programming direction, an erase operation needs to be performed first. The erase manner adopted when performing the erase operation is determined according to the actual application scenario. Exemplarily, the erase manner can mean that the storage units connected to each word line in the memory block are all erased (also referred to as full erase), or can mean that only the storage units connected to part of the word lines in each word line are erased (also referred to as partial erase). The specific case of the partial erase is not limited in the embodiments of the present application. Exemplarily, the specific case of the partial erase includes but is not limited to: only the storage units connected to the first stack word lines in each word line are erased (also referred to as first stack erase), only the storage units connected to the second stack word lines in each word line are erased (also referred to as second stack erase), only the storage units connected to the middle part of the word lines in each word line are erased (also referred to as middle erase), only the storage units connected to a plurality of non-adjacent word lines in each word line are erased, etc.

[0135] Exemplarily, the storage units connected to the first stack word lines in one memory string are referred to as first stack storage units, and the storage units connected to the second stack word lines in one memory string are referred to as second stack storage units. For the case of the partial erase being the first stack erase, the first stack storage units in each memory string in the memory block are erased (for example, as shown in FIG. 2B, the first stack storage units in each memory string in the memory block are erased, and the second stack storage units in each memory string in the memory block are not erased). Figure 4(b) in FIG. 2B). In the case of partial erasure, the second stack storage cells in each of the storage strings in the memory block are erased (as shown in Figure 4 (b) in FIG. 2B). In the case of partial erasure, the second stack storage cells in each of the storage strings in the memory block are erased (as shown in Figure 4 In FIG. 2B, the unerased storage cells are marked with black, and the erased storage cells are marked with white. Note that the cases of the erased storage cells in the storage strings are not limited to the two cases shown in Figure 4 In FIG. 2B, the unerased storage cells are marked with black, and the erased storage cells are marked with white. Note that the cases of the erased storage cells in the storage strings are not limited to the two cases shown in

[0136] Exemplarily, for a memory block, the process of programming in the programming direction includes a plurality of programming stages, each of which is used to write data to selected storage cells connected to a selected word line. The selected word line refers to the word line selected in the process of programming in the programming direction, and the selected storage cells connected to the selected word line refer to the storage cells in the selected word line that need to write data. The storage string in which the selected storage cells are located is referred to as the selected storage string, and the storage string in which the storage cells not needing to write data in the selected word line are located is referred to as the non-selected storage string.

[0137] Note that the selected word line changes constantly as the process of programming in the programming direction proceeds. The positional relationship between the selected word line in the next programming stage and the selected word line in the previous programming stage is related to the programming direction. Exemplarily, if the programming direction is the direction from the input end connected to the source line to the input end connected to the bit line (also referred to as the forward programming direction), the selected word line in the next programming stage is located above the selected word line in the previous programming stage. For example, as shown in Figure 1 FIG. 2A, if the selected word line in the previous programming stage is WL1, the selected word line in the next programming stage is one of WL2 to WLn, that is, the selected word line in the next programming stage is located above the selected word line in the previous programming stage.

[0138] If the programming direction is the direction from the input end connected to the bit line to the input end connected to the source line (also referred to as the reverse programming direction), the selected word line in the next programming stage is located below the selected word line in the previous programming stage. For example, as shown in Figure 1 FIG. 2B, if the selected word line in the previous programming stage is WLn, the selected word line in the next programming stage is one of WLn-1 to WL1, that is, the selected word line in the next programming stage is located below the selected word line in the previous programming stage. Exemplarily, for the case of partial erasure, the selected word line is selected from the word line connected to the storage cells that are erased.

[0139] In a programming phase, when programming selected memory cells connected to a selected word line, i.e., writing data to the selected memory cells connected to the selected word line, a programming voltage is applied to the selected word line to cause electrons in the channel of the selected memory cells to tunnel to the floating gate or charge trapping layer. However, the programming voltage can possibly cause electrons in the memory cells connected to the selected word line in the unselected memory strings to tunnel as well, i.e., the memory cells connected to the selected word line in the unselected memory strings are subject to program disturb when the selected memory cells are programmed. Exemplarily, the memory cells connected to the selected word line in the unselected memory strings are referred to as target memory cells in the unselected memory strings.

[0140] To reduce program disturb, before the programming voltage is applied to the selected word line, the unselected memory strings are pre-charged to reduce the number of electrons in the channel of the target memory cells in the unselected memory strings and to increase the potential of the channel of the target memory cells in the unselected memory strings, so that the probability of electron tunneling in the target memory cells can be effectively reduced when the selected memory cells are programmed, and thus the program disturb to the target memory cells can be reduced. In exemplary embodiments, to facilitate operation, the selected memory string in which the selected memory cells are located is also pre-charged in addition to the pre-charging of the unselected memory strings.

[0141] Some embodiments utilize a pre-charging method in which, when the programming direction is a reverse programming direction, a pre-charging voltage is applied to the input end connected to the source line of the unselected memory strings, and a small voltage (e.g., 0V) is applied to the gate of each memory cell in the unselected memory strings; when the programming direction is a forward programming direction, a pre-charging voltage is applied to the input end connected to the bit line of the unselected memory strings, and a small voltage (e.g., 0V) is applied to the gate of each memory cell in the unselected memory strings. The small voltage can only turn on the channel of an unprogrammed memory cell.

[0142] It should be noted that, to ensure that the input end to which the pre-charging voltage is applied can attract electrons in the channel of the target memory cells, after the pre-charging voltage is applied to a certain input end, a turn-on voltage is applied to the gate of the select transistor located on the side of the input end to which the pre-charging voltage is applied to turn on the channel of the select transistor located on the side of the input end to which the pre-charging voltage is applied. For example, if the pre-charging voltage is applied to the input end connected to the bit line, a turn-on voltage is applied to the gate of TSG; if the pre-charging voltage is applied to the input end connected to the source line, a turn-on voltage is applied to the gate of BSG. Exemplarily, the turn-on voltage applied to the gate of the select transistor is greater than the threshold voltage of the select transistor.

[0143] By using the pre-charge method described in some embodiments to pre-charge the unselected memory string, a relatively sufficient pre-charge can be achieved if the erase method corresponding to the memory block is a full erase. For example, taking the programming direction as the forward programming direction, and the pre-charge method as applying a pre-charge voltage to the input terminal connected to the bit line of the unselected memory string, and applying a small voltage (e.g., 0V) to the gate of each memory cell in the unselected memory string, when the erase method corresponding to the memory block is a full erase, all the first stack memory cells connected to the first stack word lines (Upper deckWLs) in the unselected memory string are not written with data. Here, "not written with data" means that data was erased but not written during the programming process. For example, memory cells without written data do not store data and can be considered to be in the E state.

[0144] In the second stack memory cells connected to the second stack word lines (Lower deck WLs), memory cells connected to word lines above the selected word line (PGM WL) and target memory cells connected to the PGM WL are all left unwritten with data. Memory cells connected to word lines below the PGM WL are either fully or partially rewritten with data, or none are written with data. Rewriting data refers to data that has been erased and then rewritten during programming. For example, memory cells that have been rewritten with data contain data and can be considered to be in the P state.

[0145] When the erase mode corresponding to the memory block is full erase, the memory cell containing data can only be located between the target memory cell and the input terminal connected to the source line. That is, even if the channel is not conducting under a small applied voltage, the channel of the memory cell containing data will not block the movement of electrons in the channel of the target memory cell toward the input terminal connected to the bit line, thereby enabling a relatively sufficient pre-charge.

[0146] For example, when the erase method corresponding to the storage block is full erase, pre-charging is performed using the pre-charging method in some embodiments, and the state of the channel of the non-selected storage string is as follows: Figure 5 As shown in (a), the channels of memory cells above the target memory cell in the non-selected memory string are turned on. All free electrons in the turned-on channels are attracted to the input terminal connected to the bit line. The electron density at the input terminal connected to the bit line is relatively high, resulting in sufficient pre-charging. For example, the pre-charging method of applying a pre-charging voltage to the input terminal connected to the bit line of the non-selected memory string can be simply referred to as BL pre-charging. It should be noted that... Figure 5 The following example illustrates the method of rewriting all data in the storage cells connected by word lines below PGM WL, but the embodiments of this application are not limited thereto.

[0147] With the development of modern society communication and big data, the demand for storage capacity will continue to increase, and with the increase of the number of storage layers and the number of unit storage bits, the full erase mode in units of storage blocks will be slower and slower in erase speed. Therefore, the partial erase mode of the storage block is usually selected to improve the erase speed. The inventors found that if the erase mode corresponding to the storage block is partial erase, the pre-charge mode in some embodiments may cause the channel of the unerased storage unit to be non-conductive, resulting in blockage of the pre-charge process, insufficient pre-charge, and strong programming interference.

[0148] Exemplarily, taking the programming direction as a positive programming direction, the pre-charge mode is that a pre-charge voltage is applied to the input end connected with the bit line of the unselected storage string, and a small voltage (such as 0V) is applied to the gate of each storage unit in the unselected storage string. In the case that the erase mode corresponding to the storage block is the second stack erase, all the first stack storage units connected with the first stack word line in the storage unit in the unselected storage string are unerased; in the second stack storage unit connected with the second stack word line, the storage units connected with the word line above PGM WL and the target storage unit connected with PGM WL are all unerased, the storage units connected with the word line below PGM WL are all or partially re-written data, or all unerased. Exemplarily, the unerased storage unit stores data and can be considered to be in the P state.

[0149] In the case that the erase mode corresponding to the storage block is the second stack erase, there is a storage unit storing data between the target storage unit and the input end connected with the bit line. In this case, under the applied small voltage, the channel of the storage unit storing data between the target storage unit and the input end connected with the bit line is non-conductive, which blocks the movement of the electrons in the channel of the target storage unit towards the input end connected with the bit line, so that sufficient pre-charge cannot be achieved.

[0150] Exemplarily, in the case that the erase mode corresponding to the storage block is the second stack erase, the pre-charge is performed by using the pre-charge mode in some embodiments, and the state of the channel of the unselected storage string is as shown in (b) of FIG. 8. Figure 5 In the case that the erase mode corresponding to the storage block is the second stack erase, there is a storage unit storing data between the target storage unit and the input end connected with the bit line. In this case, under the applied small voltage, the channel of the storage unit storing data between the target storage unit and the input end connected with the bit line is non-conductive, which blocks the movement of the electrons in the channel of the target storage unit towards the input end connected with the bit line, so that sufficient pre-charge cannot be achieved.

[0151] According to the above analysis, it is difficult to pre-charge the unselected storage string sufficiently by using the pre-charge mode in some embodiments, therefore, it is crucial to provide a mode capable of pre-charging the unselected storage string sufficiently.

[0152] This application provides a pre-charge method applied to a control circuit 220 in a memory 200. The pre-charge method pre-charges a non-selected memory string before writing data to a selected memory cell connected to a selected word line.

[0153] For a memory block, the programming process according to the programming direction includes multiple programming stages. Different programming stages correspond to different selected word lines. A programming stage is used to write data to the selected memory cell connected to the selected word line corresponding to that programming stage. Before each programming stage, there is a precharge stage, which is used to precharge the non-selected memory string corresponding to the programming stage. That is, before writing data to the selected memory cell connected to the selected word line corresponding to each programming stage, the non-selected memory string corresponding to each programming stage needs to be precharged.

[0154] The principle of pre-charging the non-selected memory strings corresponding to each programming stage is the same. This application embodiment uses any programming stage as an example for illustration. That is, the selected word lines and non-selected memory strings in this application embodiment refer to the selected word lines and non-selected memory strings corresponding to any programming stage. It should be noted that the selected word lines corresponding to different programming stages are different, and the non-selected memory strings corresponding to different programming stages may be the same or different. This is related to whether the selected memory strings containing the selected memory cells connected by the selected word lines of different programming stages are the same. Which memory cells connected by the selected word lines are selected memory cells are flexibly determined according to the actual data storage requirements, and this application embodiment does not limit this.

[0155] It should be noted that there may be one or more non-selected memory strings. The principle of precharging each non-selected memory string is the same. This application embodiment takes one non-selected memory string as an example for illustration. If there are multiple non-selected memory strings, the precharging method provided in this application embodiment can be used to precharge each non-selected memory string.

[0156] like Figure 6 As shown, the pre-charging method provided in this application embodiment includes steps 601 and 602.

[0157] In step 601, a pre-charge voltage is applied to the target input terminal of the unselected memory string. The target input terminal is either the input terminal of the unselected memory string connected to the bit line or the input terminal connected to the source line.

[0158] The input terminals at two ends of the unselected memory string are respectively an input terminal connected with a bit line and an input terminal connected with a source line. The target input terminal can be an input terminal connected with a bit line or an input terminal connected with a source line. After the target input terminal is determined, a pre-charge voltage is applied to the target input terminal, and the pre-charge voltage is used to apply an electric field force to the electrons in the channel of the target memory cell in the unselected memory string, so that the electrons can leave the channel of the target memory cell under the action of the electric field force and be absorbed by the target input terminal, thereby increasing the potential of the channel of the target memory cell. The target memory cell refers to the memory cell connected with the selected word line in the unselected memory string. The pre-charge voltage is not limited in the embodiments of the present application, and is exemplarily a voltage in the range of 0-10V, such as 2V.

[0159] In an exemplary embodiment, the target input terminal is connected with BL or SL, and the pre-charge voltage is applied to the target input terminal in the following manner: the pre-charge voltage is applied to the BL or SL connected with the target input terminal to apply the pre-charge voltage to the target input terminal.

[0160] Exemplarily, in the process of pre-charging the unselected memory string, the other input terminal except the target input terminal can be grounded, that is, 0V is applied to the other input terminal except the target input terminal, or a voltage greater than 0V but less than the pre-charge voltage can be applied to the other input terminal except the target input terminal.

[0161] In an exemplary embodiment, in the process of pre-charging the unselected memory string, a turn-on voltage needs to be applied to the gate of the selection transistor on the side of the target input terminal to ensure that the electrons in the channel of the target memory cell can move to the target input terminal under the attraction of the pre-charge voltage. When the target input terminal is an input terminal connected with a bit line, the selection transistor on the side of the target input terminal is TSG; when the target input terminal is an input terminal connected with a source line, the selection transistor on the side of the target input terminal is BSG. After the target input terminal is selected, the selection transistor on the side of the target input terminal can be determined, and then a turn-on voltage is applied to the gate of the selection transistor on the side of the target input terminal.

[0162] The turn-on voltage is used to turn on the channel of the selection transistor on the side of the target input terminal, that is, to open the selection transistor on the side of the target input terminal, so as to avoid the selection transistor on the side of the target input terminal from blocking the movement of the electrons in the channel of the target memory cell towards the target input terminal. Exemplarily, the turn-on voltage is greater than the threshold voltage of the selection transistor on the side of the target input terminal, so as to ensure that the channel of the selection transistor on the side of the target input terminal is turned on. Exemplarily, the threshold voltage of the selection transistor on the side of the target input terminal is 1V, and the turn-on voltage is 2V.

[0163] In the example embodiment, the gate of the target input side selection transistor is connected to a selection line (DSL or SSL), and the on voltage is applied to the gate of the target input side selection transistor by applying the on voltage to the selection line to which the target input side selection transistor is connected.

[0164] In step 602, the channel of the memory cell between the target input terminal and the target memory cell in the non-selected memory string is turned on, and the memory cell between the target input terminal and the target memory cell includes a programmed memory cell.

[0165] The target memory cell is the memory cell in the non-selected memory string connected to the selected word line.

[0166] The programmed memory cell refers to a memory cell between the target input terminal and the target memory cell storing data, and the threshold voltage of the programmed memory cell is relatively large. At a small voltage (e.g., 0V), the channel of the programmed memory cell is not turned on. Therefore, if the memory cell between the target input terminal and the target memory cell includes a programmed memory cell, the electrons in the channel of the target memory cell cannot be sufficiently attracted to the target input terminal by using the pre-charge method of some embodiments. In the example embodiment, the channel of the memory cell between the target input terminal and the target memory cell is turned on when the memory cell between the target input terminal and the target memory cell includes a programmed memory cell, thereby avoiding the phenomenon that the non-conducting channel blocks the movement of the electrons in the channel of the target memory cell to the target input terminal, so that the electrons in the channel of the target memory cell can be more fully attracted to the target input terminal.

[0167] The example embodiment does not limit whether the memory cell between the target input terminal and the target memory cell includes an unprogrammed memory cell. The unprogrammed memory cell refers to a memory cell between the target input terminal and the target memory cell not storing data. That is, the memory cell between the target input terminal and the target memory cell can all be programmed memory cells, or can include programmed memory cells and unprogrammed memory cells.

[0168] For example, any programmed memory cell can refer to a memory cell that has not been erased or a memory cell that has been re-written with data, and any unprogrammed memory cell can refer to a memory cell that has not been written with data. For example, each memory cell includes a storage layer, and whether a memory cell is a programmed memory cell or an unprogrammed memory cell can be determined according to whether the storage layer of the memory cell stores an electron. If the storage layer of the memory cell stores an electron, the memory cell is a programmed memory cell. If the storage layer of the memory cell does not store an electron, the memory cell is an unprogrammed memory cell. For example, the storage layer of the memory cell can be a floating gate or a charge trapping layer, and embodiments of the present application do not limit the same.

[0169] The programmed memory cells can all be memory cells that have not been erased, can all be memory cells that have been re-written with data, or can be partially memory cells that have not been erased and partially memory cells that have been re-written with data. Next, the programmed memory cells in the non-selected memory string in some example cases are introduced.

[0170] In a possible implementation, the programming direction is a direction close to the target input end. In this case, the memory cells that have been re-written with data are all located between the target input end and the target memory cell, that is, there are memory cells that have not been erased between the target input end and the target memory cell, and there are no memory cells that have been re-written with data. Therefore, when the programming direction is a direction close to the target input end, the programmed memory cells are all memory cells that have not been erased.

[0171] For example, the programming direction close to the target input end includes the following two cases: the target input end is an input end connected to a bit line, and the programming direction is a direction from an input end connected to a source line to the input end connected to the bit line; or the target input end is an input end connected to a source line, and the programming direction is a direction from an input end connected to a bit line to the input end connected to the source line.

[0172] That is, when the target input end is an input end connected to a bit line, and the programming direction is a direction from an input end connected to a source line to the input end connected to the bit line, the programmed memory cells are all memory cells that have not been erased. When the target input end is an input end connected to a source line, and the programming direction is a direction from an input end connected to a bit line to the input end connected to the source line, the programmed memory cells are all memory cells that have not been erased.

[0173] In one possible implementation, the programming direction is a direction away from the target input terminal. In this case, there can be unerased storage cells between the target input terminal and the target storage cell, and there can be no storage cells that have been re-written with data; there can be storage cells that have been re-written with data, and there can be no unerased storage cells; or there can be both unerased storage cells and storage cells that have been re-written with data.

[0174] When there are unerased storage cells between the target input terminal and the target storage cell, and there are no storage cells that have been re-written with data, all of the programmed storage cells are unerased storage cells. When there are storage cells that have been re-written with data between the target input terminal and the target storage cell, and there are no unerased storage cells, all of the programmed storage cells are storage cells that have been re-written with data. When there are both unerased storage cells and storage cells that have been re-written with data between the target input terminal and the target storage cell, the programmed storage cells are both storage cells that have been re-written with data and unerased storage cells. Therefore, when the programming direction is a direction away from the target input terminal, all of the programmed storage cells are either storage cells that have been re-written with data, or all of the programmed storage cells are unerased storage cells, or the programmed storage cells are both storage cells that have been re-written with data and unerased storage cells.

[0175] Exemplarily, the programming direction being a direction away from the target input terminal includes the following two cases: the target input terminal is an input terminal connected to a bit line, and the programming direction is a direction from the input terminal connected to the bit line to an input terminal connected to a source line; or the target input terminal is an input terminal connected to a source line, and the programming direction is a direction from the input terminal connected to the source line to an input terminal connected to a bit line.

[0176] That is, when the target input terminal is an input terminal connected to a bit line, and the programming direction is a direction from the input terminal connected to the bit line to an input terminal connected to a source line, all of the programmed storage cells are either storage cells that have been re-written with data, or all of the programmed storage cells are unerased storage cells, or the programmed storage cells are both storage cells that have been re-written with data and unerased storage cells. When the target input terminal is an input terminal connected to a source line, and the programming direction is a direction from the input terminal connected to the source line to an input terminal connected to a bit line, all of the programmed storage cells are either storage cells that have been re-written with data, or all of the programmed storage cells are unerased storage cells, or the programmed storage cells are both storage cells that have been re-written with data and unerased storage cells.

[0177] In the exemplary embodiments, the specific conditions of the programmed storage cells in the unselected storage string are different in different combinations of the programming direction and the presence state of the unerased storage cells in the unselected storage string.

[0178] Exemplarily, one combination case of the programming direction and the presence state of the un-erased storage unit in the non-selected storage string is that the programming direction is from the input end connected with the source line to the input end connected with the bit line, and the un-erased storage unit in the non-selected storage string is located at the side of the input end connected with the bit line. In this case, the input end connected with the bit line can be selected as the target input end, or the input end connected with the source line can be selected as the target input end.

[0179] The un-erased storage unit in the non-selected storage string located at the side of the input end connected with the bit line can indicate that the corresponding erasing mode of the storage block is the second stack erasing, that is, the corresponding erasing mode of the storage block is to erase the storage units connected with one or more adjacent word lines close to the side of the input end connected with the source line. Since the selected word line is selected from the word lines connected with the erased storage units, the target storage unit in the non-selected storage string must be farther away from the input end connected with the bit line than the un-erased storage unit, that is, the un-erased storage unit in the non-selected storage string is located between the input end connected with the bit line and the target storage unit.

[0180] In the case that the programming direction is from the input end connected with the source line to the input end connected with the bit line, there can be no storage unit in the non-selected storage string that rewrites data, or there can be storage units in the non-selected storage string that rewrite data. If there are storage units that rewrite data, the storage units that rewrite data are all closer to the input end connected with the source line than the target storage unit, that is, the storage units that rewrite data in the non-selected storage string are all located between the input end connected with the source line and the target storage unit.

[0181] Based on the above analysis, in the case that the programming direction is from the input end connected with the source line to the input end connected with the bit line, and the un-erased storage unit in the non-selected storage string is located at the side of the input end connected with the bit line, if the input end connected with the bit line is selected as the target input end, the storage unit storing data located between the input end connected with the bit line and the target storage unit refers to the un-erased storage unit in the non-selected storage string, that is, the programmed storage unit is the un-erased storage unit in the non-selected storage string. If the input end connected with the source line is selected as the target input end and there are storage units in the non-selected storage string that rewrite data, the storage unit storing data located between the input end connected with the source line and the target storage unit refers to the storage unit that rewrites data in the non-selected storage string, that is, the programmed storage unit is the storage unit that rewrites data in the non-selected storage string.

[0182] For example, in a case where the programming direction is from the input end connected to the bit line to the input end connected to the source line, and the un-erased memory cell in the non-selected memory string is located at the side of the input end connected to the source line, the input end connected to the bit line can be selected as the target input end, or the input end connected to the source line can be selected as the target input end.

[0183] In a case where the programming direction is from the input end connected to the bit line to the input end connected to the source line, and the un-erased memory cell in the non-selected memory string is located at the side of the input end connected to the source line, the input end connected to the bit line can be selected as the target input end, or the input end connected to the source line can be selected as the target input end.

[0184] In a case where the programming direction is from the input end connected to the bit line to the input end connected to the source line, the memory cell in the non-selected memory string that can not exist re-written data can exist re-written data. If the memory cell that exists re-written data exists, the memory cell that exists re-written data is all closer to the input end connected to the bit line than the target memory cell, that is, the memory cell that exists re-written data in the non-selected memory string is all located between the input end connected to the bit line and the target memory cell.

[0185] Based on the above analysis, in a case where the programming direction is from the input end connected to the bit line to the input end connected to the source line, and the un-erased memory cell in the non-selected memory string is located at the side of the input end connected to the source line, if the input end connected to the source line is selected as the target input end, the memory cell that stores data and is located between the input end connected to the source line and the target memory cell refers to the un-erased memory cell in the non-selected memory string, that is, the programmed memory cell is the un-erased memory cell in the non-selected memory string. If the input end connected to the bit line is selected as the target input end and the non-selected memory string exists the memory cell that exists re-written data, the memory cell that stores data and is located between the input end connected to the bit line and the target memory cell refers to the memory cell that exists re-written data in the non-selected memory string, that is, the programmed memory cell is the memory cell that exists re-written data in the non-selected memory string.

[0186] Exemplarily, one combination of the programming direction and the existence state of the unerased memory cells in the non-selected memory string is that the programming direction is from the input end connected with the bit line to the input end connected with the source line, and the unerased memory cells in the non-selected memory string are located at the side of the input end connected with the bit line. In this case, the unerased memory cells in the non-selected memory string are all located between the input end connected with the bit line and the target memory cell, and the memory cells in the non-selected memory string that can not exist re-written data can exist re-written data. If the memory cells that can not exist re-written data exist re-written data, the memory cells that exist re-written data in the non-selected memory string are all located between the input end connected with the bit line and the target memory cell.

[0187] In the case that the programming direction is from the input end connected with the bit line to the input end connected with the source line, and the unerased memory cells in the non-selected memory string are located at the side of the input end connected with the bit line, the input end connected with the bit line is selected as the target input end. If the memory cells that can not exist re-written data exist re-written data in the non-selected memory string, the memory cells that store data located between the input end connected with the bit line and the target memory cell refer to the unerased memory cells and the memory cells that exist re-written data in the non-selected memory string, that is, the programmed memory cells are the unerased memory cells and the memory cells that exist re-written data in the non-selected memory string. If the memory cells that can not exist re-written data do not exist re-written data in the non-selected memory string, the memory cells that store data located between the input end connected with the bit line and the target memory cell refer to the unerased memory cells in the non-selected memory string, that is, the programmed memory cells are the unerased memory cells in the non-selected memory string.

[0188] Exemplarily, one combination of the programming direction and the existence state of the unerased memory cells in the non-selected memory string is that the programming direction is from the input end connected with the source line to the input end connected with the bit line, and the unerased memory cells in the non-selected memory string are located at the side of the input end connected with the source line. In this case, the unerased memory cells in the non-selected memory string are all located between the input end connected with the source line and the target memory cell, and the memory cells in the non-selected memory string that can not exist re-written data can exist re-written data. If the memory cells that can not exist re-written data exist re-written data, the memory cells that exist re-written data in the non-selected memory string are all located between the input end connected with the source line and the target memory cell.

[0189] In the case that the unerased memory cells in the non-selected memory string are located at the side of the input end connected with the source line, the input end connected with the source line is selected as the target input end, and if there is a memory cell of which data is re-written in the non-selected memory string, the memory cells storing data between the input end connected with the source line and the target memory cell are the unerased memory cells in the non-selected memory string and the memory cell of which data is re-written, that is, the programmed memory cells are the unerased memory cells in the non-selected memory string and the memory cell of which data is re-written. If there is no memory cell of which data is re-written in the non-selected memory string, the memory cells storing data between the input end connected with the source line and the target memory cell are the unerased memory cells in the non-selected memory string, that is, the programmed memory cells are the unerased memory cells in the non-selected memory string.

[0190] Exemplarily, one combination of the programming direction and the existence state of the unerased memory cells in the non-selected memory string is that the programming direction is from the input end connected with the bit line to the input end connected with the source line, and the unerased memory cells in the non-selected memory string do not exist (that is, the erasing mode corresponding to the memory block is full erasing). In this case, if there is data of which is re-written in the non-selected memory string and the input end connected with the bit line is selected as the target input end, the programmed memory cells are the memory cells of which data is re-written in the non-selected memory string.

[0191] Exemplarily, one combination of the programming direction and the existence state of the unerased memory cells in the non-selected memory string is that the programming direction is from the input end connected with the source line to the input end connected with the bit line, and the unerased memory cells in the non-selected memory string do not exist (that is, the erasing mode corresponding to the memory block is full erasing). In this case, if there is data of which is re-written in the non-selected memory string and the input end connected with the source line is selected as the target input end, the programmed memory cells are the memory cells of which data is re-written in the non-selected memory string.

[0192] It should be noted that the above combination of the programming direction and the existence state of the unerased memory cells in the non-selected memory string is only exemplarily, and the embodiments of the present application are not limited thereto. In other combinations of the programming direction and the existence state of the unerased memory cells in the non-selected memory string, the programmed memory cells in the non-selected memory string can also be other cases.

[0193] In a possible implementation, the implementation of turning on the channel of the memory cell between the target input terminal and the target memory cell in the unselected memory string can be: a first voltage is applied to the gate of the memory cell between the target input terminal and the target memory cell, and the first voltage is greater than the threshold voltage of the programmed memory cell.

[0194] Since the threshold voltage of the unprogrammed memory cell is less than the threshold voltage of the programmed memory cell, no matter whether the memory cell between the target input terminal and the target memory cell includes the unprogrammed memory cell, the channel of the memory cell between the target input terminal and the target memory cell can be turned on by applying the first voltage to the gate of the memory cell between the target input terminal and the target memory cell. The operation of applying the first voltage to the gate of the memory cell between the target input terminal and the target memory cell is relatively convenient.

[0195] Exemplarily, the number of the programmed memory cells is a plurality, the threshold voltages of different programmed memory cells can be different, and the first voltage is a voltage greater than the threshold voltage of each programmed memory cell. Exemplarily, the threshold voltage of the programmed memory cell ranges from 0 to 5 V, and correspondingly, the first voltage ranges from 5 to 7 V.

[0196] The application does not limit the size relationship between the pre-charge voltage and the first voltage. In an exemplary embodiment, the pre-charge voltage is greater than the first voltage. Of course, the pre-charge voltage can also be less than the first voltage.

[0197] In an exemplary embodiment, different memory cells are connected to different word lines, and the manner of applying the first voltage to the gate of the memory cell between the target input terminal and the target memory cell is: the first voltage is applied to the word line connected to the memory cell between the target input terminal and the target memory cell, so as to apply the first voltage to the gate of the memory cell between the target input terminal and the target memory cell. It should be noted that the word line includes the gates of a plurality of memory cells in the same layer and the gate line for coupling the gates, and can also be understood as that the gate line is coupled with the gates of a plurality of memory cells to form a word line, and based on this, the voltage can be applied to the gates of a plurality of memory cells in the same layer by applying the voltage to the word line.

[0198] In an exemplary embodiment, the memory cell between the target input terminal and the target memory cell also includes an unprogrammed memory cell, and in this case, the implementation of turning on the channel of the memory cell between the target input terminal and the target memory cell in the unselected memory string can also be: a first voltage is applied to the gate of the programmed memory cell; and a second voltage is applied to the gate of the unprogrammed memory cell. The first voltage is greater than the threshold voltage of the programmed memory cell, and the second voltage is greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

[0199] The second voltage can make the channel of the unprogrammed memory cell conductive and is less than the first voltage. By applying the first voltage and the second voltage to the gate of the programmed memory cell and the gate of the unprogrammed memory cell respectively, power resource can be saved on the basis of ensuring that the channels of the programmed memory cell and the unprogrammed memory cell are both conductive.

[0200] Exemplarily, the threshold voltage of the unprogrammed memory cell is negative, and the second voltage can be 0 V. Exemplarily, the second voltage is a default voltage that is continuously applied to the gate of the memory cell, that is, the second voltage is continuously applied to the gate of the unprogrammed memory cell.

[0201] Exemplarily, the implementation manner of applying the first voltage to the gate of the programmed memory cell is that the first voltage is applied to the word line to which the programmed memory cell is connected, so as to apply the first voltage to the gate of the programmed memory cell. The implementation manner of applying the second voltage to the gate of the unprogrammed memory cell is that the second voltage is applied to the word line to which the unprogrammed memory cell is connected, so as to apply the second voltage to the gate of the unprogrammed memory cell.

[0202] In the exemplary embodiment, the memory cell between the target input terminal and the target memory cell includes the target memory cell itself. Since the target memory cell is an unprogrammed memory cell, the second voltage is also applied to the gate of the target memory cell. Of course, in the exemplary embodiment, the memory cell between the target input terminal and the target memory cell can also not include the target memory cell itself. In this case, in addition to applying the first voltage and the second voltage to the gate of the programmed memory cell and the gate of the unprogrammed memory cell respectively, the second voltage can also be applied to the gate of the target memory cell, so as to make the channel of the target memory cell conductive, thereby making more electrons in the channel of the target memory cell be attracted to the target input terminal, and further improving the potential of the channel of the target memory cell.

[0203] In the exemplary embodiment, the first voltage and the second voltage are applied to the gate of the programmed memory cell and the gate of the unprogrammed memory cell respectively, and the second voltage is a default voltage that is continuously applied. Since part of the electrons in the channel of the target memory cell will gather near the programmed memory cell after the first voltage is applied to the gate of the programmed memory cell, the order of the cutoff time of applying the pre-charge voltage and the first voltage is limited, so as to further improve the potential of the channel of the target memory cell. In the exemplary embodiment, the order of the cutoff time of applying the pre-charge voltage and the first voltage is that the cutoff time of applying the first voltage to the gate of the programmed memory cell is earlier than the cutoff time of applying the pre-charge voltage to the target input terminal. Exemplarily, when the cutoff time of the voltage is reached, the voltage drops to a default voltage, and exemplarily, the default voltage is 0 V.

[0204] The turn-off time of the first voltage applied to the gate of the programmed memory cell is earlier than the turn-off time of the pre-charge voltage applied to the target input terminal, so that the process of applying the first voltage to the gate of the programmed memory cell is turned off earlier than the process of applying the pre-charge voltage to the target input terminal, and the phenomenon that the voltage of the target input terminal is 0V but the voltage of the gate of the programmed memory cell is not 0V is avoided, thereby avoiding the phenomenon that the electrons adsorbed by the programmed memory cell are blocked from moving to the target input terminal. That is, when the voltage applied to the gate of the programmed memory cell drops to 0V, that is, when the channel of the programmed memory cell is not conductive or has poor conductivity, the electrons located at the channel of the programmed memory cell can still continue to migrate and diffuse to the target input terminal under the electric field force of the pre-charge voltage, thereby further improving the electric potential of the channel of the target memory cell.

[0205] In the example embodiment, in addition to applying the pre-charge voltage to the target input terminal and applying the first voltage to the gate of the programmed memory cell, a turn-on voltage is also applied to the gate of the selection transistor on the target input terminal side. In this case, the turn-off time of the turn-on voltage applied to the gate of the selection transistor on the target input terminal side is earlier than the turn-off time of the pre-charge voltage applied to the target input terminal and later than the turn-off time of the first voltage applied to the gate of the programmed memory cell, so as to ensure sufficient pre-charge.

[0206] In the example embodiment, when the number of programmed memory cells is multiple, the turn-off time of the first voltage applied to the gate of the programmed memory cell far from the target input terminal is not later than the turn-off time of the first voltage applied to the gate of the programmed memory cell close to the target input terminal. That is, the turn-off time of the first voltage applied to the gate of each programmed memory cell is the same. Alternatively, the farther the distance between the gate of the programmed memory cell and the target input terminal, the earlier the turn-off time of the first voltage applied to the gate of the programmed memory cell.

[0207] The present embodiment does not limit the relationship among the start time of applying the pre-charge voltage to the target input terminal, the start time of applying the turn-on voltage to the gate of the selection transistor on the target input terminal side, and the start time of applying the first voltage to the gate of the programmed memory cell. For example, the start time of applying the pre-charge voltage to the target input terminal, the start time of applying the turn-on voltage to the gate of the selection transistor on the target input terminal side, and the start time of applying the first voltage to the gate of the programmed memory cell are the same, that is, the pre-charge voltage is applied to the target input terminal, the turn-on voltage is applied to the gate of the selection transistor on the target input terminal side, and the first voltage is applied to the gate of the programmed memory cell at the same time.

[0208] In the non-selected memory string, in addition to the memory cell located between the target input terminal and the target memory cell, the memory cell not located between the target input terminal and the target memory cell is also included. In the exemplary embodiment, in addition to turning on the channel of the memory cell located between the target input terminal and the target memory cell, the channel of the memory cell not located between the target input terminal and the target memory cell in the non-selected memory string is also turned on, so that the channel of all the memory cells in the non-selected memory string is turned on. The principle of turning on the channel of the memory cell not located between the target input terminal and the target memory cell is the same as that of turning on the channel of the memory cell located between the target input terminal and the target memory cell, and will not be described here.

[0209] Of course, in the exemplary embodiment, since the memory cell not located between the target input terminal and the target memory cell storing data will not block the movement of the electrons in the channel of the target memory cell towards the target input terminal, only the default voltage (e.g. 0V) needs to be applied to the gate of the memory cell not located between the target input terminal and the target memory cell, and it is not necessary to pay attention to whether the channel of the memory cell not located between the target input terminal and the target memory cell is turned on.

[0210] In the exemplary embodiment, in the pre-charge phase between the programming phases, in addition to pre-charging the non-selected memory string, the selected memory string can also be pre-charged for the convenience of operation. The implementation process of pre-charging the selected memory string is the same as that of pre-charging the non-selected memory string, and will not be described here.

[0211] In the exemplary embodiment, in the process of pre-charging each memory string in the memory block that needs to be pre-charged, since the memory cells in each memory string that needs to be pre-charged share a group of word lines, if the positions of the programmed memory cells in each memory string that needs to be pre-charged are the same, the positions of the unprogrammed memory cells in each memory string that needs to be pre-charged are also the same. In this case, the first voltage can be applied to the word line connected to the programmed memory cells in a certain memory string that needs to be pre-charged, and the first voltage can also be applied to the gates of the programmed memory cells in each memory string, and the second voltage can be applied to the word line connected to the unprogrammed memory cells in a certain memory string that needs to be pre-charged, and the second voltage can also be applied to the gates of the unprogrammed memory cells in each memory string.

[0212] In the example embodiment, the positions of the programmed memory cells in each memory string requiring pre-charge can be different, in which case, the pre-charge can be performed on each memory string requiring pre-charge according to the manners of steps 601 and 602. Alternatively, the union of the word lines connected to the programmed memory cells in each memory string requiring pre-charge can be taken as the first word line, and the intersection of the word lines connected to the unprogrammed memory cells in each memory string requiring pre-charge can be taken as the second word line. By applying the first voltage to the first word line and the second voltage to the second word line, the channels of the memory cells between the target input and the target memory cell in each memory string requiring pre-charge are ensured to be turned on. Then, by applying the pre-charge voltage to the target input of each memory string requiring pre-charge, the pre-charge of each memory string requiring pre-charge can be realized.

[0213] After the pre-charge of each memory string requiring pre-charge in the memory block is completed, the pre-charge phase before the programming phase is completed. After the pre-charge phase before the programming phase is completed, the programming phase is entered to program the selected memory cells in the selected memory string.

[0214] In the example embodiment, the programming of the selected memory cells in the selected memory string is performed by applying the programming voltage to the gate of the selected memory cells in the selected memory string, applying the turn-on voltage to the gates of the memory cells other than the selected memory cells in the selected memory string, and applying the power supply voltage to the gate of the TSG.

[0215] The programming voltage is relatively high, for example, 22V, so that a sufficiently high positive voltage difference between the gate and the channel of the selected memory cell can be obtained, and thus the electrons in the channel of the selected memory cell can enter the floating gate or the charge trapping layer of the selected memory cell through the tunneling effect, so as to realize the writing of data, i.e., the selected memory cell is changed from not storing data to storing data. By adjusting the size of the programming voltage, the number of electrons stored in the floating gate or the charge trapping layer can be adjusted, and thus the threshold voltage of the selected memory cell can be adjusted. The minimum voltage that makes the electrons in the channel tunnel to the floating gate or the charge trapping layer of the selected memory cell is referred to as the tunneling voltage. It can be understood that the tunneling voltage is a voltage greater than the threshold voltage.

[0216] By applying the turn-on voltage to the gates of the memory cells other than the selected memory cells in the selected memory string, the channels of the memory cells other than the selected memory cells in the selected memory string can be turned on. The turn-on voltage is lower than the programming voltage, so that the voltage difference between the gate and the channel of the memory cells other than the selected memory cells in the selected memory string is relatively small, and thus the tunneling of the electrons in the channel to the floating gate or the charge trapping layer can be avoided, so as to realize the programming inhibition of the memory cells other than the selected memory cells in the selected memory string. The power supply voltage is used to turn on the TSG of the selected memory string.

[0217] In the example embodiment, in the process of programming the selected memory string, the channels of the TSG and the BSG of the non-selected memory string are all turned off to make the channel of the non-selected memory string float, and in the case of more sufficient pre-charging of the non-selected memory string, the floating of the channel of the non-selected memory string can make the voltage difference between the gate and the channel of the target memory cell in the non-selected memory string connected to the selected word line be relatively small when the programming voltage is applied to the selected word line connected to the selected memory cell, thereby avoiding the electrons in the channel from tunneling to the floating gate or the charge trapping layer to a large extent, and realizing the programming inhibition of the target memory cell in the non-selected memory string connected to the selected word line.

[0218] In the example embodiment, the principle of programming the selected memory cell in each selected memory string in the memory block is the same, and for example, the selected memory cell in each selected memory string is connected to the same word line, and the other memory cells at each position in each selected memory string are connected to the same word line, and therefore, in the process of programming the selected memory cell in each selected memory string, the programming voltage is applied to the gate of the selected memory cell in each selected memory string by applying the programming voltage to the word line connected to the selected memory cell in a certain selected memory string, and the turn-on voltage is applied to the gate of the other memory cell in each selected memory string by applying the turn-on voltage to the word line connected to the other memory cell in a certain selected memory string.

[0219] Based on the method provided in the embodiments of the present application, in the case that the memory cell between the target input terminal and the target memory cell in the non-selected memory string includes a programmed memory cell, more sufficient pre-charging of the non-selected memory string can be realized in the case of full erasing or partial erasing, so as to increase the potential of the channel of the target memory cell and reduce the programming interference received by the target memory cell.

[0220] The pre-charging method provided in the embodiments of the present application turns on the channel of the memory cell between the target input terminal and the target memory cell after the pre-charging voltage is applied to the target input terminal, which can avoid the phenomenon that the non-conducting channel blocks the movement of the electrons in the channel of the target memory cell to the target input terminal, so that the electrons in the channel of the target memory cell can be more fully attracted to the target input terminal, thereby realizing more sufficient pre-charging of the non-selected memory string, and further greatly reducing the programming interference received by the target memory cell.

[0221] Next, taking each memory string in the memory block as a memory string that needs to be pre-charged and the positions of the programmed memory cells in each memory string being the same as an example, the voltage application in the pre-charging phase and the programming phase is described.

[0222] Exemplarily, in the case that the erase mode corresponding to the storage block is the first stack erase, and the programming direction is the reverse programming direction, the storage string is as shown in FIG. 8A. As shown in FIG. 8A, the upper selection transistor of the storage string is located at the input end side connected with the bit line, and the lower selection transistor is located at the input end side connected with the source line. The storage units connected in sequence between the upper selection transistor and the lower selection transistor are the storage unit connected with the first stack programming state word line (Upper deck PGMed WLs) for re-writing data, the storage unit connected with the target word line (Target WL) for not writing data, the storage unit connected with the first stack non-programming state word line (Upper deck Un-PGMed WLs) for not writing data, and the storage unit connected with the second stack programming state word line (Lower deck PGMed WLs) for not being erased. Figure 7

[0223] In the case that the storage string is as shown in FIG. 8A, the default target input end in the pre-charge mode in some embodiments is the input end connected with the source line. The voltage application in the process of programming the selected storage unit based on the pre-charge mode in some embodiments is as shown in (a) of FIG. 8B. In (a) of FIG. 8B, in the pre-charge phase, the pre-charge voltage Vpre is applied on the source line connected with the selected storage string and the non-selected storage string, and the turn-on voltage Vbsg is applied on the gate of the lower selection transistor of the selected storage string and the non-selected storage string. The 0V voltage is applied on the bit line connected with the selected storage string and the non-selected storage string, and the 0V voltage (i.e., the second voltage) is applied on each word line. The 0V voltage is applied on the gate of the selected upper selection transistor in the selected storage string and the non-selected upper selection transistor of the non-selected storage string. The start time of applying Vpre and the start time of applying Vbsg are the same, the end time of applying Vbsg is earlier than the end time of applying Vpre, and the 0V voltage is the default voltage continuously applied. Figure 7 Figure 8 Figure 8

[0224] Figure 8 ​​​​​In (a) in the figure, in the programming stage, a power supply voltage Vcc is applied to the gate of the selected upper select transistor in the selected memory string, a turn-on voltage Vpass is applied to the first stack programming state word line, the first stack non-programming state word line and the second stack programming state word line, a programming voltage Vpgm is applied to the target word line, 0V voltage is applied to the gate of the non-selected upper select transistor of the non-selected memory string, 0V voltage is applied to the gate of the lower select transistor of the selected memory string and the non-selected memory string, 0V voltage is applied to the source line connected to the selected memory string and the non-selected memory string, and 0V voltage is applied to the bit line connected to the selected memory string and the non-selected memory string. Wherein, the start time of applying Vcc, the start time of applying Vpass and the start time of applying Vpgm are the same, the end time of applying Vcc, the end time of applying Vpass and the end time of applying Vpgm are the same, and the 0V voltage is a default voltage continuously applied.

[0225] In the case of the memory string as shown in the figure, based on the pre-charge method provided by the embodiment of the present application, either the input end connected to the source line can be taken as the target input end, or the input end connected to the bit line can be taken as the target input end. Figure 7

[0226] In the case of taking the input end connected to the source line as the target input end, the programmed memory cell is the second stack memory cell connected to the second stack programming state word line, and in this case, the voltage application in the process of programming the selected memory cell is as shown in (b) in the figure. Figure 8 Compared with the voltage application as shown in (a) in the figure, the voltage application in the programming stage is the same as (a) in the figure. Figure 8 The difference between the voltage application in the pre-charge stage and (a) in the figure is that the voltage applied to the second stack programming state word line is not the second voltage of 0V, but the first voltage Vpass which is higher, so that the second stack memory cell in each memory string connected to the second stack programming state word line is turned on. Figure 8 Figure 8 In the pre-charge stage in (b) in the figure, the start time of applying Vpre, the start time of applying Vbsg and the start time of applying Vpass are the same, the end time of applying Vbsg is earlier than the end time of applying Vpre and later than the end time of applying Vpass, and the 0V voltage is a default voltage continuously applied.

[0227] In the case of taking the input end connected to the bit line as the target input end, the programmed memory cell needs to be the memory cell of the re-written data connected to the first stack programming state word line, and in this case, the voltage application in the process of programming the selected memory cell is as shown in (b) in the figure. Figure 8

[0228] In the case of taking the input end connected to the bit line as the target input end, the programmed memory cell needs to be the memory cell of the re-written data connected to the first stack programming state word line, and in this case, the voltage application in the process of programming the selected memory cell is as shown in (b) in the figure.​​​Figure 8 In the pre-charge phase of (c) in FIG. 6, a pre-charge voltage Vpre is applied to the bit lines connected to the selected memory strings and the unselected memory strings, a turn-on voltage Vtsg is applied to the gates of the selected upper select transistors of the selected memory strings and the unselected upper select transistors of the unselected memory strings, a higher first voltage Vpass is applied to the first stack program state word line, so that the memory cells in each memory string connected to the first stack program state word line are all turned on. A 0V voltage is applied to the source lines connected to the selected memory strings and the unselected memory strings, 0V voltages (i.e., a second voltage) are applied to the word lines other than the first stack program state word line, and 0V voltages are applied to the gates of the lower select transistors of the selected memory strings and the unselected memory strings. The voltage application in the programming phase is consistent with (a) in FIG. 6. Figure 8

[0229] In the pre-charge phase of (c) in FIG. 6, the start time of applying Vpre, the start time of applying Vtsg, and the start time of applying Vpass are the same, the end time of applying Vtsg is earlier than the end time of applying Vpre and later than the end time of applying Vpass, and the 0V voltage is a default voltage that is continuously applied. Figure 8

[0230] Exemplarily, in the case where the erase mode corresponding to the memory block is the second stack erase, and the programming direction of the memory cells in the memory string is the forward programming direction, the memory string is as shown in (c) in FIG. 7. The upper select transistor of the memory string is located at the input end side connected to the bit line, the lower select transistor is located at the input end side connected to the source line, and the unerased memory cells connected to the first stack program state word line, the unprogrammed memory cells connected to the second stack non-program state word line, the memory cells connected to the target word line, and the reprogrammed memory cells connected to the second stack program state word line are sequentially connected in series between the upper select transistor and the lower select transistor. Figure 9 In the case where the memory string is as shown in (c) in FIG. 7, the input end connected to the bit line is taken as the target input end by default in the pre-charge mode in some embodiments. The voltage application in the process of programming the selected memory cells based on the pre-charge mode in some embodiments is as shown in (a) in FIG. 8. In the pre-charge phase of (a) in FIG. 8, a pre-charge voltage Vpre is applied to the bit line connected to the target input end, a turn-on voltage Vtsg is applied to the gate of the upper select transistor of the selected memory string, a higher first voltage Vpass is applied to the first stack program state word line, so that the memory cells in each memory string connected to the first stack program state word line are all turned on. A 0V voltage is applied to the source line connected to the selected memory string, 0V voltages are applied to the word lines other than the first stack program state word line, and 0V voltages are applied to the gates of the lower select transistors of the selected memory string and the unselected memory string. The voltage application in the programming phase is consistent with (a) in FIG. 6.

[0231] Figure 9 Figure 10 Figure 10 ​​​​​In (a) of the diagram, during the precharge phase, a precharge voltage Vpre is applied to the bit lines connecting the selected and non-selected memory strings. A turn-on voltage Vtsg is applied to the gates of the selected up-select transistor in the selected memory string and the non-selected up-select transistor in the non-selected memory string. A 0V voltage is applied to the source lines connecting the selected and non-selected memory strings, a 0V voltage (i.e., the second voltage) is applied to each word line, and a 0V voltage is applied to the gates of the down-select transistors in the selected and non-selected memory strings. The start time of applying Vpre is the same as the start time of applying Vtsg, the end time of applying Vtsg is earlier than the end time of applying Vpre, and the 0V voltage is the default voltage applied continuously.

[0232] exist Figure 10 In (a) of the above, during the programming phase, a supply voltage Vcc is applied to the gate of the selected up-select transistor in the selected memory string; a turn-on voltage Vpass is applied to the first stack programming word line, the second stack non-programming word line, and the second stack programming word line; a programming voltage Vpgm is applied to the target word line; a 0V voltage is applied to the gate of the non-selected up-select transistor in the non-selected memory string; a 0V voltage is applied to the gate of the down-select transistor in both the selected and non-selected memory strings; a 0V voltage is applied to the source line connecting the selected and non-selected memory strings; and a 0V voltage is applied to the bit line connecting the selected and non-selected memory strings. The start times for applying Vcc, Vpass, and Vpgm are the same, as are the end times for applying Vcc, Vpass, and Vpgm. The 0V voltage is the default voltage applied continuously.

[0233] In storage string such Figure 9 As shown, based on the pre-charging method provided in the embodiments of this application, either the input terminal connected to the source line or the input terminal connected to the bit line can be used as the target input terminal.

[0234] When the input terminal connected to the bit line is selected as the target input terminal, the programmed memory cell is the first stack memory cell connected to the first stack programming state word line. In this case, the voltage applied during the programming process of the selected memory cell is as follows: Figure 10 As shown in (b) above, with Figure 10 Compared to the voltage application scenario shown in (a), the voltage application scenario during the programming phase is different. Figure 10 Consistent with (a) in [the previous section]. The voltage applied during the pre-charge phase is the same as [the previous section]. Figure 10The difference in (a) is that the voltage applied to the first stack programming word line is not a second voltage of 0V, but a higher first voltage Vpass, so that the first stack memory cells in each memory string connected to the first stack programming word line are all turned on.

[0235] exist Figure 10 In the pre-charge phase of (b), the start time of applying Vpre, the start time of applying Vtsg, and the start time of applying Vpass are the same. The end time of applying Vtsg is earlier than the end time of applying Vpre and later than the end time of applying Vpass. The 0V voltage is the default voltage that is continuously applied.

[0236] When the input terminal connected to the source line is used as the target input terminal, the programmed memory cell is the memory cell for rewriting data connected to the second stack programming word line. In this case, the voltage applied during the programming process of the selected memory cell is as follows: Figure 10 As shown in (c), during the pre-charge phase, a pre-charge voltage Vpre is applied to the source lines connecting the selected and non-selected memory strings, an on-state voltage Vbsg is applied to the gates of the down-select transistors of the selected and non-selected memory strings, and a higher first voltage Vpass is applied to the second stack programming word lines to turn on all memory cells in each memory string connected to the second stack programming word lines. A 0V voltage is applied to the bit lines connecting the selected and non-selected memory strings, and a 0V voltage (i.e., the second voltage) is applied to all word lines except the second stack programming word lines. A 0V voltage is applied to the gates of the selected up-select transistors of the selected memory strings and the non-selected up-select transistors of the non-selected memory strings. The voltage application during the programming phase is similar to... Figure 10 (a) is consistent with this.

[0237] exist Figure 10 In the pre-charge phase of (c), the start time of applying Vpre, the start time of applying Vbsg, and the start time of applying Vpass are the same. The end time of applying Vbsg is earlier than the end time of applying Vpre and later than the end time of applying Vpass. The 0V voltage is the default voltage that is continuously applied.

[0238] In an exemplary embodiment, the pre-charging method provided in this application is also applicable to applications having, for example, Figure 11 The unselected memory strings of the structure shown are precharged.

[0239] like Figure 11As shown, the non-selected memory string 500 includes a select transistor stack 530 and a memory cell stack 520 between its input terminals connected to the bit lines and its input terminals connected to the source lines. The memory cell stack 520 and the select transistor stack 530 are connected through a doped region 540. The memory cell stack 520 and the select transistor stack 530 are stacked above the substrate 510, with the select transistor stack 530 located on the side of the memory cell stack 520 away from the substrate. Exemplarily, the memory cell stack 520 is composed of memory cells from the non-selected memory string 500 and a BSG (Bit Cell Generation Group), meaning that all memory cells from the non-selected memory string 500 are located within the memory cell stack 520. The select transistor stack 530 is composed of TSGs (Total Selective Generation Groups) from the non-selected memory string 500.

[0240] The substrate 510 can be made of silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0241] The memory cell stack 520 may include alternating conductive layers 521 and dielectric layers 522. The conductive layers 521 are made of conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. The conductive layers 521 may extend laterally to form SSLs or word lines.

[0242] like Figure 11 As shown, the memory cell stack 520 includes a channel structure extending vertically through a conductive layer 521 and a dielectric layer 522. The channel structure of the memory cell stack 520 includes a channel 523, a tunneling layer 524, a storage layer 525, and a barrier layer 526. The tunneling layer 524, storage layer 525, and barrier layer 526 may be referred to as functional layers. In some embodiments, the channel 523 may be made of silicon, for example, polycrystalline silicon. The tunneling layer 524 may be made of silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 525 may be made of silicon nitride, silicon oxynitride, or any combination thereof; exemplaryly, the storage layer 525 may be a floating gate or a charge trapping layer. The barrier layer 526 may be made of silicon oxide, silicon oxynitride, a high-dielectric-constant dielectric, or any combination thereof. In some embodiments, the channel structure of the storage cell stack 520 may have a column shape (e.g., cylinder, prism, frustum, etc.), with the channel 523, tunneling layer 524, storage layer 525 and barrier layer 526 arranged radially from the center of the column toward the outer surface of the column in this order.

[0243] The selector stack 530 may include alternating conductive layers 531 and dielectric layers 532. The conductive layer 531 is made of a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. The conductive layer 531 may extend laterally to form a DSL.

[0244] like Figure 11 As shown, the selector stack 530 includes a channel structure extending vertically through the conductive layer 531 and the dielectric layer 532. The channel structure of the selector stack 530 includes a channel 533 and an insulating layer 534. In some embodiments, the channel 533 may be made of silicon, for example, polycrystalline silicon. The insulating layer 534 may be made of silicon oxide. In some embodiments, the channel structure of the selector stack 530 may have a columnar shape (e.g., a cylinder, prism, frustum, etc.), with the channel 533 and the insulating layer 534 arranged radially from the center of the column toward the outer surface of the column in this order.

[0245] like Figure 11 As shown, the channel structure size of the selector stack 530 is smaller than that of the memory cell stack 520. This structure can reduce the space occupied by the channel structure of the selector stack 530, thereby providing a larger process window for forming the top select gate cutout structure, which is beneficial to improving the unit storage density of the memory.

[0246] The transistor stack 530 and the memory cell stack 520 are connected via a doped region 540, which is formed by doping a semiconductor material with impurities. For example, the material of the doped region 540 is a heavily N-type doped material to enhance its conductivity. Heavy doping refers to the situation where the concentration of impurities incorporated into the semiconductor material exceeds a concentration threshold. This concentration threshold is set empirically or can be flexibly adjusted according to the application scenario; for example, a concentration threshold of 10-1 per cubic centimeter. 18 Each atom. Doped region 540 is used to ensure a tight connection between the selector stack 530 and the memory cell stack 520.

[0247] It should be understood that, despite Figure 11 Not shown, but the non-selected memory string 500 may also include other additional components, including but not limited to gate line gaps, source contacts, local contacts, interconnect layers, etc.

[0248] For the structure of non-selected memory strings, such as Figure 11In the case shown, there are a large number of electrons in the doped region in the unselected memory string, which can reduce the channel potential of the memory cells in the memory cell stack of the unselected memory string during programming, thereby enhancing the programming interference suffered by the memory cells in the memory cell stack. Exemplarily, the electrons in the doped region have a greater adverse effect on the memory cells in the memory cell stack that are closer to the doped region.

[0249] Therefore, in the process of pre-charging the unselected memory string, in addition to the need to reduce the electrons in the channel of the target memory cell, the electrons in the doped region also need to be reduced. Among them, reducing the electrons in the channel of the target memory cell can increase the channel potential coupled out by the target memory cell during programming, and reducing the electrons in the doped region can reduce the degree of reduction of the channel potential of the target memory cell by the electrons in the doped region. By reducing the electrons in the channel of the target memory cell and reducing the electrons in the doped region, the target memory cell can have a higher channel potential during programming, and the target memory cell can have a smaller pressure difference between the gate and the channel, thereby reducing the programming interference suffered by the target memory cell.

[0250] In the process of pre-charging the unselected memory string having a structure as shown in Figure 11 The input end connected with the bit line is taken as a target input end. That is, the unselected memory string having a structure as shown in Figure 11 The pre-charging manner of the unselected memory string having a structure as shown in

[0251] Since the doped region is located between the input end connected with the bit line and the target memory cell, and the doped region and the input end connected with the bit line are a selection tube stack without memory cells, the memory cells located between the input end connected with the bit line and the target memory cell include the memory cells between the doped region and the target memory cell.

[0252] The storage unit between the input end connected with the bit line and the target storage unit includes the programmed storage unit, that is, the doped region and the target storage unit. Exemplarily, the case that the storage unit between the doped region and the target storage unit includes the programmed storage unit includes but is not limited to: the storage block corresponds to the full erase mode, the programming direction is the reverse programming direction, and there is the storage unit of which the data is rewritten between the doped region and the target storage unit; or, the storage block corresponds to the partial erase mode, the programming direction is the forward programming direction, and there is the storage unit which is not erased between the doped region and the target storage unit; or, the storage block corresponds to the partial erase mode, the programming direction is the reverse programming direction, and there is the storage unit which is not erased or the storage unit of which the data is rewritten between the doped region and the target storage unit.

[0253] The non-selected storage string having the structure as shown in FIG. 1 is pre-charged based on the method provided in the embodiments of the present application, the channel of the storage unit between the doped region and the target storage unit is turned on, the electrons in the doped region and the electrons in the channel of the target storage unit can be fully attracted to the input end connected with the bit line, so that the non-selected storage string is fully pre-charged, and the programming interference on the target storage unit is greatly reduced. Figure 12

[0254] Referring to FIG. 1, Figure 13 The pre-charging device is used for pre-charging the non-selected storage string before writing data to the selected storage unit, and the device includes:

[0255] The voltage application module 1201 is configured to apply a pre-charging voltage to a target input end of the non-selected storage string, the target input end being an input end of the non-selected storage string connected with the bit line or an input end connected with the source line;

[0256] The turning-on module 1202 is configured to turn on the channel of the storage unit between the target input end and the target storage unit in the non-selected storage string, the storage unit between the target input end and the target storage unit including the programmed storage unit, and the target storage unit being the storage unit connected with the selected word line in the non-selected storage string.

[0257] In a possible implementation, the turning-on module 1202 is configured to apply a first voltage to the gate of the storage unit between the target input end and the target storage unit, the first voltage being greater than the threshold voltage of the programmed storage unit.

[0258] ​In a possible implementation, the storage unit between the target input end and the target storage unit further includes an unprogrammed storage unit; the conducting module 1202 is configured to apply a first voltage to the gate of the programmed storage unit, the first voltage being greater than the threshold voltage of the programmed storage unit; and apply a second voltage to the gate of the unprogrammed storage unit, the second voltage being greater than the threshold voltage of the unprogrammed storage unit and less than the first voltage.

[0259] In a possible implementation, the programming direction is a direction close to the target input end, and the programmed storage units are all unerased storage units.

[0260] In a possible implementation, the programming direction is a direction away from the target input end, and the programmed storage units are all re-written data storage units, or the programmed storage units are all unerased storage units, or the programmed storage units are re-written data storage units and unerased storage units.

[0261] In a possible implementation, the conducting module 1202 is further configured to conduct the channel of the storage unit, which is not between the target input end and the target storage unit, in the non-selected storage string.

[0262] In a possible implementation, the turn-off time of applying the first voltage to the gate of the programmed storage unit is earlier than the turn-off time of applying the pre-charge voltage to the target input end.

[0263] In a possible implementation, the number of the programmed storage units is a plurality, and the turn-off time of applying the first voltage to the gate of the programmed storage unit far from the target input end is not later than the turn-off time of applying the first voltage to the gate of the programmed storage unit close to the target input end.

[0264] In a possible implementation, the input end connected with the bit line and the input end connected with the source line include a selection tube stack and a storage unit stack connected through a doped region, the target input end is the input end connected with the bit line, and the storage unit between the target input end and the target storage unit includes the storage unit between the doped region and the target storage unit.

[0265] The pre-charge device provided by the embodiment of the present application conducts the channel of the storage unit between the target input end and the target storage unit after applying the pre-charge voltage to the target input end, can avoid the phenomenon that the channel not being conducted blocks the movement of the electrons in the channel of the target storage unit to the target input end, so that the electrons in the channel of the target storage unit can be more fully attracted to the target input end, thereby realizing more sufficient pre-charge of the non-selected storage string, and further greatly reducing the programming interference on the target storage unit.

[0266] It should be noted that the apparatus provided by the above embodiments is only exemplified by the above division of functional modules when realizing its functions, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above-described functions. In addition, the apparatus and method embodiments provided by the above embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0267] In an example embodiment, a control circuit is also provided, the control circuit comprising programmable logic circuitry and / or program instructions, the control circuit being configured to pre-charge unselected memory strings according to the following steps before writing data to a selected memory cell:

[0268] applying a pre-charge voltage to a target input terminal of the unselected memory string, the target input terminal being an input terminal of the unselected memory string connected to a bit line or an input terminal connected to a source line;

[0269] conducting channels of memory cells in the unselected memory string between the target input terminal and a target memory cell, the memory cells between the target input terminal and the target memory cell including programmed memory cells, the target memory cell being a memory cell of the unselected memory string connected to the selected word line.

[0270] In a possible implementation, the control circuit is configured to apply a first voltage to gates of the memory cells between the target input terminal and the target memory cell, the first voltage being greater than a threshold voltage of the programmed memory cells.

[0271] In a possible implementation, the memory cells between the target input terminal and the target memory cell further include unprogrammed memory cells; the control circuit is configured to apply a first voltage to gates of the programmed memory cells, the first voltage being greater than a threshold voltage of the programmed memory cells; and apply a second voltage to gates of the unprogrammed memory cells, the second voltage being greater than a threshold voltage of the unprogrammed memory cells and less than the first voltage.

[0272] In a possible implementation, the programming direction is a direction close to the target input terminal, and the programmed memory cells are all unerased memory cells.

[0273] In a possible implementation, the programming direction is a direction away from the target input terminal, and the programmed memory cells are all re-written memory cells, or the programmed memory cells are all unerased memory cells, or the programmed memory cells are re-written memory cells and unerased memory cells.

[0274] In a possible implementation, the control circuit is further configured to turn on a channel of a storage cell in the non-selected storage string that is not between the target input and the target storage cell.

[0275] In a possible implementation, the turn-off time of applying the first voltage to the gate of the programmed storage cell is earlier than the turn-off time of applying the pre-charge voltage to the target input.

[0276] In a possible implementation, the number of programmed storage cells is a plurality, and the turn-off time of applying the first voltage to the gate of the programmed storage cell that is far from the target input is not later than the turn-off time of applying the first voltage to the gate of the programmed storage cell that is close to the target input.

[0277] In a possible implementation, the input connected with the bit line and the input connected with the source line between the target input and the target storage cell include a selection tube stack and a storage cell stack connected through a doped region, the target input is the input connected with the bit line, and the storage cell between the target input and the target storage cell includes the storage cell between the doped region and the target storage cell.

[0278] In an example embodiment, a memory is also provided, comprising: a storage array and a control circuit communicatively connected with the storage array; the storage array comprises a non-selected storage string, and the control circuit is configured to pre-charge the non-selected storage string according to the following steps before writing data to a selected storage cell:

[0279] applying a pre-charge voltage to a target input of the non-selected storage string, the target input being an input connected with a bit line or an input connected with a source line of the non-selected storage string;

[0280] turning on a channel of a storage cell in the non-selected storage string that is between the target input and the target storage cell, the storage cell between the target input and the target storage cell including a programmed storage cell, and the target storage cell being a storage cell connected with a selected word line in the non-selected storage string.

[0281] In a possible implementation, the control circuit is configured to apply a first voltage to the gate of the storage cell between the target input and the target storage cell, the first voltage being greater than a threshold voltage of the programmed storage cell.

[0282] In a possible implementation, the storage cell between the target input and the target storage cell further includes an unprogrammed storage cell; the control circuit is configured to apply a first voltage to the gate of the programmed storage cell, the first voltage being greater than a threshold voltage of the programmed storage cell; and apply a second voltage to the gate of the unprogrammed storage cell, the second voltage being greater than a threshold voltage of the unprogrammed storage cell and less than the first voltage.

[0283] In a possible implementation, the programming direction is a direction close to the target input terminal, and the programmed storage cells are all unerased storage cells.

[0284] In a possible implementation, the programming direction is a direction away from the target input terminal, and the programmed storage cells are all re-written data storage cells, or all unerased storage cells, or both re-written data storage cells and unerased storage cells.

[0285] In a possible implementation, the control circuit is further configured to turn on the channel of the storage cell in the non-selected storage string that is not between the target input terminal and the target storage cell.

[0286] In a possible implementation, the turn-off time of the first voltage applied to the gate of the programmed storage cell is earlier than the turn-off time of the pre-charge voltage applied to the target input terminal.

[0287] In a possible implementation, the number of programmed storage cells is a plurality, and the turn-off time of the first voltage applied to the gate of the programmed storage cell far from the target input terminal is not later than the turn-off time of the first voltage applied to the gate of the programmed storage cell close to the target input terminal.

[0288] In a possible implementation, the input terminal connected with the bit line and the input terminal connected with the source line comprise a selection tube stack and a storage cell stack through a doped region, the target input terminal is the input terminal connected with the bit line, and the storage cell between the target input terminal and the target storage cell comprises the storage cell between the doped region and the target storage cell.

[0289] In an example embodiment, a storage system is also provided, which comprises a memory and a controller coupled to the memory, the controller being configured to control the memory. The memory comprises a storage array and a control circuit communicatively connected with the storage array; the storage array comprises a non-selected storage string, and the control circuit is configured to pre-charge the non-selected storage string before writing data to a selected storage cell according to the following steps:

[0290] applying a pre-charge voltage to a target input terminal of the non-selected storage string, the target input terminal being the input terminal connected with the bit line or the input terminal connected with the source line of the non-selected storage string;

[0291] turning on the channel of the storage cell in the non-selected storage string that is between the target input terminal and the target storage cell, the storage cell between the target input terminal and the target storage cell comprising a programmed storage cell, and the target storage cell being the storage cell connected with the selected word line in the non-selected storage string.

[0292] In a possible implementation, the control circuit is configured to apply a first voltage to the gate of the storage unit between the target input terminal and the target storage unit, the first voltage being greater than the threshold voltage of the programmed storage unit.

[0293] In a possible implementation, the storage unit between the target input terminal and the target storage unit further comprises an unprogrammed storage unit; the control circuit is configured to apply a first voltage to the gate of the programmed storage unit, the first voltage being greater than the threshold voltage of the programmed storage unit; and apply a second voltage to the gate of the unprogrammed storage unit, the second voltage being greater than the threshold voltage of the unprogrammed storage unit and less than the first voltage.

[0294] In a possible implementation, the programming direction is a direction close to the target input terminal, and the programmed storage units are all unerased storage units.

[0295] In a possible implementation, the programming direction is a direction away from the target input terminal, and the programmed storage units are all re-written data storage units, or the programmed storage units are all unerased storage units, or the programmed storage units are re-written data storage units and unerased storage units.

[0296] In a possible implementation, the control circuit is further configured to turn on the channel of the storage unit in the non-selected storage string and not between the target input terminal and the target storage unit.

[0297] In a possible implementation, the turn-off time of applying the first voltage to the gate of the programmed storage unit is earlier than the turn-off time of applying the pre-charge voltage to the target input terminal.

[0298] In a possible implementation, the number of programmed storage units is a plurality, and the turn-off time of applying the first voltage to the gate of the programmed storage unit far from the target input terminal is not later than the turn-off time of applying the first voltage to the gate of the programmed storage unit close to the target input terminal.

[0299] In a possible implementation, the input terminal connected with the bit line and the input terminal connected with the source line comprise a selection tube stack and a storage unit stack connected through a doped region, the target input terminal is the input terminal connected with the bit line, and the storage unit between the target input terminal and the target storage unit comprises the storage unit between the doped region and the target storage unit.

[0300] Exemplarily, a storage system is shown as Figure 2 The storage system 1300 comprises the memory 200 and the controller 300.

[0301] The memory 200 can operate in response to a control of the controller 300. The structure of the memory 200 can refer to FIG. 1, and thus a detailed description thereof will not be given here. Figure 3 or Figure 14 herein.

[0302] The memory 200 can receive a command, an address, and data from the controller 300. The memory 200 can perform an operation corresponding to the command on a region selected according to the address received from the controller 300. For example, the memory 200 can perform a write operation (a program operation), a read operation, and an erase operation. During the program operation, the memory 200 can program data into a region selected according to an address. During the read operation, the memory 200 can read data from a region selected according to an address. During the erase operation, the memory 200 can erase data stored in a region selected according to an address.

[0303] The controller 300 can control the operation of the memory 200. For example, the controller 300 can control the operation of the memory 200 in response to a request received from the host 400. Of course, the controller 300 can also control the operation of the memory 200 without receiving a request from the host 400.

[0304] Illustratively, the controller 300 can control the memory 200 to perform a program operation, a read operation, or an erase operation at the request from the host 400. During the program operation, the controller 300 can provide a program command, a physical address, and data to the memory 200. During the read operation, the controller 300 can provide a read command and a physical address to the memory 200. During the erase operation, the controller 300 can provide an erase command and a physical address to the memory 200.

[0305] In an exemplary embodiment, the controller 300 can generate a program command, an address, and data without a request from the host 400 and deliver the program command, the address, and the data to the memory 200. For example, the controller 300 can provide a command, an address, and data to the memory 200 to perform a background operation such as a program operation for wear leveling and a program operation for garbage collection.

[0306] The host 400 can be a processor (for example, a Central Processing Unit (CPU)) or a System on Chip (SoC) (for example, an Application Processor (AP)) of an electronic device. The host 400 can be communicatively connected with the memory system 1300.

[0307] Illustratively, as Figure 15As shown, the controller 300 includes a random access memory (RAM) 310, a processing unit 320, a host interface 330, a memory interface 340, and an error correction block 350.

[0308] The RAM 310 can be used as an operating memory for the processing unit 320, a cache memory between the memory 200 and the host 400, and / or a buffer memory between the memory 200 and the host 400.

[0309] The processing unit 320 can be configured to control read operations, program operations, erase operations, and background operations of the memory 200. The processing unit 320 can be configured to operate firmware to control the memory 200.

[0310] Exemplarily, the processing unit 320 can also be configured to randomize data received from the host 400. For example, the processing unit 320 can randomize data received from the host 400 by using a randomization seed. The randomized data can be provided to the memory 200 such that a storage array in the memory 200 can be programmed with the randomized data.

[0311] Exemplarily, the processing unit 320 can also be configured to de-randomize data from the memory 200 during a read operation. For example, the processing unit 320 can de-randomize data received from the memory 200 by using a de-randomization seed. The de-randomized data can be output to the host 400. Exemplarily, the processing unit 320 can perform the randomization operation and the de-randomization operation by driving software or firmware.

[0312] The host interface 330 can include a protocol for data exchange between the host 400 and the controller 300. The memory interface 440 can interface with the memory 200. For example, the memory interface 440 can include a NAND flash interface. The error correction block 350 can detect and correct errors in data received from the memory 200 by using error correction codes. In addition, the error correction block 350 can also correct errors in read page data by using error correction codes.

[0313] The memory 200 and the controller 300 can be integrated into one semiconductor device. Exemplarily, the memory 200 and the controller 300 can be integrated into a single semiconductor device to form a memory card. Exemplarily, the memory 200 and the controller 300 can be integrated into a single semiconductor device to form a Solid State Disk (SSD). The SSD can include a storage system 1300 for storing data in the memory 200. When the storage system 1300 is used in the SSD, the operation speed of a host 400 connected to the storage system 1300 can be significantly improved.

[0314] In an exemplary embodiment, the storage system 1300 can be used as one of several elements of various electronic devices such as a computer, an ultra-mobile personal computer, a workstation, a netbook, a personal digital assistant, a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player, a portable game console, a navigation system, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a wearable electronic device, a smart sensor, a virtual reality device, an augmented reality device, a device for transmitting / receiving information in a wireless environment, a device for a home network, a device for a computer network, a device for a telematics network, a Radio Frequency Identification (RFID) device, or other electronic devices having a storage system, etc.

[0315] Figure 15 A structural diagram of a memory card is shown as Figure 12As shown, the controller 300 and the single memory 200 can be integrated into a memory card 1500. The memory card 1500 includes, but is not limited to, a PC (Personal Computer Memory Card International Association, PC for short) card, a CF (CompactFlash, CF for short) card, an SM (Smart Media, SM for short) card, a memory stick, an MMC (Multi-Media Card, MMC for short), an RS-MMC (Reduced-Size MMC, RS-MMC for short), an MMCmicro (micro multi-media card), an SD (Secure Digital Memory Card, SD for short), a miniSD (mini secure digital memory card), a microSD (micro secure digital memory card), an SDHC (Secure Digital High Capacity, SDHC for short), a UFS (Universal Flash Storage, UFS for short) card, and the like. The memory card 1500 can also include a memory card connector 1510 that couples the memory card 1500 with a host (e.g., the host 400 in Figure 13 and Figure 16 ).

[0316] Figure 16 A structural schematic diagram of a solid state drive is shown as Figure 12 As shown, the controller 300 and the plurality of memories 200 can be integrated into a solid state drive 1600. The solid state drive 1600 can also include a solid state drive connector 1610 that couples the solid state drive 1600 with a host (e.g., the host 400 in Figure 13 and Figure 17 ). In some embodiments, the storage capacity and / or operating speed of the solid state drive 1600 is greater than the storage capacity and / or operating speed of the memory card 1500.

[0317] In an exemplary embodiment, an electronic device is also provided, as shown in ​ The electronic device includes a processor 1700 and a storage system 1300, the processor 1700 being configured to read and write data from and to the storage system 1300.

[0318] The storage system 1300 includes a memory and a controller coupled to the memory, the controller being configured to control the memory; the memory includes a storage array and a control circuit communicatively connected to the storage array; the storage array includes a non-selected storage string, the control circuit being configured to pre-charge the non-selected storage string according to the following steps before writing data to a selected storage cell:

[0319] applying a pre-charge voltage to a target input end of a non-selected memory string, the target input end being an input end of the non-selected memory string connected to a bit line or an input end connected to a source line;

[0320] conducting a channel of a memory cell between the target input end and a target memory cell in the non-selected memory string, the memory cell between the target input end and the target memory cell including a programmed memory cell, the target memory cell being a memory cell of the non-selected memory string connected to the selected word line.

[0321] In a possible implementation, the control circuit is configured to apply a first voltage to a gate of the memory cell between the target input end and the target memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell.

[0322] In a possible implementation, the memory cell between the target input end and the target memory cell further includes an unprogrammed memory cell; the control circuit is configured to apply a first voltage to the gate of the programmed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell; and apply a second voltage to the gate of the unprogrammed memory cell, the second voltage being greater than a threshold voltage of the unprogrammed memory cell and less than the first voltage.

[0323] In a possible implementation, the programming direction is a direction close to the target input end, and the programmed memory cells are all unerased memory cells.

[0324] In a possible implementation, the programming direction is a direction away from the target input end, and the programmed memory cells are all re-written data memory cells, or the programmed memory cells are all unerased memory cells, or the programmed memory cells are re-written data memory cells and unerased memory cells.

[0325] In a possible implementation, the control circuit is further configured to conduct a channel of a memory cell of the non-selected memory string not between the target input end and the target memory cell.

[0326] In a possible implementation, a turn-off time of applying the first voltage to the gate of the programmed memory cell is earlier than a turn-off time of applying the pre-charge voltage to the target input end.

[0327] In a possible implementation, the number of the programmed memory cells is a plurality, and a turn-off time of applying the first voltage to the gate of the programmed memory cell far from the target input end is not later than a turn-off time of applying the first voltage to the gate of the programmed memory cell close to the target input end.

[0328] In a possible implementation manner, the input end connected with the bit line and the input end connected with the source line comprise a selection tube stack and a storage unit stack connected through a doped region, the target input end is the input end connected with the bit line, and the storage unit between the target input end and the target storage unit comprises a storage unit between the doped region and the target storage unit.

[0329] It should be understood that the "multiple" mentioned herein refers to two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents that the associated objects before and after it are in an "or" relationship.

[0330] The above are only exemplary embodiments of the present application, and are not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A pre-charging method, characterized in that, The pre-charge method is used to pre-charge a non-selected memory string before writing data to a selected memory cell, the method comprising: A pre-charge voltage is applied to the target input terminal of the non-selected memory string, wherein the target input terminal is either the input terminal of the non-selected memory string connected to the bit line or the input terminal connected to the source line. The channel of the storage cell located between the target input terminal and the target storage cell in the non-selected storage string is connected, wherein the storage cell located between the target input terminal and the target storage cell includes a programmed storage cell, and the target storage cell is the storage cell in the non-selected storage string connected to the selected word line; The step of turning on the channel of the memory cell located between the target input terminal and the target memory cell in the non-selected memory string includes: applying a first voltage to the gate of the programmed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell, and the cutoff time for applying the first voltage to the gate of the programmed memory cell being earlier than the cutoff time for applying the pre-charge voltage to the target input terminal.

2. The method according to claim 1, characterized in that, The storage unit located between the target input terminal and the target storage unit further includes an unprogrammed storage unit; the step of connecting the channel of the storage unit located between the target input terminal and the target storage unit in the non-selected storage string further includes: The first voltage is applied to the gate of the unprogrammed memory cell.

3. The method according to claim 1, characterized in that, The storage unit located between the target input terminal and the target storage unit further includes an unprogrammed storage unit; the step of connecting the channel of the storage unit located between the target input terminal and the target storage unit in the non-selected storage string further includes: A second voltage is applied to the gate of the unprogrammed memory cell, the second voltage being greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

4. The method according to any one of claims 1-3, characterized in that, The programming direction is towards the target input terminal, and all programmed storage units are storage units that have not been erased.

5. The method according to any one of claims 1-3, characterized in that, The programming direction is away from the target input terminal. All programmed storage units are storage units that have been rewritten with data, or all programmed storage units are storage units that have not been erased, or the programmed storage units are storage units that have been rewritten with data and storage units that have not been erased.

6. The method according to any one of claims 1-3, characterized in that, The method further includes: Connect the channels of the memory cells in the non-selected memory string that are not located between the target input terminal and the target memory cell.

7. The method according to claim 1, characterized in that, The number of programmed memory cells is multiple, and the cutoff time for applying the first voltage to the gate of the programmed memory cell that is far from the target input terminal is no later than the cutoff time for applying the first voltage to the gate of the programmed memory cell that is close to the target input terminal.

8. The method according to any one of claims 1-3 and 7, characterized in that, The input terminal connected to the bit line and the input terminal connected to the source line include a select transistor stack and a memory cell stack, which are connected through a doped region. The target input terminal is the input terminal connected to the bit line, and the memory cell located between the target input terminal and the target memory cell includes the memory cell between the doped region and the target memory cell.

9. A pre-charging device, characterized in that, The pre-charging device is used to pre-charge a non-selected memory string before writing data to a selected memory cell, the device comprising: A voltage application module is configured to apply a pre-charge voltage to a target input terminal of the unselected memory string, wherein the target input terminal is either an input terminal of the unselected memory string connected to a bit line or an input terminal connected to a source line. The conduction module is configured to conduct the channel of the memory cell located between the target input terminal and the target memory cell in the non-selected memory string, wherein the memory cell located between the target input terminal and the target memory cell includes a programmed memory cell, and the target memory cell is the memory cell in the non-selected memory string connected to the selected word line; The step of turning on the channel of the memory cell located between the target input terminal and the target memory cell in the non-selected memory string includes: applying a first voltage to the gate of the programmed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell, and the cutoff time for applying the first voltage to the gate of the programmed memory cell being earlier than the cutoff time for applying the pre-charge voltage to the target input terminal.

10. A control circuit, characterized in that, The control circuit includes programmable logic circuitry and / or program instructions, and is configured to precharge a non-selected memory string according to the following steps before writing data to a selected memory cell: A pre-charge voltage is applied to the target input terminal of the non-selected memory string, wherein the target input terminal is either the input terminal of the non-selected memory string connected to the bit line or the input terminal connected to the source line. The channel of the storage cell located between the target input terminal and the target storage cell in the non-selected storage string is connected, wherein the storage cell located between the target input terminal and the target storage cell includes a programmed storage cell, and the target storage cell is the storage cell in the non-selected storage string connected to the selected word line; The step of turning on the channel of the memory cell located between the target input terminal and the target memory cell in the non-selected memory string includes: applying a first voltage to the gate of the programmed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell, and the cutoff time for applying the first voltage to the gate of the programmed memory cell being earlier than the cutoff time for applying the pre-charge voltage to the target input terminal.

11. A memory, characterized in that, The memory includes: a memory array and a control circuit communicatively connected to the memory array; The storage array includes non-selected memory strings, and the control circuitry is configured to pre-charge the non-selected memory strings according to the following steps before writing data to selected memory cells: A pre-charge voltage is applied to the target input terminal of the non-selected memory string, wherein the target input terminal is either the input terminal of the non-selected memory string connected to the bit line or the input terminal connected to the source line. The channel of the storage cell located between the target input terminal and the target storage cell in the non-selected storage string is connected, wherein the storage cell located between the target input terminal and the target storage cell includes a programmed storage cell, and the target storage cell is the storage cell in the non-selected storage string connected to the selected word line; The step of turning on the channel of the memory cell located between the target input terminal and the target memory cell in the non-selected memory string includes: applying a first voltage to the gate of the programmed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell, and the cutoff time for applying the first voltage to the gate of the programmed memory cell being earlier than the cutoff time for applying the pre-charge voltage to the target input terminal.

12. A storage system, characterized in that, The storage system includes a memory and a controller coupled to the memory, the controller being configured to control the memory; The memory includes a memory array and control circuitry communicatively connected to the memory array; the memory array includes non-selected memory strings, and the control circuitry is configured to pre-charge the non-selected memory strings according to the following steps before writing data to selected memory cells: A pre-charge voltage is applied to the target input terminal of the non-selected memory string, wherein the target input terminal is either the input terminal of the non-selected memory string connected to the bit line or the input terminal connected to the source line. The channel of the storage cell located between the target input terminal and the target storage cell in the non-selected storage string is connected, wherein the storage cell located between the target input terminal and the target storage cell includes a programmed storage cell, and the target storage cell is the storage cell in the non-selected storage string connected to the selected word line; The step of turning on the channel of the memory cell located between the target input terminal and the target memory cell in the non-selected memory string includes: applying a first voltage to the gate of the programmed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell, and the cutoff time for applying the first voltage to the gate of the programmed memory cell being earlier than the cutoff time for applying the pre-charge voltage to the target input terminal.

13. An electronic device, characterized in that, The electronic device includes a processor and a storage system, the processor being configured to read and write data from the storage system; The storage system includes a memory and a controller coupled to the memory, the controller being configured to control the memory; The memory includes a memory array and control circuitry communicatively connected to the memory array; the memory array includes non-selected memory strings, and the control circuitry is configured to pre-charge the non-selected memory strings according to the following steps before writing data to selected memory cells: A pre-charge voltage is applied to the target input terminal of the non-selected memory string, wherein the target input terminal is either the input terminal of the non-selected memory string connected to the bit line or the input terminal connected to the source line. The channel of the storage cell located between the target input terminal and the target storage cell in the non-selected storage string is connected, wherein the storage cell located between the target input terminal and the target storage cell includes a programmed storage cell, and the target storage cell is the storage cell in the non-selected storage string connected to the selected word line; The step of turning on the channel of the memory cell located between the target input terminal and the target memory cell in the non-selected memory string includes: applying a first voltage to the gate of the programmed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell, and the cutoff time for applying the first voltage to the gate of the programmed memory cell being earlier than the cutoff time for applying the pre-charge voltage to the target input terminal.

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