Monocrystalline silicon stack formation and bonding to complementary metal-oxide-semiconductor wafer

Abstract

Systems, methods, and apparatuses are provided for single crystal silicon stack formation and bonding to a complementary metal-oxide-semiconductor (CMOS) wafer for forming vertical three-dimensional (3D) memory. An example method for forming an array of vertical stacks for formation of memory cells includes providing a silicon substrate; forming a single crystal silicon germanium layer onto a surface of the substrate; epitaxially growing the silicon germanium to form a thicker silicon germanium layer; forming a single crystal silicon layer onto a surface of the silicon germanium; epitaxially growing the silicon germanium to form a thicker silicon layer; and in a repeating stack, forming a silicon germanium layer and a silicon layer to form a vertical stack of alternating silicon layers and silicon germanium layers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory devices, and more specifically to single crystal silicon stacks formed and bonded to a complementary metal-oxide-semiconductor (CMOS) wafer for forming vertical three-dimensional (3D) memory. BACKGROUND

[0002] Memory is typically implemented in electronic systems such as computers, cellular phones, handheld devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory can require power to maintain its data, and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can provide persistent data by retaining stored data when unpowered, and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase change memory (e.g., phase change random access memory), resistive memory (e.g., resistive random access memory), cross point memory, ferroelectric random access memory (FeRAM), etc.

[0003] As design rules shrink, less semiconductor space is available for fabricating memory including DRAM arrays. A respective memory cell for a DRAM can include an access device (e.g., a transistor) having first and second source / drain regions separated by a channel region. A gate can be opposite the channel region and separated from the channel region by a gate dielectric. An access line, such as a word line, is electrically connected to the gate of a DRAM cell. The DRAM cell can include a storage node, such as a capacitor cell, coupled to a digit line by the access device. The access device can be activated (e.g., to select the cell) by the access line coupled to the access transistor. The capacitor can store an electrical charge corresponding to a data value (e.g., a logic "1" or "0") of the respective cell. SUMMARY

[0004] Aspects of the present disclosure provide a method for forming an array of vertical stacks for formation of memory cells, wherein the method comprises: providing a silicon substrate; forming a single crystal silicon germanium layer onto a surface of the substrate; epitaxially growing silicon germanium to form a thicker silicon germanium layer; forming a single crystal silicon layer onto a surface of the silicon germanium; epitaxially growing the silicon formed onto the surface of the silicon germanium to form a thicker single crystal silicon layer; and in a repeating stack, forming a silicon germanium layer and a silicon layer to form a vertical stack of alternating silicon layers and silicon germanium layers.

[0005] Another aspect of the disclosure provides a device formed by bonding a stack of materials to a CMOS wafer, where the device includes: a CMOS wafer; a first monocrystalline silicon germanium layer attached to a surface of the CMOS wafer; a first monocrystalline silicon layer positioned on a surface of the silicon germanium; and in a repeating superposition, silicon germanium layers and silicon layers forming a vertical stack of alternating silicon layers and silicon germanium layers.

[0006] Another aspect of the disclosure provides a method for forming a vertical stack of memory cell arrays, where the method includes: providing a silicon substrate; forming a monocrystalline silicon germanium layer onto a surface of the substrate; forming a monocrystalline silicon layer onto a surface of the silicon germanium; in a repeating superposition, forming silicon germanium layers and silicon layers to form a vertical stack of alternating silicon layers and silicon germanium layers; and bonding a surface of the vertical stack to a CMOS wafer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1A is a schematic illustration of a vertical three-dimensional (3D) memory according to embodiments of the disclosure.

[0008] Figure 1B is a perspective view of a portion of a digit line and body contact region for a semiconductor device according to embodiments of the disclosure.

[0009] Figure 2A is a schematic illustration of a vertical three-dimensional (3D) memory according to embodiments of the disclosure.

[0010] Figure 2B is a perspective view of a portion of a three-node access device in a vertical three-dimensional (3D) memory array according to embodiments of the disclosure.

[0011] Figure 3 is a perspective view of a portion of a three-node access device in a vertical three-dimensional (3D) memory cell according to embodiments of the disclosure.

[0012] Figure 4 illustrates an example process for growing a monocrystalline silicon stack for a vertical three-dimensional (3D) memory according to embodiments of the disclosure.

[0013] Figure 5 illustrates an example process for bonding a monocrystalline silicon stack to a CMOS wafer according to embodiments of the disclosure.

[0014] Figure 6 illustrates another example process for bonding a monocrystalline silicon stack to a CMOS wafer according to embodiments of the disclosure.

[0015] Figure 7An example patterned vertical memory array formed from a single crystalline silicon stack bonded to a CMOS wafer is described in accordance with embodiments of the present disclosure.

[0016] Figure 8 A block diagram of a device in the form of a computing system including a memory device is provided in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] Embodiments of the present disclosure describe systems, devices, and methods for forming a single crystalline silicon stack and bonding to a CMOS wafer.

[0018] In vertically stacked memory array structures, such as transistor structures, polysilicon (also known as polysilicon) can leak, allowing current to leak through the polysilicon structure, making the transistor less effective. Single crystalline silicon does not leak as readily, however, single crystalline silicon cannot be grown on amorphous dielectric materials, such as oxides or nitrides, which are common materials for forming transistors. Additionally, the temperatures required for growth of single crystalline silicon are too high for CMOS components on which the vertically stacked memory array structures can be formed, thereby prohibiting the use of single crystalline silicon in such implementations.

[0019] However, as disclosed in embodiments of the present disclosure, it is possible to use a silicon wafer of transistors that can act as a substrate during the high temperature processes required for single crystalline silicon formation. In such embodiments, a silicon germanium layer can be grown on the silicon substrate. Single crystalline silicon can then be grown on the silicon germanium.

[0020] This can be accomplished, for example, by providing a thin single crystalline silicon germanium layer as a seed layer, and then heating the layer to grow the single crystalline silicon germanium layer thickness by epitaxial growth. Once the desired layer thickness is formed, a silicon layer can be formed into the surface of the silicon germanium layer. As with the silicon germanium layer, this can be accomplished, for example, by providing a thin single crystalline silicon layer as a seed layer, and then heating the layer to grow the thin single crystalline silicon layer thickness into a thicker single crystalline silicon layer by epitaxial growth.

[0021] Depending on the silicon germanium concentration, if silicon is x amount and germanium is y amount, and if y is less than x, then the silicon / silicon germanium has a smaller lattice mismatch to the lattice of single crystalline silicon. This allows silicon to grow on top of the silicon germanium with a single crystalline structure. If a thin layer of single crystalline silicon is applied to the surface of the silicon germanium, then the entire silicon layer acts as a seed for the growth of the single crystalline silicon layer. This layering can be done in an alternating stack (e.g., SiGe / Si / SiGe / Si, etc.) to produce a superlattice structure in a vertically stacked form, as shown in Figure 4

[0022] ​For example, a seed layer of silicon germanium can be formed, with a thickness (height) of 100 Angstroms, and can be grown to, for example, 1000 Angstroms. A thin silicon seed layer can be formed on the surface of a silicon germanium layer, for example, 50 Angstroms, and can be grown to a thickness of, for example, 300 Angstroms. Unless explicitly recited in a particular claim, these thicknesses are provided as examples only and should not be considered limiting.

[0023] This unpatterned (not patterned within the layer) vertical stack can then be attached to a CMOS wafer. Because there is no pattern yet within any of the vertical stack layers, the alignment between the CMOS wafer and the vertical stack can not be as precise, for example, the interconnects between the vertical stack and the CMOS wafer are not yet defined in the vertical stack. The transistor devices of the present disclosure have better performance in I-on, I-off, drivability, and / or leakage current because there are no grain boundaries and thus current does not leak through the grain boundaries, which are where leakage often occurs in polysilicon. In some embodiments, the devices can have lower I-off (leakage) of, for example, three orders of magnitude.

[0024] Advantages of the structures and processes described herein can include lower off-current (Ioff) for access devices (compared to silicon-based (Si-based) access devices, such as transistors), and / or reduced gate / drain induced leakage (GIDL) for access devices.

[0025] The drawings herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify an element or component in the figure. Similar elements or components between different figures can be identified by the use of similar digits. For example, reference numeral 104 can refer to element "04" in Figure 2A and similar elements can be denoted as 204 in Figure 2B Multiple similar elements within a figure can be denoted using a reference numeral followed by a hyphen and another numeral or letter. For example, 302-1 can refer to element 302-1 in Figure 3 and 302-2 can refer to element 302-2, which can be similar to element 302-1. Such similar elements can be generally referred to without the hyphen and extra numeral or letter. For example, elements 302-1 and 302-2 or other similar elements can be generally denoted as 302.

[0026] Figure 1A Block diagram of a device according to embodiments of the present disclosure. Figure 1A Diagram showing a circuit diagram of a cell array of a three-dimensional (3D) semiconductor memory device according to embodiments of the present disclosure. Figure 1AThe array of memory cells can have a plurality of sub-array of memory cells 101-1, 101-2,... 101-N. The sub-arrays of memory cells 101-1, 101-2,... 101-N can be arranged along a second direction (D2) 105. Each of the sub-arrays of memory cells (e.g., sub-array of memory cells 101-2) can include a plurality of access lines 107-1, 107-2,... 107-Q (which can also be referred to as word lines). In addition, each of the sub-arrays of memory cells (e.g., sub-array of memory cells 101-2) can include a plurality of digit lines 103-1, 103-2,... 103-Q (which can also be referred to as bit lines, data lines, or sense lines). In Figure 1A In the figures, the access lines 107-1, 107-2,... 107-Q are illustrated as extending in a first direction (D1) 109, and the digit lines 103-1, 103-2,... 103-Q are illustrated as extending in a third direction (D3) 111. According to embodiments, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“X-Y”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Thus, according to embodiments described herein, the digit lines 103-1, 103-2,... 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).

[0027] A memory cell (e.g., 110) can include an access device (e.g., an access transistor) and a storage node at an intersection of each access line 107-1, 107-2,... 107-Q and each digit line 103-1, 103-2,... 103-Q. The access lines 107-1, 107-2,... 107-Q and the digit lines 103-1, 103-2,... 103-Q can be used to write to or read from a memory cell. The access lines 107-1, 107-2,... 107-Q can conductively interconnect memory cells along a horizontal row of each sub-array of memory cells 101-1, 101-2,... 101-N, and the digit lines 103-1, 103-2,... 103-Q can conductively interconnect memory cells along a vertical column of each sub-array of memory cells 101-1, 101-2,... 101-N. One memory cell (e.g., 110) can be located between one access line (e.g., 107-2) and one digit line (e.g., 103-2). Each memory cell can be uniquely addressed by a combination of an access line 107-1, 107-2,... 107-Q and a digit line 103-1, 103-2,... 103-Q.

[0028] Access lines 107-1, 107-2,... 107-P can be or include electrically conductive patterns (e.g., metal lines) disposed on and spaced apart from a substrate. Access lines 107-1, 107-2,... 107-Q can extend in a first direction (D1) 109. Access lines 107-1, 107-2,... 107-Q in one subcell array (e.g., 101-2) can be spaced apart from one another in a vertical direction (e.g., in a third direction (D3) 111).

[0029] Digital lines 103-1, 103-2,... 103-Q can be or include electrically conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., in a third direction (D3) 111) relative to a substrate. Digital lines in one subcell array (e.g., 101-2) can be spaced apart from one another in a first direction (D1) 109.

[0030] A gate of a memory cell (e.g., memory cell 110) can be connected to an access line (e.g., 107-2), and a first conductive node (e.g., a first source / drain region) of an access device (e.g., a transistor) of memory cell 110 can be connected to a digital line (e.g., 103-2). Each of the memory cells (e.g., memory cell 110) can be connected to a storage node, such as a capacitor. A second conductive node (e.g., a second source / drain region) of the access device (e.g., a transistor) of memory cell 110 can be connected to the storage node, such as a capacitor. While first and second source / drain region references are used herein to refer to two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as the "first" and / or "second" source / drain regions have some unique meaning. It is only intended that one of the source / drain regions be connected to a digital line, such as 103-2, and the other can be connected to a storage node.

[0031] Figure 1B A perspective view showing a portion of a subcell array 101-2 as a vertically oriented stack of memory cells in an array is shown in FIG. 1C in accordance with some embodiments of the present disclosure. Figure 1A A perspective view showing a portion of a subcell array 101-2 as a vertically oriented stack of memory cells in an array is shown in FIG. 1C in accordance with some embodiments of the present disclosure.

[0032] As shown in FIG. 1A, a substrate 100 can have formed thereon a combination of Figure 1B As shown in FIG. 1A, a substrate 100 can have formed thereon a combination of Figure 1A One of the plurality of subcell arrays (e.g., 101-2) described is depicted. For example, substrate 100 can be or include a silicon substrate, a germanium substrate, or a silicon- germanium substrate, among others. However, embodiments are not limited to these examples.

[0033] As shown in FIG. 1A, a substrate 100 can have formed thereon a combination of Figure 1B As shown in FIG. 1A, a substrate 100 can have formed thereon a combination ofFigure 1A The memory cells 110 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 1A The memory cells 110 are formed in multiple vertical layers, such as a first layer (L1), a second layer (L2), and a third layer (L3). They can be arranged vertically (e.g., along the vertical direction). Figure 1A The diagram shows a third-party (D3) 111) arrangement (e.g., “stacked”) of repeating vertical layers L1, L2, and L3, which are separated from the substrate 100 by an insulating material 120. Each of the repeating vertical layers L1, L2, and L3 may include multiple discrete components (e.g., regions) of horizontally oriented access devices 130 (e.g., transistors) and memory nodes (e.g., capacitors), including access lines 107-1, 107-2, ... 107-Q connectors and digital lines 103-1, 103-2, ... 103-Q connectors. The multiple discrete components of the horizontally oriented access devices 130 (e.g., transistors) may be formed in multiple stacks of vertical repeating layers within each layer, as described below. Figure 4 A more detailed description, and may be available in similar formats. Figure 1A The second direction (D2) 105 shown in the figure extends horizontally on the second direction (D2) 105.

[0034] A plurality of discrete components of a lateral access device 130 (e.g., a transistor) may include a first source / drain region 121 and a second source / drain region 123 separated by a channel region 125 extending laterally in a second direction (D2) 105 and formed in the body of the access device. In some embodiments, the channel region 125 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 121 and the second source / drain region 123 may comprise an n-type dopant region formed in the p-type doped body of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 121 and the second source / drain region 123 may comprise a p-type dopant formed in the n-type doped body of the access device to form a p-type conductive transistor. By way of example, but not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in a relatively doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0035] Storage node 127 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 1BAs shown, storage node 127 (e.g., a capacitor) can be connected to a second source / drain region 123 of the access device. Storage nodes can be or contain memory elements capable of storing data. Each of the storage nodes can be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g. Figure 1A Each memory node associated with an access device in memory cell 110 can be similarly located in a memory node with a memory node ... Figure 1A The second direction (D2)105 shown in the middle extends upwards.

[0036] like Figure 1B As shown, multiple horizontally oriented access lines 107-1, 107-2, ... 107-Q extend along a first direction (D1) 109 similar to that in Figure 1A. The multiple horizontally oriented access lines 107-1, 107-2, ... 107-Q can be similar to... Figure 1A Access lines 107-1, 107-2, ... 107-Q are shown in the diagram. Multiple horizontally oriented access lines 107-1, 107-2, ... 107-Q may be arranged (e.g., "stacked") along a third direction (D3) 111. The multiple horizontally oriented access lines 107-1, 107-2, ... 107-Q may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0037] In each of the vertical hierarchies (L1)113-1, (L2)113-2, and (L3)113-P, the horizontally oriented memory cells (e.g.) Figure 1AThe memory cells 110 in each tier can be horizontally spaced apart from one another in a first direction (Dl) 109. However, the horizontally oriented access devices 130 having a plurality of discrete components (e.g., first and second source / drain regions 121, 123 separated by a channel region 125) extending laterally in a second direction (D2) 105, and a plurality of horizontally oriented access lines 107-1, 107-2,... 107-Q extending laterally in the first direction (Dl) 109 can be formed within different vertical layers within each tier. For example, the plurality of horizontally oriented access lines 107-1, 107-2,... 107-Q extending in the first direction (Dl) 109 can be formed on a top surface opposite and electrically coupled to the channel region 125, separated from the channel region 125 by a gate dielectric, and orthogonal to the horizontally oriented access devices 130 (e.g., transistors) extending laterally in the second direction (D2) 105. In some embodiments, the plurality of horizontally oriented access lines 107-1, 107-2,... 107-Q extending in the first direction (Dl) 109 are formed in a higher vertical layer within a tier (e.g., within tier (LI)) that is further from the substrate 100 than a layer in which the discrete components of the horizontally oriented access devices (e.g., first and second source / drain regions 121, 123 separated by a channel region 125) are formed.

[0038] As shown in example embodiments of Figure 1B The digit lines 103-1, 103-2,... 103-Q extend in a vertical direction relative to the substrate 100 (e.g., in a third direction (D3) 111). Further, as shown in Figure 1B example, a subcell array (e.g., Figure 1AThe digit lines 103-1, 103-2,... 103-Q in the subunit array 101-2) can be spaced apart from one another in the first direction (D1) 109. The digit lines 103-1, 103-2,... 103-Q can be provided to extend vertically in the third direction (D3) 111 relative to the substrate 100 in a form that is vertically aligned with the source / drain regions that function as the first source / drain regions 121, or as shown, vertically adjacent to the first source / drain regions 121 of each of the horizontally oriented access devices 130 (e.g., transistors) that laterally extend in the second direction (D2) 105, but adjacent to one another in the first direction (D1) 109 on a level (e.g., a first level (LI)). Each of the digit lines 103-1, 103-2,... 103-Q can vertically extend in the third direction (D3) on a sidewall of a respective one of the vertically stacked plurality of horizontally oriented access devices 130 (e.g., transistors) adjacent to the first source / drain regions 121. In some embodiments, the plurality of vertically oriented digit lines 103-1, 103-2,... 103-Q extending in the third direction (D3) 111 can be connected directly and / or through additional contacts containing metal silicides to the side surfaces of the first source / drain regions 121.

[0039] For example, a first one of the vertically extending digit lines (e.g., 103-1) can be adjacent to a sidewall of a first one of the horizontally oriented access devices 130 (e.g., transistors) in the first level (LI) 113-1, a sidewall of a first one of the horizontally oriented access devices 130 (e.g., transistors) in the second level (L2) 113-2, and a sidewall of a first one of the horizontally oriented access devices 130 (e.g., transistors) in the third level (L3) 113-P, etc. Similarly, a second one of the vertically extending digit lines (e.g., 103-2) can be adjacent to a sidewall of a second one of the horizontally oriented access devices 130 (e.g., transistors) in the first level (LI) 113-1, spaced apart from the first one of the horizontally oriented access devices 130 (e.g., transistors) in the first level (LI) 113-1 in the first direction (D1) 109. Also, the second one of the vertically extending digit lines (e.g., 103-2) can be adjacent to a sidewall of a second one of the horizontally oriented access devices 130 (e.g., transistors) in the second level (L2) 113-2, and a sidewall of a second one of the horizontally oriented access devices 130 (e.g., transistors) in the third level (L3) 113-P, etc. Embodiments are not limited to a particular number of levels.

[0040] The vertically extending digital lines 103-1, 103-2, ... 103-Q may contain conductive materials, such as doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. The digital lines 103-1, 103-2, ... 103-Q may correspond to... Figure 1A The described digital line (DL).

[0041] like Figure 1B As shown in the example embodiment, the conductive body contact region may be formed to extend along the end surface of a horizontally oriented access device 130 (e.g., a transistor) in a first direction (D1) 109 along each of the horizontally oriented access devices 130 (L1) 113-1, (L2) 113-2, and (L3) 113-P above the substrate 100. The body contact region may be connected to each memory cell (e.g., Figure 1A The body of the horizontally oriented access device 130 (e.g., a transistor) in the memory cell 110 (e.g.) Figure 3 (As shown in 336), for example, the body contact region. The body contact region may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0042] although Figure 1B Not shown, but insulating material may fill other spaces in a vertically stacked array of memory cells. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples. Figure 2A This is a block diagram of a device according to several embodiments of the present disclosure. Figure 2A The illustration shows a circuit diagram of a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure. Figure 2A The cell array can have multiple sub-cell arrays 201-1, 201-2, ..., 201-N. Sub-cell arrays 201-1, 201-2, ..., 201-N can be arranged along a second direction (D2) 205. Each sub-cell array (e.g., sub-cell array 201-2) can contain multiple access lines 203-1, 203-2, ..., 203-Q (which may also be called word lines). Additionally, each sub-cell array (e.g., sub-cell array 201-2) can contain multiple digital lines 207-1, 207-2, ..., 207-Q (which may also be called bit lines, data lines, or sensing lines). Figure 2A The text describes the digital lines 207-1, 207-2, ..., 207-Q extending in the first direction (D1) 209, and the access lines 203-1, 203-2, ..., 203-Q extending in the third direction (D3) 211.

[0043] The first direction (D1) 209 and the second direction (D2) 205 can be considered to be in a horizontal ("X-Y") plane. The third direction (D3) 211 can be considered to be in a vertical ("Z") direction (e.g., transverse to the X-Y plane). Thus, according to the embodiments described herein, the access lines 203-1, 203-2,... 203-Q extend in the vertical direction (e.g., the third direction (D3) 211).

[0044] A memory cell (e.g., 210) can include an access device (e.g., an access transistor) and a storage node at an intersection of each access line 203-1, 203-2,... 203-Q and each digit line 207-1, 207-2,... 207-Q. The access lines 203-1, 203-2,... 203-Q and the digit lines 207-1, 207-2,... 207-Q can be used to write to or read from a memory cell. The digit lines 207-1, 207-2,... 207-Q can conductively interconnect memory cells along a horizontal column of each sub-cell array 201-1, 201-2,... 201-N, and the access lines 203-1, 203-2,... 203-Q can conductively interconnect memory cells along a vertical row of each sub-cell array 201-1, 201-2,... 201-N. One memory cell (e.g., 210) can be located between one access line (e.g., 203-2) and one digit line (e.g., 207-2). Each memory cell can be uniquely addressed by a combination of an access line 203-1, 203-2,... 203-Q and a digit line 207-1, 207-2,... 207-Q.

[0045] The digit lines 207-1, 207-2,... 207-Q can be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from a substrate. The digit lines 207-1, 207-2,... 207-Q can extend in the first direction (D1) 209. The digit lines 207-1, 207-2,... 207-Q in one sub-cell array (e.g., 201-2) can be spaced apart from one another in a vertical direction (e.g., in the third direction (D3) 211).

[0046] The access lines 203-1, 203-2,... 203-Q can be or include conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., in the third direction (D3) 211) relative to a substrate. The access lines in one sub-cell array (e.g., 201-2) can be spaced apart from one another in the first direction (D1) 209.

[0047] The gate of a memory cell (e.g., memory cell 210) may be connected to an access line (e.g., 203-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 210 may be connected to a digital line (e.g., 207-2). Each of the memory cells (e.g., memory cell 210) may be connected to a storage node (e.g., a capacitor). The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 210 may be connected to a storage node (e.g., a capacitor). The storage node (e.g., a capacitor) may be formed of a ferroelectric and / or dielectric material, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), lead zirconate titanate (PZT, Pb[Zr(x)Ti(1-x)]O3), barium titanate (BaTiO3), aluminum oxide (e.g., Al2O3), combinations of these with or without dopants, or other suitable materials.

[0048] Although this paper uses the references of first and second source / drain regions to refer to two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" have a specific meaning. It is only desirable that one of the source / drain regions is connected to a digital line (e.g., 207-2), and the other is connected to a memory node.

[0049] Figure 2B The illustration shows a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure (e.g., Figure 2A The perspective view shown is a portion of the sub-cell array 201-2 as a vertically oriented stack of memory cells in the array. Figure 3 Explanation and display Figure 2B The unit cell of the 3D semiconductor memory device shown in the image (e.g.) Figure 2A A perspective view of the memory cell 210 shown in the image.

[0050] like Figure 2B As shown, substrate 200 may have a bonding formed thereon. Figure 2A One of the described array of sub-cells (e.g., 201-2). For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0051] like Figure 2B As shown in the example embodiments, memory cells extending in a vertical direction (e.g., third direction (D3) 211) can be fabricated on the substrate 200. Figure 2A The memory cells 210 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g.,Figure 2A The memory cells 210 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). They can be arranged vertically (e.g., along the vertical direction). Figure 2A The diagram shows a third-party (D3) 211) arrangement (e.g., “stacked”) of repeating vertical layers L1, L2, and L3, which are separated from the substrate 200 by an insulating material 220. Each of the repeating vertical layers L1, L2, and L3 may include multiple discrete components (e.g., regions) of laterally oriented access devices 230 (e.g., transistors) and memory nodes (e.g., capacitors), including access lines 203-1, 203-2, ..., 203-Q connectors and digital lines 207-1, 207-2, ..., 207-Q connectors. The multiple discrete components of the laterally oriented access devices 230 (e.g., transistors) may be formed in multiple stacks of vertical repeating layers within each layer, as described below. Figure 4 A more detailed description, and may be available in similar formats. Figure 2A The second direction (D2) 205 shown in the figure extends horizontally on the second direction (D2) 205.

[0052] A plurality of discrete components of a lateral access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225 extending laterally in a second direction (D2) 205 and formed in the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise an n-type dopant region formed in the p-type doped body of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise a p-type dopant formed in the n-type doped body of the access device to form a p-type conductive transistor. By way of example, but not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in a relatively doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0053] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 2B As shown, storage node 227 (e.g., a capacitor) can be connected to the second source / drain region 223 of the access device. Storage nodes can be or contain memory elements capable of storing data. Each of the storage nodes can be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g.Figure 2A Each memory node associated with an access device in memory cell 210 can be similarly located in a memory node with a memory access device ... Figure 2A The second direction (D2)205 shown in the middle extends upwards.

[0054] like Figure 2B As shown, multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q extend in a first direction (D1) 209 similar to that in Figure 2A. The multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q can be similar to... Figure 2A The digital lines 207-1, 207-2, ... 207-Q shown are illustrated. Multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q may be arranged (e.g., "stacked") along a third direction (D3) 211. The multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0055] In each of the vertical hierarchies (L1)213-1, (L2)213-2, and (L3)213-P, the horizontally oriented memory cells (e.g.) Figure 2A The memory cells 210 in the memory may be horizontally spaced apart from each other in the first direction (D1) 209. However, as described below... Figure 4As described in more detail, the laterally oriented access device 230 may have multiple discrete components extending laterally in the second direction (D2) 205 (e.g., a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225), and multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q extending laterally in the first direction (D1) 209, which may be formed in different vertical layers within each level. For example, the multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q extending in the first direction (D1) 209 may be disposed on and electrically contacted on the top surface of the first source / drain region 221, and orthogonal to the laterally oriented access device 230 (e.g., a transistor) extending laterally in the second direction (D2) 205. In some embodiments, a plurality of horizontally oriented digital lines 207-1, 207-2, ... 207-Q extending in the first direction (D1) 209 are formed in a higher vertical layer within a layer hierarchy (e.g., within layer (L1)), which is further away from the substrate 200 than the layer in which discrete components of laterally oriented access devices (e.g., the first source / drain region 221 and the second source / drain region 223 separated by channel region 225) are formed. In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ... 207-Q extending in the first direction (D1) 209 may be directly and / or connected to the top surface of the first source / drain region 221 via additional contacts comprising metal silicide.

[0056] like Figure 2B As shown in the example embodiments, access lines 203-1, 203-2, ... 203-Q extend in a vertical direction relative to substrate 200 (e.g., on third direction (D3) 211). Furthermore, as... Figure 2B As shown, a sub-cell array (e.g., Figure 2A Access lines 203-1, 203-2, ..., 203-Q in the sub-cell array 201-2 can be spaced apart from each other in a first direction (D1) 209. Access lines 203-1, 203-2, ..., 203-Q can be provided that extend vertically in a third direction (D3) 211 relative to the substrate 200 between a pair of laterally oriented access devices 230 (e.g., transistors) extending laterally in a second direction (D2) 205, but adjacent to each other in a layer (e.g., a first layer (L1)) in the first direction (D1) 209. Each of the access lines 203-1, 203-2, ..., 203-Q can extend vertically in a third direction (D3) on the sidewall of the corresponding of a plurality of laterally oriented access devices 230 (e.g., transistors) stacked vertically.

[0057] For example, and suchFigure 3 As shown in more detail, a first of the vertically-extending access lines (e.g., 203-1) can be adjacent to a sidewall of a channel region 225 of a first of the laterally-oriented access devices 230 (e.g., transistors) in the first level (LI) 213-1, a sidewall of the channel region 225 of the first of the laterally-oriented access devices 230 (e.g., transistors) in the second level (L2) 213-2, a sidewall of the channel region 225 of the first of the laterally-oriented access devices 230 (e.g., transistors) in the third level (L3) 213-P, etc. Similarly, a second of the vertically-extending access lines (e.g., 203-2) can be adjacent to a sidewall of a channel region 225 of a second of the laterally-oriented access devices 230 (e.g., transistors) in the first level (LI) 213-1, spaced apart from the first of the laterally-oriented access devices 230 (e.g., transistors) in the first level (LI) 213-1 in the first direction (Dl) 209. Also, the second of the vertically-extending access lines (e.g., 203-2) can be adjacent to a sidewall of the channel region 225 of the second of the laterally-oriented access devices 230 (e.g., transistors) in the second level (L2) 213-2, and a sidewall of the channel region 225 of the second of the laterally-oriented access devices 230 (e.g., transistors) in the third level (L3) 213-P, etc. Embodiments are not limited to a particular number of levels.

[0058] The vertically-extending access lines 203-1, 203-2,... 203-Q can include an electrically-conductive material, such as one of a doped semiconductor material, an electrically-conductive metal nitride, a metal, and / or a metal-semiconductor compound. The access lines 203-1, 203-2,... 203-Q can correspond to the word lines (WL) described in connection with Figure 2A

[0059] As shown in the example embodiment of FIG. 3A, the electrically-conductive body contact region 295 can be formed to extend along end surfaces of the laterally-oriented access devices 230 (e.g., transistors) in each of the levels (LI) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200 in the first direction (Dl) 209. The body contact region 295 can be connected to a body (e.g., a body region) of the laterally-oriented access device 230 (e.g., transistor) in each of the memory cells 210, such as shown at 336 in FIG. 3B. Figure 2B As shown in the example embodiment of FIG. 3A, the electrically-conductive body contact region 295 can be formed to extend along end surfaces of the laterally-oriented access devices 230 (e.g., transistors) in each of the levels (LI) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200 in the first direction (Dl) 209. The body contact region 295 can be connected to a body (e.g., a body region) of the laterally-oriented access device 230 (e.g., transistor) in each of the memory cells 210, such as shown at 336 in FIG. 3B. Figure 2A As shown in the example embodiment of FIG. 3A, the electrically-conductive body contact region 295 can be formed to extend along end surfaces of the laterally-oriented access devices 230 (e.g., transistors) in each of the levels (LI) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200 in the first direction (Dl) 209. The body contact region 295 can be connected to a body (e.g., a body region) of the laterally-oriented access device 230 (e.g., transistor) in each of the memory cells 210, such as shown at 336 in FIG. 3B. Figure 3 The body contact region 295 can include an electrically-conductive material, such as one of a doped semiconductor material, an electrically-conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0060] Although Figure 2B ​The insulative material can fill other spaces in the vertically-stacked array of memory cells, although not shown. For example, the insulative material can include one or more of a silicon oxide material, a silicon nitride material, and / or a silicon oxynitride material, among others. However, embodiments are not limited to these examples.

[0061] Figure 3 A unit cell (e.g., a memory cell 210 in the vertically-stacked array of memory cells 200) according to some embodiments of the present disclosure is described in more detail. For example, a unit cell (e.g., a memory cell 210 in the vertically-stacked array of memory cells 200) according to some embodiments of the present disclosure is described in more detail. Figure 2A Figure 2A Figure 3 As shown in the vertically-stacked array of memory cells 200, a first source / drain region 321 and a second source / drain region 323 can be impurity-doped regions of a laterally-oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to the first source / drain region 221 and the second source / drain region 223 shown in the vertically-stacked array of memory cells 200. The first and second source / drain regions can be separated by a channel 325 formed in a body (e.g., a body region 326) of semiconductor material of the laterally-oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be formed from n-type or p-type dopants doped in the body region 326. Embodiments are not limited in this regard. Figure 2B

[0062] For example, for an n-type conductivity transistor configuration, the body region 326 of the laterally-oriented access device 330 (e.g., a transistor) can be formed from a low-doped (p-) p-type semiconductor material. In some embodiments, the body region 326 and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 can include a low-doped p-type (e.g., lower dopant concentration (p-)) polysilicon material composed of boron (B) atoms as an impurity dopant of the polysilicon. The first source / drain region 321 and the second source / drain region 323 can also include a metal composite including at least one of ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), a highly-doped degenerate semiconductor material, and / or indium oxide (In2O3) or indium tin oxide (In 2-x Sn x O3) formed using an atomic layer deposition process, among others. However, embodiments are not limited in this regard.

[0063] ​​​As used herein, degenerate semiconductor material refers to a semiconductor material, such as polycrystalline silicon, containing a high level of doping with significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain a moderate level of doping, where the dopant atoms are well separated from each other in the semiconductor bulk lattice with negligible interactions.

[0064] In this example, the first source / drain region 321 and the second source / drain region 323 may contain highly doped n-type conductive impurities (e.g., highly doped (n+)) doped into the first source / drain region 321 and the second source / drain region 323. In some embodiments, the highly doped n-type conductive first drain region 321 and the second drain region 323 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the laterally oriented access device 330 (e.g., a transistor) may have a p-type conductive configuration, in which case the conductivity type of the impurities (e.g., dopants) will be reversed.

[0065] like Figure 3 As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body 326 of the laterally oriented access device 330 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface 324 within the body 326 of the laterally oriented access device 330, which is vertically higher in a third direction (D3) 311 compared to the bottom surface of the body 326 of the laterally oriented access device 330. Thus, the laterally oriented transistor 330 may have a region lower than the first source / drain region 321 and in contact with the body (e.g., Figure 2B The main body portion 326 of the electrical contact shown in Figure 295. Furthermore, as... Figure 3 As shown in the example embodiments, similar to Figure 2B The numerical lines 207-1, 207-2, ..., 207-Q and Figure 2A The digital lines 207-1, 207-2, ..., 207-Q shown in the figure (e.g., 307-1) can be placed on the top surface 322 of the first source / drain region 321 and electrically coupled thereto.

[0066] like Figure 3 As shown in the example embodiments, the access line (e.g., similar to) Figure 2B Access lines 203-1, 203-2, ..., 203-Q and Figure 2AThe 303-1) of 203-1, 203-2,... 203-Q in FIG. 3 can vertically extend on a third direction (D3) 311 adjacent to a sidewall of a channel region 325 portion of a body 326 of a laterally oriented access device 330 (e.g., transistor), which is conductive horizontally along a second direction (D2) 305 between a first source / drain region 321 and a second source / drain region 323. A gate dielectric material 304 can be interposed between the access line 303-1 (a portion of which forms a gate of the laterally oriented access device 330 (e.g., transistor)) and the channel region 325.

[0067] The gate dielectric material 304 can include, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc., or combinations thereof. Embodiments are not limited in this context. For example, in a high-k dielectric material example, the gate dielectric material 304 can include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0068] Figure 4 An example process for producing a single crystalline silicon stack for a vertical three-dimensional (3D) memory is described, for example, in FIGS. 1-3 and in accordance with a number of embodiments of the present disclosure. The vertical stack includes a plurality of layers of single crystalline silicon germanium 430 and single crystalline silicon 432 formed on a substrate 437.

[0069] As discussed above, this can be accomplished, for example, by providing a thin single crystalline silicon germanium layer as a seed layer, and then heating the layer to grow the single crystalline silicon germanium layer thickness by epitaxial growth. Once the desired layer thickness is formed, a silicon layer can be formed into the surface of the silicon germanium layer. As with the silicon germanium layer, this can be accomplished, for example, by providing a thin single crystalline silicon layer as a seed layer, and then heating the layer to grow the single crystalline silicon layer thickness by epitaxial growth.

[0070] For example, the single crystalline silicon germanium 430 can be grown epitaxially by flowing a silicon-based gas over a thin seed layer of single crystalline silicon germanium of a first layer formed on a surface of the substrate 437, and for subsequent single crystalline silicon germanium layers, over a thin seed layer of single crystalline silicon germanium formed on a surface of an exposed single crystalline silicon layer of the vertical stack. For example, disilane (Si2H6) gas can be utilized to epitaxially grow single crystalline silicon germanium from an exposed surface of a thin layer of single crystalline silicon germanium that has been deposited as a seed for epitaxial growth of single crystalline silicon germanium. However, embodiments are not limited in this context. For example, dichlorosilane (SiH2Cl2) gas can be flowed over a seed layer to epitaxially grow single crystalline silicon germanium 430 onto an exposed surface of the seed layer.

[0071] In some embodiments, flowing a silicon-based gas over the seed layer at a selected temperature (e.g., between 300 degrees Celsius (°C) to 1100 °C) can cause the single crystal silicon germanium 430 to grow epitaxially at a predictable rate. Based on this predictable growth rate, the single crystal silicon germanium layer can be grown to a desired height in a predetermined period of time. In some implementations, for single crystal silicon and / or single crystal silicon germanium epitaxial growth, the temperature range can be, for example, less than 900 °C, as at higher temperatures, germanium can begin to diffuse, and single crystal silicon and single crystal silicon germanium can begin to mix. All individual values and subranges between 300 °C to 1100 °C are included; for example, the silicon gas can be flowed at a temperature of a lower limit of 300 °C, 400 °C, 450 °C, 500 °C, 550 °C, 600 °C, 650 °C, 700 °C, 750 °C, 800 °C, 850 °C, or 900 °C to an upper limit of 900 °C, 950 °C, 1000 °C, 1050 °C, or 1100 °C. However, embodiments are not limited to these examples. For example, the silicon-based gas can be flowed at a temperature of 300 °C to 1100 °C to cause the single crystal silicon germanium to grow epitaxially. All individual values and subranges between 300 °C to 1100 °C are included.

[0072] Additionally, the silicon-based gas can be flowed for 1 minute to 15 minutes to cause the single crystal silicon germanium to grow epitaxially. All individual values and subranges between 1 minute to 15 minutes are included; for example, the silicon gas can be flowed for a time frame of a lower limit of 1 minute, 2 minutes, 3 minutes, 4 minutes, 5 minutes, 6 minutes, 7 minutes, 8 minutes, 9 minutes, or 10 minutes to an upper limit of 8 minutes, 9 minutes, 10 minutes, 11 minutes, 12 minutes, 13 minutes, 14 minutes, or 15 minutes. For example, the silicon-based gas can be flowed at a temperature of 800 °C to 900 °C for 7 to 10 minutes to cause the single crystal silicon germanium to grow epitaxially.

[0073] However, embodiments are not limited to these examples. For example, the length of time the silicon-based gas is flowed over the single crystal silicon germanium seed layer can vary depending on the temperature of the silicon-based gas. For example, the silicon-based gas can be flowed for 1 minute to 500 minutes to cause the single crystal silicon to grow epitaxially based on the temperature. All individual values and subranges between 1 minute to 500 minutes are included.

[0074] To form a single crystal silicon layer on the previously formed single crystal silicon germanium layer, depending on the silicon germanium concentration, if silicon is x amount and germanium is y amount, and if y is less than x, then the silicon / silicon germanium has a smaller lattice mismatch relative to the lattice of the single crystal silicon, as discussed above. This allows the single crystal silicon to grow on top of the single crystal silicon germanium with a single crystal structure. If a thin layer of single crystal silicon is applied to the surface of the single crystal silicon germanium, the entire single crystal silicon layer acts as a seed for the growth of the single crystal silicon layer.

[0075] The processes and parameters for forming the monocrystalline silicon layer are similar to those described above with respect to the monocrystalline silicon germanium layer. For example, the monocrystalline silicon 432 can be epitaxially grown by flowing a silicon-based gas over a thin seed layer of monocrystalline silicon formed on the surface of the previously formed vertically stacked exposed monocrystalline silicon germanium layer of a thin seed layer of monocrystalline silicon. For example, disilane (Si2H6) gas can be utilized to epitaxially grow monocrystalline silicon from the exposed surface of the thin layer of monocrystalline silicon that has been deposited as a seed for epitaxial growth of the monocrystalline silicon layer.

[0076] However, embodiments are not limited thereto. For example, dichlorosilane (SiH2Cl2) gas can be flowed over the seed layer to epitaxially grow monocrystalline silicon 432 onto the exposed surface of the monocrystalline silicon seed layer.

[0077] In some embodiments, similar to the formation of the monocrystalline silicon germanium layer, the flow of the silicon-based gas over the monocrystalline silicon seed layer at a selected temperature, for example, between 300 °C to 1100 °C, can cause the monocrystalline silicon 432 to epitaxially grow at a predictable rate. Based on this predictable growth rate, the monocrystalline silicon layer can be grown to a desired height in a predetermined period of time. All individual values and subranges from 300 °C to 1100 °C are included; for example, the silicon gas can be flowed at a temperature of a lower limit of 300 °C, 400 °C, 450 °C, 500 °C, 550 °C, 600 °C, 650 °C, 700 °C, 750 °C, 800 °C, 850 °C, or 900 °C to an upper limit of 900 °C, 950 °C, 1000 °C, 1050 °C, or 1100 °C. However, embodiments are not limited to these examples. For example, the silicon-based gas can be flowed at a temperature of 300 °C to 4000 °C to epitaxially grow monocrystalline silicon. All individual values and subranges from 300 °C to 4000 °C are included.

[0078] Additionally, the silicon-based gas can be flowed for 1 minute to 15 minutes to epitaxially grow monocrystalline silicon. All individual values and subranges from 1 minute to 15 minutes are included; for example, the silicon gas can be flowed for a time frame of a lower limit of 1 minute, 2 minutes, 3 minutes, 4 minutes, 5 minutes, 6 minutes, 7 minutes, 8 minutes, 9 minutes, or 10 minutes to an upper limit of 8 minutes, 9 minutes, 10 minutes, 11 minutes, 12 minutes, 13 minutes, 14 minutes, or 15 minutes. For example, the silicon-based gas can be flowed at a temperature of 800 °C to 900 °C for 7 to 10 minutes to epitaxially grow monocrystalline silicon.

[0079] This layering can be alternately stacked (e.g., SiGe / Si / SiGe / Si, etc.) to produce a superlattice structure in a vertical stack. This unpatterned (not patterned within the layer) vertical stack can then be attached to a CMOS wafer, as described with respect to FIG. 1. Figure 5As described. One advantage of this process is that, because the vertical stack is not yet patterned, it does not require careful alignment with the CMOS wafer.

[0080] Figure 5 This describes example processes for stacking and bonding single-crystal silicon to a CMOS wafer 545 according to several embodiments of the present disclosure. In some embodiments, such as Figure 5 As explained, single-crystal silicon germanium 530 and single-crystal silicon 532 layers have been epitaxially grown onto substrate 537 and epitaxially grown together to form a structure as described above. Figure 4 After the vertical stacking of the layers described herein, the vertical stack 501 can be bonded to the complementary metal-oxide-semiconductor (CMOS) wafer 545.

[0081] In some embodiments, CMOS wafer 545 may include a silicon substrate material and transistors suitable for peripheral circuitry. That is, CMOS components may be formed on the silicon substrate material. In some embodiments, an unprocessed silicon layer may be bonded to a vertical stack 501 via an oxide intermediate, and once bonded to the vertical stack 501, the unprocessed silicon layer may be processed to form a CMOS component. In some embodiments, this may be because the process for forming the CMOS component can be performed at a lower temperature (e.g., 250°C) than the temperature used to form the silicon and silicon-germanium layers of the vertical stack.

[0082] like Figure 5 As shown in the example, vertically stacked 501 units can be rotated 180 degrees (e.g., flipped), making... Figure 4 The top silicon-germanium layer (with an exposed surface) becomes a bonding surface, onto which bonding material 540 (e.g., an "adhesive" layer) can be placed and used to bond the vertically stacked 501 to the CMOS wafer 545. Figure 5 In this configuration, both the vertical stack and the CMOS wafer have bonding materials (540 and 542, respectively) on them, and these materials are bonded together to join the vertical stack and the CMOS wafer. However, in some embodiments, the bonding materials may be positioned on the vertical stack or the CMOS wafer prior to bonding. Any suitable bonding material can be used to join the vertical stack and the CMOS wafer.

[0083] Figure 6 This describes another example of a process for stacking and bonding single-crystal silicon to a CMOS wafer according to several embodiments of this disclosure. For example... Figure 5 As illustrated in the embodiments, when the bonding materials are bonded together, a dielectric layer 644 can be formed between the vertical stack 601 and the CMOS wafer 645.

[0084] In some embodiments, such as Figure 6As described, the original substrate can be removed after the vertically stacked 601 is bonded to the CMOS wafer 645 (e.g., Figure 5 Substrate 537 in the middle). Figure 6 In one embodiment, the original substrate has been removed and a hard mask material 646 has been formed in its place. This can be used during the patterning of vertically stacked layers.

[0085] exist Figure 7 The image shows an example of a memory cell array that can be produced by patterned, vertically stacked layers. However, vertically stacked structures formed from single-crystal silicon and silicon-germanium are extremely versatile and can therefore be used to fabricate many different types of vertical memory cell arrays.

[0086] Figure 7 This describes example patterned vertical memory arrays formed from stacks of single-crystal silicon bonded to a CMOS wafer, according to several embodiments of the present disclosure. For example... Figure 7 As described, the memory array includes a CMOS wafer 745 bonded to a vertically stacked 701 via a bonding material 744, which has now been patterned to form a plurality of stacked memory cells. Each memory cell may be, for example, a horizontally oriented memory node (e.g., a capacitor cell) already formed by a semiconductor manufacturing process, wherein a first electrode 761 (e.g., a bottom electrode to be coupled to the source / drain region of a horizontal access device) and a second electrode 756 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) are separated by a cell dielectric 763 and may have conductive lines 777. However, the embodiments are not limited to the components shown in this example.

[0087] Conductive lines 777 (e.g., digital lines or word lines) may be formed from a conductive material provided within an interlayer dielectric (ILD) layer 778. In the illustrated structure, when a mask is removed, for example via an inner liner process (e.g., Figure 6 When the top layer having conductive lines 777 and ILD 778 is exposed after step 646), the top layer may be formed on top of the top monocrystalline silicon layer 730. The monocrystalline silicon layer 730 may form the channel region of the memory cell. The silicon-germanium layer or a portion thereof may be selectively removed to form a structure, for example, conductive lines 777, a first ILD layer 778, and a second ILD layer 779. Figure 7 The memory cell array described herein also demonstrates, as previously discussed... Figure 2B The main contact area 795 (e.g., conductive main contact area 295) and the mask layer 748 which can be used as part of the memory array formation process.

[0088] The memory cell array may also have source / drain regions formed therein. For example, a doped layer may be used to form the source / drain regions of the access transistors.

[0089] In some embodiments, the vertically stacked memory array can be bonded to a CMOS wafer after the memory cells are formed. This can be beneficial because the two components can be formed separately and then combined, which can allow for more specialized manufacturing processes that can be focused on either the CMOS wafer formation process or the memory array formation process.

[0090] As Figure 7 As illustrated in embodiments of FIG. 7, the bonding material can form a dielectric layer 744 between the vertically stacked 701 and the CMOS 745 when bonded together.

[0091] Figure 8 is a block diagram of a device in the form of a computing system including a memory device, in accordance with a number of embodiments of the present disclosure. Figure 8 is a block diagram of a device in the form of a computing system 800 including a memory device 803, in accordance with a number of embodiments of the present disclosure. As used herein, the memory device 803, the memory array 810, and / or the host 802 may, for example, also be considered “devices” respectively. According to embodiments, the memory device 802 can include at least one memory array 810 having a three-node access device of vertical three-dimensional (3D) memory, as has been described herein.

[0092] In this example, the system 800 includes a host 802 coupled to the memory device 803 via an interface 804. The computing system 800 can be a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, a memory card reader, or an Internet of Things (IoT)-enabled device, among various other types of systems. The host 802 can include one or more processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing the memory 803. The system 800 can include separate integrated circuits, or both the host 802 and the memory device 803 can be on the same integrated circuit. For example, the host 802 can be a system controller of a memory system that includes multiple memory devices 803, where the system controller 805 provides access to the respective memory devices 803 by another processing resource, such as a central processing unit (CPU).

[0093] In Figure 8In the example shown in FIG. 8, the host 802 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., from memory device 803 via controller 805). The OS and / or various applications can be loaded from memory device 803 by providing access commands from host 802 to memory device 803 to access data comprising the OS and / or various applications. Host 802 can also access the data utilized by the OS and / or various applications by providing access commands to memory device 803 to retrieve the data for execution of the OS and / or various applications.

[0094] For clarity, system 800 has been simplified to focus on features with particular relevance to the disclosure. Memory array 810 can be a DRAM array, a SRAM array, a STT RAM array, a PCRAM array, a TRAM array, a RRAM array, a NAND flash array, and / or a NOR flash array, including at least one three-node access device of three-dimensional (3D) memory. For example, memory array 810 can be an unmasked DL 4F2 array, such as a 3D-DRAM memory array. Array 810 can include memory cells arranged in rows coupled by word lines (which can be referred to herein as access lines or select lines) and columns coupled by digit lines (which can be referred to herein as sense lines or data lines). Although a single array 810 is shown in FIG. 8, embodiments are not so limited. For example, memory device 803 can include a number of arrays 810 (e.g., an array of DRAM cells).

[0095] Memory device 803 includes address circuitry 806 to latch address signals provided by interface 804. The interface can include a physical interface employing a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus). Such a protocol can be custom or proprietary, or interface 804 can utilize a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, etc. Row decoder 808 and column decoder 812 receive and decode address signals to access memory array 810. Data can be read from memory array 810 by sensing voltage and / or current changes on the sense lines using sense circuitry 811. Sense circuitry 811 can include, for example, a sense amplifier that can read and latch a page (e.g., a row) of data from memory array 810. I / O circuitry 807 can be used for bidirectional data communication between memory device 803 and host 802 over interface 804. Read / write circuitry 813 is used to write data to and read data from memory array 810. As an example, circuitry 813 can include various drivers, latches, etc.

[0096] The control circuitry 805 decodes signals provided by the host 802. The signals can be commands provided through the host 802. These signals can include chip enable signals, write enable signals, and address latch signals used to control the operations performed on the memory array 810, including data read, data write, and data erase operations. In various embodiments, the control circuitry 805 is responsible for executing instructions from the host 802. The control circuitry 805 can comprise a state machine, a sequencer, and / or some other type of control circuitry, which can be implemented in hardware, firmware, or software, or any combination of the three. In some instances, the host 802 can be a controller external to the memory device 803. For example, the host 802 can be a memory controller coupled to a processing resource of a computing device.

[0097] The term semiconductor may, for example, refer to a material, wafer, or substrate, and includes any base semiconductor structure. A "semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon on a base semiconductor structure, as well as other semiconductor structures. Furthermore, when reference is made to a semiconductor, previous processing steps can have been utilized to form regions / junctions in the base semiconductor structure, and the term semiconductor can include the underlying material containing these regions / junctions.

[0098] Transistors formed using the processes described herein can have several benefits. For example, the transistors will have better performance in I-on and I-off, drivability, and leakage current. Polysilicon leaks due to the robustness of the polysilicon material, but the single-crystal layer does not have robustness, and thus, current does not easily leak through the single-crystal material. In some implementations, embodiments of the disclosure can improve I-off, for example, by three orders of magnitude or better, compared to previous devices.

[0099] The drawings herein follow a numbering convention in which the first numeral or numerals correspond to the figure number, and a remaining numeral identifies an element or component within the figure. Similar (e.g., identical) elements or components between different figures can be identified by the use of similar digits. As should be appreciated, elements shown in the various embodiments herein can be added, exchanged, and / or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportions and relative scales of the various elements illustrated in the figures can be exaggerated, provided that the specifics are intended to aid in the description of the embodiments of the disclosure and are not meant to be limiting as such.

[0100] As used herein, "a number of" or "an amount of" something can refer to one or more of such things. For example, a number of or an amount of memory units can refer to one or more memory units. A plurality of something intends two or more. As used herein, a plurality of actions performed simultaneously refers to actions that at least partially overlap in a particular time period. As used herein, the term "coupled" can include electrically coupled, directly coupled and / or directly connected (e.g., by direct physical contact) without intermediate elements, or indirectly coupled and / or connected with intermediate elements, or wirelessly coupled. The term coupled can further include two or more elements that cooperate or interact with each other (e.g., as in a cause an effect relationship). An element coupled between two elements can be between and coupled to each of the two elements.

[0101] It should be appreciated that the term vertical accounts for variations from "exact" vertical due to normal manufacturing, measurement, and / or assembly variations, and one of ordinary skill in the art would know the implications of the term "vertical." For example, vertical can correspond to the z-direction. As used herein, when a particular element is "adjacent to" another element, the particular element can cover the other element, can be above or lateral to the other element, and / or can be in direct physical contact with the other element. For example, lateral can refer to a horizontal direction (e.g., y-direction or x-direction) that can be perpendicular to the z-direction.

[0102] While specific embodiments have been illustrated and described in this specification, the general principles thereof can be applied to other arrangements, which will be readily apparent to those of ordinary skill in the art. The disclosure is intended to encompass all such arrangements. It should be appreciated that the above description is illustrative and not restrictive. The scope of the various embodiments of the present disclosure will be determined by the appended claims and equivalents thereof.

Claims

1. A method for forming an array of formed vertical stacks of layers for memory cells, comprising: forming a monocrystalline silicon germanium layer (430; 530; 630) onto a surface of a silicon substrate (437; epitaxially growing the silicon germanium to form a thicker silicon germanium layer; forming a monocrystalline silicon layer (432; 532; 632) onto a surface of the thicker silicon germanium (430; 530; 630); epitaxially growing monocrystalline silicon to form a thicker monocrystalline silicon layer; and in a repeating stack, forming several additional monocrystalline silicon germanium layers (430; 530; 630) and monocrystalline silicon layers (432; 532; 632) to form a vertical stack of alternating monocrystalline silicon layers and monocrystalline silicon germanium layers.

2. The method of claim 1, further comprising: removing the silicon substrate from the vertical stack of alternating monocrystalline silicon layers and monocrystalline silicon germanium layers; wherein the vertical stack of alternating monocrystalline silicon layers and monocrystalline silicon germanium layers has two monocrystalline silicon germanium layers with exposed surfaces; and applying a hard mask material (646) to one of the exposed surfaces of the vertical stack of alternating monocrystalline silicon layers and monocrystalline silicon germanium layers.

3. The method of claim 2, further comprising: applying a bonding material to another exposed surface of the vertical stack of alternating monocrystalline silicon layers and monocrystalline silicon germanium layers; and bonding the bonding material to a surface of a CMOS wafer.

4. The method of claim 2, further comprising: applying a bonding material to another exposed surface of the vertical stack of alternating monocrystalline silicon layers and monocrystalline silicon germanium layers; and bonding the bonding material to a surface of a bonding material layer of a complementary metal oxide semiconductor (CMOS) wafer.

5. The method of claim 1, further comprising forming the vertical stack separate from a complementary metal oxide semiconductor (CMOS) wafer and separately bonding the vertical stack to the CMOS wafer.

6. A device formed by bonding a first substrate to a second substrate, the device comprising: a number of CMOS components formed on the first substrate; the second substrate attached to the first substrate, wherein the second substrate comprises: a first monocrystalline silicon germanium layer (430; 530; 630) formed on a surface of the first substrate; a first monocrystalline silicon layer (432; 532; 632) formed on a surface of the monocrystalline silicon germanium; and a repeating stack of monocrystalline silicon germanium layers and monocrystalline silicon layers forming a vertical stack of alternating monocrystalline silicon layers (432; 532; 632) and monocrystalline silicon germanium layers (430; 530; 630).

7. The device of claim 6, further comprising: a bonding material layer (542) providing the attachment between the surface of the first substrate and the first monocrystalline silicon germanium layer, wherein the bonding material layer is a dielectric material.

8. The device of claim 6, further comprising: at least one layer of the vertical stack having word lines defined therein; and at least one layer of the vertical stack having digit lines defined therein. ​ 9. The device of claim 6, wherein the vertical stack is electrically coupled in an open digit line architecture.

10. The device of claim 6, wherein the vertical stack is electrically coupled in a folded digit line architecture.

11. A method for forming an array of memory cells in a vertical stack of layers, comprising: forming a monocrystalline silicon germanium layer (430; 530; 630) onto a surface of a silicon substrate (437; 537); forming a monocrystalline silicon layer (432; 532; 632) onto a surface of the monocrystalline silicon germanium; and in a repeating superposition, forming a number of additional monocrystalline silicon germanium layers and monocrystalline silicon layers to form a vertical stack of alternating monocrystalline silicon layers (432; 532; 632) and monocrystalline silicon germanium layers (430; 530; 630).

12. The method of claim 11, further comprising: bonding a surface of the vertical stack to a substrate having a number of CMOS components formed thereon, wherein the bonding of the surface of the vertical stack to the substrate having the number of CMOS components formed thereon is achieved at a temperature range that is lower than a temperature range used to form at least one of the layers of the vertical stack; and wherein the temperature range used to form the layers of the vertical stack is 600 degrees Celsius (°C) to 1100 °C.

13. The method of claim 11, further comprising: performing a patterning process of one or more layers of the vertical stack to create memory cells within the vertical stack.

14. The method of claim 11, further comprising: performing a patterning process of one or more layers of the vertical stack at a temperature range that is lower than a temperature range used to form at least one of the layers.

15. The method of claim 11, further comprising: patterning at least one layer of the vertical stack to define word lines therein; and patterning at least one layer of the vertical stack to define digit lines therein.

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