Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of increasing a capacitor capacity. The semiconductor storage device of the embodiments includes a memory cell array including a plurality of memory cells, and a control circuit that controls an operation of the memory cells and includes a first capacitor. The first capacitor includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, and including a first semiconductor region of a p-type, a second semiconductor region of an n-type provided between the first surface and the first semiconductor region, and a third semiconductor region of a p-type provided between the first surface and the second semiconductor region and electrically connected to the first semiconductor region. The first capacitor also includes a first electrode electrically connected to the second semiconductor region, and a first insulating film provided between the third semiconductor region and the first electrode.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2020-182677 (filed on October 30, 2020). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to semiconductor memory devices. Background Technology

[0004] A semiconductor memory includes: an array of memory cells comprising multiple memory cells capable of storing data; and control circuitry for controlling the operation of the memory cells. The control circuitry includes, for example, various capacitors such as capacitors for stabilizing the voltage and capacitors for charge pumps that boost an input external voltage to generate a higher internal voltage. To improve the characteristics of the semiconductor memory, it is desirable to increase the capacitance of the capacitors. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor storage device capable of increasing the capacitance of a capacitor.

[0006] The semiconductor memory device of the embodiment includes: a memory cell array including a plurality of memory cells; and a control circuit for controlling the operation of the memory cells, and including a first capacitor, the first capacitor including: a semiconductor substrate having a first surface and a second surface facing the first surface, and including a p-type first semiconductor region, an n-type second semiconductor region disposed between the first surface and the first semiconductor region, and a p-type third semiconductor region disposed between the first surface and the second semiconductor region and electrically connected to the first semiconductor region; a first electrode electrically connected to the second semiconductor region; and a first insulating film disposed between the third semiconductor region and the first electrode. Attached Figure Description

[0007] Figure 1 This is a block diagram of a semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is an equivalent circuit diagram of the memory cell array of the semiconductor memory device according to the first embodiment.

[0009] Figure 3 (a) and (b) are schematic cross-sectional views of a portion of the memory cell array of the semiconductor memory device according to the first embodiment.

[0010] Figure 4 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0011] Figure 5 This is a pattern layout diagram of the semiconductor memory device according to the first embodiment.

[0012] Figure 6 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0013] Figure 7 This is a schematic cross-sectional view of a comparative example semiconductor memory device.

[0014] Figure 8 (a) and (b) are explanatory diagrams of the function and effect of the semiconductor memory device according to the first embodiment.

[0015] Figure 9 This is a schematic cross-sectional view of a first modified example of the semiconductor memory device according to the first embodiment.

[0016] Figure 10 This is a pattern layout diagram of a second variation of the semiconductor memory device according to the first embodiment.

[0017] Figure 11 This is a schematic cross-sectional view of a second variation of the semiconductor memory device according to the first embodiment.

[0018] Figure 12 This is a schematic cross-sectional view of the semiconductor memory device according to the second embodiment.

[0019] Figure 13 This is a schematic cross-sectional view of the semiconductor memory device according to the third embodiment.

[0020] Figure 14 This is a pattern layout diagram of a semiconductor memory device according to the third embodiment.

[0021] Figure 15 This is a schematic cross-sectional view of the semiconductor memory device according to the third embodiment.

[0022] Figure 16 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment.

[0023] Figure 17 This is a pattern layout diagram of a semiconductor memory device according to the fourth embodiment.

[0024] Figure 18 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment.

[0025] Figure 19 This is a schematic cross-sectional view of the semiconductor memory device according to the fifth embodiment.

[0026] Figure 20 This is a pattern layout diagram of a semiconductor memory device according to the fifth embodiment.

[0027] Figure 21 This is a schematic cross-sectional view of the semiconductor memory device according to the fifth embodiment.

[0028] Explanation of reference numerals in the attached figures

[0029] 10 Semiconductor substrate

[0030] 11 Semiconductor layer

[0031] 16 Charge storage layers

[0032] 30 p-type region (first semiconductor region)

[0033] 32 First n-well (second semiconductor region)

[0034] 34 First p-well (third semiconductor region)

[0035] 34a First p-well (third semiconductor region)

[0036] 34b First p-well (sixth semiconductor region)

[0037] 38. Second n-type contact region (fourth semiconductor region)

[0038] 44. First n-type region (fifth semiconductor region)

[0039] 46 First capacitor electrode (first electrode)

[0040] 48 First capacitor insulating film (first insulating film)

[0041] 62 Second n-well (Seventh semiconductor region)

[0042] 64 Second p-well (eighth semiconductor region)

[0043] 76 Second capacitor electrode (second electrode)

[0044] 78. Second capacitor insulating film (second insulating film)

[0045] 100 Non-volatile memory (semiconductor memory device)

[0046] 101 memory cell array

[0047] 102-word line driver (control circuit)

[0048] 103-line decoder (control circuit)

[0049] 104. Readout Amplifier (Control Circuit)

[0050] 105-column decoder (control circuit)

[0051] 106 Controller (Control Circuit)

[0052] 107 Charge Pump (Control Circuit)

[0053] 108 Input / Output Circuit (Control Circuit)

[0054] 110 First Capacitor

[0055] 120 Second capacitor

[0056] MC memory unit

[0057] P1 First Page

[0058] P2 Second Page

[0059] V1 First Voltage

[0060] V2 Second Voltage

[0061] WL word line (gate electrode) Detailed Implementation

[0062] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and descriptions of components that have been described once before will sometimes be omitted.

[0063] Additionally, for convenience, the terms "upper" or "lower" are sometimes used in this specification. "Upper" or "lower" are merely terms indicating relative positional relationships within the accompanying drawings, and do not specify positional relationships relative to gravity.

[0064] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor memory device described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectrometry (EDX), and electron energy loss spectrometry (EELS). Furthermore, SIMS can be used, for example, to measure the depth of the semiconductor region constituting the semiconductor memory device. Additionally, measurements of the thickness of the components constituting the semiconductor memory device, the distance between components, etc., can be performed, for example, by transmission electron microscopy (TEM).

[0065] In this specification, when there is n + Type, n-type, n -In the case of type marking, it means that the concentration of n-type impurities is determined by n. + Type, n-type, n - The order of types decreases. Additionally, when there is p... + Type, p type, p - In the case of p-type marking, it means that the concentration of p-type impurities is based on p... + Type, p type, p - The order of the types is reduced. Additionally, sometimes n is... + Type, n-type, n - The type is collectively referred to as type n and is only labeled as type n. Additionally, sometimes p is used... + Type, p type, p - The type is collectively referred to as p-type only.

[0066] (First Implementation)

[0067] The semiconductor memory device of the first embodiment includes a memory cell array comprising a plurality of memory cells and a control circuit for controlling the operation of the memory cells and including a first capacitor. The first capacitor includes: a semiconductor substrate having a first surface and a second surface facing the first surface, and including a p-type first semiconductor region, an n-type second semiconductor region disposed between the first surface and the first semiconductor region, and a p-type third semiconductor region disposed between the first surface and the second semiconductor region and electrically connected to the first semiconductor region; a first electrode electrically connected to the second semiconductor region; and a first insulating film disposed between the third semiconductor region and the first electrode.

[0068] The semiconductor memory device of the first embodiment is a non-volatile memory 100. The non-volatile memory 100 of the first embodiment is a three-dimensional NAND flash memory with a plurality of memory cells arranged in three dimensions. The non-volatile memory 100 is an example of a semiconductor memory device.

[0069] Figure 1 This is a block diagram of a semiconductor memory device according to the first embodiment. Figure 1 This describes the circuit configuration of the non-volatile memory 100 according to the first embodiment. For example... Figure 1 As shown, the non-volatile memory 100 includes a memory cell array 101, a word line driver 102, a row decoder 103, a sense amplifier 104, a column decoder 105, a charge pump 106, an input / output circuit 107, and a controller 108.

[0070] The memory cell array 101 includes multiple memory cells MC. A word line driver 102, a row decoder 103, a sense amplifier 104, a column decoder 105, a charge pump 106, an input / output circuit 107, and a controller 108 control the operation of the memory cells MC. The word line driver 102, row decoder 103, sense amplifier 104, column decoder 105, charge pump 106, input / output circuit 107, and controller 108 are an example of the control circuitry.

[0071] Figure 2 This is an equivalent circuit diagram of the memory cell array of the semiconductor memory device according to the first embodiment. Figure 2 The wiring structure within the memory cell array 101 is schematically shown. The memory cell array 101 of the first embodiment has a three-dimensional structure in which a plurality of memory cells MC are arranged in a three-dimensional manner.

[0072] Below, the y-direction intersects the x-direction. The z-direction intersects both the x-direction and the y-direction. For example, the x-direction is orthogonal to the y-direction. For example, the z-direction is orthogonal to both the x-direction and the y-direction.

[0073] like Figure 2 As shown, the memory cell array 101 includes multiple memory cells MC, source select transistor SST, drain select transistor SDT, multiple word lines WL, multiple bit lines BL, common source line CSL, source select gate line SGS, and multiple drain select gate lines SGD.

[0074] Multiple memory cells MC are connected in series in the z-direction. These multiple memory cells MC are connected between the source selection transistor SST and the drain selection transistor SDT.

[0075] Memory cells (MC) may have, for example, a MONOS (Metal Oxide Nitride Oxide Semiconductor) structure with an insulating charge storage layer. The threshold voltage of the transistor in the memory cell MC varies depending on the amount of charge stored in the charge storage layer. Changes in the threshold voltage of the transistor result in changes in the transistor's on-current. For example, if a state with a high threshold voltage and low on-current is defined as data "0", and a state with a low threshold voltage and high on-current is defined as data "1", then the memory cell MC can store one bit of data, representing both "0" and "1".

[0076] The word line WL functions as the gate electrode of the transistor in the memory cell MC. The word line WL is used to control the gate voltage of the memory cell MC. The word line WL is an example of a gate electrode.

[0077] The source-select transistor SST is electrically connected to the common-source line CSL. The source-select transistor SST is controlled by the voltage applied to the source-select gate line SGS.

[0078] The drain-select transistor SDT is connected to BL. The drain-select transistor SDT is controlled by the voltage applied to the drain-select gate line SGD.

[0079] Multiple word lines WL are electrically connected to word line driver 102. Multiple bit lines BL are electrically connected to sense amplifier 104.

[0080] The row decoder 103 has the function of selecting word lines WL according to the input row address signal. The word line driver 102 has the function of applying a specified gate voltage to the word lines WL selected by the row decoder 103.

[0081] The column decoder 105 has the function of selecting a bit line BL according to the input column address signal. The sense amplifier 104 has the function of applying a predetermined voltage to the bit line BL selected by the column decoder 105. In addition, it has the function of detecting and amplifying the current or voltage flowing through the selected bit line BL.

[0082] The charge pump 106 has the function of boosting a power supply voltage input from an external source into the non-volatile memory 100 to generate a higher internal voltage. The charge pump 106 is a boost circuit. For example, when boosting the input power supply voltage and writing data to the memory cell MC, a program voltage is generated applied to the word line WL. The charge pump 106 includes a capacitor (not shown).

[0083] The input / output circuit 107 has the function of transmitting and receiving input / output signals (I / O) between the input / output circuit 100 and the external environment via I / O terminals. The input / output circuit 107 includes capacitors for voltage stabilization.

[0084] The controller 108 has the functions of controlling word line driver 102, row decoder 103, sense amplifier 104, column decoder 105, charge pump 106, input / output circuit 107, and other circuits not shown.

[0085] The circuitry of word line driver 102, row decoder 103, sense amplifier 104, column decoder 105, charge pump 106, input / output circuit 107, and controller 108, etc., is, for example, composed of... Figure 1 as well as Figure 2 The transistors and wiring layers using a semiconductor substrate are not shown in the figure.

[0086] For example, in Figure 2In this process, when reading data stored in memory cell MC, a read voltage is applied to the word line WL connected to memory cell MC. By turning on the transistor in memory cell MC, current flows between the common source line CSL and the bit line BL. Based on the current flowing from the common source line CSL to the bit line BL, the data stored in memory cell MC is determined.

[0087] For example, the current flowing through the bit line BL is amplified by the sense amplifier 104, and the data stored in the memory cell MC is determined by the controller 108. Alternatively, the voltage change of the bit line BL is amplified by the sense amplifier 104, and the data stored in the memory cell MC is determined by the controller 108.

[0088] exist Figure 2 The example illustrates the case where there are six memory cells MC connected in series and two bit lines, but the number of memory cells MC connected in series and the number of bit lines are not limited to six or two.

[0089] Figure 3 of (a), Figure 3 (b) is a schematic cross-sectional view of a portion of the memory cell array of the semiconductor memory device according to the first embodiment. Figure 3 (a) is the yz section of the memory cell array 101. Figure 3 (a) is Figure 3 BB' section of (b). Figure 3 (b) is the xy section of the memory cell array 101. Figure 3 (b) is Figure 3 AA' section of (a).

[0090] exist Figure 3 (a) and Figure 3 In (b), the area enclosed by the dashed line is a memory cell MC.

[0091] The memory cell array 101 includes a semiconductor layer 11, an interlayer insulating layer 12, a tunnel insulating film 14, a charge storage layer 16, a barrier insulating film 18, a core insulating layer 20, and a word line WL. The word line WL is an example of a gate electrode.

[0092] A charge storage layer 16 is disposed between the semiconductor layer 11 and the word line WL. A tunnel insulating film 14 is disposed between the semiconductor layer 11 and the charge storage layer 16. A barrier insulating film 18 is disposed between the charge storage layer 16 and the word line WL.

[0093] Semiconductor layer 11 functions as the channel of the transistor in memory cell MC. Charge storage layer 16 functions as the charge storage layer. Word line WL functions as the gate electrode of the transistor in memory cell MC.

[0094] Semiconductor layer 11 is, for example, polysilicon. Interlayer insulating layer 12 is, for example, silicon oxide. Tunnel insulating film 14 is, for example, silicon oxide. Charge storage layer 16 is, for example, silicon nitride. Barrier insulating film 18 is, for example, aluminum oxide. Core insulating layer 20 is, for example, silicon oxide. Word line WL is, for example, tungsten (W).

[0095] Figure 4 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 5 This is a pattern layout diagram of the semiconductor memory device according to the first embodiment. Figure 6 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 4 yes Figure 5 The CC' section. Figure 6 yes Figure 5 DD' section.

[0096] Figure 4 , Figure 5 as well as Figure 6 This is a schematic diagram of the first capacitor 110 of the non-volatile memory 100. The first capacitor 110 is, for example, a capacitor included in the charge pump 106.

[0097] The first capacitor 110 includes a semiconductor substrate 10, a component separation region 45, a first capacitor electrode 46, a first capacitor insulating film 48, an interlayer insulating layer 49, contact plugs 50a, 50b, 50c, 50d, and 50e, a first wiring layer 52a, and a second wiring layer 52b. The semiconductor substrate 10 includes a p-type region 30, a first n-well 32, a first p-well 34, a first n-type contact region 36, a second n-type contact region 38, a first p-type contact region 40, a second p-type contact region 42, and a first n-type region 44.

[0098] p-type region 30 is an example of a first semiconductor region. First n-well 32 is an example of a second semiconductor region. First p-well 34 is an example of a third semiconductor region. Second n-type contact region 38 is an example of a fourth semiconductor region. First n-type region 44 is an example of a fifth semiconductor region. First capacitor electrode 46 is an example of a first electrode. First capacitor insulating film 48 is an example of a first insulating film.

[0099] The semiconductor substrate 10 is, for example, a single-crystal semiconductor. The semiconductor substrate 10 is, for example, single-crystal silicon.

[0100] The semiconductor substrate 10 has a first surface P1 and a second surface P2. The second surface P2 is opposite to the first surface P1. The first surface P1 is the surface of the semiconductor substrate 10. The second surface P2 is the back surface of the semiconductor substrate 10.

[0101] p-type region 30 is p - The semiconductor is a p-type region 30 containing p-type impurities. The p-type impurity is, for example, boron (B). The maximum impurity concentration of the p-type impurity in the p-type region 30 is, for example, 1 × 10⁻⁶. 14 cm -3 Above and 1×10 15 cm -3 the following.

[0102] The first n-well 32 is located between the first surface P1 and the p-type region 30. The first n-well 32 is, for example, surrounded by the p-type region 30.

[0103] The first n-well 32 is an n-type semiconductor. For example, the first n-well 32 is an n-type single-crystal silicon.

[0104] The first n-well 32 contains n-type impurities. An example of an n-type impurity is phosphorus (P). The maximum impurity concentration of the n-type impurity in the first n-well 32 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 18 cm -3 Below. The depth of the first n-well 32 ( Figure 4 d1 in the example is above 2μm and below 4μm.

[0105] The first p-well 34 is disposed between the first surface P1 and the first n-well 32. The first p-well 34 is, for example, surrounded by the first n-well 32. The first p-well 34 is a p-type semiconductor. The first p-well 34 is, for example, a p-type single-crystal silicon.

[0106] The first p-well 34 is electrically connected to the p-type region 30.

[0107] The first p-well 34 includes p-type impurities. The p-type impurity is, for example, boron (B). The maximum impurity concentration of the p-type impurity in the first p-well 34 is, for example, higher than the maximum impurity concentration of the p-type impurity in the p-type region 30. The maximum impurity concentration of the p-type impurity in the first p-well 34 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 18 cm -3 the following.

[0108] The depth of the first p-well 34 ( Figure 4 d2) is deeper than the first n-well 32. Figure 4 The depth of d1 in the first p-well 34 is shallow. Figure 4 d2 in the example is above 1 μm and below 3 μm.

[0109] The first n-type contact region 36 is located between the first surface P1 and the first n-well 32. The first n-type contact region 36 is, for example, surrounded by the first n-well 32. The first n-type contact region 36 is n +Type n semiconductor. The first n-type contact region 36 is, for example, n... + Type of monocrystalline silicon.

[0110] The first n-type contact region 36 includes n-type impurities. The n-type impurities are, for example, arsenic (As) or phosphorus (P). The maximum impurity concentration of the n-type impurities in the first n-type contact region 36 is, for example, higher than the maximum impurity concentration of the n-type impurities in the first n-well 32. The maximum impurity concentration of the n-type impurities in the first n-type contact region 36 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 The following is the depth of the first n-type contact region 36 ( Figure 4 d3) is deeper than the first n-well 32. Figure 4 d1) is shallow.

[0111] The second n-type contact region 38 is disposed between the first surface P1 and the first p-well 34. The second n-type contact region 38 is, for example, surrounded by the first p-well 34. The second n-type contact region 38 is disposed on the side of the first p-well 34 at the end of the first capacitor electrode 46. The second n-type contact region 38 is, for example, disposed in the first p-well 34 on both sides with the first capacitor electrode 46 in the middle.

[0112] The second type n contact region 38 is n + Type n semiconductor. The second n-type contact region 38 is, for example, n... + Type of monocrystalline silicon.

[0113] The second n-type contact region 38 contains n-type impurities. The n-type impurities are, for example, arsenic (As) or phosphorus (P). The maximum impurity concentration of the n-type impurities in the second n-type contact region 38 is, for example, higher than the maximum impurity concentration of the n-type impurities in the first n-well 32. The maximum impurity concentration of the n-type impurities in the second n-type contact region 38 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 the following.

[0114] The depth of the second n-type contact region 38 ( Figure 4 d3) is deeper than the first p-well 34. Figure 4 The d2 in the middle is shallow.

[0115] The second n-type contact region 38 is electrically connected to the first p-well 34 and the p-type region 30.

[0116] The first p-type contact area 40 is located between the first surface P1 and the p-type area 30. The first p-type contact area 40 is, for example, surrounded by the p-type area 30. The first p-type contact area 40 is p +p-type semiconductor. The first p-type contact region 40 is, for example, p... + Type of monocrystalline silicon.

[0117] The first p-type contact region 40 contains p-type impurities. The p-type impurity is, for example, boron (B). The maximum impurity concentration of the p-type impurity in the first p-type contact region 40 is higher than the maximum impurity concentration of the p-type impurity in the p-type region 30.

[0118] The first p-type contact area 40 is electrically connected to the second n-type contact area 38 and the second p-type contact area 42.

[0119] The second p-type contact region 42 is located between the first surface P1 and the first p-well 34. The second p-type contact region 42 is, for example, surrounded by the first p-well 34. The second p-type contact region 42 is p + Type 42 semiconductor. The second p-type contact region 42 is, for example, p... + Type of monocrystalline silicon.

[0120] The second p-type contact region 42 contains p-type impurities. The p-type impurity is, for example, boron (B). The maximum impurity concentration of the p-type impurity in the second p-type contact region 42 is higher than the maximum impurity concentration of the p-type impurity in the first p-well 34.

[0121] The second p-type contact area 42 is electrically connected to the second n-type contact area 38 and the first p-type contact area 40.

[0122] The first n-type region 44 is located between the first surface P1 and the first p-well 34. The first n-type region 44 is, for example, surrounded by the first p-well 34. The first n-type region 44 is located between the first capacitor insulating film 48 and the first p-well 34. The first n-type region 44 is in contact with the second n-type contact region 38. The first n-type region 44 is, for example, in contact with the first capacitor insulating film 48.

[0123] The first n-type region 44 is an n-type semiconductor. For example, the first n-type region 44 is n-type single-crystal silicon.

[0124] The first n-type region 44 contains n-type impurities. The n-type impurities are, for example, arsenic (As) or phosphorus (P). The maximum impurity concentration of the n-type impurities in the first n-type region 44 is, for example, lower than the maximum impurity concentration of the n-type impurities in the second n-type contact region 38. The depth of the first n-type region 44 ( Figure 4 d4 in the middle, for example, is deeper than the second n-type contact region 38. Figure 4 d3) in the shallow.

[0125] The component separation region 45 is disposed on the first surface P1 side of the semiconductor substrate 10. For example, the component separation region 45 is disposed between the first n-type contact region 36 and the second n-type contact region 38. For example, the component separation region 45 is disposed between the second n-type contact region 38 and the second p-type contact region 42. For example, the component separation region 45 is disposed between the second p-type contact region 42 and the first p-type contact region 40.

[0126] The component separation region 45 is an insulator. The component separation region 45 may contain, for example, silicon oxide.

[0127] The first capacitor electrode 46 is disposed on the first surface P1 side of the semiconductor substrate 10. The first capacitor electrode 46 is disposed on the first p-well 34. The first capacitor electrode 46 is disposed on the first n-type region 44.

[0128] The first capacitor electrode 46 is a conductor. The first capacitor electrode 46 is, for example, a semiconductor, a metal-semiconductor compound, or a metal. The first capacitor electrode 46 is, for example, polycrystalline silicon containing n-type or p-type impurities.

[0129] The first capacitor electrode 46 is electrically connected to the first n-well 32 and the first n-type contact region 36.

[0130] The first capacitor insulating film 48 is disposed between the first p-well 34 and the first capacitor electrode 46. For example, the first capacitor insulating film 48 is disposed between the first n-type region 44 and the first capacitor electrode 46.

[0131] The first capacitor insulating film 48 is an insulator. The first capacitor insulating film 48 is, for example, an oxide, a nitride, or a nitrogen oxide. The first capacitor insulating film 48 may contain, for example, silicon oxide.

[0132] The thickness of the insulating film 48 of the first capacitor is, for example, 2 nm or more and 45 nm or less. The thickness of the insulating film 48 of the first capacitor is, for example, 30 nm or more and 45 nm or less.

[0133] An interlayer insulating layer 49 is disposed on the first surface P1 side of the semiconductor substrate 10. The interlayer insulating layer 49 is disposed on the first n-type contact region 36, the second n-type contact region 38, the first p-type contact region 40, the second p-type contact region 42, the component separation region 45, and the first capacitor electrode 46.

[0134] Interlayer insulating layer 49 is an insulator. Interlayer insulating layer 49 is, for example, an oxide, a nitride, or a oxynitride. Interlayer insulating layer 49 may contain, for example, silicon oxide.

[0135] Contact plugs 50a, 50b, 50c, 50d, and 50e are disposed within the interlayer insulating layer 49. Contact plugs 50a, 50b, 50c, 50d, and 50e are conductive. Contact plugs 50a, 50b, 50c, 50d, and 50e are, for example, metals.

[0136] Contact plug 50a is connected to the first n-type contact area 36. Contact plug 50b is connected to the first capacitor electrode 46. Contact plug 50c is connected to the second n-type contact area 38. Contact plug 50d is connected to the second p-type contact area 42. Contact plug 50e is connected to the first p-type contact area 40.

[0137] The first wiring layer 52a and the second wiring layer 52b are disposed within the interlayer insulating layer 49. The first wiring layer 52a and the second wiring layer 52b are conductive materials. For example, the first wiring layer 52a and the second wiring layer 52b are metals.

[0138] The first wiring layer 52a is connected to contact plugs 50a and 50b. The first n-well 32 is electrically connected to the first capacitor electrode 46 using the first wiring layer 52a, contact plugs 50a and 50b.

[0139] A first voltage V1 is applied to the first wiring layer 52a. A first voltage V1 is applied to the first n-well 32 and the first capacitor electrode 46.

[0140] The first voltage V1 is, for example, the program voltage Vprog applied to the gate electrode of the memory cell MC when reading data stored in the memory cell MC. The program voltage Vprog is, for example, 20V or more and 30V or less.

[0141] The first wiring layer 52a is electrically connected, for example, to the word line WL of the memory cell array 101. The first wiring layer 52a is electrically connected to the word line WL, for example, via the row decoder 103 and the word line driver 102. The word line WL is an example of the gate electrode of the memory cell MC.

[0142] The first capacitor electrode 46 is electrically connected to the first wiring layer 52a. Therefore, the first capacitor electrode 46 is electrically connected to the word line WL.

[0143] The second wiring layer 52b is connected to contact plugs 50c, 50d, and 50e. The second n-type contact region 38, the first p-well 34, and the p-type region 30 are electrically connected using the second wiring layer 52b, contact plugs 50c, 50d, and 50e.

[0144] A second voltage V2 is applied to the second wiring layer 52b. The second voltage V2 is applied to the second n-type contact region 38, the first p-well 34, and the p-type region 30.

[0145] The first voltage V1 is higher than the second voltage V2. The second voltage V2 is, for example, 0V. The second wiring layer 52b is, for example, grounded. The second wiring layer 52b is, for example, fixed to the ground potential.

[0146] Next, the function and effects of the semiconductor memory device according to the first embodiment will be explained.

[0147] A semiconductor memory comprises an array of memory cells, each containing multiple memory cells capable of storing data, and control circuitry that controls the operation of the memory cells. The control circuitry includes various capacitors, such as capacitors for voltage stabilization and capacitors for charge pumps that boost an external input voltage to generate a higher internal voltage. To improve the characteristics of the semiconductor memory, it is desirable to increase the capacitance of the capacitors.

[0148] Figure 7 This is a schematic cross-sectional view of a comparative example semiconductor memory device. Figure 7 Is with Figure 4 The corresponding cross-sectional view. Figure 7 This is a cross-sectional view of capacitor 910.

[0149] The capacitor 910 differs from the first capacitor 110 of the first embodiment in that it does not contain the first n-well 32.

[0150] The capacitor 910 includes a semiconductor substrate 10, a component separation region 45, a first capacitor electrode 46, a first capacitor insulating film 48, an interlayer insulating layer 49, contact plugs 50b, 50c, 50d, and 50e, a first wiring layer 52a, and a second wiring layer 52b. The semiconductor substrate 10 includes a p-type region 30, a first p-well 34, a second n-type contact region 38, a first p-type contact region 40, a second p-type contact region 42, and a first n-type region 44.

[0151] The first wiring layer 52a is connected to the contact plug 50b. A first voltage V1 is applied to the first wiring layer 52a. A first voltage V1 is also applied to the first capacitor electrode 46.

[0152] The second wiring layer 52b is connected to contact plugs 50c, 50d, and 50e. The second n-type contact region 38, the first p-well 34, and the p-type region 30 are electrically connected using the second wiring layer 52b, contact plugs 50c, 50d, and 50e.

[0153] A second voltage V2 is applied to the second wiring layer 52b. The second voltage V2 is applied to the second n-type contact region 38, the first p-well 34, and the p-type region 30.

[0154] The first voltage V1 is higher than the second voltage V2. The second voltage V2 is, for example, 0V. The second wiring layer 52b is, for example, grounded. The second wiring layer 52b is, for example, fixed to the ground potential.

[0155] Figure 8 This is an explanatory diagram illustrating the function and effects of the semiconductor memory device according to the first embodiment. Figure 8 (a) is the equivalent circuit diagram of capacitor 910 in the comparative example. Figure 8 (b) is the equivalent circuit diagram of the first capacitor 110 in the first embodiment.

[0156] The capacitor 910 of the comparative example, as a capacitor capacitor, has an insulating film capacitance Cox of a capacitor composed of a first capacitor electrode 46, a first capacitor insulating film 48, and a first n-type region 44.

[0157] On the other hand, the first capacitor 110 of the first embodiment, as a capacitor capacitor, has, in addition to the insulating film capacitor Cox, a junction capacitance Cnwell / pwell between the first n-well 32 and the first p-well 34, and a junction capacitance Cnwell / psub between the first n-well 32 and the p-type region 30.

[0158] Therefore, compared to capacitor 910, the capacitance of the first capacitor 110 increases by the amount of capacitance of junction capacitance Cnwell / pwell and junction capacitance Cnwell / psub. Thus, according to the first embodiment of the non-volatile memory 100, the capacitance can be increased compared to the comparative example.

[0159] The first capacitor 110 has a first n-type region 44 between the first p-well 34 and the first capacitor insulating film 48. By having the first n-type region 44, the insulating film capacitance Cox is stable compared to the case without the first n-type region 44.

[0160] By having the first n-type region 44, the reversal voltage of the first p-well 34 is reduced when the first voltage V1 is applied to the first capacitor electrode 46. Therefore, for example, even if the first voltage V1 varies, the capacitance in the strongly reversed state can be stably utilized, and the insulating film capacitance Cox is stable.

[0161] exist Figure 4The example described uses the case where a contact plug 50c is provided only on the second n-type contact region 38 at one end of the first capacitor electrode 46. However, a contact plug 50c may also be provided on the second n-type contact region 38 at the other end of the first capacitor electrode 46 and connected to the second wiring layer 52b.

[0162] (First variation)

[0163] Figure 9 This is a schematic cross-sectional view of a first modified example of the semiconductor memory device according to the first embodiment. Figure 9 Is with Figure 4 The corresponding cross-sectional view.

[0164] The first capacitor 110 of the first modification differs from the first capacitor 110 of the first embodiment in that it does not include the first n-type region 44. Like the first capacitor 110 of the first embodiment, the first capacitor 110 of the first modification has an increased capacitance compared to the comparative example.

[0165] (Second variation)

[0166] Figure 10 This is a pattern layout diagram of a second variation of the semiconductor memory device according to the first embodiment. Figure 10 Is with Figure 5 The corresponding pattern layout diagram. Figure 11 This is a schematic cross-sectional view of a second variation of the semiconductor memory device according to the first embodiment. Figure 11 yes Figure 10 The EE' section.

[0167] The first capacitor 110 of the second modification differs from the first capacitor 110 of the first embodiment in that the first capacitor electrode 46 is connected directly above the contact plug 50b and the component separation region 45. Like the first capacitor 110 of the first embodiment, the first capacitor 110 of the second modification has a higher capacitance compared to the comparative example.

[0168] According to the semiconductor memory device of the first embodiment, the capacitance of the capacitor can be increased.

[0169] (Second Implementation)

[0170] The semiconductor memory device of the second embodiment differs from that of the semiconductor memory device of the first embodiment in that the control circuit further includes a second capacitor. The second capacitor includes: a semiconductor substrate comprising an n-type seventh semiconductor region disposed between the first surface and the first semiconductor region and separated from the second semiconductor region, and a p-type eighth semiconductor region disposed between the first surface and the seventh semiconductor region and electrically connected to the first semiconductor region; a second electrode electrically connected to the seventh semiconductor region; and a second insulating film disposed between the eighth semiconductor region and the second electrode, the film thickness of which is thinner than that of the first insulating film. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0171] The semiconductor memory device of the second embodiment is a non-volatile memory 200. The non-volatile memory 200 of the second embodiment is a three-dimensional NAND flash memory with multiple memory cells arranged in three dimensions. The non-volatile memory 200 is an example of a semiconductor memory device.

[0172] Figure 12 This is a schematic cross-sectional view of the semiconductor memory device according to the second embodiment. Figure 12 Is with Figure 4 The corresponding schematic cross-sectional view. The non-volatile memory 200 includes a first capacitor 110 and a second capacitor 120.

[0173] Figure 12 This is a schematic cross-sectional view of a first capacitor 110 and a second capacitor 120 of a non-volatile memory 200. The first capacitor 110 is, for example, a capacitor included in a charge pump 106. The second capacitor is, for example, a capacitor included in an input / output circuit 107.

[0174] The first capacitor 110 includes a semiconductor substrate 10, a component separation region 45, a first capacitor electrode 46, a first capacitor insulating film 48, an interlayer insulating layer 49, contact plugs 50a, 50b, 50c, 50d, and 50e, a first wiring layer 52a, and a second wiring layer 52b. The semiconductor substrate 10 includes a p-type region 30, a first n-well 32, a first p-well 34, a first n-type contact region 36, a second n-type contact region 38, a first p-type contact region 40, a second p-type contact region 42, and a first n-type region 44.

[0175] The second capacitor 120 includes a semiconductor substrate 10, a component separation region 45, a second capacitor electrode 76, a second capacitor insulating film 78, an interlayer insulating layer 49, contact plugs 80a, 80b, 80c, and 80d, a third wiring layer 82, and a second wiring layer 52b. The semiconductor substrate 10 includes a p-type region 30, a second n-well 62, a second p-well 64, a third n-type contact region 66, a fourth n-type contact region 68, a third p-type contact region 72, and a second n-type region 74.

[0176] The second n-well 62 is an example of a seventh semiconductor region. The second p-well 64 is an example of an eighth semiconductor region. The second capacitor electrode 76 is an example of a second electrode. The second capacitor insulating film 78 is an example of a second insulating film.

[0177] The first capacitor 110 and the second capacitor 120 share the semiconductor substrate 10 and the p-type region 30.

[0178] The second n-well 62, the second p-well 64, the third n-type contact region 66, the fourth n-type contact region 68, the third p-type contact region 72, and the second n-type region 74 have the same configuration as the first n-well 32, the first p-well 34, the first n-type contact region 36, the second n-type contact region 38, the second p-type contact region 42, and the first n-type region 44.

[0179] The second n-well 62 is separated from the first n-well 32. The first n-well 32 is electrically separated from the second n-well 62.

[0180] The second capacitor electrode 76, the second capacitor insulating film 78, the contact plugs 80a, 80b, 80c, 80d, and the third wiring layer 82 have the same configuration as the first capacitor electrode 46, the first capacitor insulating film 48, the contact plugs 50a, 50b, 50c, 50d, and the first wiring layer 52a.

[0181] The thickness of the second capacitor insulating film 78 is thinner than that of the first capacitor insulating film 48. The thickness of the first capacitor insulating film 48 is, for example, 2 nm or more and 7 nm or less.

[0182] A first voltage V1 is applied to the first wiring layer 52a. A first voltage V1 is applied to the first n-well 32 and the first capacitor electrode 46.

[0183] The first voltage V1 is, for example, the program voltage Vprog applied to the gate electrode of the memory cell MC when reading data stored in the memory cell MC. The program voltage Vprog is, for example, 15V or more and 30V or less.

[0184] The first wiring layer 52a is electrically connected, for example, to the word line WL of the memory cell array 101. The first wiring layer 52a is electrically connected to the word line WL, for example, via the row decoder 103 and the word line driver 102. The word line WL is an example of the gate electrode of the memory cell MC.

[0185] The first wiring layer 52a is electrically connected to the first capacitor electrode 46. Therefore, the first capacitor electrode 46 is electrically connected to the word line WL.

[0186] A third voltage V3 is applied to the third wiring layer 82. The second capacitor electrode 76 and the second n-well 62 are electrically connected to the third wiring layer 82. Therefore, a third voltage V3 is applied to the second capacitor electrode 76 and the second n-well 62. The third voltage V3 is lower than the first voltage V1.

[0187] The third voltage V3 is, for example, the externally input power supply voltage Vdd. The power supply voltage Vdd is, for example, above 1.5V and below 3V.

[0188] The second wiring layer 52b is connected to contact plugs 50c, 50d, 50e, 80c, and 80d. The second wiring layer 52b, contact plugs 50c, 50d, 50e, 80c, and 80d are used to electrically connect the second n-type contact region 38, the first p-well 34, the p-type region 30, the fourth n-type contact region 68, and the second p-well 64.

[0189] A second voltage V2 is applied to the second wiring layer 52b. A second voltage V2 is applied to the second n-type contact region 38, the first p-well 34, the p-type region 30, the fourth n-type contact region 68, and the second p-well 64.

[0190] The first voltage V1 and the third voltage V3 are higher than the second voltage V2. The second voltage V2 is, for example, 0V. The second wiring layer 52b is, for example, grounded. The second wiring layer 52b is, for example, fixed to the ground potential.

[0191] According to the non-volatile memory 200 of the second embodiment, by thinning the film thickness of the insulating film of the second capacitor 120, which has a lower applied voltage than the first capacitor 110, the capacitance of the second capacitor 120 can be increased compared to the first capacitor 110.

[0192] According to the semiconductor memory device of the second embodiment, the capacitance of the capacitor can be increased.

[0193] (Third Implementation)

[0194] The semiconductor memory device of the third embodiment differs from the semiconductor memory device of the first embodiment in that the first capacitor does not include a fourth semiconductor region and a fifth semiconductor region. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0195] The semiconductor memory device of the third embodiment is a non-volatile memory 300. The non-volatile memory 300 of the third embodiment is a three-dimensional NAND flash memory with multiple memory cells arranged in three dimensions. The non-volatile memory 300 is an example of a semiconductor memory device.

[0196] Figure 13 This is a schematic cross-sectional view of the semiconductor memory device according to the third embodiment. Figure 14 This is a pattern layout diagram of a semiconductor memory device according to the third embodiment. Figure 15 This is a schematic cross-sectional view of the semiconductor memory device according to the third embodiment. Figure 13 yes Figure 14 The FF' section. Figure 15 yes Figure 14 The GG' section.

[0197] Figure 13 , Figure 14 as well as Figure 15 This is a schematic diagram of the first capacitor 110 of the non-volatile memory 300. The first capacitor 110 is, for example, a capacitor included in the charge pump 106 or the input / output circuit 107.

[0198] The first capacitor 110 includes a semiconductor substrate 10, a component separation region 45, a first capacitor electrode 46, a first capacitor insulating film 48, an interlayer insulating layer 49, contact plugs 50a, 50b, 50d, and 50e, a first wiring layer 52a, and a second wiring layer 52b. The semiconductor substrate 10 includes a p-type region 30, a first n-well 32, a first p-well 34, a first n-type contact region 36, a first p-type contact region 40, and a second p-type contact region 42.

[0199] The p-type region 30 is an example of a first semiconductor region. The first n-well 32 is an example of a second semiconductor region. The first p-well 34 is an example of a third semiconductor region. The first capacitor electrode 46 is an example of a first electrode. The first capacitor insulating film 48 is an example of a first insulating film.

[0200] p-type region 30 is p - p-type semiconductors. The p-type region 30 is, for example, p-type single-crystal silicon.

[0201] The first n-well 32 is disposed between the first surface P1 and the p-type region 30. The first n-well 32 is, for example, surrounded by the p-type region 30. The first n-well 32 is an n-type semiconductor. The first n-well 32 is, for example, an n-type single-crystal silicon.

[0202] The first p-well 34 is disposed between the first surface P1 and the first n-well 32. The first p-well 34 is, for example, surrounded by the first n-well 32. The first p-well 34 is a p-type semiconductor. The first p-well 34 is, for example, a p-type single-crystal silicon.

[0203] The first p-well 34 is electrically connected to the p-type region 30.

[0204] The first n-type contact region 36 is located between the first surface P1 and the first n-well 32. The first n-type contact region 36 is, for example, surrounded by the first n-well 32. The first n-type contact region 36 is n + Type n semiconductor. The first n-type contact region 36 is, for example, n... + Type of monocrystalline silicon.

[0205] The first p-type contact area 40 is located between the first surface P1 and the p-type area 30. The first p-type contact area 40 is, for example, surrounded by the p-type area 30. The first p-type contact area 40 is p + p-type semiconductor. The first p-type contact region 40 is, for example, p... + Type of monocrystalline silicon.

[0206] The first p-type contact area 40 is electrically connected to the second p-type contact area 42.

[0207] The second p-type contact region 42 is disposed between the first surface P1 and the first p-well 34. The second p-type contact region 42 is, for example, surrounded by the first p-well 34. The second p-type contact region 42 is disposed on the side of the first p-well 34 at the end of the first capacitor electrode 46. The second p-type contact region 42 is, for example, disposed in the first p-well 34 on both sides with the first capacitor electrode 46 in between.

[0208] The second p-type contact area 42 is p + Type 42 semiconductor. The second p-type contact region 42 is, for example, p... + Type of monocrystalline silicon.

[0209] The second p-type contact area 42 is electrically connected to the first p-type contact area 40.

[0210] The component separation region 45 is disposed on the first surface P1 side of the semiconductor substrate 10. For example, the component separation region 45 is disposed between the first n-type contact region 36 and the second p-type contact region 42. For example, the component separation region 45 is disposed between the second p-type contact region 42 and the first p-type contact region 40.

[0211] The component separation region 45 is an insulator. The component separation region 45 may contain, for example, silicon oxide.

[0212] The first capacitor electrode 46 is disposed on the first surface P1 side of the semiconductor substrate 10. The first capacitor electrode 46 is disposed on the first p-well 34. The first capacitor electrode 46 is a conductor.

[0213] The first capacitor electrode 46 is electrically connected to the first n-well 32 and the first n-type contact region 36.

[0214] The first capacitor insulating film 48 is disposed between the first p-well 34 and the first capacitor electrode 46. The first capacitor insulating film 48 is in contact with the first p-well 34.

[0215] The first capacitor insulating film 48 is an insulator. The first capacitor insulating film 48 is, for example, an oxide, a nitride, or a nitrogen oxide. The first capacitor insulating film 48 may contain, for example, silicon oxide.

[0216] An interlayer insulating layer 49 is disposed on the first surface P1 side of the semiconductor substrate 10. The interlayer insulating layer 49 is disposed on the first n-type contact region 36, the first p-type contact region 40, the second p-type contact region 42, the component separation region 45, and the first capacitor electrode 46. The interlayer insulating layer 49 is an insulator.

[0217] Contact plugs 50a, 50b, 50d, and 50e are disposed within the interlayer insulating layer 49. Contact plugs 50a, 50b, 50d, and 50e are conductive.

[0218] Contact plug 50a is connected to the first n-type contact area 36. Contact plug 50b is connected to the first capacitor electrode 46. Contact plug 50d is connected to the second p-type contact area 42. Contact plug 50e is connected to the first p-type contact area 40.

[0219] The first wiring layer 52a and the second wiring layer 52b are disposed within the interlayer insulating layer 49. The first wiring layer 52a and the second wiring layer 52b are conductive materials. For example, the first wiring layer 52a and the second wiring layer 52b are metals.

[0220] The first wiring layer 52a is connected to contact plugs 50a and 50b. The first n-well 32 is electrically connected to the first capacitor electrode 46 using the first wiring layer 52a, contact plugs 50a and 50b.

[0221] A first voltage V1 is applied to the first wiring layer 52a. A first voltage V1 is applied to the first n-well 32 and the first capacitor electrode 46.

[0222] The first voltage V1 is, for example, the program voltage Vprog applied to the gate electrode of the memory cell MC when reading data stored in the memory cell MC. The program voltage Vprog is, for example, 20V or more and 30V or less. The first voltage V1 is, for example, an externally input power supply voltage Vdd. The power supply voltage Vdd is, for example, 1.5V or more and 3V or less.

[0223] The first wiring layer 52a is electrically connected, for example, to the word line WL of the memory cell array 101. The first wiring layer 52a is electrically connected to the word line WL, for example, via the row decoder 103 and the word line driver 102. The word line WL is an example of the gate electrode of the memory cell MC.

[0224] The first capacitor electrode 46 is electrically connected to the first wiring layer 52a. Therefore, the first capacitor electrode 46 is electrically connected to the word line WL.

[0225] The second wiring layer 52b is connected to contact plugs 50d and 50e. The first p-well 34 and the p-type region 30 are electrically connected using the second wiring layer 52b, contact plugs 50d and 50e.

[0226] A second voltage V2 is applied to the second wiring layer 52b. A second voltage V2 is also applied to the first p-well 34 and the p-type region 30.

[0227] The first voltage V1 is higher than the second voltage V2. The second voltage V2 is, for example, 0V. The second wiring layer 52b is, for example, grounded. The second wiring layer 52b is, for example, fixed to the ground potential.

[0228] The first capacitor 110 of the non-volatile memory 300 of the third embodiment is the same as the first capacitor 110 of the non-volatile memory 100 of the first embodiment. As a capacitor, in addition to the insulating film capacitor Cox, it also has, in parallel, the junction capacitance Cnwell / pwell between the first n-well 32 and the first p-well 34, and the junction capacitance Cnwell / psub between the first n-well 32 and the p-type region 30. Therefore, according to the non-volatile memory 300 of the third embodiment, the capacitor capacitance can be increased.

[0229] Additionally, the insulating film capacitance Cox of the first capacitor 110 of the non-volatile memory 300 utilizes the capacitance between the first capacitor electrode 46 and the inversion layer formed in the first p-well 34.

[0230] According to the semiconductor memory device of the third embodiment, the capacitance of the capacitor can be increased.

[0231] (Fourth Implementation)

[0232] The semiconductor memory device of the fourth embodiment differs from that of the semiconductor memory device of the first embodiment in that, in the first capacitor, the semiconductor substrate further includes a p-type sixth semiconductor region. This p-type sixth semiconductor region is disposed between the first surface and the second semiconductor region, separated from the third semiconductor region, and electrically connected to both the first and third semiconductor regions. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0233] The semiconductor memory device of the fourth embodiment is a non-volatile memory 400. The non-volatile memory 400 of the fourth embodiment is a three-dimensional NAND flash memory with multiple memory cells arranged in three dimensions. The non-volatile memory 400 is an example of a semiconductor memory device.

[0234] Figure 16 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment. Figure 17 This is a pattern layout diagram of a semiconductor memory device according to the fourth embodiment. Figure 18 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment. Figure 16 yes Figure 17 The HH' section. Figure 18 yes Figure 17 Section II'.

[0235] Figure 16 , Figure 17 as well as Figure 18 This is a schematic diagram of the first capacitor 110 of the non-volatile memory 400. The first capacitor 110 is, for example, a capacitor included in the charge pump 106 or the input / output circuit 107.

[0236] The first capacitor 110 includes a semiconductor substrate 10, a component separation region 45, a first capacitor electrode 46, a first capacitor insulating film 48, an interlayer insulating layer 49, contact plugs 50a, 50b, 50c, 50d, and 50e, a first wiring layer 52a, and a second wiring layer 52b. The semiconductor substrate 10 includes a p-type region 30, a first n-well 32, a first p-well 34a, a first p-well 34b, a first p-well 34c, a first n-type contact region 36, a second n-type contact region 38, a first p-type contact region 40, a second p-type contact region 42, and a first n-type region 44.

[0237] p-type region 30 is an example of a first semiconductor region. First n-well 32 is an example of a second semiconductor region. First p-well 34a is an example of a third semiconductor region. First p-well 34b is an example of a sixth semiconductor region. Second n-type contact region 38 is an example of a fourth semiconductor region. First n-type region 44 is an example of a fifth semiconductor region. First capacitor electrode 46 is an example of a first electrode. First capacitor insulating film 48 is an example of a first insulating film.

[0238] p-type region 30 is p - p-type semiconductors. The p-type region 30 is, for example, p-type single-crystal silicon.

[0239] The first n-well 32 is disposed between the first surface P1 and the p-type region 30. The first n-well 32 is, for example, surrounded by the p-type region 30. The first n-well 32 is an n-type semiconductor. The first n-well 32 is, for example, an n-type single-crystal silicon.

[0240] The first p-wells 34a, 34b, and 34c are disposed between the first surface P1 and the first n-well 32. The first p-wells 34a, 34b, and 34c are separated by the first n-well 32. For example, the first p-wells 34a, 34b, and 34c are each surrounded by the first n-well 32.

[0241] The first p-well 34a, the first p-well 34b, and the first p-well 34c are p-type semiconductors. For example, the first p-well 34a, the first p-well 34b, and the first p-well 34c are p-type single-crystal silicon.

[0242] The first p-well 34a, the first p-well 34b, and the first p-well 34c are electrically connected to the p-type region 30.

[0243] The first n-type contact region 36 is located between the first surface P1 and the first n-well 32. The first n-type contact region 36 is, for example, surrounded by the first n-well 32. The first n-type contact region 36 is n + Type n semiconductor. The first n-type contact region 36 is, for example, n... + Type of monocrystalline silicon.

[0244] The second n-type contact region 38 is disposed between the first surface P1 and each of the first p-wells 34a, 34b, and 34c. The second n-type contact region 38 is disposed at the end of the first capacitor electrode 46. The second n-type contact region 38 is disposed on both sides, for example, with the first capacitor electrode 46 in the middle.

[0245] The second n-type contact region 38 is electrically connected to the first p-well 34a, the first p-well 34b, the first p-well 34c, and the p-type region 30.

[0246] The first p-type contact area 40 is located between the first surface P1 and the p-type area 30. The first p-type contact area 40 is, for example, surrounded by the p-type area 30. The first p-type contact area 40 is p + p-type semiconductor. The first p-type contact region 40 is, for example, p... + Type of monocrystalline silicon.

[0247] The first p-type contact area 40 is electrically connected to the second n-type contact area 38 and the second p-type contact area 42.

[0248] The second p-type contact region 42 is disposed between the first surface P1 and each of the first p-wells 34a, 34b, and 34c. The second p-type contact region 42 is p + Type 42 semiconductor. The second p-type contact region 42 is, for example, p... + Type of monocrystalline silicon.

[0249] The second p-type contact area 42 is electrically connected to the second n-type contact area 38, the first p-type contact area 40, and the p-type area 30.

[0250] The first n-type region 44 is disposed between the first surface P1 and each of the first p-wells 34a, 34b, and 34c. The first n-type region 44 is disposed between the first capacitor insulating film 48 and each of the first p-wells 34a, 34b, and 34c. The first n-type region 44 is in contact with the second n-type contact region 38. For example, the first n-type region 44 is in contact with the first capacitor insulating film 48.

[0251] The first n-type region 44 is an n-type semiconductor. For example, the first n-type region 44 is n-type single-crystal silicon.

[0252] The component separation region 45 is disposed on the first surface P1 side of the semiconductor substrate 10. For example, the component separation region 45 is disposed between the first n-type contact region 36 and the second n-type contact region 38. For example, the component separation region 45 is disposed between the second n-type contact region 38 and the second p-type contact region 42. For example, the component separation region 45 is disposed between the second p-type contact region 42 and the first p-type contact region 40.

[0253] The component separation region 45 is an insulator. The component separation region 45 may contain, for example, silicon oxide.

[0254] The first capacitor electrode 46 is disposed on the first surface P1 side of the semiconductor substrate 10. The first capacitor electrode 46 is disposed on each of the first p-wells 34a, 34b, and 34c. The first capacitor electrode 46 is disposed on the first n-type region 44.

[0255] The first capacitor electrode 46 is a conductor. The first capacitor electrode 46 is, for example, a semiconductor, a metal-semiconductor compound, or a metal. The first capacitor electrode 46 is, for example, polycrystalline silicon containing n-type or p-type impurities.

[0256] The first capacitor electrode 46 is electrically connected to the first n-well 32 and the first n-type contact region 36.

[0257] A first capacitor insulating film 48 is disposed between each of the first p-wells 34a, 34b, and 34c and the first capacitor electrode 46. For example, the first capacitor insulating film 48 is disposed between the first n-type region 44 and the first capacitor electrode 46.

[0258] The first capacitor insulating film 48 is an insulator. The first capacitor insulating film 48 is, for example, an oxide, a nitride, or a nitrogen oxide. The first capacitor insulating film 48 may contain, for example, silicon oxide.

[0259] An interlayer insulating layer 49 is disposed on the first surface P1 side of the semiconductor substrate 10. The interlayer insulating layer 49 is disposed on the first n-type contact region 36, the second n-type contact region 38, the first p-type contact region 40, the second p-type contact region 42, the component separation region 45, and the first capacitor electrode 46.

[0260] Contact plugs 50a, 50b, 50c, 50d, and 50e are disposed within the interlayer insulating layer 49. Contact plugs 50a, 50b, 50c, 50d, and 50e are conductive.

[0261] Contact plug 50a is connected to the first n-type contact area 36. Contact plug 50b is connected to the first capacitor electrode 46. Contact plug 50c is connected to the second n-type contact area 38. Contact plug 50d is connected to the second p-type contact area 42. Contact plug 50e is connected to the first p-type contact area 40.

[0262] The first wiring layer 52a and the second wiring layer 52b are disposed within the interlayer insulating layer 49. The first wiring layer 52a and the second wiring layer 52b are conductive materials. For example, the first wiring layer 52a and the second wiring layer 52b are metals.

[0263] The first wiring layer 52a is connected to contact plugs 50a and 50b. The first n-well 32 is electrically connected to the first capacitor electrode 46 using the first wiring layer 52a, contact plugs 50a and 50b.

[0264] A first voltage V1 is applied to the first wiring layer 52a. A first voltage V1 is applied to the first n-well 32 and the first capacitor electrode 46.

[0265] The second wiring layer 52b is connected to contact plugs 50c, 50d, and 50e. The second wiring layer 52b, contact plugs 50c, 50d, and 50e are used to electrically connect the second n-type contact region 38, the first p-well 34a, the first p-well 34b, the first p-well 34c, and the p-type region 30.

[0266] A second voltage V2 is applied to the second wiring layer 52b. The second voltage V2 is applied to the second n-type contact region 38, the first p-well 34, and the p-type region 30.

[0267] The first voltage V1 is higher than the second voltage V2. The second voltage V2 is, for example, 0V. The second wiring layer 52b is, for example, grounded. The second wiring layer 52b is, for example, fixed to the ground potential.

[0268] The first capacitor 110 of the non-volatile memory 400 in the fourth embodiment is the same as the first capacitor 110 of the non-volatile memory 100 in the first embodiment. As a capacitor, in addition to the insulating film capacitor Cox, it also includes, in parallel, a first n-well 32, a junction capacitance Cnwell / pwell between the first p-well 34a, the first p-well 34b, and the first p-well 34c, and a junction capacitance Cnwell / psub between the first n-well 32 and the p-type region 30. Furthermore, the junction capacitance Cnwell / pwell can be derived from the capacitance of the side portions of the first p-well 34a, the first p-well 34b, and the first p-well 34c. Therefore, the junction capacitance Cnwell / pwell is increased. Thus, according to the non-volatile memory 400 of the fourth embodiment, the capacitor capacitance can be increased.

[0269] exist Figures 16 to 18 The example given is the case where there are three first p-wells in the first n-well 32, but the number of first p-wells can be two or more.

[0270] According to the semiconductor memory device of the fourth embodiment, the capacitance of the capacitor can be increased.

[0271] (Fifth Implementation)

[0272] The semiconductor memory device of the fifth embodiment differs from that of the semiconductor memory device of the third embodiment in that the semiconductor substrate of the first capacitor further includes a p-type sixth semiconductor region. This p-type sixth semiconductor region is disposed between the first surface and the second semiconductor region, separate from the third semiconductor region, and electrically connected to both the first and third semiconductor regions. Hereinafter, descriptions that are repeated in the first and third embodiments will sometimes be omitted.

[0273] The semiconductor memory device of the fifth embodiment is a non-volatile memory 500. The non-volatile memory 500 of the fifth embodiment is a three-dimensional NAND flash memory with multiple memory cells arranged in three dimensions. The non-volatile memory 500 is an example of a semiconductor memory device.

[0274] Figure 19 This is a schematic cross-sectional view of the semiconductor memory device according to the fifth embodiment. Figure 20 This is a pattern layout diagram of a semiconductor memory device according to the fifth embodiment. Figure 21 This is a schematic cross-sectional view of the semiconductor memory device according to the fifth embodiment. Figure 19 yes Figure 20 The JJ' section. Figure 21 yes Figure 20 The KK' section.

[0275] Figure 19 , Figure 20 as well as Figure 21 This is a schematic diagram of the first capacitor 110 of the non-volatile memory 500. The first capacitor 110 is, for example, a capacitor included in the charge pump 106 or the input / output circuit 107.

[0276] The first capacitor 110 includes a semiconductor substrate 10, a component separation region 45, a first capacitor electrode 46, a first capacitor insulating film 48, an interlayer insulating layer 49, contact plugs 50a, 50b, 50d, and 50e, a first wiring layer 52a, and a second wiring layer 52b. The semiconductor substrate 10 includes a p-type region 30, a first n-well 32, a first p-well 34a, a first p-well 34b, a first p-well 34c, a first n-type contact region 36, a first p-type contact region 40, and a second p-type contact region 42.

[0277] The p-type region 30 is an example of a first semiconductor region. The first n-well 32 is an example of a second semiconductor region. The first p-well 34a is an example of a third semiconductor region. The first p-well 34b is an example of a sixth semiconductor region. The first capacitor electrode 46 is an example of a first electrode. The first capacitor insulating film 48 is an example of a first insulating film.

[0278] p-type region 30 is p - p-type semiconductors. The p-type region 30 is, for example, p-type single-crystal silicon.

[0279] The first n-well 32 is disposed between the first surface P1 and the p-type region 30. The first n-well 32 is, for example, surrounded by the p-type region 30. The first n-well 32 is an n-type semiconductor. The first n-well 32 is, for example, an n-type single-crystal silicon.

[0280] The first p-wells 34a, 34b, and 34c are located between the first surface P1 and the first n-well 32. The first p-wells 34a, 34b, and 34c are separated by the first n-well 32. The first p-wells 34a, 34b, and 34c are each surrounded by the first n-well 32.

[0281] The first p-well 34a, the first p-well 34b, and the first p-well 34c are p-type semiconductors. For example, the first p-well 34a, the first p-well 34b, and the first p-well 34c are p-type single-crystal silicon.

[0282] The first p-well 34a, the first p-well 34b, and the first p-well 34c are electrically connected to the p-type region 30.

[0283] The first n-type contact region 36 is located between the first surface P1 and the first n-well 32. The first n-type contact region 36 is, for example, surrounded by the first n-well 32. The first n-type contact region 36 is n + Type n semiconductor. The first n-type contact region 36 is, for example, n... + Type of monocrystalline silicon.

[0284] The first p-type contact area 40 is located between the first surface P1 and the p-type area 30. The first p-type contact area 40 is, for example, surrounded by the p-type area 30. The first p-type contact area 40 is p + p-type semiconductor. The first p-type contact region 40 is, for example, p... + Type of monocrystalline silicon.

[0285] The first p-type contact area 40 is electrically connected to the second p-type contact area 42.

[0286] The second p-type contact region 42 is disposed between the first surface P1 and each of the first p-wells 34a, 34b, and 34c. The second p-type contact region 42 is disposed at the end of the first capacitor electrode 46. The second p-type contact region 42 is disposed on both sides, for example, with the first capacitor electrode 46 in the middle.

[0287] The second p-type contact area 42 is p + Type 42 semiconductor. The second p-type contact region 42 is, for example, p... + Type of monocrystalline silicon.

[0288] The second p-type contact area 42 is electrically connected to the first p-type contact area 40.

[0289] The component separation region 45 is disposed on the first surface P1 side of the semiconductor substrate 10. For example, the component separation region 45 is disposed between the first n-type contact region 36 and the second p-type contact region 42. For example, the component separation region 45 is disposed between the second p-type contact region 42 and the first p-type contact region 40.

[0290] The component separation region 45 is an insulator. The component separation region 45 may contain, for example, silicon oxide.

[0291] The first capacitor electrode 46 is disposed on each of the first p-wells 34a, 34b, and 34c. The first capacitor electrode 46 is a conductor.

[0292] The first capacitor electrode 46 is electrically connected to the first n-well 32 and the first n-type contact region 36.

[0293] A first capacitor insulating film 48 is disposed between each of the first p-wells 34a, 34b, and 34c and the first capacitor electrode 46. The first capacitor insulating film 48 is in contact with the first p-wells 34a, 34b, and 34c.

[0294] The first capacitor insulating film 48 is an insulator. The first capacitor insulating film 48 is, for example, an oxide, a nitride, or a nitrogen oxide. The first capacitor insulating film 48 may contain, for example, silicon oxide.

[0295] An interlayer insulating layer 49 is disposed on the first surface P1 side of the semiconductor substrate 10. The interlayer insulating layer 49 is disposed on the first n-type contact region 36, the first p-type contact region 40, the second p-type contact region 42, the component separation region 45, and the first capacitor electrode 46. The interlayer insulating layer 49 is an insulator.

[0296] Contact plugs 50a, 50b, 50d, and 50e are disposed within the interlayer insulating layer 49. Contact plugs 50a, 50b, 50d, and 50e are conductive.

[0297] Contact plug 50a is connected to the first n-type contact area 36. Contact plug 50b is connected to the first capacitor electrode 46. Contact plug 50d is connected to the second p-type contact area 42. Contact plug 50e is connected to the first p-type contact area 40.

[0298] The first wiring layer 52a and the second wiring layer 52b are disposed within the interlayer insulating layer 49. The first wiring layer 52a and the second wiring layer 52b are conductive materials. For example, the first wiring layer 52a and the second wiring layer 52b are metals.

[0299] The first wiring layer 52a is connected to contact plugs 50a and 50b. The first n-well 32 is electrically connected to the first capacitor electrode 46 using the first wiring layer 52a, contact plugs 50a and 50b.

[0300] A first voltage V1 is applied to the first wiring layer 52a. A first voltage V1 is applied to the first n-well 32 and the first capacitor electrode 46.

[0301] The first capacitor electrode 46 is electrically connected to the first wiring layer 52a. Therefore, the first capacitor electrode 46 is electrically connected to the word line WL.

[0302] The second wiring layer 52b is connected to contact plugs 50d and 50e. The first p-well 34a, the first p-well 34b, the first p-well 34c, and the p-type region 30 are electrically connected using the second wiring layer 52b, contact plugs 50d and 50e.

[0303] A second voltage V2 is applied to the second wiring layer 52b. The second voltage V2 is applied to the first p-well 34a, the first p-well 34b, the first p-well 34c, and the p-type region 30.

[0304] The first voltage V1 is higher than the second voltage V2. The second voltage V2 is, for example, 0V. The second wiring layer 52b is, for example, grounded. The second wiring layer 52b is, for example, fixed to the ground potential.

[0305] The first capacitor 110 of the non-volatile memory 500 of the fifth embodiment is the same as the first capacitor 110 of the non-volatile memory 300 of the third embodiment. As a capacitor, in addition to the insulating film capacitor Cox, it also includes, in parallel, the junction capacitance Cnwell / pwell between the first p-well 34a, the first p-well 34b, and the first p-well 34c and the first p-well 34, and the junction capacitance Cnwell / psub between the first n-well 32 and the p-type region 30. Furthermore, the junction capacitance Cnwell / pwell can be obtained from the side portions of the first p-well 34a, the first p-well 34b, and the first p-well 34c. Therefore, the junction capacitance Cnwell / pwell is increased. Thus, according to the non-volatile memory 500 of the fifth embodiment, the capacitor capacitance can be increased.

[0306] exist Figures 19 to 21 The example given is the case where there are three first p-wells in the first n-well 32, but the number of first p-wells can be two or more.

[0307] According to the semiconductor memory device of the fifth embodiment, the capacitance of the capacitor can be increased.

[0308] In the first to fifth embodiments, the positional relationship of the cell array, the first capacitor, or the second capacitor within the memory chip is not particularly limited. For example, the first capacitor or the second capacitor may be disposed in the peripheral area of ​​the memory cell array, or it may be disposed directly below the memory cell array.

[0309] In the first to fifth embodiments, three-dimensional NAND flash memory was described as an example of a semiconductor storage device, but the semiconductor storage device is not limited to three-dimensional NAND flash memory.

[0310] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent material of one embodiment may be replaced or modified with the constituent material of another embodiment. These embodiments and their variations are included within the scope and spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device, wherein, have: A memory cell array, comprising multiple memory cells; as well as A control circuit, which controls the operation of the memory cell, and includes a first capacitor. The first capacitor includes: A semiconductor substrate having a first surface and a second surface facing the first surface, comprising: The first semiconductor region of the p-type type; A second n-type semiconductor region is disposed between the first surface and the first semiconductor region; and A p-type third semiconductor region is disposed between the first surface and the second semiconductor region, and is electrically connected to the first semiconductor region; The first electrode is electrically connected to the second semiconductor region; and A first insulating film is disposed between the third semiconductor region and the first electrode.

2. The semiconductor memory device as claimed in claim 1, wherein, The semiconductor substrate further includes an n-type fourth semiconductor region, which is disposed between the first surface and the third semiconductor region, and is located on the third semiconductor region side at the end of the first electrode, and is electrically connected to the third semiconductor region.

3. The semiconductor memory device as claimed in claim 2, wherein, The n-type impurity concentration in the fourth semiconductor region is higher than that in the second semiconductor region.

4. The semiconductor memory device as claimed in claim 2, wherein, The semiconductor substrate further includes an n-type fifth semiconductor region, which is disposed between the third semiconductor region and the first insulating film and is connected to the fourth semiconductor region.

5. The semiconductor memory device as claimed in claim 4, wherein, The fifth semiconductor region is in contact with the first insulating film.

6. The semiconductor memory device of claim 4, wherein, The n-type impurity concentration in the fifth semiconductor region is lower than that in the fourth semiconductor region.

7. The semiconductor memory device of claim 4, wherein, The concentration of n-type impurities in the fifth semiconductor region is higher than that in the second semiconductor region.

8. The semiconductor memory device of claim 4, wherein, The depth of the fifth semiconductor region is shallower than the depth of the fourth semiconductor region.

9. The semiconductor memory device of claim 1, wherein, The semiconductor substrate further includes a p-type sixth semiconductor region, which is disposed between the first surface and the second semiconductor region, separate from the third semiconductor region, and electrically connected to the first semiconductor region and the third semiconductor region.

10. The semiconductor memory device of claim 2, wherein, The semiconductor substrate further includes a p-type sixth semiconductor region, which is disposed between the first surface and the second semiconductor region, separate from the third semiconductor region, and electrically connected to the first semiconductor region and the third semiconductor region.

11. The semiconductor memory device of claim 1, wherein, The first voltage applied to the first electrode and the second semiconductor region is higher than the second voltage applied to the first semiconductor region and the third semiconductor region.

12. The semiconductor memory device of claim 1, wherein, The memory cell includes: a semiconductor layer; a gate electrode; and a charge storage layer disposed between the semiconductor layer and the gate electrode. The gate electrode is electrically connected to the first electrode.

13. The semiconductor memory device of claim 1, wherein, The control circuit also includes a second capacitor. The second capacitor includes: The semiconductor substrate includes: A seventh semiconductor region of type n is disposed between the first surface and the first semiconductor region, and is separated from the second semiconductor region; and The p-type eighth semiconductor region is disposed between the first surface and the seventh semiconductor region, and is electrically connected to the first semiconductor region; The second electrode is electrically connected to the seventh semiconductor region; and A second insulating film is disposed between the eighth semiconductor region and the second electrode, and the film thickness is thinner than that of the first insulating film.

14. The semiconductor memory device of claim 13, wherein, The first voltage applied to the first electrode and the second semiconductor region is higher than the second voltage applied to the first semiconductor region and the third semiconductor region. The third voltage applied to the second electrode and the seventh semiconductor region is higher than the second voltage and lower than the first voltage.

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