Display panel and display device

Abstract

Embodiments of the present application disclose a display panel and a display device. The display panel has a first region, a second region, and a third region arranged in sequence. The display panel includes a substrate, a plurality of first traces, and a plurality of second traces. The plurality of first traces are disposed on the substrate and spaced apart. The first traces extend from the first region to the second region. The plurality of second traces are disposed on the substrate and spaced apart. The second traces extend from the second region to the third region. The first traces and the second traces are disposed on different layers. The first traces and the second traces are connected to each other in a one-to-one correspondence through vias. The vias are staggered in the second region. In the display panel provided by the embodiments of the present application, the vias connecting the first traces and the second traces are staggered. During the process of manufacturing the vias, even if the problem of over-etching occurs, the grooves generated by the over-etching will not be in the same straight line as the adjacent vias. Therefore, the stress at the grooves and the vias can be dispersed, and the problem of stress concentration at the vias for wire transfer can be improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] In a display panel, it is common to electrically connect the traces of different film layers through vias. During the research and practice of the prior art, the inventors of this application found that during the preparation of vias, due to over-etching, relatively long grooves are likely to be formed on the insulating layer. As a result, stress concentration occurs at the grooves and vias, thereby affecting the lifespan of the flexible display panel. Summary of the Invention

[0003] Embodiments of this application provide a display panel and a display device, which can improve the problem of stress concentration at the vias for internal wiring in the display panel.

[0004] Embodiments of this application provide a display panel. The display panel has a first region, a second region, and a third region arranged in sequence. The display panel includes:

[0005] A substrate;

[0006] Multiple first traces, the multiple first traces are disposed on the substrate and are spaced apart, and the first traces extend from the first region to the second region;

[0007] Multiple second traces, the multiple second traces are disposed on the substrate and are spaced apart, the second traces extend from the second region to the third region, the first traces and the second traces are arranged in different layers, the first traces and the second traces are connected to each other through vias in a one-to-one correspondence, and the vias are staggeredly arranged in the second region.

[0008] Optionally, in some embodiments of this application, the display panel further includes an insulating layer. The insulating layer is disposed on a side of the first traces and the second traces away from the substrate, and through holes are provided on the insulating layer. The orthographic projection of the via on the substrate is located within the orthographic projection of the through hole on the substrate.

[0009] Optionally, in some embodiments of this application, adjacent n through holes are grouped as a set, and the vias corresponding to each set of through holes are staggeredly arranged, where n is a natural number greater than or equal to 2.

[0010] Optionally, in some embodiments of this application, at least a part of the second traces has a bent trace portion.

[0011] Optionally, in some embodiments of this application, at least a part of the first traces has a bent trace portion.

[0012] Optionally, in some embodiments of the present application, the bent trace portion is disposed in the second region.

[0013] Optionally, in some embodiments of the present application, the bent trace portion includes a plurality of bent units connected in sequence, at least one parallel trace is connected to the bent unit, and the parallel trace is disposed in parallel with the bent trace portion.

[0014] Optionally, in some embodiments of the present application, the display panel further includes a chip-on-film (COF), the COF is disposed in the third region, the second trace is connected to the COF, and the second region is a bent region.

[0015] Optionally, in some embodiments of the present application, the vertical distance between the first trace and the substrate is greater than the vertical distance between the second trace and the substrate.

[0016] Optionally, in some embodiments of the present application, the display panel further includes an interlayer insulating layer, the interlayer insulating layer is disposed on the second trace, the first trace is disposed on the interlayer insulating layer, and the via is opened on the interlayer insulating layer.

[0017] Correspondingly, an embodiment of the present application further provides a display device, the display device includes a display panel and a packaging structure, the display panel is the display panel described in any one of the above, and the packaging structure is disposed on the display panel.

[0018] Embodiments of the present application provide a display panel and a display device. The display panel has a first region, a second region, and a third region arranged in sequence. The display panel includes a substrate, a plurality of first traces, and a plurality of second traces. The plurality of first traces are disposed on the substrate and spaced apart. The first trace extends from the first region to the second region. The plurality of second traces are disposed on the substrate and spaced apart. The second trace extends from the second region to the third region. The first trace and the second trace are disposed on different layers. The first trace and the second trace are connected in one-to-one correspondence through vias. The vias are staggered in the second region. In the display panel provided by the embodiments of the present application, the vias connecting the first trace and the second trace are staggered. During the process of manufacturing the vias, even if an over-etching problem occurs, the grooves generated by the over-etching will not be in the same straight line as the adjacent vias. Therefore, the stress at the grooves and the vias can be dispersed, and the problem of stress concentration at the vias of the transfer line can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0020] Figure 1 is a first top - view structural schematic diagram of a display panel provided by an embodiment of the present application;

[0021] Figure 2 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0022] Figure 3 is along Figure 1 a cross - sectional structural schematic diagram of the AA' line in

[0023] Figure 4 is along Figure 1 a cross - sectional structural schematic diagram of the BB' line in

[0024] Figure 5 is a second top - view structural schematic diagram of a display panel provided by an embodiment of the present application;

[0025] Figure 6 is a third top - view structural schematic diagram of a display panel provided by an embodiment of the present application;

[0026] Figure 7 is a fourth top - view structural schematic diagram of a display panel provided by an embodiment of the present application;

[0027] Figure 8 is a partial structural schematic diagram of a first wiring in a display panel provided by an embodiment of the present application;

[0028] Figure 9 is a structural schematic diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the drawings; and "inner" and "outer" refer to the outline of the device.

[0030] An embodiment of the present application provides an array substrate and a method for manufacturing the array substrate. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0031] Please refer to Figures 1 to 4 , Figure 1 which is a first top - view structural schematic diagram of a display panel provided by an embodiment of the present application. Figure 2 which is a structural schematic diagram of a display panel provided by an embodiment of the present application. Figure 3 is a cross - sectional structural schematic diagram along the Figure 1 AA' line in Figure 4 is a cross - sectional structural schematic diagram along the Figure 1 BB' line in. The display panel 100 has a first region 10A, a second region 10B, and a third region 10C arranged in sequence. The display panel 100 includes a substrate 101, a plurality of first traces 104, and a plurality of second traces 102. The plurality of first traces 104 are disposed on the substrate 101. The first traces 104 extend from the first region 10A to the second region 10B, and the plurality of first traces 104 are spaced apart. The plurality of second traces 102 are disposed on the substrate 101. The second traces 102 extend from the second region 10B to the third region 10C, and the plurality of second traces 102 are spaced apart. The first traces 104 and the second traces 102 are arranged in different layers. The first traces 104 and the second traces 102 are connected to each other one - to - one through vias 10a. The vias 10a are staggered in the second region 10B.

[0032] The display panel 100 provided by an embodiment of the present application has a first region 10A, a second region 10B, and a third region 10C arranged in sequence. The first region 10A, the second region 10B, and the third region 10C may all be located in the display area of the display panel 100. In the display area of the display panel 100, there is usually a situation where metal traces are fabricated on different film layers and connected through vias 10a. At this time, if the positions of the vias 10a for wire transfer are not designed, over - etching problems may also occur in the vias 10a. In addition, the first region 10A, the second region 10B, and the third region 10C may respectively refer to the display area (active area, AA), the bending area, and the bonding area of the display panel 100. For this case, detailed descriptions will be given below.

[0033] When fabricating the vias 10a, an etching method is usually adopted. However, due to process condition limitations, over-etching problems are likely to occur during etching. Therefore, if the vias 10a connecting the first trace 104 and the second trace 102 are set on the same straight line, the grooves generated by over-etching during the etching of the vias 10a are likely to extend on the same straight line, thereby leading to stress concentration problems at the vias 10a where the over-etching-generated grooves occur. In the display panel 100 provided by the embodiments of the present application, the vias 10a connecting the first trace 104 and the second trace 102 are staggeredly arranged. During the process of fabricating the vias 10a, even if over-etching problems occur, the grooves generated by over-etching will not be on the same straight line as the adjacent vias 10a. Therefore, the stress at the grooves and the vias 10a can be dispersed, and the stress concentration problem occurring at the vias 10a for wire transfer can be improved.

[0034] It can be understood that, in order to more clearly show the top view structure of the traces in the display panel 100, the substrate is not shown in Figure 1 . And the upper film layers are schematically shown with semi-transparent patterns to clearly show the upper and lower stacking relationships between the film layers.

[0035] Optionally, please continue to refer to Figure 1 , the display panel 100 further includes an insulating layer 105. The insulating layer 105 is disposed on a side of the first trace 104 and the second trace 102 away from the substrate 101. A through hole 10b is provided on the insulating layer 105. The orthographic projection of the via 10a on the substrate 101 is located within the orthographic projection of the through hole 10b on the substrate 101.

[0036] In a flexible display panel, the display panel 100 often needs to be bent or curved. Then the traces in the panel are likely to be squeezed during bending. Therefore, covering the insulating layer 105 on the first trace 104 and the second trace 102 can protect the first trace 104 and the second trace 102, preventing short circuits or open circuits from occurring to the first trace 104 and the second trace 102 when the display panel 100 is bent.

[0037] In addition, a through hole 10b is provided on the insulating layer 105. The through hole 10b is provided in the second region 10B. When the second region 10B is bent, the through hole 10b is provided to disperse the bending stress. In addition, since wire transfer occurs in the second region 10B and there are more film layers and greater thickness in the wire transfer region, providing the through hole 10b can reduce the film layer thickness in the wire transfer region and further reduce the bending stress.

[0038] Optionally, please refer to Figure 1 and Figure 2 . Figure 1 For Figure 2Partial enlarged schematic diagram at position C in the figure. The display panel 100 provided in the embodiment of the present application further includes a chip on film 106. The chip on film 106 is disposed in the third region 10C. The second trace 102 is connected to the chip on film 106. The second region 10B is a bending region. Optionally, the first region 10A is a display region, and the third region 10C is a bonding region. The display panel further includes a fourth region 10D, and the fourth region 10D is a non-display region, which can also be referred to as a border region. Among them, the second region 10B and the fourth region 10D at least partially overlap.

[0039] The chip on film (COF) is bonded to the bonding region of the display panel 100. The COF is formed by bonding and mounting a chip (for example, a source driver IC or a gate driver IC) on a flexible wiring substrate formed with a wiring pattern. The wiring pattern of the COF generally consists of inner leads connected to the electrodes of the chip and outer leads connected to external circuits. The second trace 102 connects the COF and the first trace 104 in the display region, and transmits the output signal of the COF to the first trace 104, and then inputs it to the display panel 100.

[0040] In order to increase the screen-to-body ratio of the display region of the display panel 100, the border of the display panel 100 is narrowed. Generally, a part of the display panel 100 can be bent to the back of the display panel 100. In this embodiment, the third region 10C can be bent to the back of the display panel 100. In order to prevent the traces from being exposed outside during bending, the first trace 104 in the display region is usually transferred to the second trace 102 made of a lower metal film layer through a via 10a, and then bent to the back of the display panel 100.

[0041] In the embodiment of the present application, since the vias 10a are arranged in a staggered manner, the grooves generated due to over-etching are not easily connected together during manufacturing. Therefore, it is not easy to have a problem of stress concentration at the vias 10a. When the third region 10C of the display panel 100 is bent to the back of the display panel 100, there will be no problem of film layer fracture due to bending stress, and the failure of the display panel 100 can be avoided.

[0042] Optionally, please refer to Figure 3 and Figure 4 . The vias 10a are arranged in a staggered manner in the second region 10B. It can be that the distance D1 between the via 10a at the AA' line position and the insulating layer 105 close to the third region 10C is not equal to the distance D2 between the via 10a at the BB' line position and the insulating layer 105 close to the third region 10C.

[0043] Optionally, the vertical distance between the first trace 104 and the substrate 101 is greater than the vertical distance between the second trace 102 and the substrate 101.

[0044] When the display panel 100 needs to be bent, the second region 10B can be used as the bending region for bending. Therefore, in the second region 10B, the first trace 104 is transferred to the lower metal trace, that is, the second trace 102. This can make the trace in the bending region closer to the bending center, thereby reducing the bending stress on the second trace 102 during bending.

[0045] Specifically, the display panel 100 further includes an interlayer insulating layer 103. The interlayer insulating layer 103 is disposed on the second trace 102. The first trace 104 is disposed on the interlayer insulating layer 103, and the via 10a is formed in the interlayer insulating layer 103. The material of the interlayer insulating layer 103 can be selected from one or a combination of silicon dioxide, nitrogen dioxide, and silicon oxynitride.

[0046] Optionally, please refer to Figure 1 and Figure 5 . Figure 5 FIG. Figure 5 is a second top view structural schematic diagram of the display panel provided by the embodiment of the present application. Adjacent n vias 10b are in a group, and the corresponding vias 10a in each group of vias 10b are staggeredly arranged, where n is a natural number greater than or equal to 2.

[0047] Specifically, n can be 2, 3, 4, 5, 6. For example, when n is 2, please refer to Figure 5 . Adjacent two vias 10b are in a group, and the corresponding vias 10a in each group of vias 10b are staggeredly arranged. Figure 5 The embodiment shown can be understood as arranging the vias 10a of the odd-numbered traces on the same straight line, and arranging the vias 10a of the even-numbered traces on another straight line. Such a design of staggeredly arranging the vias 10a connecting the first trace 104 and the second trace 102 has a simple manufacturing process and is easy to implement. Moreover, the misalignment of the vias 10a can be achieved under simple process conditions, increasing the distance between the grooves generated by over-etching of adjacent vias 10a and improving the stress concentration at the wire transfer location.

[0048] For example, when n is 4, please continue to refer to Figure 1 . Figure 1 The embodiment shown takes adjacent four vias 10b as a group, and the corresponding vias 10a in each group of vias 10b are staggeredly arranged as an example for illustration. Within the same group of vias 10b, the vias 10a corresponding to each via 10b are not on the same straight line within the via 10b. This setting method can ensure a better staggering effect of the vias 10a and more effectively avoid the problem of stress concentration.

[0049] When n is 2, it can also be that the vias 10a in adjacent groups of vias 10b are staggeredly arranged. Please continue to refer to Figure 1 . Figure 1It can also mean that every two adjacent through holes 10b form a group, and the corresponding via holes 10a in each group of through holes 10b are staggeredly arranged. Moreover, the via holes 10a in adjacent groups of through holes 10b are also staggeredly arranged. Of course, when n takes other values, the via holes 10a in adjacent groups of through holes 10b can also be staggeredly arranged.

[0050] For the value of n, natural numbers greater than or equal to 2 are all within the protection scope of the embodiments of the present application. The embodiments of the present application take n as 2, 3, 4, 5, and 6 as examples, and specifically illustrate the structures when n is 2 and 4, but this is not a limitation on the embodiments of the present application. It can be understood that the value of n should not be too large either. Because in the display panel 100, the area of the through holes 10b is limited. Since it is preferred that the orthographic projection of the via hole 10a and the substrate 101 is located within the orthographic projection area of the through hole 10b on the substrate 101, when the value of n is too large, it is impossible to ensure that the distance between the grooves generated by over-etching of two adjacent via holes 10a in the wiring direction can be widened, and the grooves generated by over-etching may still be connected, resulting in stress concentration and further affecting the performance of the display panel 100.

[0051] Optionally, please refer to Figure 6 , Figure 6 which is the third top view structure schematic diagram of the display panel provided by the embodiments of the present application. In the Figure 6 illustrated embodiment, at least part of the second wiring 102 has a bent wiring portion 10c. It can be understood that the lengths of the bent wiring portions 10c of different second wirings 102 can be different. The bent wiring portion 10c is a bent wiring design for part of the second wiring 102. Optionally, the bent wiring portion 10c can be arranged in the second area 10B. When the second area 10B is a bent area, the bent wiring design of the bent wiring portion 10c can further disperse stress.

[0052] In addition, since the via holes 10a are staggeredly arranged, the wiring lengths of the second wirings 102 are different. By designing the bent wiring portion 10c for the second wiring 102, the lengths of multiple second wirings 102 can be made the same or approximately the same. This solves the problem of inconsistent resistance and capacitance of the second wirings 102 in different rows. For the display panel 100 provided by the embodiments of the present application, by designing the bending manner of the second wiring 102, the problem of bright and dark lines on the panel can be improved.

[0053] When the first area 10A is a display area, the second area 10B is a bent area, and the third area 10C is a bonding area, the width of the second wiring 102 is usually set to be smaller than the width of the first wiring 104. Therefore, it is easier to implement the bent wiring portion 10c for the second wiring 102 with a thinner wiring width in the manufacturing process.

[0054] Optionally, please refer to Figure 7 , Figure 7This is the fourth top - view structural schematic diagram of the display panel provided by the embodiments of the present application. In Figure 7 In the illustrated embodiment, at least part of the first trace 104 has a bent trace portion 10c. It can be understood that the lengths of the bent trace portions 10c of different first traces 104 can be different. The bent trace portion 10c is a design of bending and winding a part of the first trace 104. Optionally, the bent trace portion 10c can be arranged in the second region 10B. When the second region 10B is a bending region, the bending and winding design of the bent trace portion 10c can further disperse stress.

[0055] In addition, since the vias 10a are stagger - arranged, the trace lengths of the first traces 104 are different. By designing the bent trace portion 10c for the first trace 104, the lengths of multiple first traces 104 can be made the same or approximately the same. This solves the problem of inconsistent resistance and capacitance of the first traces 104 in different rows. For the display panel 100 provided by the embodiments of the present application, by designing the bending manner of the first trace 104, the problem of bright and dark lines on the panel can be improved.

[0056] When the first region 10A is a display region, the second region 10B is a bending region, and the third region 10C is a bonding region, the vertical distance between the first trace 104 and the substrate 101 is greater than the vertical distance between the second trace 102 and the substrate 101. That is, the first trace 104 is arranged at a higher layer position. Therefore, when the second region 10B is bent, the bending stress received by the first trace 104 is greater than the bending stress received by the second trace 102. By arranging the bent trace portion 10c on the first trace 104, the effect of dispersing the bending stress is better, thus further improving the stress concentration problem generated when the display panel 100 is bent.

[0057] Among them, the bending manner of the bent trace portion 10c can be a concave - convex broken - line shape, a wavy shape or a saw - tooth shape. These bending forms can bend longer first traces 104 and second traces 102 in a smaller space, saving the layout space of the first trace 104 or the second trace 102, which is beneficial to the narrow - bezel design of the panel. Figure 6 and Figure 7 The bending of the bent trace portion 10c into a concave - convex broken - line shape is used as an example.

[0058] It should be noted that in the display panel 100 of the embodiments of the present application, both the first trace 104 and the second trace 102 can also have the bent trace portion 10c.

[0059] Optionally, please continue to refer to Figure 6 and Figure 7。The orthographic projection of the partial bent trace portion 10c on the substrate 101 is located within the orthographic projection of the via hole 10b on the substrate 101. The partial bent trace portion 10c is disposed between the insulating layer 105 and the substrate 101. Since the first trace 104 and the second trace 102 are usually made of a metal material, different bending angles are likely to occur when they are bent with respect to the surrounding inorganic material film layers. Therefore, it is designed that the orthographic projection of the partial bent trace portion 10c on the substrate 101 is located within the orthographic projection of the via hole 10b on the substrate 101. The partial bent trace portion 10c is disposed between the insulating layer 105 and the substrate 101. When bending, the insulating layer 105 generates a certain extrusion force on the bent trace portion 10c to prevent the first trace 104 or the second trace 102 from falling off.

[0060] Optionally, please refer to Figure 8 , Figure 8 is a schematic diagram of a partial structure of the first trace in the display panel provided by the embodiment of the present application. The bent trace portion 10c includes a plurality of bent units 101c connected in sequence. At least one parallel trace 102c is connected to the bent unit 101c. The parallel trace 102c is disposed in parallel with the bent trace portion 10c.

[0061] One parallel trace 102c is connected to the bent trace portion 10c. The parallel trace 102c is disposed in parallel with the bent trace portion 10c. Since the bending designs of the first traces 104 and the second traces 102 in different rows are different in the second region 10B, uneven etching may occur during the manufacturing process. Therefore, the etching uniformity can be improved by connecting the parallel trace 102c in the middle. The design of the parallel trace 102c is equivalent to connecting a resistor in parallel in the bent trace portion 10c. By adjusting the connection position of the parallel trace 102c, the resistance values of the first trace 104 and the second trace 102 are ensured to remain unchanged, and the winding length of the first trace 104 and the second trace 102 is also increased, thereby improving the etching uniformity to a certain extent. In addition, adding the parallel trace 102c can also improve the connection stability of the bent trace portion 10c. To prevent the width of the non-display area border of the display panel from increasing, the width of the second region 10B cannot be too large. Then, the area for bending the bent trace portion 10c in the second region 10B is small, and the distance between adjacent bent trace portions 10c is narrow, so the problem of open circuit is likely to occur during etching. Connecting at least one parallel trace 102c in the bent trace portion 10c can avoid the problem that the signal cannot be transmitted after a section of the first trace 104 and the second trace 102 is open circuited.

[0062] It should be noted that, while ensuring that the lengths of the first routing line 104 and the second routing line 102 remain unchanged, the number of parallel routing lines 102c can be increased in areas with denser wiring. For example, if the length of the bent routing line portion 10c of the first routing line 104 with the via 10a far from the third area 10C is shorter, and the bending density in the second area 10B is smaller, the number of parallel routing lines 102c can be reduced. If the length of the bent routing line portion 10c of the first routing line 104 with the via 10a close to the third area 10C is longer, and the bending density in the second area 10B is larger, the number of parallel routing lines 102c can be increased.

[0063] Optionally, the number of bending units 101c may be considered based on the length of the first wiring 104 or the second wiring 102 in the through hole 10b. There is no fixed standard and range for the size of the through hole 10b, and there is no fixed standard and range for the length of the first wiring 104 or the second wiring 102 in the through hole 10b, and it is necessary to comprehensively consider factors such as resolution, the number of the first wiring 104 and the second wiring 102, etc.

[0064] In addition, the lateral capacitance between the plurality of first routing lines 104 and the plurality of second routing lines 102 also needs to be considered. Because the first routing line 104 can be a signal line in the display panel. In a high-resolution panel, the slight difference between the signal lines has a greater impact on the pixel display, and the more the number of the first routing lines 104, the greater the difference in lateral capacitance. Then, when there are more first routing lines 104 and second routing lines 102, the distance between adjacent first routing lines 104 and adjacent second routing lines 102 will be reduced. Therefore, the number of bending units 101c should be more, so that the distance between adjacent first routing lines 104 and adjacent second routing lines 102 can be increased under the same routing length. Therefore, optionally, the number of first routing lines 104 and second routing lines 102 is proportional to the number of bending units 101c.

[0065] It should be noted that Figure 8 The first routing line 104 is taken as an example, and the second routing line 102 may also have the same design, which will not be described in detail here.

[0066] Accordingly, the present application also provides a display device. Figure 9 , Figure 9 1 is a schematic diagram of a structure of a display device provided in an embodiment of the present application. The display device 1000 includes a display panel 100 and a packaging structure 200. The display panel 100 is any of the display panels 100 described above. The packaging structure 200 is disposed on the display panel 100.

[0067] The display device 1000 provided by an embodiment of the present application includes a display panel 100. The display panel 100 has a first region, a second region, and a third region arranged in sequence. The display panel 100 includes a substrate, a plurality of first traces, and a plurality of second traces. The plurality of first traces are disposed on the substrate and spaced apart. The first traces extend from the first region to the second region. The plurality of second traces are disposed on the substrate and spaced apart. The second traces extend from the second region to the third region. The first traces and the second traces are disposed on different layers. The first traces and the second traces are connected to each other in a one-to-one correspondence through vias. The vias are staggeredly disposed in the second region. In the display panel provided by the embodiment of the present application, the vias connecting the first traces and the second traces are staggeredly disposed. During the process of fabricating the vias, even if an over-etching problem occurs, the grooves generated by the over-etching will not be in a straight line with adjacent vias. Therefore, the stress at the grooves and the vias can be dispersed, and the problem of stress concentration at the vias for wire transfer can be improved.

[0068] Optionally, the first region may be a display region, the second region may be a bending region, and the third region may be a bonding region. In order to increase the screen occupation ratio of the display region of the display panel 100 and narrow the border of the display panel 100. Generally, a part of the region of the display panel 100 can be bent to the back of the display panel 100. In this embodiment, the third region can be bent to the back of the display panel 100. In order to prevent the traces from being exposed outside during bending, usually, the first traces in the display region are transferred to the second traces fabricated on the lower metal film layer through vias, and then bent to the back of the display panel 100.

[0069] In the embodiment of the present application, since the vias are staggeredly disposed, the grooves generated by over-etching during fabrication are not easily connected together. Therefore, the problem of stress concentration at the vias is not easily generated. When the third region of the display panel 100 is bent to the back of the display panel 100, the problem of film layer fracture due to bending stress will not occur, and the failure of the display panel can be avoided.

[0070] The above has introduced in detail a display panel and a display device provided by an embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, characterized in that, The display panel has a first region, a second region, and a third region arranged in sequence, and the second region is a bending region. The display panel includes: a substrate; a plurality of first traces, the plurality of first traces are disposed on the substrate and spaced apart, and the first traces extend from the first region to the second region; a plurality of second traces, the plurality of second traces are disposed on the substrate and spaced apart, the second traces extend from the second region to the third region, the first traces and the second traces are disposed on different layers, and the first traces and the second traces are connected in a one-to-one correspondence through vias, and the vias are staggered in the second region.

2. The display panel according to claim 1, wherein The display panel further includes an insulating layer, the insulating layer is disposed on a side of the first traces and the second traces away from the substrate, and through holes are formed in the insulating layer, and a positive projection of the via on the substrate is located within a positive projection of the through hole on the substrate.

3. The display panel according to claim 2, wherein Adjacent n of the through holes are grouped together, and the vias corresponding to each group of through holes are staggered, where n is a natural number greater than or equal to 2.

4. The display panel according to claim 1, wherein At least a part of the second traces has a bent trace portion.

5. The display panel according to claim 1, wherein At least a part of the first traces has a bent trace portion.

6. The display panel according to claim 4 or 5, characterized in that, The bent trace portion is disposed in the second region.

7. The display panel according to claim 4 or 5, characterized in that, The bent trace portion includes a plurality of bent units connected in sequence, and at least one parallel trace is connected to the bent unit, and the parallel trace is disposed in parallel with the bent trace portion.

8. The display panel according to claim 1, wherein The display panel further includes a chip-on-film, the chip-on-film is disposed in the third region, the second traces are connected to the chip-on-film, and the second region is a bending region.

9. The display panel according to claim 1, wherein A vertical distance between the first traces and the substrate is greater than a vertical distance between the second traces and the substrate.

10. The display panel according to claim 9, wherein The display panel further includes an interlayer insulating layer, the interlayer insulating layer is disposed on the second traces, the first traces are disposed on the interlayer insulating layer, and the vias are formed in the interlayer insulating layer.

11. A display device, characterized in that, The display device includes a display panel and a packaging structure, the display panel is the display panel according to any one of claims 1 to 10, and the packaging structure is disposed on the display panel.

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