Hybrid parallel computing encryption and decryption system, transmitter device and receiver device

Abstract

The present application relates to the field of encryption technology, and specifically provides a hybrid parallel computing encryption and decryption system, including a transmitting end device and a receiving end device, wherein the transmitting end device includes a data generation module and a data encryption module, wherein the data encryption module obtains at least one data packet from the data generation module, encrypts the data packet via a fourth-order encryptor, and then outputs an encrypted sequence. The receiving end device includes a data target module and a data decryption module. The data decryption module obtains the encrypted sequence from the transmitting end device, decrypts the encrypted sequence via a fourth-order decryptor, and then outputs the restored data packet to the data target module.

Description

Technical Field

[0001] The present application relates to the field of encryption technology and provides an encryption and decryption system, a transmitting end device and a receiving end device. Background Art

[0002] Advanced Encryption Standard (AES), also known as Rijndael encryption in cryptography, is a block encryption standard adopted by the U.S. federal government. This standard is used to replace the original DES, has been analyzed by many parties and is widely used around the world.

[0003] The Advanced Encryption Standard has been cracked many times. The 128-bit key version of AES has 10 encryption cycles, the 192-bit key version has 12 encryption cycles, and the 256-bit key version has 14 encryption cycles. As of 2006, the most famous attacks were against the 128-bit key version of AES with 7 encryption cycles, the 192-bit key version with 8 encryption cycles, and the 256-bit key version with 9 encryption cycles. As hardware becomes more efficient, it is estimated that the day when AES can be completely cracked by brute force attacks is not far away.

[0004] In addition, with the continuous upgrading of hardware, artificial intelligence has now reached the stage of commercialization. Through the processing performance of hardware and the powerful computing power of artificial intelligence, the encryption standards widely used today are likely to be cracked by artificial intelligence through a large number of calculations. For the above reasons, it is necessary to improve the existing encryption technology. Summary of the invention

[0005] To solve the above problems, the present application provides a hybrid parallel computing encryption and decryption system, including a transmitting end device and a receiving end device. The data generation module includes an encryption level setter and a four-stage encryptor, wherein the four-stage encryptor includes a parallel stream encryptor, a sixty-four-bit stream encryptor, a one hundred and twenty-eight-bit stream encryptor, and a two hundred and fifty-six-bit stream encryptor connected in sequence, the encryption level setter is used to select an encryption level, the data encryption module obtains at least one data packet from the data generation module, and the four-stage encryptor encrypts the data packet according to the encryption level and outputs an encryption sequence. The receiving device includes a data target module and a data decryption module, the data decryption module includes a decryption level setter and a four-stage decryptor, wherein the four-stage decryptor includes a parallel stream decryptor, a sixty-four-bit stream decryptor, a one hundred and twenty-eight-bit stream decryptor and a two hundred and fifty-six-bit stream decryptor connected in sequence, the decryption level corresponds to the encryption level to select the decryption level, the data decryption module obtains the encryption sequence from the transmitting device, and the four-stage decryptor decrypts the encryption sequence according to the decryption level and outputs the restored data packet.

[0006] The present application further provides a transmitting end device including a data generation module and a data encryption module. The data encryption module includes an encryption level setter and a four-stage encryptor, wherein the four-stage encryptor includes a parallel stream encryptor, a sixty-four-bit stream encryptor, a one hundred and twenty-eight-bit stream encryptor, and a two hundred and fifty-six-bit stream encryptor connected in sequence, the encryption level setter is used to select an encryption level, the data encryption module obtains at least one data packet from the data generation module, and the four-stage encryptor encrypts the data packet according to the encryption level and outputs an encryption sequence.

[0007] The present application further provides a receiving end device including a data target module and a data decryption module. The data decryption module includes a decryption level setter and a four-stage decryptor, wherein the four-stage decryptor includes a parallel stream decryptor, a sixty-four-bit stream decryptor, a one hundred and twenty-eight-bit stream decryptor, and a two hundred and fifty-six-bit stream decryptor connected in sequence, the decryption level corresponds to the encryption level to select the decryption level, the data decryption module obtains an encryption sequence from the transmitting end device, and the four-stage decryptor decrypts the encryption sequence according to the decryption level and outputs a restored data packet.

[0008] Therefore, compared with the prior art, the present application can adjust the key to an internal key or an external key according to the required encryption mode and adjust the encryption level according to the needs, and can implement different encryption methods through a set of hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 Module schematic diagram of the hybrid parallel computing encryption and decryption system provided in an embodiment of the present application (I).

[0011] Figure 2 Module schematic diagram of the hybrid parallel computing encryption and decryption system provided in an embodiment of the present application (II).

[0012] Figure 3 A schematic diagram of a module of a parallel stream encryptor provided in an embodiment of the present application.

[0013] Figure 4 A module diagram of an encryption key setter provided in an embodiment of the present application.

[0014] Figure 5 A module diagram of the encryption input controller provided in an embodiment of the present application.

[0015] Figure 6 A schematic diagram of the logical operation of a parallel stream encryptor provided in an embodiment of the present application.

[0016] Figure 7 A schematic diagram of the logical operation of a fourth-order encryptor provided in an embodiment of the present application.

[0017] Figure 8 A schematic diagram of a module of a parallel stream decryptor provided in an embodiment of the present application.

[0018] Fig. 9 A schematic diagram of a module of a decryption key setter provided in an embodiment of the present application.

[0019] Fig.10 A module diagram of a decryption input controller provided in an embodiment of the present application.

[0020] Fig.11 A schematic diagram of the logical operation of a parallel stream decryptor provided in an embodiment of the present application.

[0021] Fig.12 A schematic diagram of the logical operation of a fourth-order decryptor provided in an embodiment of the present application.

[0022] Fig.13 A flow chart of a hybrid parallel computing encryption and decryption system provided in an embodiment of the present application.

[0023] Fig.14 A schematic diagram of the process flow of a fourth-order encryptor provided in an embodiment of the present application.

[0024] Fig.15 A schematic diagram of the flow of a fourth-order decryptor provided in an embodiment of the present application.

[0025] 100: hybrid parallel computing encryption and decryption system; 10: transmitter device; 12: data generation module; 14: data encryption module; 142: encryption level setter; 144: fourth-order encryptor; 1442: parallel stream encryptor; 14422: eight-bit encryption operand generator; 14422L: encryption linear feedback shift register; 14422G: generate encryption logic gate; 14424: sixteen-bit encryption operand generator; 14424L: encryption linear feedback shift register; 14424G: generate encryption logic gate; 14426: thirty-two-bit encryption operand generator; 14426L: encryption linear feedback shift register; 14426G: generate encryption logic gate; 1442O: external encryption key input 14422O: encryption key generator; 14424O: encryption controller; 1442I: internal decryption key storage; G1: encryption logic operator; G12: encryption logic operation module; G14: data encryption logic gate; 1444: 64-bit stream encryptor; 1444L: encryption linear feedback shift register; 1444G: encryption logic gate; 1446: 128-bit stream encryptor; 1446L: encryption linear feedback shift register; 1446G: encryption logic gate; 1448: 256-bit stream encryptor; 1448L: encryption linear feedback shift register; 1448G: encryption logic gate; 146: encryption key setter; 20: receiving end device; 22: data target Module; 24: Data decryption module; 242: Decryption level setter; 244: Four-level decryptor; 2442: Parallel stream decryptor; 24422: Eight-bit decryption operand generator; 24422L: Decryption linear feedback shift register; 24422G: Generate decryption logic gate; 24424: Sixteen-bit decryption operand generator; 24424L: Decryption linear feedback shift register; 24424G: Generate decryption logic gate; 24426: Thirty-two-bit decryption operand generator; 24426L: Decryption linear feedback shift register; 24426G: Generate decryption logic gate; 2442O: External decryption key input; 24422O: Decryption key generator; 24424O: Decryption controller; 24 42I: internal decryption key storage; G2: decryption logic operator; G22: decryption logic operation module; G24: data decryption logic gate; 2444: sixty-four-bit stream decryptor; 2444L: decryption linear feedback shift register; 2444G: decryption logic gate; 2446: one hundred and twenty-eight-bit stream decryptor; 2446L: decryption linear feedback shift register; 2446G: decryption logic gate; 2448: two hundred and fifty-six-bit stream decryptor; 2448L: decryption linear feedback shift register; 2448G: decryption logic gate; 246: decryption key setter; 30: encryption input controller; 32: encryption input; 34: encryption controller; 40: decryption input controller; 42: decryption input;44: decryption controller; A1: encryption operand; B1: encryption operand; C1: encryption operand; D1: encryption operand; E1: encryption operand; F1: encryption operand; A2: decryption operand; B2: decryption operand; C2: decryption operand; D2: decryption operand; E2: decryption operand; F2: decryption operand; ES1: first encryption sequence; ES2: second encryption sequence; ES3: third encryption sequence; ES4: fourth encryption sequence. ; DETAILED DESCRIPTION

[0026] The detailed description and technical content of this application are described below with reference to the accompanying drawings. Figure 1 , is a module diagram (I) of the parallel computing encryption and decryption system of this application, as shown in the figure:

[0027] This embodiment mainly provides a hybrid parallel computing encryption and decryption system 100, which is used to encrypt and decrypt the data transmitted by the devices when multiple devices transmit data to each other. The device that generates data or receives data can be a computer, a server, a mobile device, an Internet of Things device (for example, a monitor, a television, a cloud hard drive, a lamp, etc.), a large number of manufacturing equipment or machines, etc., which are not limited in this application. In this application, the device is defined as a transmitter device 10 as a data transmission source and a receiving device 20 corresponding to the transmitter device 10 for receiving the data of the transmitter device 10 based on the signal transmission and reception relationship. It should be noted that this application is not limited to the transmitter device 10 only performing the data encryption function and the receiving device 20 only performing the data decryption function. Specifically, the transmitter device 10 and the receiving device 20 described herein generally have encryption and decryption functions at the same time to ensure that the data is encrypted or decrypted with each other's keys during the two-way transmission process, which must be stated in advance.

[0028] Data can be transmitted between the transmitting device 10 and the receiving device 20 via a wired or wireless network.

[0029] In one preferred embodiment, the transmitting device 10 and the receiving device 20 can transmit data through the Internet, a local area network, or between any wired or wireless communication ports, which is not limited in this application. In order to complete the functions of data encryption, decryption and transmission, the transmitting device 10 and the receiving device 20 should at least include a processor, a storage unit, and a communication unit to cooperate with each other to complete the corresponding functions, such as a physical line network card, a wireless network card, a Bluetooth module, a Zigbee module, etc. The transmission method and transmission interface of the signal are not within the scope of the application.

[0030] In one embodiment, the modules, devices, units or their combinations and the corresponding functions performed in the hybrid parallel computing encryption and decryption system 100 of the present application can be collaboratively executed by a single chip or a combination of multiple chips, and the number of chip configurations is not within the scope of the present application. In addition, the chip can be, but is not limited to, a processor, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), and other similar devices or combinations of these devices that can process, convert or perform special purposes on information or signals, which are not limited in the present application.

[0031] In one embodiment, the transmitting device 10 mainly includes a data generation module 12 and a data encryption module 14. The data generation module 12 can be, for example, a cache memory, a dynamic random access memory (DRAM), or a persistent memory for storing and managing data to be transmitted and encrypted. The data encryption module 14 obtains at least one data packet from the data generation module 12. The data encryption module 14 can be a processor or a microprocessor for performing encryption calculation processing, which is not limited in this application. Finally, the data encryption module 14 outputs the encrypted data packet to the receiving device 20. The encrypted data packet output by the data encryption module 14 is defined as an encryption sequence.

[0032] In one embodiment, please refer to Figure 2The data encryption module 14 includes an encryption level setter 142 and a fourth-order encryptor 144. The output end of the encryption level setter 142 is connected to the input end of the fourth-order encryptor 144. The encryption level setter 142 is used to select the encryption level of the fourth-order encryptor 144. The fourth-order encryptor 144 encrypts the data packet according to the encryption level and outputs an encrypted sequence.

[0033] In one embodiment, the data encryption module 14 further includes an encryption key setter 146, the output end of the encryption key setter 146 is connected to another input end of the fourth-order encryptor 144, and the encryption key setter 146 selects an external encryption key mode or an internal encryption key mode.

[0034] In one embodiment, the four-stage encryptor 144 includes a parallel stream encryptor 1442, a sixty-four-bit stream encryptor 1444, a one hundred and twenty-eight-bit stream encryptor 1446, and a two hundred and fifty-six-bit stream encryptor 1448 connected in sequence. Figure 3 The parallel stream encryptor 1442 includes an 8-bit encryption operand generator 14422, a 16-bit encryption operand generator 14424, a 32-bit encryption operand generator 14426, an external encryption key input device 1422O, an internal encryption key storage device 1442I, and an encryption logic operator G1. (The 8-bit encryption operand generator 14422, the 16-bit encryption operand generator 14424, and the 32-bit encryption operand generator 14426 are collectively referred to as encryption operand generators.) The output end of the encryption key setter 146 is connected to the input end of the external encryption key input device 1442O and the output end of the internal encryption key storage device 1442I, respectively. The encryption key setter 146 is used to select an external encryption key mode or an internal encryption key mode. In the external encryption key mode, the external encryption key input device 1442O is started and the external encryption key is output. In the internal encryption key mode, the internal encryption key storage device 1442I is started and the internal encryption key is output. The output end of the external encryption key input 1442O is connected to the input end of the encryption operand generator, and the output end of the internal encryption key storage 1442I is connected to another input end of the encryption operand generator. The encryption operand generator generates encryption operands according to the external encryption key generated by the external encryption key input or the internal encryption key stored in the internal encryption key storage. The encryption operands and the data packet are operated via the encryption logic operator G1 to obtain a first encryption sequence ES1.

[0035] In one embodiment, see Figure 4, the eight-bit encryption operand generator 14422, the sixteen-bit encryption operand generator 14424, and the thirty-two-bit encryption operand generator 14426 respectively include an encryption linear feedback shift register (LFSR) and one or more encryption logic gates (LogicGate). The encryption linear feedback shift register has the internal encryption key or the external encryption key. The encryption linear feedback shift register performs a logical operation on multiple encryption bit taps of the internal encryption key or the external encryption key through the encryption logic gate to obtain the encryption operand. The encryption operand will be fed back to the first bit of the encryption linear feedback shift register as an update of the encryption key. The update means that the encryption operand will be input into the first bit of the encryption key of the encryption linear feedback shift register, so that the original first bit of the encryption key is moved to the second bit, the original second bit of the encryption key is moved to the third bit, and so on. The last bit of the original encryption key will be overwritten by the previous bit, thereby achieving the update of the encryption key. The eight-bit encryption operand generator 14422 includes an encryption linear feedback shift register 14422L (stores eight-bit encryption keys a[1] to a[8], a[n] is the nth bit of the eight-bit encryption key) and generates an encryption logic gate 14422G. The sixteen-bit encryption operand generator 14424 includes an encryption linear feedback shift register 14424L (stores sixteen-bit encryption keys b[1] to b

[16] , b[n] is the nth bit of the thirty-two-bit encryption key) and generates an encryption logic gate 14424G. The thirty-two-bit encryption operand generator 14426 includes an encryption linear feedback shift register 14426L (stores thirty-two-bit encryption keys c[1] to c

[32] , c[n] is the nth bit of the thirty-two-bit encryption key) and generates an encryption logic gate 14426G. The eight-bit encryption key, the sixteen-bit encryption key and the thirty-two-bit encryption key can be internal encryption keys or external encryption keys. The encryption linear feedback shift register 14422L performs a logical operation on multiple encryption bit taps of an eight-bit encryption key through a generated encryption logic gate 14422G to obtain an encryption operand A1; the encryption linear feedback shift register 14424L performs a logical operation on multiple encryption bit taps of a sixteen-bit encryption key through a generated encryption logic gate 14424G to obtain an encryption operand B1; the encryption linear feedback shift register 14426L performs a logical operation on multiple encryption bit taps of a thirty-two-bit encryption key through a generated encryption logic gate 14426G to obtain an encryption operand C1.

[0036] In one embodiment, the generated encryption logic gates 14422G, 14424G, 14426G and logic operations all use Exclusive Or (XOR) as operations.

[0037] In one embodiment, the generated encryption logic gates 14422G, 14424G, 14426G and logic operations can be implemented using AND gates, OR gates, other logic gates or a combination of multiple logic gates, which is not limited in the present application.

[0038] In one embodiment, the number of bits of the encryption bit tap is two.

[0039] In one embodiment, the number of encryption bit taps may be an even number.

[0040] In one embodiment, see Figure 5 , the external encryption key input device 1442O includes an encryption key generator 14422O and an encryption controller 14424O. The encryption key generator 14422O can be (but not limited to) a key generator (Key Generator), a random number generator (Random Number Generator, RNG) or a pseudo-random number generator (Pseudorandom Number Generator, PRNG) and other devices that can generate various sequences, which are not limited in this application. The encryption key generator 14422O generates an external encryption key according to the external encryption key mode. The encryption controller 14424O can be (but not limited to) a controller (Controller) or other devices that can control signal output, which are not limited in this application. The encryption controller 14424O outputs the external encryption key to the encryption operand generator according to the external encryption key mode.

[0041] In another embodiment, see Figure 6 , the external encryption key input device 1442O is an encryption input controller 30, and the encryption input controller 30 includes an encryption input device 32 and an encryption controller 34. The encryption input device 32 can be (but not limited to) an input device (Input Device), a keyboard (Keyboard), a computer (Computer) or other devices that can be used to provide data and control signals, which is not limited in this application. The encryption input device 32 is used to input an external encryption key. The encryption controller 34 can be (but not limited to) a controller (Controller) or other devices that can control signal output. The encryption controller 34 outputs the external encryption key to the encryption operand generator according to the input external encryption key and the external encryption key mode.

[0042] In one embodiment, the internal encryption key storage 1424I can be (but not limited to) a device such as a persistent memory that can be used to store and manage data, which is not limited in this application. The internal encryption key storage 1424I outputs the internal encryption key of the encryption operand generator according to the internal encryption key mode.

[0043] In one embodiment, see Figure 3 , the encryption logic operator G1 includes an encryption logic operation module G12 and a data encryption logic gate G14. The input end of the encryption logic operation module G12 is respectively connected to the output end of the eight-bit encryption operand generator 14422, the output end of the sixteen-bit encryption operand generator 14424 and the output end of the thirty-two-bit encryption operand generator 14426. The encryption logic operation module G12 receives the encryption operands A1, B1, C1 and calculates to obtain a parallel encryption operand. The input end of the data encryption logic gate G14 receives the parallel encryption operand and the data packet respectively. The data encryption logic gate G14 is used to encrypt the data packet via the parallel encryption operand and output the first encryption sequence ES1. The encryption logic operation module G12 and the data encryption logic gate G14 are one or more logic gates (LogicGate). The logic gates all use exclusive or gates (Exclusive Or, XOR) as operations.

[0044] In one embodiment, the logic gate can be implemented by AND gate, OR gate, other logic gates or a combination of multiple logic gates, which is not limited in the present application.

[0045] In one embodiment, see Figure 7The sixty-four-bit stream encryptor 1444, the one hundred and twenty-eight-bit stream encryptor 1446, and the two hundred and fifty-six-bit stream encryptor 1448 respectively include an encrypted linear feedback shift register (LFSR) and one or more encrypted logic gates. The encrypted linear feedback shift register has an encryption key. The encrypted linear feedback shift register performs a logic operation on multiple encryption bit taps of the encryption key through the encryption logic gate to obtain an encryption operand. The encryption operand is fed back to the first bit of the encryption linear feedback shift register as an update of the encryption key. The update means that the encryption operand will be input into the first bit of the encryption key of the encryption linear feedback shift register, so that the original first bit of the encryption key is moved to the second bit, the original second bit of the encryption key is moved to the third bit, and so on. The last bit of the original encryption key will be overwritten by the previous bit, thereby achieving the update of the encryption key. The sixty-four-bit stream encryptor 1444 includes an encryption linear feedback shift register 1444L (storing sixty-four-bit encryption keys d[1] to d

[64] , d[n] being the nth bit of the sixty-four-bit encryption key) and an encryption logic gate 1444G. The one hundred and twenty-eight-bit stream encryptor 1446 includes an encryption linear feedback shift register 1446L (storing one hundred and twenty-eight-bit encryption keys e[1] to e

[128] , d[n] being the nth bit of the one hundred and twenty-eight-bit encryption key) and an encryption logic gate 1446G. The two hundred and fifty-six-bit stream encryptor 1448 includes an encryption linear feedback shift register 1448L (storing two hundred and fifty-six-bit encryption keys f[1] to f

[256] , d[n] being the nth bit of the two hundred and fifty-six-bit encryption key) and an encryption logic gate 1448G. The encryption linear feedback shift register 1444L performs a logical operation on multiple encryption bit taps of a sixty-four-bit encryption key through an encryption logic gate 1444G to obtain an encryption operand D1; the encryption linear feedback shift register 1446L performs a logical operation on multiple encryption bit taps of a one hundred and twenty-eight-bit encryption key through an encryption logic gate 1446G to obtain an encryption operand E1; the encryption linear feedback shift register 1448L performs a logical operation on multiple encryption bit taps of a two hundred and fifty-six-bit encryption key through an encryption logic gate 1448G to obtain an encryption operand F1.

[0046] In one embodiment, the encryption logic gates 1444G, 1446G, 1448G and logic operations all use Exclusive Or (XOR) as operations.

[0047] In one embodiment, the encryption logic gates 1444G, 1446G, 1448G and logic operations can be implemented using AND gates, OR gates, other logic gates or a combination of multiple logic gates, which are not limited in this application. In one embodiment, the number of bits of the encryption bit tap is two.

[0048] In one embodiment, the number of encryption bit taps may be an even number.

[0049] In one embodiment, see Figure 1 , the receiving device 20 includes a data target module 22 and a data decryption module 24. The data target module 22 can also be a cache memory, a dynamic random access memory (DRAM), or a persistent memory to store and manage the received data. The data decryption module 24 can be a processor or a microprocessor for performing decryption calculation processing, which is not limited in this application. Finally, the data decryption module 24 is used to decrypt the received encryption sequence through the internal decryption key mode and the external decryption key encryption mode corresponding to the internal encryption key mode and the external encryption key mode, and then output the restored original data packet to the data target module 22 for storage.

[0050] In one embodiment, please refer to Figure 2 The data decryption module 24 includes a decryption level setter 242 and a fourth-order decryptor 244. The output end of the decryption level setter 242 is connected to the input end of the fourth-order decryptor 244. The decryption level setter 242 is used to select the decryption level of the fourth-order decryptor 244. The fourth-order decryptor 244 decrypts the encrypted sequence according to the decryption level and outputs the data packet.

[0051] In one embodiment, the data decryption module 24 further includes a decryption key setter 246 , the output end of the decryption key setter 246 is connected to another input end of the fourth-order decryptor 244 , and the decryption key setter 246 selects an external decryption key mode or an internal decryption key mode.

[0052] In one embodiment, the four-stage decryptor 244 includes a parallel stream decryptor 2442, a sixty-four-bit stream decryptor 2444, a one hundred and twenty-eight-bit stream decryptor 2446, and a two hundred and fifty-six-bit stream decryptor 2448 connected in sequence. Figure 8The parallel stream decryptor 2442 includes an 8-bit decryption operand generator 24422, a 16-bit decryption operand generator 24424, a 32-bit decryption operand generator 24426, an external decryption key input device 2442O, an internal decryption key storage device 2442I, and a decryption logic operator G2. (The 8-bit decryption operand generator 24422, the 16-bit decryption operand generator 24424, and the 32-bit decryption operand generator 24426 are collectively referred to as decryption operand generators.) The output end of the decryption key setter 246 is connected to the input end of the external decryption key input device 2442O and the output end of the internal decryption key storage device 2442I, respectively. The decryption key setter 246 is used to select an external decryption key mode or an internal decryption key mode. In the external decryption key mode, the external decryption key input device 2442O is activated and outputs an external decryption key. In the internal decryption key mode, the internal decryption key storage device 2442I is activated and outputs an internal decryption key. The output end of the external decryption key input 2442O is connected to the input end of the decryption operand generator, and the output end of the internal decryption key storage 2442I is connected to another input end of the decryption operand generator. The decryption operand generator generates a decryption operand based on the external decryption key generated by the external decryption key input or the internal decryption key stored in the internal decryption key storage. The decryption operand and the first encryption sequence ES1 are operated via the decryption logic operator G2 to obtain a restored data packet.

[0053] In one embodiment, see Fig. 9, the eight-bit decryption operand generator 24422, the sixteen-bit decryption operand generator 24424, and the thirty-two-bit decryption operand generator 24426 respectively include a decryption linear feedback shift register (LFSR) and one or more decryption logic gates (LogicGate). The decryption linear feedback shift register has the internal decryption key or the external decryption key. The decryption linear feedback shift register performs a logical operation on multiple decryption bit taps of the internal decryption key or the external decryption key through the decryption logic gate to obtain the decryption operand. The decryption operand will be fed back to the first bit of the decryption linear feedback shift register as an update of the decryption key. The update means that the decryption operand will be input into the first bit of the decryption key of the decryption linear feedback shift register, so that the original first bit of the decryption key is moved to the second bit, the original second bit of the decryption key is moved to the third bit, and so on. The last bit of the original decryption key will be overwritten by the previous bit, thereby achieving the update of the decryption key. The eight-bit decryption operand generator 24422 includes a decryption linear feedback shift register 24422L (which stores an eight-bit decryption key identical to the eight-bit encryption key a[1] to a[8], and this number is the same as the eight-bit encryption key) and generates a decryption logic gate 24422G. The sixteen-bit decryption operand generator 24424 includes a decryption linear feedback shift register 24424L (which stores a sixteen-bit decryption key identical to the sixteen-bit encryption key b[1] to b

[16] , and this number is the same as the sixteen-bit encryption key) and generates a decryption logic gate 24424G. The thirty-two-bit decryption operand generator 24426 includes a decryption linear feedback shift register 24426L (which stores a thirty-two-bit decryption key identical to the thirty-two-bit encryption key c[1] to c

[32] , and this number is the same as the thirty-two-bit encryption key) and generates a decryption logic gate 24426G. The eight-bit decryption key, the sixteen-bit decryption key, and the thirty-two-bit decryption key can be internal decryption keys or external decryption keys. The decryption linear feedback shift register 24422L performs a logical operation on multiple decryption bit taps of an eight-bit decryption key through a generated decryption logic gate 24422G to obtain a decryption operand A2; the decryption linear feedback shift register 24424L performs a logical operation on multiple decryption bit taps of a sixteen-bit decryption key through a generated decryption logic gate 24424G to obtain a decryption operand B2; the decryption linear feedback shift register 24426L performs a logical operation on multiple decryption bit taps of a thirty-two-bit decryption key through a generated decryption logic gate 24426G to obtain a decryption operand C2.In principle, the generated decryption logic gates 24422G, 24424G, and 24426G in the parallel stream decryptor 2442 must perform reverse logic operations with the parallel stream encryptor 1442 (for example, if the parallel stream encryptor 1442 is an AND gate, then the parallel stream decryptor 2442 is a NAND gate).

[0054] In one embodiment, the number of bits of the decryption bit tap is two.

[0055] In one embodiment, the number of decryption bit taps may be an even number.

[0056] In one embodiment, see Fig.10 , the external decryption key input device 2442O includes a decryption key generator 24422O and a decryption controller 24424O. The decryption key generator 24422O can be (but not limited to) a key generator (Key Generator), a random number generator (Random Number Generator, RNG) or a pseudo-random number generator (Pseudorandom Number Generator, PRNG) and other devices that can generate various sequences, which are not limited in this application. The decryption key generator 24422O generates an external decryption key according to the external decryption key mode. The decryption controller 24424O can be (but not limited to) a controller (Controller) or other devices that can control signal output, which are not limited in this application. The decryption controller 24424O outputs the external decryption key to the decryption operand generator according to the external decryption key mode.

[0057] In another embodiment, see Fig.11 , the external decryption key input device 2442O is a decryption input controller 40, and the decryption input controller 40 includes a decryption input device 42 and a decryption controller 44. The decryption input device 42 can be (but not limited to) an input device (Input Device), a keyboard (Keyboard), a computer (Computer) or other devices that can be used to provide data and control signals, which is not limited in this application. The decryption input device 42 is used to input an external decryption key. The decryption controller 44 can be (but not limited to) a controller (Controller) or other devices that can control signal output. The decryption controller 44 outputs the external decryption key to the decryption operand generator according to the input external decryption key and the external decryption key mode.

[0058] In one embodiment, the internal decryption key storage 24242I can be (but not limited to) a device such as a persistent memory that can be used to store and manage data, which is not limited in this application. The internal decryption key storage 24242I outputs the internal decryption key of the decryption operand generator according to the internal decryption key mode.

[0059] In one embodiment, see Figure 8 The decryption logic operator G2 includes a decryption logic operation module G22 and a data decryption logic gate G24. The input end of the decryption logic operation module G22 is respectively connected to the output end of the eight-bit decryption operand generator 24422, the output end of the sixteen-bit decryption operand generator 24424, and the output end of the thirty-two-bit decryption operand generator 24426. The decryption logic operation module G22 receives the decryption operands A2, B2, and C2 and calculates to obtain a parallel decryption operand. The input end of the data decryption logic gate G24 receives the parallel decryption operand and the first encryption sequence ES1 respectively. The data decryption logic gate G24 is used to decrypt the first encryption sequence ES1 through the parallel decryption operand and output the restored data packet. The decryption logic operation module G22 and the data decryption logic gate G24 are one or more logic gates. In principle, the decryption logic operation module G22 and the data decryption logic gate G24 must perform reverse logic operations with the parallel stream encryptor 1442 (for example, if the parallel stream encryptor 1442 is AND, the parallel stream decryptor 2442 is NAND).

[0060] In one embodiment, see Fig.12The sixty-four-bit stream decryptor 2444, the one hundred and twenty-eight-bit stream decryptor 2446, and the two hundred and fifty-six-bit stream decryptor 2448 respectively include a decryption linear feedback shift register (LFSR) and one or more decryption logic gates. The decryption linear feedback shift register has a decryption key. The decryption linear feedback shift register performs a logic operation on multiple decryption bit taps of the decryption key through the decryption logic gates to obtain a decryption operand. The decryption operand is fed back to the first bit of the decryption linear feedback shift register as an update of the decryption key. The update means that the decryption operand will be input into the first bit of the decryption key of the decryption linear feedback shift register, so that the original first bit of the decryption key is moved to the second bit, the original second bit of the decryption key is moved to the third bit, and so on. The last bit of the original decryption key will be overwritten by the previous bit, thereby achieving the update of the decryption key. The sixty-four-bit stream decryptor 2444 includes a decryption linear feedback shift register 2444L (storing sixty-four-bit decryption keys d[1] to d

[64] , d[n] being the nth bit of the sixty-four-bit decryption key) and a decryption logic gate 2444G. The one hundred and twenty-eight-bit stream decryptor 2446 includes a decryption linear feedback shift register 2446L (storing one hundred and twenty-eight-bit decryption keys e[1] to e

[128] , d[n] being the nth bit of the one hundred and twenty-eight-bit decryption key) and a decryption logic gate 2446G. The two hundred and fifty-six-bit stream decryptor 2448 includes a decryption linear feedback shift register 2448L (storing two hundred and fifty-six-bit decryption keys f[1] to f

[256] , d[n] being the nth bit of the two hundred and fifty-six-bit decryption key) and a decryption logic gate 2448G. The decryption linear feedback shift register 2444L taps off multiple decryption bits of the sixty-four-bit decryption key and performs a logical operation to obtain a decryption operand D2. The decryption operand D2 and the second encryption sequence ES2 are logically operated with the decryption logic gate 2444G to obtain the first encryption sequence ES1; the decryption linear feedback shift register 2446L taps off multiple decryption bits of the one hundred and twenty-eight-bit decryption key and performs a logical operation to obtain a decryption operand E2. The decryption operand E2 and the third encryption sequence ES3 are logically operated with the decryption logic gate 2446G to obtain the second encryption sequence ES2; the decryption linear feedback shift register 2448L taps off multiple decryption bits of the two hundred and fifty-six-bit decryption key and performs a logical operation to obtain a decryption operand F2. The decryption operand F2 and the fourth encryption sequence ES4 are logically operated with the decryption logic gate 2448G to obtain the third encryption sequence ES3.

[0061] In one embodiment, the decryption logic gates 2444G, 2446G, 2448G and logic operations all use Exclusive Or (XOR) as operations.

[0062] In one embodiment, the decryption logic gates 2444G, 2446G, 2448G and logic operations can be implemented using AND gates, OR gates, other logic gates or a combination of multiple logic gates, which is not limited in this application.

[0063] In one embodiment, the number of bits of the decryption bit tap is two.

[0064] In one embodiment, the number of decryption bit taps may be an even number.

[0065] The above is a description of a specific embodiment of the hardware architecture of the present application. The working procedure of the present application will be further described below. Please refer to Fig.13 , is a flow chart of the hybrid parallel computing encryption and decryption system of this application:

[0066] Before data transmission, the encryption level setter 142 and the decryption level setter 242 will set the same encryption / decryption level according to the user setting / automatic configuration (for example, when the encryption level setter 142 selects the encryption level of the fourth-level encryptor 144 as the third level, the decryption level setter 242 will select the decryption level of the fourth-level decryptor 244 as the third level), which is explained here in advance.

[0067] Similarly, the encryption key setter 146 and the decryption key setter 246 will set the same external key encryption / decryption mode and internal key encryption / decryption mode according to the user setting / automatic configuration. For example, when the encryption key setter 146 selects the 8-bit encryption operand generator 14422 of the fourth-order encryptor 144 as the external encryption key mode, the 16-bit encryption operand generator 14424 as the external encryption key mode, and the 32-bit encryption operand generator 14426 as the internal encryption key mode (setting two external encryption key modes and one internal encryption key mode), the decryption key setter 246 selects the 8-bit decryption operand generator 24422 of the fourth-order decryptor 244 as the external decryption key mode, the 16-bit decryption operand generator 24424 as the external decryption key mode, and the 32-bit decryption operand generator 24426 as the internal decryption key mode (setting two external decryption key modes and one internal decryption key mode).

[0068] Specifically, the encryption operand generator can be various permutations and combinations of external encryption key modes and internal encryption key modes; the decryption operand generator can be various permutations and combinations of external decryption key modes and internal decryption key modes matched with the encryption operand generator. Specifically, any one or more of the encryption operand generators can be set to an external encryption key mode or an internal encryption key mode according to the aforementioned permutations and combinations; any one or more of the decryption operand generators can be set to an external decryption key mode or an internal decryption key mode according to the combination of the encryption operand generator. The aforementioned various permutations, combinations and changes are not within the scope intended to be limited by the present application (for example: when setting one external encryption key mode and two internal encryption key modes, one external decryption key mode and two internal decryption key modes will be set accordingly, when three external decryption key modes are set accordingly, three external decryption key modes will be set accordingly, and when three internal encryption key modes are set accordingly, three internal decryption key modes will be set accordingly).

[0069] First, in the transmitting end device 10 , the data packet is output from the data generating module 12 to the data encryption module 14 (step S201 ).

[0070] The data packet is received by the fourth-order encryptor 144 of the data encryption module 14 and is encrypted according to the encryption level and the outer encryption key mode or the inner encryption key mode set by the encryption level setter 142 and the encryption key setter 146 (step S202 ).

[0071] The encrypted data packet is outputted as an encrypted sequence by the fourth-order encryptor 144 to the receiving device 20 (step S203 ).

[0072] The encrypted sequence is decrypted by the fourth-order decryptor 244 in the data decryption module 24 according to the decryption package and the external decryption key mode or the internal decryption key mode set by the decryption level setter 242 and the decryption key setter 246 (step S204 ).

[0073] The decrypted encrypted sequence is outputted by the fourth-order decryptor 244 as a restored data packet to the data target module 22 for storage (step S205 ).

[0074] The following specifically lists an embodiment, wherein the fourth-order encryptor 144 includes a parallel stream encryptor 1442, a sixty-four-bit stream encryptor 1444, a one hundred and twenty-eight-bit stream encryptor 1446, and a two hundred and fifty-six-bit stream encryptor 1448 connected in sequence, wherein the parallel stream encryptor 1442 includes an eight-bit encryption operand generator 14422, a sixteen-bit encryption operand generator 14424, a thirty-two-bit encryption operand generator 14426, an external encryption key input device 1442O, an internal encryption key storage device 1442I, and an encryption logic operation. The fourth-order decryptor 244 includes a parallel stream decryptor 2442, a sixty-four-bit stream decryptor 2444, a one hundred and twenty-eight-bit stream decryptor 2446, and a two hundred and fifty-six-bit stream decryptor 2448 connected in sequence, wherein the parallel stream decryptor 2442 includes an eight-bit decryption operand generator 24422, a sixteen-bit decryption operand generator 24424, a thirty-two-bit decryption operand generator 24426, an external decryption key input device 2442O, an internal decryption key storage device 2442I, and a decryption logic operator G2. Fig.14 , Fig.15 , which is a schematic diagram of the encryption process of the fourth-order encryptor 144 and the decryption process of the fourth-order decryptor 244 of the present application.

[0075] The aforementioned step S202 can be replaced by one or more steps among steps S2021-S2024 according to the encryption level, and the multiple steps must exist in sequence (for example: in the case of the third-level encryption level, step S202 needs to be replaced by the corresponding step S2023, and steps S2021 and S2022 must also be included at this time, so step S202 can be replaced by steps S2021-S2023 in the case of the third-level encryption level); step S204 can be replaced by one or more steps among steps S2041-S2044 according to the decryption level, and the multiple steps must exist in reverse sequence (for example: in the case of the third-level decryption level, step S204 needs to be replaced by the corresponding step S2042, and steps S2043 and S2044 must also be included at this time, so step S204 can be replaced by steps S2042-S2044). The contents of the steps previously described will not be repeated here, but will be explained first.

[0076] In this embodiment, the logic operations described in the fourth-order encryptor 144 are all XOR (exclusive OR gate); the logic operations described in the fourth-order decryptor 244 are all XOR.

[0077] In one embodiment, the aforementioned logical operation can be AND, NAND and other logical operations, which are not limited in this application; in this embodiment, the multiple decryption tap bits selected by the decryption linear feedback shift register and the multiple decryption tap bits and quantity selected by the decryption feedback shift register are only one embodiment, and the decryption / decryption tap bits can be selected and changed in quantity according to actual needs (for example: select the first and seventh bits as decryption / decryption tap bits; select the fourth, fifth, sixth and eighth bits as decryption / decryption tap bits; select the second and thirty-seventh bits when there are more bits, etc.), and the selection of the decryption / decryption tap bits is not within the scope of the application. The aforementioned decryption tap bits will be selected corresponding to the encryption tap bits to match the decryption. In this embodiment, the number of encryption bit taps of the eight-bit encryption operand generator 14422, the sixteen-bit encryption operand generator 14424, the thirty-two-bit encryption operand generator 14426, the sixty-four-bit stream encryptor 1444, the one hundred and twenty-eight-bit stream encryptor 1446, and the two hundred and fifty-six-bit stream decryptor 1448 is two; the number of decryption bit taps of the eight-bit decryption operand generator 24422, the sixteen-bit decryption operand generator 24424, the thirty-two-bit decryption operand generator 24426, the sixty-four-bit stream decryptor 2444, the one hundred and twenty-eight-bit stream decryptor 2446, and the two hundred and fifty-six-bit stream decryptor 2448 is two, which is described in advance. In one embodiment, the number of bits of the aforementioned decryption bit taps and decryption bit taps is an even number.

[0078] The following describes steps S2021-S2024. Please refer to Figure 4 , Figure 7 as well as Fig.14 .

[0079] The data packet is received by the parallel stream encryptor 1442 , and the data packet is encrypted and output by the parallel stream encryptor 1442 (step S2021 ).

[0080] In one embodiment, the eight-bit encryption operand generator 14422 in the parallel stream encryptor 1442 extracts the second bit a[2] and the fifteenth bit a[7] for logical operation to obtain the encryption operand A1; the sixteen-bit encryption operand generator 14424 extracts the second bit b[2] and the fifteenth bit b

[15] for logical operation to obtain the encryption operand B1; the thirty-two-bit encryption operand generator 14426 extracts the first bit c[1] and the thirty-second bit b

[32] for logical operation to obtain the encryption operand C1, the encryption operand A1, the encryption operand B1 and the encryption operand C1 are operated via the encryption logic operation module G12 to obtain parallel encryption operands, and the data packet and the parallel encryption operand are encrypted and output via the data encryption logic gate G14. When the encryption level setter 142 is set to encryption of level two or above, the first encryption sequence ES1 output by the parallel stream encryptor 1442 will be output to the sixty-four-bit stream encryptor 1444; when the encryption level setter 142 is set to encryption of level one, the first encryption sequence ES1 output by the parallel stream encryptor 1442 will be output to the receiving device 20.

[0081] The first encrypted sequence ES1 is received by the 64-bit stream encryptor 1444 , and the first encrypted sequence ES1 is encrypted and output by the 64-bit stream encryptor 1444 (step S2022 ).

[0082] In one embodiment, the encryption linear feedback shift register 1444L of the sixty-four-bit stream encryptor 1444 extracts the second bit d[2] and the sixty-four-bit d

[64] to perform a logic operation to obtain the encryption operand D1. The encryption operand D1 and the first encryption sequence ES1 are encrypted and output via the encryption logic gate 1444G. When the encryption level setting device 142 is set to encryption of level three or above, the second encryption sequence ES2 output by the sixty-four-bit stream encryptor 1444 is output to the one hundred and twenty-eight-bit stream encryptor 1446; when the encryption level setting device 142 is set to encryption of level two, the second encryption sequence ES2 output by the sixty-four-bit stream encryptor 1444 is output to the receiving end device 20.

[0083] The second encrypted sequence ES2 is received by the one hundred and twenty-eight bit stream encryptor 1446, and the second encrypted sequence ES2 is encrypted and output by the one hundred and twenty-eight bit stream encryptor 1446 (step S2023).

[0084] In one embodiment, the encryption linear feedback shift register 1446L of the 128-bit stream encryptor 1446 extracts the first bit e[1] and the 128-bit d

[128] to perform a logic operation to obtain the encryption operand E1. The encryption operand E1 and the second encryption sequence ES2 are encrypted and output via the encryption logic gate 1446G. When the encryption level setting device 142 is set to encryption of level 4 or above, the third encryption sequence ES3 output by the 128-bit stream encryptor 1446 is output to the 256-bit stream encryptor 1448; when the encryption level setting device 142 is set to encryption of level 3, the third encryption sequence ES3 output by the 128-bit stream encryptor 1446 is output to the receiving end device 20.

[0085] The third encrypted sequence ES3 is received by the 256-bit stream encryptor 1448 , and the third encrypted sequence ES3 is encrypted and output by the 256-bit stream encryptor 1448 (step S2024 ).

[0086] In one embodiment, the encryption linear feedback shift register 1448L of the 256-bit stream encryptor 1448 extracts the first bit f[1] and the 254-bit f

[254] to perform a logic operation to obtain the encryption operand F1, and the encryption operand F1 and the third encryption sequence ES3 are encrypted and output via the encryption logic gate 1448G. When the encryption level setter 142 is set to the fourth level of encryption, the fourth encryption sequence ES4 output by the 256-bit stream encryptor 1448 will be output to the receiving end device 20.

[0087] The following describes steps S2041-S2044. Please refer to Fig. 9 , Fig.12 as well as Fig.15 .

[0088] The fourth encrypted sequence ES4 is received by the 256-bit stream decryptor 2448 , and the fourth encrypted sequence ES43 is decrypted and output by the 256-bit stream decryptor 2448 (step S2041 ).

[0089] In one embodiment, the encrypted linear feedback shift register 2448L of the 256-bit stream decryptor 2448 extracts the first bit f[1] and the 254-bit f

[254] for logical operation to obtain the encrypted operand F2. The encrypted operand F2 and the fourth encrypted sequence ES4 are decrypted via the decryption logic gate 2448G and output the third encrypted sequence ES3 to the 128-bit stream decryptor 2446.

[0090] The third encrypted sequence ES3 is received by the one hundred and twenty-eight bit stream decryptor 2446, and the third encrypted sequence ES3 is decrypted and output by the one hundred and twenty-eight bit stream decryptor 2446 (step S2042).

[0091] In one embodiment, the encryption linear feedback shift register 2446L of the one hundred and twenty-eight-bit stream decryptor 2446 extracts the first bit e[1] and the one hundred and twenty-eight bit d

[128] for logical operation to obtain the encryption operand E2. The encryption operand E2 and the third encryption sequence ES3 are decrypted via the decryption logic gate 2446G and output the second encryption sequence ES2 to the sixty-four-bit stream decryptor 2444.

[0092] The second encrypted sequence ES1 is received by the 64-bit stream decryptor 2444 , and the second encrypted sequence ES2 is decrypted and output by the 64-bit stream decryptor 2444 (step S2043 ).

[0093] In one embodiment, the encrypted linear feedback shift register 2444L of the sixty-four-bit stream decryptor 2444 extracts the second bit d[2] and the sixty-four-bit d

[64] to perform a logical operation to obtain a decryption operand D2. The decryption operand D2 and the second encrypted sequence ES1 are decrypted via the decryption logic gate 2444G and the first encrypted sequence ES1 is output to the parallel stream decryptor 2442.

[0094] The first encrypted sequence ES1 is received by the parallel stream decryptor 2442 , and the first encrypted sequence ES1 is decrypted and output by the parallel stream decryptor 2442 (step S2044 ).

[0095] In one embodiment, the eight-bit decryption operand generator 24422 in the parallel stream decryptor 2442 extracts the second bit a[2] and the fifteenth bit a[7] for logical operation to obtain the decryption operand A2; the sixteen-bit decryption operand generator 24424 extracts the second bit b[2] and the fifteenth bit b

[15] for logical operation to obtain the decryption operand B2; the thirty-two-bit decryption operand generator 24426 extracts the first bit c[1] and the thirty-second bit b

[32] for logical operation to obtain the decryption operand C2, the decryption operand A2, the decryption operand B2 and the decryption operand C2 are operated via the decryption logic operation module G22 to obtain parallel decryption operands, and the parallel decryption operands and the first encryption sequence ES1 are decrypted via the data decryption logic gate G24 and the restored data packet is output.

[0096] Compared with the prior art, the present application can adjust the key to an internal key or an external key according to the required decryption mode and adjust the decryption level according to the needs, and can implement different decryption methods through a set of hardware.

[0097] The present application has been described in detail above. However, what is described above is only a preferred embodiment of the present application and should not be used to limit the scope of implementation of the present application. That is, all equivalent changes and modifications made according to the scope of the patent application of the present application should still fall within the scope of the patent application of the present application.

Claims

1. A hybrid parallel computing encryption and decryption system, characterized in that: include: A transmitting end device, comprising a data generation module and a data encryption module, wherein the data encryption module comprises an encryption level setter and a four-stage encryptor, wherein the four-stage encryptor comprises a parallel stream encryptor, a sixty-four-bit stream encryptor, a one hundred and twenty-eight-bit stream encryptor, and a two hundred and fifty-six-bit stream encryptor connected in sequence, wherein the encryption level setter is used to select an encryption level, the data encryption module obtains at least one data packet from the data generation module, and the four-stage encryptor encrypts the data packet according to the encryption level and then outputs an encrypted sequence; and A receiving end device includes a data target module and a data decryption module, wherein the data decryption module includes a decryption level setter and a four-stage decryptor, wherein the four-stage decryptor includes a parallel stream decryptor, a sixty-four-bit stream decryptor, a one hundred and twenty-eight-bit stream decryptor, and a two hundred and fifty-six-bit stream decryptor connected in sequence, wherein the decryption level selects a decryption level corresponding to the encryption level, the data decryption module obtains the encryption sequence from the transmitting end device, and the four-stage decryptor decrypts the encryption sequence according to the decryption level and outputs the restored data packet; The data packet is received by the parallel stream encryptor, and the data packet is encrypted and output by the parallel stream encryptor; when the encryption level setting device is set to encryption of level 2 or above, the first encryption sequence output by the parallel stream encryptor is output to the 64-bit stream encryptor; when the encryption level setting device is set to encryption of level 1, the first encryption sequence output by the parallel stream encryptor is output to the receiving end device; The first encrypted sequence is received by the 64-bit stream encryptor, and the first encrypted sequence is encrypted and output by the 64-bit stream encryptor; when the encryption level setting device is set to encryption of level 3 or above, the second encrypted sequence output by the 64-bit stream encryptor is output to the 128-bit stream encryptor; when the encryption level setting device is set to encryption of level 2, the second encrypted sequence output by the 64-bit stream encryptor is output to the receiving end device; The second encrypted sequence is received by the 128-bit stream encryptor, and the second encrypted sequence is encrypted and output by the 128-bit stream encryptor; when the encryption level setting device is set to encryption of level 4 or above, the third encrypted sequence output by the 128-bit stream encryptor is output to the 256-bit stream encryptor; when the encryption level setting device is set to encryption of level 3, the third encrypted sequence output by the 128-bit stream encryptor is output to the receiving end device; The third encrypted sequence is received by the 256-bit stream encryptor, and the third encrypted sequence is encrypted and output by the 256-bit stream encryptor; When the encryption level setting device is set to the fourth level of encryption, the fourth encryption sequence output by the 256-bit stream encryptor will be output to the receiving end device.

2. The hybrid parallel computing encryption and decryption system according to claim 1, characterized in that: The sixty-four-bit stream encryptor, the one hundred and twenty-eight-bit stream encryptor and the two hundred and fifty-six-bit stream encryptor respectively include an encryption linear feedback shift register and one or more encryption logic gates, the encryption linear feedback shift register has an encryption key, the encryption linear feedback shift register performs a logic operation on multiple encryption bit taps of the encryption key through the encryption logic gate to obtain an encryption operand, the encryption operand and the data packet are encrypted through the encryption logic gate to obtain the encryption sequence; the sixty-four-bit stream decryptor, the one hundred and twenty-eight-bit stream decryptor and the two hundred and fifty-six-bit stream decryptor respectively include a decryption linear feedback shift register and one or more decryption logic gates, the decryption linear feedback shift register has a decryption key, the decryption linear feedback shift register performs a logic operation on multiple decryption bit taps of the decryption key through the decryption logic gate to obtain a decryption operand, the decryption operand and the encryption sequence are decrypted through the decryption logic gate to obtain the restored data packet.

3. The hybrid parallel computing encryption and decryption system according to claim 1, characterized in that: The data encryption module also includes an encryption key setter, the parallel stream encryptor includes an eight-bit encryption operand generator, a sixteen-bit encryption operand generator, a thirty-two-bit encryption operand generator, an external encryption key input device, an internal encryption key storage device and an encryption logic operator, the encryption key setter selects an external encryption key mode or an internal encryption key mode, the eight-bit encryption operand generator, the sixteen-bit encryption operand generator and the thirty-two-bit encryption operand generator respectively generate encryption operands according to the external encryption key generated by the external encryption key input device or the internal encryption key stored in the internal encryption key storage device, and the encryption operands and the data packet are operated by the encryption logic operator to obtain a first encryption sequence; the data decryption module The invention also includes a decryption key setter, wherein the parallel stream decryptor includes an eight-bit decryption operand generator, a sixteen-bit decryption operand generator, a thirty-two-bit decryption operand generator, an external decryption key input device, an internal decryption key storage device and a decryption logic operator. The decryption key setter selects an external decryption key mode or an internal decryption key mode in response to the encryption key setter. The eight-bit decryption operand generator, the sixteen-bit decryption operand generator and the thirty-two-bit decryption operand generator respectively generate decryption operands according to the external decryption key generated by the external decryption key input device or the internal decryption key stored in the internal decryption key storage device. The decryption operand and the first encryption sequence are operated by the decryption logic operator to obtain the restored data packet.

4. The hybrid parallel computing encryption and decryption system as claimed in claim 3, characterized in that: The external encryption key input device includes an encryption key generator and an encryption controller, wherein the encryption key generator generates the external encryption key according to the external encryption key mode, and the encryption controller outputs the external encryption key according to the external encryption key mode; The decryption key input device includes a decryption key generator and a decryption controller. The decryption key generator generates the external decryption key according to the external decryption key mode, and the decryption controller outputs the external decryption key according to the external decryption key mode.

5. The hybrid parallel computing encryption and decryption system as claimed in claim 3, characterized in that: The external encryption key input device is an encryption input controller, which includes an encryption input device and an encryption controller. The encryption input device is used to input the external encryption key, and the encryption controller outputs the external encryption key according to the external encryption key mode. The decryption key input device is a decryption input controller, which includes a decryption input device and a decryption controller. The decryption input device is used to input the external decryption key, and the decryption controller outputs the external decryption key according to the external decryption key mode.

6. The hybrid parallel computing encryption and decryption system according to claim 4 or claim 5, characterized in that: The eight-bit encryption operand generator, the sixteen-bit encryption operand generator, and the thirty-two-bit encryption operand generator respectively include an encryption linear feedback shift register and one or more encryption generation logic gates, the encryption linear feedback shift register has the internal encryption key or the external encryption key, and the encryption linear feedback shift register performs a logic operation on multiple encryption bit taps of the internal encryption key or the external encryption key through the encryption generation logic gate to obtain the encryption operand; the eight-bit decryption operand generator, the sixteen-bit decryption operand generator, and the thirty-two-bit decryption operand generator respectively include a decryption linear feedback shift register and one or more decryption generation logic gates, the decryption linear feedback shift register has the internal decryption key or the external decryption key, and the decryption linear feedback shift register performs a logic operation on multiple decryption bit taps of the internal decryption key or the external decryption key through the encryption generation logic gate to obtain the decryption operand.

7. A transmitting end device, characterized in that: include: Data generation module; as well as A data encryption module, the data encryption module includes an encryption level setter and a four-stage encryptor, wherein the four-stage encryptor includes a parallel stream encryptor, a sixty-four-bit stream encryptor, a one hundred and twenty-eight-bit stream encryptor, and a two hundred and fifty-six-bit stream encryptor connected in sequence, the encryption level setter is used to select an encryption level, the data encryption module obtains at least one data packet from the data generation module, and the four-stage encryptor encrypts the data packet according to the encryption level and then outputs an encrypted sequence; The data packet is received by the parallel stream encryptor, and the data packet is encrypted and output by the parallel stream encryptor; when the encryption level setting device is set to encryption of level 2 or above, the first encryption sequence output by the parallel stream encryptor is output to the 64-bit stream encryptor; when the encryption level setting device is set to encryption of level 1, the first encryption sequence output by the parallel stream encryptor is output to the receiving end device; The first encrypted sequence is received by the 64-bit stream encryptor, and the first encrypted sequence is encrypted and output by the 64-bit stream encryptor; when the encryption level setting device is set to encryption of level 3 or above, the second encrypted sequence output by the 64-bit stream encryptor is output to the 128-bit stream encryptor; when the encryption level setting device is set to encryption of level 2, the second encrypted sequence output by the 64-bit stream encryptor is output to the receiving end device; The second encrypted sequence is received by the 128-bit stream encryptor, and the second encrypted sequence is encrypted and output by the 128-bit stream encryptor; when the encryption level setting device is set to encryption of level 4 or above, the third encrypted sequence output by the 128-bit stream encryptor is output to the 256-bit stream encryptor; when the encryption level setting device is set to encryption of level 3, the third encrypted sequence output by the 128-bit stream encryptor is output to the receiving end device; The third encrypted sequence is received by the 256-bit stream encryptor, and the third encrypted sequence is encrypted and output by the 256-bit stream encryptor; When the encryption level setting device is set to the fourth level of encryption, the fourth encryption sequence output by the 256-bit stream encryptor will be output to the receiving end device.

8. The transmitting end device according to claim 7, characterized in that: The sixty-four-bit stream encryptor, the one hundred and twenty-eight-bit stream encryptor, and the two hundred and fifty-six-bit stream encryptor respectively include an encryption linear feedback shift register and one or more encryption logic gates. The encryption linear feedback shift register has an encryption key. The encryption linear feedback shift register performs a logical operation on multiple encryption bit taps of the encryption key through the encryption logic gate to obtain an encryption operand. The encryption operand and the data packet are encrypted through the encryption logic gate to obtain the encryption sequence.

9. The transmitting end device according to claim 7, characterized in that: The data encryption module also includes an encryption key setter, and the parallel stream encryptor includes an eight-bit encryption operand generator, a sixteen-bit encryption operand generator, a thirty-two-bit encryption operand generator, an external encryption key input device, an internal encryption key storage device, and an encryption logic operator. The encryption key setter selects an external encryption key mode or an internal encryption key mode. The eight-bit encryption operand generator, the sixteen-bit encryption operand generator, and the thirty-two-bit encryption operand generator respectively generate encryption operands based on the external encryption key generated by the external encryption key input device or the internal encryption key stored in the internal encryption key storage device. The encryption operands and the data packet are operated by the encryption logic operator to obtain a first encryption sequence.

10. The transmitting end device according to claim 9, characterized in that: The external encryption key input device includes an encryption key generator and an encryption controller. The encryption key generator generates the external encryption key according to the external encryption key mode, and the encryption controller outputs the external encryption key according to the external encryption key mode.

11. The transmitting end device according to claim 9, characterized in that: The external encryption key input device is an encryption input controller, which includes an encryption input device and an encryption controller. The encryption input device is used to input the external encryption key, and the encryption controller outputs the external encryption key according to the external encryption key mode.

12. The transmitting end device according to claim 10 or claim 11, characterized in that: The eight-bit encryption operand generator, the sixteen-bit encryption operand generator, and the thirty-two-bit encryption operand generator respectively include an encryption linear feedback shift register and one or more encryption generation logic gates. The encryption linear feedback shift register has the internal encryption key or the external encryption key. The encryption linear feedback shift register performs a logical operation on multiple encryption bit taps of the internal encryption key or the external encryption key through the encryption generation logic gate to obtain the encryption operand.

13. A receiving device, characterized in that: include: Data target module; as well as A data decryption module, the data decryption module includes a decryption level setter and a four-stage decryptor, wherein the four-stage decryptor includes a parallel stream decryptor, a sixty-four-bit stream decryptor, a one hundred and twenty-eight-bit stream decryptor, and a two hundred and fifty-six-bit stream decryptor connected in sequence, the decryption level selects a decryption level corresponding to the encryption level, the data decryption module obtains an encryption sequence from a transmitting end device, and the four-stage decryptor decrypts the encryption sequence according to the decryption level and outputs a restored data packet; The fourth encrypted sequence is received by the 256-bit stream decryptor, and the fourth encrypted sequence is decrypted and output by the 256-bit stream decryptor; The third encrypted sequence is received by the one hundred and twenty-eight bit stream decryptor, and the third encrypted sequence is decrypted and output by the one hundred and twenty-eight bit stream decryptor; The second encrypted sequence is received by the 64-bit stream decryptor, and the second encrypted sequence is decrypted and output by the 64-bit stream decryptor; The first encrypted sequence is received by the parallel stream decryptor, and the first encrypted sequence is decrypted and output by the parallel stream decryptor.

14. The receiving end device according to claim 13, characterized in that: The sixty-four-bit stream decryptor, the one hundred and twenty-eight-bit stream decryptor, and the two hundred and fifty-six-bit stream decryptor respectively include a decryption linear feedback shift register and one or more decryption logic gates. The decryption linear feedback shift register has a decryption key. The decryption linear feedback shift register performs a logical operation on a plurality of decryption bit taps of the decryption key through the decryption logic gate to obtain a decryption operand. The decryption operand and the encryption sequence are decrypted through the decryption logic gate to obtain the restored data packet.

15. The receiving end device according to claim 13, characterized in that: The data decryption module also includes a decryption key setter, and the parallel stream decryptor includes an eight-bit decryption operand generator, a sixteen-bit decryption operand generator, a thirty-two-bit decryption operand generator, an external decryption key input device, an internal decryption key storage device, and a decryption logic operator. The decryption key setter corresponds to the encryption key setter to select an external decryption key mode or an internal decryption key mode. The eight-bit decryption operand generator, the sixteen-bit decryption operand generator, and the thirty-two-bit decryption operand generator generate decryption operands according to the external decryption key generated by the external decryption key input device or the internal decryption key stored in the internal decryption key storage device. The decryption operand and the first encryption sequence are operated by the decryption logic operator to obtain the restored data packet.

16. The receiving end device according to claim 15, characterized in that: The decryption key input device includes a decryption key generator and a decryption controller. The decryption key generator generates the external decryption key according to the external decryption key mode, and the decryption controller outputs the external decryption key according to the external decryption key mode.

17. The receiving end device according to claim 15, characterized in that: The decryption key input device is a decryption input controller, which includes a decryption input device and a decryption controller. The decryption input device is used to input the external decryption key, and the decryption controller outputs the external decryption key according to the external decryption key mode.

18. The receiving end device according to claim 16 or claim 17, characterized in that: The eight-bit decryption operand generator, the sixteen-bit decryption operand generator, and the thirty-two-bit decryption operand generator respectively include a decryption linear feedback shift register and one or more generation decryption logic gates, the decryption linear feedback shift register has the internal decryption key or the external decryption key, and the decryption linear feedback shift register performs a logical operation on multiple decryption bit taps of the internal decryption key or the external decryption key through the generation decryption logic gates to obtain the decryption operand.

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