Integrated capacitor with extended head bump bond pillars
By forming conductive pillars and extension heads in microelectronic devices, the problem of large capacitor footprint is solved, enabling tight integration and increased capacitance of capacitors at high frequencies, thus meeting the high-frequency operation requirements of microelectronic devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2020-09-28
- Publication Date
- 2026-08-04
AI Technical Summary
In microelectronic devices operating at high frequencies, the use of capacitors increases device size and makes it difficult to integrate them tightly with other microelectronic devices.
By forming conductive pillars and extensions in microelectronic devices, and using conductive materials of the same composition to form both pillars and extensions simultaneously, electrical coupling is achieved. The plates of the integrated capacitor are provided by the extensions, reducing the area occupied by the device.
This allows for increased capacitor integration and capacitance without increasing the size of microelectronic devices, while reducing the area occupied by the devices.
Smart Images
Figure CN114450771B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of microelectronic devices. More specifically, this disclosure relates to integrated capacitors in microelectronic devices. Background Technology
[0002] Some microelectronic devices operate at high frequencies and use capacitors to regulate high-frequency currents. These capacitors should be tightly integrated with the microelectronic device to achieve better performance. However, capacitors require a large area and may unnecessarily increase the size of the microelectronic device. Summary of the Invention
[0003] This disclosure discloses a microelectronic device having a die with a connection surface, a first conductive pillar, and a second conductive pillar. These pillars are mechanically coupled to the connection surface. The microelectronic device includes a first conductive extension electrically coupled to the first pillar and a second conductive extension electrically coupled to the second pillar. The first and second pillars have conductive materials of the same composition, and the first and second extensions also have conductive materials of the same composition. The first extension provides a bump pad for the microelectronic device, and the second extension provides at least a portion of the electrode of an integrated capacitor of the microelectronic device. The microelectronic device is formed by simultaneously forming the first and second pillars and simultaneously forming the first and second extensions. Attached Figure Description
[0004] Figures 1A to 1G This is a cross-section of an example microelectronic device with integrated capacitors, depicted at various stages of the example formation method.
[0005] Figures 2A to 2F This is a cross-section of another example microelectronic device with integrated capacitors, depicted at various stages of another example formation method.
[0006] Figures 3A to 3J This is a cross-section of a further example microelectronic device with integrated capacitors, depicted at various stages of a further example formation method.
[0007] Figures 4A to 4G This is a cross-section of another example microelectronic device with integrated capacitors, depicted at various stages of another example formation method.
[0008] Figures 5A to 5C This is a cross-section of a further example microelectronic device with integrated capacitors, depicted at various stages of a further example formation method. Detailed Implementation
[0009] This disclosure has been described with reference to the accompanying drawings. These drawings are not to scale and are for illustrative purposes only. Several aspects of this disclosure are described below with reference to example applications for illustrative purposes. It should be understood that many specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the order of actions or events shown, as some actions may occur in a different order and / or simultaneously with other actions or events. Furthermore, not all actions or events shown are necessary to implement the methods according to this disclosure.
[0010] A microelectronic device has a die such as an integrated circuit, a discrete semiconductor device, a microelectromechanical system (MEMS) device, or a microfluidic device. The die has a connection surface. External electrical connections to components of the microelectronic device are achieved at the connection surface. The microelectronic device includes a first pillar and a second pillar, both of which are conductive and mechanically coupled to the connection surface. The first and second pillars have the same conductive material composition. The microelectronic device includes a first extension electrically coupled to the first pillar and a second extension electrically coupled to the second pillar. Both the first and second extensions are conductive and have the same conductive material composition. The first extension provides a bump pad, and the second extension provides at least a portion of a first plate of an integrated capacitor of the microelectronic device. The second plate of the integrated capacitor may be located above or below the first plate. The microelectronic device is formed by simultaneously forming the first and second pillars and by simultaneously forming the first and second extensions.
[0011] It should be noted that terms such as above, above, below, and under may be used in this disclosure. These terms should not be construed as limiting the position or orientation of a structure or element, but should be used to provide spatial relationships between structures or elements.
[0012] Figures 1A to 1G This is a cross-section of an example microelectronic device with integrated capacitors, depicted at various stages of the example fabrication method. (Reference) Figure 1A The microelectronic device 100 includes a die 101. For example, the die 101 may be implemented as an integrated circuit, a discrete semiconductor device, a MEMS device, or a microfluidic device. The die 101 of this example has a substrate 102, which may include a semiconductor material such as silicon, a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, glass, sapphire, ceramic, or a polymer material such as polyimide, silicone, or polyethylene. The substrate 102 may be part of a wafer or workpiece containing additional dies, or may include only the die 101. The die 101 has a connection surface 103; as Figure 1A As shown, substrate 102 can extend to connection surface 103.
[0013] The die 101 in this example includes a first terminal 104, a second terminal 105, and a third terminal 106 at a connection surface 103. The first terminal 104, second terminal 105, and third terminal 106 are conductive and may include, for example, aluminum, copper, nickel, palladium, platinum, gold, titanium, or tungsten. For example, the first terminal 104, second terminal 105, and third terminal 106 may be implemented as bump bonding pads or through-holes through the substrate. The first terminal 104, second terminal 105, and third terminal 106 may be electrically coupled to components in the die 101 through a through-hole 107 or other interconnect elements. A protective outer coating (PO) layer 108 may be disposed above the connection surface 103 and has openings exposing the first terminal 104, second terminal 105, and third terminal 106. For example, the PO layer 108 may comprise silicon dioxide, silicon nitride, silicon oxynitride, or polyimide. The PO layer 108 may optionally be part of the die 101.
[0014] In this example, die 101 includes a second plate 109 of an integrated capacitor 110. The second plate 109 may have a composition of conductive material similar to that of the first terminal 104, the second terminal 105, and the third terminal 106. Figure 1A As shown, the second electrode 109 may be covered by the PO layer 108. The second electrode 109 may be electrically coupled to a component in the die 101 through one or more through holes 107.
[0015] A first interface layer 111 is formed above the connection surface 103 and contacts terminals 104, 105, and 106. The first interface layer 111 is conductive. The first interface layer 111 may include an adhesive sublayer (in) contacting the PO layer 108 and terminals 104, 105, and 106. Figure 1A (Not shown in the image). The adhesive sublayer may comprise titanium or tungsten, for example, to provide adhesion of the first interface layer 111 to the PO layer 108 and terminals 104, 105, and 106. The first interface layer 111 may be included in a barrier sublayer on the adhesive sublayer (in... Figure 1A (Not shown in the diagram). For example, the barrier sublayer may contain nickel, cobalt, tantalum, tantalum nitride, titanium, or titanium nitride, for example, to reduce copper diffusion from the first pillar 113, the second pillar 114, and the third pillar 115 into the die 101. Copper diffusion into the die 101 can degrade the performance of the microelectronic device 100. The first interface layer 111 may be included in a plated seed layer on the barrier sublayer (in... Figure 1A (Not shown in the image). The seed layer may contain copper, nickel, or gold to provide a low-resistivity layer suitable for electroplating. The first interface layer 111 may be formed by a series of sputtering processes, evaporation processes, cold spraying processes, or other thin film deposition processes.
[0016] A pillar mask 112 is formed on a first interface layer 111. The pillar mask 112 exposes the first interface layer 111 in regions for the first pillar 113, the second pillar 114, and the third pillar 115. The region for the first pillar 113 is located above the first terminal 104, the region for the second pillar 114 is located above the second terminal 105, and the region for the third pillar 115 is located above the third terminal 106. The pillar mask 112 may contain photoresist and may be formed using a photolithography process. Alternatively, the pillar mask 112 may be formed using a tape application process, an additive process such as material jetting or material extrusion, or a subtractive process such as laser ablation. For example, the pillar mask 112 may have a thickness from 1 micrometer to 100 micrometers.
[0017] Using a first plating process with a first plating solution 116, the first pillar 113, the second pillar 114, and the third pillar 115 are simultaneously formed on the first interface layer 111 in the area exposed by the pillar mask 112. The first plating solution 116 may contain copper ions, such that the pillars 113, 114, and 115 contain copper. In addition to copper ions, the first plating solution 116 may also contain other metal ions such as nickel ions or gold ions, such that the pillars 113, 114, and 115 contain nickel or gold, to provide the desired mechanical properties in the pillars 113, 114, and 115. The first plating process may be implemented as an electroplating process, wherein current flows from the first plating solution 116 to the first interface layer 111, thereby providing a more consistent plating rate. Alternatively, the first plating process may be implemented as a chemical plating process, thereby reducing the manufacturing complexity of the microelectronic device 100. For example, the pillars 113, 114, and 115 may have a height perpendicular to the connection surface 103 from 1 micrometer to 100 micrometers. Pillars 113, 114, and 115 are thus mechanically coupled to the connection surface 103 via the first interface layer 111. After the pillars 113, 114, and 115 are formed, the microelectronic device 100 is separated from the first plating solution 116. The pillar mask 112 remains in place for subsequent manufacturing steps.
[0018] refer to Figure 1B A second interface layer 117 is formed over the pillar mask 112 and contacts the pillars 113, 114, and 115. The second interface layer 117 is conductive. The second interface layer 117 may include an adhesive sublayer contacting the pillar mask 112 and the pillars 113, 114, and 115, and may include a plating seed layer contacting the adhesive sublayer. The adhesive sublayer of the second interface layer 117 may have a composition similar to that disclosed for the adhesive sublayer of the first interface layer 111. The plating seed layer of the second interface layer 117 may have a composition similar to that disclosed for the plating seed layer of the first interface layer 111.
[0019] A head mask 118 is formed over the second interface layer 117. The head mask 118 exposes the second interface layer 117 in the regions for the subsequent formation of the first extension head 119 and the subsequent formation of the second extension head 120; Figure 1C The first extension head 119 and the second extension head 120 are shown. (Return to Reference) Figure 1B The region for the first extension head 119 exposes a second interface layer 117 over the first pillar 113 and extends across the first pillar 113 in at least one direction parallel to the connection surface 103. The region for the second extension head 120 exposes a second interface layer 117 over the second pillar 114 and the third pillar 115, extending across the second pillar 114 in at least one direction parallel to the connection surface 103 and across the third pillar 115 in at least one direction parallel to the connection surface 103. The head mask 118 may comprise photoresist and may be formed using a photolithography process. Alternatively, the head mask 118 may be formed using a tape application process, an additive process such as material jetting or material extrusion, or a subtractive process such as laser ablation. The head mask 118 may have a different composition than the pillar mask 112, or may be formed using a different process than that used to form the pillar mask 112.
[0020] refer to Figure 1C A second electroplating process using a second plating solution 121 simultaneously forms the first extension head 119 and the second extension head 120 on the second interface layer 117 in the area exposed by the head mask 118. The second plating solution 121 may contain copper ions, such that the first extension head 119 and the second extension head 120 contain copper. In addition to copper ions, the second plating solution 121 may also contain other metal ions such as nickel ions or gold ions, such that the first extension head 119 and the second extension head 120 contain nickel or gold, to provide desired mechanical properties in the first extension head 119 and the second extension head 120. The second electroplating process may be implemented as an electroplating process in which current flows from the second plating solution 121 to the second interface layer 117, thereby providing a more consistent plating rate. Alternatively, the second electroplating process may be implemented as a chemical plating process, thereby reducing the manufacturing complexity of the microelectronic device 100. For example, the first extension head 119 and the second extension head 120 may have a thickness of 1 micrometer to 25 micrometers perpendicular to the connection surface 103. The first extension head 119 is electrically coupled to the first pillar 113 through the second interface layer 117 and extends across the first pillar 113 in at least one direction parallel to the connection surface 103. The second extension head 120 is electrically coupled to the second pillar 114 through the second interface layer 117 and extends across the second pillar 114 in at least one direction parallel to the connection surface 103. After the first extension head 119 and the second extension head 120 are formed, the microelectronic device 100 is separated from the second plating solution 121. The second extension head 120 is located above the second electrode plate 109.
[0021] refer to Figure 1D An isolation layer 123 is formed on the second extension head 120, covering a first portion of the second extension head 120 and exposing a second portion of the second extension head 120. For example, the isolation layer 123 may be implemented as a solder mask and may include, for example, epoxy resin, polyester or resin, and may be formed by dispensing, screen printing or photolithography processes.
[0022] refer to Figure 1E , Figure 1D The head mask 118 is removed. The head mask 118 can be removed by dissolving it in an organic solvent, leaving the isolation layer 123 in place. After removing the head mask 118, Figure 1D The second interface layer 117 is removed at the locations exposed by the first extension head 119 and the second extension head 120. The second interface layer 117 can be removed by one or more wet etching processes using a dilute acid aqueous solution. After removing the second interface layer 117 exposed by the first extension head 119 and the second extension head 120, the removal... Figure 1D The pillar mask 112. The pillar mask 112 can be removed by dissolving it in an organic solvent, leaving the isolation layer 123 in place. The pillar mask 112 can be removed by a process similar to that used to remove the head mask 118. After the pillar mask 112 is removed, Figure 1D The first interface layer 111 is removed at the locations exposed by the first pillar 113, the second pillar 114, and the third pillar 115. The first interface layer 111 can be removed by one or more wet etching processes using a dilute acid aqueous solution, which can be similar to the wet etching process used to remove the second interface layer 117.
[0023] refer to Figure 1FA lead frame 124 is provided for the microelectronic device 100. The lead frame 124 includes a first lead 125, a second lead 126, and a third lead 127. For example, leads 125, 126, and 127 may comprise copper, stainless steel, or Kovar alloy and may be plated with nickel, palladium, or gold. A first extension 119 provides a bump pad for the microelectronic device 100. For example, the bump pad may be implemented as a solder bump pad or an adhesive bump pad. The first lead 125 is electrically coupled to the first extension 119 via a first solder joint 128, and the third lead 117 is electrically coupled to a second extension 120 via a second solder joint 129 on a second portion of the second extension 120 exposed by an insulating layer 123. In an alternative embodiment of this example, the first lead 125 may be electrically coupled to the first extension 119 via a first portion of a conductive adhesive, such as an epoxy resin having copper or silver particles. In this alternative embodiment, the third lead 127 can be electrically coupled to the second extension head 120 via a second portion of the conductive adhesive. The second lead 126 is electrically isolated from the second extension head 120 via an insulating layer 123. An integrated capacitor 110 can be used to capacitively couple the signal from the third lead 127 of the lead frame 124 to the second plate 109 of the integrated capacitor 110. The integrated capacitor 110 can be formed to advantageously have the desired capacitance without consuming area in the die 101.
[0024] refer to Figure 1G An encapsulation isolation structure 130 is formed on die 101, laterally surrounding pillars 113, 114, and 115, a first extension 119, and a second extension 120, and contacting leads 125, 126, and 127. The term "lateral" refers to a direction parallel to the connection surface 103 and is equally applicable to other examples disclosed herein. The encapsulation isolation structure 130 is non-conductive and may include a dielectric material such as epoxy, silicone, or benzocyclobutene (BCB), and may include dielectric particles such as silica particles to reduce the coefficient of thermal expansion of the encapsulation isolation structure 130. The second extension 120 and a second interface layer 117 contacting the second extension 120 provide a first electrode 122 of the integrated capacitor 110. The encapsulation isolation structure 130 of this example extends between the first electrode 122 of the integrated capacitor 100 and the second electrode 109 of the integrated capacitor 110, which advantageously provides a larger capacitance for the integrated capacitor 110 compared to a capacitor without encapsulation dielectric material between the capacitor electrodes. Figure 1G The completed microelectronic device 100 is depicted.
[0025] Figures 2A to 2F This is a cross-section of another example microelectronic device with an integrated capacitor, depicted at various stages of another example fabrication method. (Reference) Figure 2AThe microelectronic device 200 includes a die 201. For example, the die 201 may be implemented as a reference. Figure 1A Any example of die 101 disclosed herein. The die 201 of this example has a substrate 202, which may be part of a wafer or workpiece including additional dies, or may consist solely of die 201. Die 201 has a connection surface 203; as... Figure 2A As shown, substrate 202 can extend to connection surface 203.
[0026] The die 201 in this example includes a first terminal 204, a second terminal 205, and a third terminal 206 at a connection surface 203. The first terminal 204, second terminal 205, and third terminal 206 are conductive. For example, terminals 204, 205, and 206 may be implemented as bump bonding pads or through-holes through the substrate. Terminals 204, 205, and 206 may be electrically coupled to components within the die 201 via through-hole 207.
[0027] In this example, die 201 includes a second plate 209 of an integrated capacitor 210. The second plate 209 is conductive. Figure 2A As shown, the second electrode 209 can extend to the connection surface 203. The second electrode 209 can be electrically coupled to a component in the die 201 through one or more through holes 207.
[0028] A strut mask 212 is formed on the connection surface 203. The strut mask 212 exposes a first terminal 204 in the region for the subsequently formed first strut 213, a second terminal 205 in the region for the subsequently formed second strut 214, and a third terminal 206 in the region for the subsequently formed third strut 215. The strut mask 212 of this example can be formed from photosensitive epoxy resin using a photolithography process. Alternatively, the strut mask 212 of this example may comprise inorganic particles in a binder material, formed by an additive manufacturing process such as material jetting or material extrusion. For example, the strut mask 212 may have a thickness from 1 micrometer to 100 micrometers. Figure 2C The first pillar 213, the second pillar 214, and the third pillar 215 are shown.
[0029] refer to Figure 2B An interface layer 231 is formed over the pillar mask 212, extending into the regions for the first pillar 213, the second pillar 214, and the third pillar 215, and contacting the first terminal 204, the second terminal 205, and the third terminal 206. The interface layer 231 is conductive. The interface layer 231 may include an adhesive sublayer for contacting terminals 204, 205, and 206. Figure 2B (Not shown in the image). Interface layer 231 may be contained within a barrier sublayer on the adhesion sublayer ( Figure 2B(Not shown in the image). Interface layer 231 may be included in a coated seed layer on the barrier sublayer ( Figure 2B (Not shown in the image). The interface layer 231 can be formed through a series of thin film deposition processes.
[0030] A head mask 218 is formed over the interface layer 231. The head mask 218 exposes the interface layer 231 in regions for the subsequently formed first extension head 219 and subsequently formed second extension head 220. The region for the first extension head 219 exposes the interface layer 231 over the first pillar 213 and extends over the first pillar 213 in at least one direction parallel to the connection surface 203. The region for the second extension head 220 exposes the interface layer 231 over the second pillar 214 and the third pillar 215, extending over the second pillar 214 in at least one direction parallel to the connection surface 203 and over the third pillar 215 in at least one direction parallel to the connection surface 203. The head mask 218 may contain photoresist and can be formed using a photolithography process. Alternatively, the head mask 218 can be formed by a tape application process, an additive process such as material jetting or material extrusion, or a subtractive process such as laser ablation. Figure 2C The first extension head 219 and the second extension head 220 are shown.
[0031] refer to Figure 2CUsing a plating process with plating solution 232, the first pillar 213, the second pillar 214, and the third pillar 215 are simultaneously formed on the interface layer 231 in the area exposed by the pillar mask 212. The plating process continues to simultaneously form a first extension head 219 on the first pillar 213 and a second extension head 220 on the second pillar 214 and the third pillar 215 in the area exposed by the head mask 218. The second extension head 220 is located above the second electrode plate 209. The plating solution 232 may contain copper ions, nickel ions, or gold ions, such that the pillars 213, 214, and 215, as well as the first extension head 219 and the second extension head 220, may contain copper, nickel, or gold. The plating process may be implemented as an electroplating process or a chemical plating process. The pillars 213, 214, and 215 may have a height of 1 micrometer to 100 micrometers perpendicular to the connection surface 203. For example, the first extension head 219 and the second extension head 220 may have a thickness of 1 micrometer to 25 micrometers perpendicular to the connection surface 203. The pillars 213, 214, and 215 are thus mechanically coupled to the connection surface 203 via the interface layer 231. The first extension head 219 is directly electrically coupled to the first pillar 213 and extends across the first pillar 213 in at least one direction parallel to the connection surface 203. The second extension head 220 is directly electrically coupled to the second pillar 214 and extends across the second pillar 214 in at least one direction parallel to the connection surface 203. After the pillars 213, 214, and 215, and the first extension head 219 and the second extension head 220 are formed, the microelectronic device 200 is separated from the plating solution 232.
[0032] refer to Figure 2D An isolation layer 223 is formed on the second extension head 220. The isolation layer 223 may be implemented as a solder mask and may include, for example, epoxy, polyester, or resin, and may be formed by dispensing, screen printing, or photolithography processes. In this example, the isolation layer 223 covers the second extension head 220 exposed by the head mask 218.
[0033] refer to Figure 2E , Figure 2D The head mask 218 is removed. The head mask 218 can be removed by dissolving it in an organic solvent, leaving the isolation layer 223 and the pillar mask 212 in place. After removing the head mask 218, Figure 2D The interface layer 231 is removed where it is exposed by the first extension head 219 and the second extension head 220, leaving the isolation layer 223 and the pillar mask 212 in place. The interface layer 231 can be removed by one or more wet etching processes using a dilute acid aqueous solution. In this example, the pillar mask 212 provides permanent support for the pillars 213, 214, and 215 and for the first extension head 219 and the second extension head 220.
[0034] refer to Figure 2FThe first extension head 219 provides a bump pad for the microelectronic device 200. For example, the bump pad may be implemented as a solder bump pad or an adhesive bump pad. Solder bumps 233 are formed on the first extension head 219. The solder bumps 233 are formed by dispensing solder paste onto the first extension head 219 and then heating the solder paste in a reflow process to provide a low-resistance interface between the solder bumps 233 and the first extension head 219.
[0035] The second extension head 220 and the interface layer 213 contacting the second extension head 220 provide the first electrode 222 of the integrated capacitor 210. The pillar mask 212 of this example extends between the first electrode 222 and the second electrode 209 of the integrated capacitor 210, which advantageously provides a larger capacitance for the integrated capacitor 210 compared to a capacitor without encapsulating dielectric material between the capacitor electrodes. Figure 2F The completed microelectronic device 200 is described.
[0036] Figures 3A to 3J This is a cross-section of a further example microelectronic device with an integrated capacitor, depicted at various stages of a further example fabrication method. Reference Figure 3A The microelectronic device 300 includes a die 301. For example, the die 301 may be implemented as a reference. Figure 1A Any example disclosed for die 101. The die 301 of this example has a substrate 302, which may be part of a wafer or workpiece including additional dies, or may consist only of die 301. Die 301 has a connection surface 303; as... Figure 3A As shown, substrate 302 can extend to connection surface 303.
[0037] The die 301 in this example includes a first terminal 304 and a second terminal 334 at a connection surface 303. The first terminal 304 and the second terminal 334 are conductive. For example, terminals 304 and 334 may be implemented as bump bonding pads or through-holes through the substrate. Terminals 304 and 334 may be electrically coupled to components in the die 301 through through-hole 307.
[0038] A first interface layer 311 is formed above the connection surface 303, contacting terminals 304 and 334. The first interface layer 311 may have a similar shape to... Figure 1A The composition and sublayer structure of the first interface layer 311. A capacitor mask 335 is formed over the first interface layer 311 and exposes the first interface layer 311 in the region of the second electrode 309 for integrating the capacitor 310. The capacitor mask 335 may contain photoresist formed by a photolithography process, or may contain polymer formed by a screen printing or additive manufacturing process.
[0039] refer to Figure 3BThe second electrode 309 of the integrated capacitor 310 is formed on the first interface layer 311 exposed by the capacitor mask 335. The second electrode 309 is formed using a first plating process using a first plating solution 336. The first plating solution 336 may contain copper ions, nickel ions, or gold ions, such that the second electrode 309 may contain copper, nickel, or gold. The first plating process may be implemented as an electroplating process or a chemical plating process. For example, the second electrode 309 may have a thickness of 1 micrometer to 100 micrometers. After the second electrode 309 is formed, the microelectronic device 300 is separated from the plating solution 336.
[0040] refer to Figure 3C , Figure 3B The capacitor mask 335 is removed, leaving the first interface layer 311 and the second electrode 309 in place. For example, the capacitor mask 335 can be removed by dissolving it in an organic solvent or organic acid. Other methods for removing the capacitor mask 335 are within the scope of this example.
[0041] refer to Figure 3D A pillar mask 312 is formed on a first interface layer 311, covering the second electrode plate 309. The pillar mask 312 exposes the first interface layer 311 in regions for the first pillar 313, the second pillar 314, and the third pillar 315. The region for the first pillar 313 is located above the first terminal 304, the region for the second pillar 314 is located on one side of the second electrode plate 309, and the region for the third pillar 315 is located on the other side of the second electrode plate 309. The pillar mask 312 may contain photoresist and can be formed using a photolithography process. Alternatively, the pillar mask 312 can be formed using a tape application process, an additive process, or a subtractive process. For example, the pillar mask 312 may have a thickness from 1 micrometer to 50 micrometers greater than the thickness of the second electrode plate 309.
[0042] refer to Figure 3E A second plating process using a second plating solution 316 simultaneously forms the first pillar 313, the second pillar 314, and the third pillar 315 on the first interface layer 311 in the area exposed by the pillar mask 312. The second plating solution 316 may contain copper ions, nickel ions, or gold ions, such that the pillars 313, 314, and 315 contain copper, nickel, or gold. The second plating process may be implemented as an electroplating process or a chemical plating process. For example, the pillars 313, 314, and 315 may have a height perpendicular to the connection surface 303, which is 1 micrometer to 50 micrometers greater than the thickness of the second electrode 309. The pillars 313, 314, and 315 are thus mechanically coupled to the connection surface 303 through the first interface layer 311. After the pillars 313, 314, and 315 are formed, the microelectronic device 300 is separated from the second plating solution 316. The pillar mask 312 remains in situ for subsequent manufacturing steps.
[0043] refer to Figure 3F A second interface layer 317 is formed over the pillar mask 312 and contacts the pillars 313, 314, and 315. The second interface layer 317 is conductive. The second interface layer 317 may include an adhesive sublayer contacting the pillar mask 312 and the pillars 313, 314, and 315, and may include a plating seed layer contacting the adhesive sublayer. The adhesive sublayer of the second interface layer 317 may have a composition similar to that disclosed for the adhesive sublayer of the reference first interface layer 311. The plating seed layer of the second interface layer 317 may have a composition similar to that disclosed for the plating seed layer of the reference first interface layer 311.
[0044] A head mask 318 is formed over the second interface layer 317. The head mask 318 exposes the second interface layer 317 in the regions for the subsequent formation of the first extension head 319 and the subsequent formation of the second extension head 320; Figure 3G A first extension head 319 and a second extension head 320 are shown. Referring back to 3F, the region for the first extension head 319 exposes a second interface layer 317 over the first pillar 313 and extends over the first pillar 313 in at least one direction parallel to the connection surface 303. The region for the second extension head 320 exposes a second interface layer 317 over the second pillar 314 and the third pillar 315, extending over the second pillar 314 in at least one direction parallel to the connection surface 303 and over the third pillar 315 in at least one direction parallel to the connection surface 303. The head mask 318 may contain photoresist and may be formed using a photolithography process. Alternatively, the head mask 318 may be formed by a tape application process, an additive process, or a subtractive process. The head mask 318 may have a different composition than the pillar mask 312, or may be formed by a different process than that used to form the pillar mask 312.
[0045] refer to Figure 3GA third plating process using a third plating solution 321 is employed to simultaneously form the first extension head 319 and the second extension head 320 on the second interface layer 317 in the area exposed by the head mask 318. The third plating solution 321 may contain copper ions, nickel ions, or gold ions, such that the first extension head 319 and the second extension head 320 contain copper, nickel, or gold. The third plating process may be implemented as an electroplating process or a chemical plating process. For example, the first extension head 319 and the second extension head 320 may have a thickness of 1 micrometer to 25 micrometers perpendicular to the connection surface 303. The first extension head 319 is electrically coupled to the first pillar 313 through the second interface layer 317 and extends across the first pillar 313 in at least one direction parallel to the connection surface 303. The second extension head 320 is electrically coupled to the second pillar 314 through the second interface layer 317 and extends across the second pillar 314 in at least one direction parallel to the connection surface 303. After the first extension head 319 and the second extension head 320 are formed, the microelectronic device 300 is separated from the third plating solution 321. The second extension head 320 is located above the second electrode plate 309.
[0046] refer to Figure 3H , Figure 3G The head mask 318 is removed. The head mask 318 can be removed by dissolving it in an organic solvent or organic acid, leaving the first extension head 319 and the second extension head 320 in place. After removing the head mask 318, Figure 3G The second interface layer 317 is removed at the locations exposed by the first extension head 319 and the second extension head 320. The second interface layer 317 can be removed by one or more wet etching processes using a dilute acid aqueous solution. After removing the second interface layer 317 exposed by the first extension head 319 and the second extension head 320... Figure 3G The pillar mask 312 is removed. The pillar mask 312 can be removed by dissolving it in an organic solvent or organic acid, leaving the first pillar 313, second pillar 314, third pillar 315, first extension head 319, and second extension head 320 in place. The pillar mask 312 can be removed by a process similar to that used to remove the head mask 318. After the pillar mask 312 is removed, Figure 3G The first interface layer 311 is removed where the pillars 313, 314, and 315 and the second electrode 309 are exposed. The first interface layer 311 can be removed by one or more wet etching processes using a dilute acid aqueous solution, similar to the wet etching process used to remove the second interface layer 317. Figure 3H As shown, the removal of the first interface layer 311 can result in the removal of the second interface layer 317 exposed by the pillars 313, 314 and 315 below the first extension head 319 and the second extension head 320.
[0047] refer to Figure 3I An encapsulation isolation structure 330 is formed on die 301, laterally surrounding pillars 313, 314, and 315, and contacting the first extension head 319 and the second extension head 320. The encapsulation isolation structure 330 is conductive. The second extension head 320 provides the first electrode 322 of the integrated capacitor 310. In this example, the encapsulation isolation structure 330 extends between the first electrode 322 and the second electrode 309 of the integrated capacitor 310, which advantageously provides a larger capacitance for the integrated capacitor 310 compared to a capacitor without encapsulating dielectric material between the capacitor's electrodes. For example, the encapsulation isolation structure 330 can be formed by injection molding or reaction injection molding. During the formation of the encapsulation isolation structure 330, the third pillar 315 can advantageously provide mechanical support for the second extension head 320.
[0048] refer to Figure 3J The first extension head 319 provides a bump pad for the microelectronic device 300. For example, the bump pad may be implemented as a solder bump pad or an adhesive bump pad. A first solder bump 333 is formed on the first extension head 319, and a second bump pad 337 is formed on the second extension head 320. The first solder bump 333 and the second solder bump 337 can be formed by dispensing solder paste onto the first extension head 319 and the second extension head 320 and then heating the solder paste in a reflow process. Figure 3J The completed microelectronic device 300 is depicted. In this example, the first plate 322 of the integrated capacitor 310 is electrically coupled to a printed circuit board or chip carrier via a second solder bump 337. Figure 3J (Not shown in the image). The first electrode plate is electrically coupled to one or more components in the die 301 via the first interface layer 311 and the second terminal 334.
[0049] Figures 4A to 4G This is a cross-section of another example microelectronic device with an integrated capacitor, depicted at various stages of another example fabrication method. (Reference) Figure 4A The microelectronic device 400 includes a die 401. For example, the die 401 may be implemented as a reference. Figure 1A Any example disclosed for die 101. Die 401 of this disclosure has a substrate 402, which may be part of a wafer or workpiece including additional dies, or may consist solely of die 401. Die 401 has a connection surface 403; as... Figure 4A As shown, substrate 402 may extend to connection surface 403. The die 401 of this example includes a first terminal 404, a second terminal 405, and a third terminal 434 at connection surface 403. For example, terminals 404, 405, and 434 are conductive and may be implemented as bump bonding pads or through-holes through the substrate. Terminals 404, 405, and 434 may be electrically coupled to components in die 401 via through-hole 407.
[0050] A first interface layer 411 is formed above the connection surface 403 and contacts terminals 404, 405, and 434. The first interface layer 411 may have a similar shape to... Figure 1A The composition and sublayer structure of the first interface 111.
[0051] A pillar mask 412 is formed on a first interface layer 411. The pillar mask 412 exposes the first interface layer 411 in the regions of a first pillar 413, a second pillar 414, and a second electrode 409 for integrating the capacitor 410. The region for the first pillar 413 is located above a first terminal 404, the region for the second pillar 414 is located above a second terminal 405, and the region for the second electrode 409 is located above a third terminal 434. The pillar mask 412 may contain photoresist and can be formed using a photolithography process, or it can be formed using a tape application process, an additive process, or a subtractive process. For example, the pillar mask 412 may have a thickness from 1 micrometer to 100 micrometers.
[0052] refer to Figure 4B A first plating process using a first plating solution 416 simultaneously forms a first pillar 413, a second pillar 414, and a second electrode 409 on a first interface layer 411 in the area exposed by the pillar mask 412. The first plating solution 416 may contain copper, nickel, or gold ions, such that pillars 413 and 414 and the second electrode 409 contain copper, nickel, or gold. The first plating process may be implemented as an electroplating process or a chemical plating process. For example, pillars 413 and 414 and the second electrode 409 may have a height of 1 micrometer to 100 micrometers perpendicular to the connection surface 403. Pillars 413 and 414 are thus mechanically coupled to the connection surface 403 through the first interface layer 411. After the formation of pillars 413 and 414 and the second electrode 409, the microelectronic device 400 is separated from the first plating solution 416. The pillar mask 412 remains in situ for subsequent manufacturing steps.
[0053] refer to Figure 4C A capacitor dielectric layer 438 is formed above the second electrode 409. The capacitor dielectric layer 438 may comprise an organic polymer such as epoxy resin or polyimide, a silicone polymer, or an inorganic material such as silica particles in an adhesive material. The capacitor dielectric layer 438 may be formed by photolithography, screen printing, or additive manufacturing processes. For example, the capacitor dielectric layer 438 may have a thickness of 100 nanometers to 10 micrometers.
[0054] refer to Figure 4DA second interface layer 417 is formed over the pillar mask 412, contacts the pillars 413 and 414, and extends over the capacitor dielectric layer 438. The second interface layer 417 is conductive. The second interface layer 417 may include an adhesive sublayer contacting the pillar mask 412, pillars 413 and 414, and the capacitor dielectric layer 438, and may include a plating seed layer contacting the adhesive sublayer. The adhesive sublayer of the second interface layer 417 may have a composition similar to that disclosed for the adhesive sublayer of the reference first interface layer 411. The plating seed layer of the second interface layer 417 may have a composition similar to that disclosed for the plating seed layer of the reference first interface layer 411.
[0055] refer to Figure 4E A head mask 418 is formed over the second interface layer 417. The head mask 418 exposes the second interface layer 417 in the regions for the subsequent formation of the first extension head 419 and the subsequent formation of the second extension head 412. Figure 4F The first extension head 419 and the second extension head 420 are shown. (Return to Reference) Figure 4E The region for the first extension head 419 exposes a second interface layer 417 over the first pillar 413 and extends across the first pillar 413 in at least one direction parallel to the connection surface 403. The region for the second extension head 420 exposes a second interface layer 417 over the second pillar 414 and the capacitor dielectric layer 438 and extends across the second pillar 414 in at least one direction parallel to the connection surface 403. The head mask 418 may contain photoresist and may be formed using a photolithography process. Alternatively, the head mask 418 may be formed using a tape application process, an additive process, or a subtractive process. The head mask 418 may have a different composition than the pillar mask 412, or may be formed using a different process than that used to form the pillar mask 412.
[0056] refer to Figure 4FA second plating process using a second plating solution 421 is employed to simultaneously form the first extension head 419 and the second extension head 420 on the second interface layer 417 in the area exposed by the head mask 418. The second plating solution 421 may contain copper ions, nickel ions, or gold ions, such that the first extension head 419 and the second extension head 420 contain copper, nickel, or gold. The second plating process may be implemented as an electroplating process or a chemical plating process. For example, the first extension head 419 and the second extension head 420 may have a thickness of 1 micrometer to 25 micrometers perpendicular to the connection surface 403. The first extension head 419 is electrically coupled to the first pillar 413 through the second interface layer 417 and extends across the first pillar 413 in at least one direction parallel to the connection surface 403. The second extension head 420 is electrically coupled to the second pillar 414 through the second interface layer 417 and extends across the second pillar 414 in at least one direction parallel to the connection surface 403. After the first extension head 419 and the second extension head 420 are formed, the microelectronic device 400 is separated from the second plating solution 421. The second extension head 420 is located above the second electrode plate 409.
[0057] refer to Figure 4G , Figure 4F The head mask 418 is removed, while the first extension head 419 and the second extension head 420 remain in place. Figure 4F The second interface layer 417 is removed where it is exposed by the first extension head 419 and the second extension head 420. Figure 4F The support mask 412 is removed, while the first support 413, the second support 414, the second electrode plate 409, the first extension head 419 and the second extension head 420 remain in place. Figure 4F The first interface layer 411 is removed where it is exposed by pillars 413 and 414 and the second electrode 409. The head mask 418, the second interface layer 417, the pillar mask 412, and the first interface layer 411 can be removed by means of the processes disclosed in other examples herein for the removal of the corresponding masks and interface layers.
[0058] An isolation layer 423 may optionally be formed on the second extension head 420. For example, the isolation layer 423 may be implemented as a solder mask and may comprise, for example, epoxy, polyester, or resin, and may be formed by dispensing, screen printing, or photolithography. The isolation layer 423 may optionally be formed before removing the head mask 418. The first extension head 419 provides a bump pad for the microelectronic device 400. For example, the bump pad may be implemented as a solder bump pad or an adhesive bump pad. A first solder bump 433 is formed on the first extension head 419. The first solder bump 433 can be connected to a reference... Figure 2F The solder bump 233 is formed using a process similar to that disclosed in the paper.
[0059] Figure 4GA completed microelectronic device 400 is depicted. A second extension head 420 and a second interface layer contacting the second extension head 420 provide a first electrode 422 of the integrated capacitor 410. The first electrode is electrically coupled to one or more components in the die 401 via a first interface layer 411 and a second terminal 414. A capacitor dielectric layer 438 separates the first electrode 422 from the second electrode 409, which advantageously provides a high capacitance value for the integrated capacitor 410 of this example.
[0060] Figures 5A to 5C This is a cross-section of a further example microelectronic device with an integrated capacitor, depicted at various stages of a further example fabrication method. Reference Figure 5A The microelectronic device 200 includes a die 501. For example, the die 501 may be implemented as a reference. Figure 1A Any example disclosed for die 101. The die 501 of this example has a substrate 502, which may be part of a wafer or workpiece including additional dies, or may consist only of die 501. Die 501 has a connection surface 503; as... Figure 5A As shown, substrate 502 extends to connection surface 503. The die 501 in this example includes a first terminal 504, a second terminal 505, and a third terminal 506 at connection surface 503. For example, terminals 504, 505, and 506 are conductive and may be implemented as bump bonding pads or through-holes through the substrate. Terminals 504, 505, and 506 may be electrically coupled to components within die 501.
[0061] A first post 513, a second post 514, and a third post 515 are simultaneously formed on a first terminal 504, a second terminal 505, and a third terminal 506, respectively. Posts 513, 514, and 515 are thus mechanically coupled to a connection surface 503. Posts 513, 514, and 515 are conductive. A first extension head 519 and a second extension head 520 are simultaneously formed on posts 513, 514, and 515. The first extension head 519 contacts the first post 513 and extends across the first post 513 in at least one direction parallel to the connection surface 503. The second extension head 520 contacts the second post 514 and the third post 515, extends across the second post 514 in at least one direction parallel to the connection surface 503, and extends across the third post 515 in at least one direction parallel to the connection surface 503. Posts 513, 514, and 515, the first extension head 519, and the second extension head 520 may be formed by any of the methods disclosed in the examples herein. Alternatively, pillars 513, 514, and 515, the first extension head 519, and the second extension head 520 may be formed by an additive manufacturing process such as three-dimensional (3D) metal printing. When pillars 513, 514, and 515 are formed by an additive manufacturing process, they are formed by the same additive manufacturing process, such that pillars 513, 514, and 515 are formed simultaneously (i.e., in the same operation or synchronously). The term "simultaneously" includes the case where a portion or all of the first pillar 513 is formed before a portion or all of the second pillar 514 is formed, which may occur when using an additive manufacturing process with a limited number of printheads or material dispensing nozzles, and is similar for the first extension head 519 and the second extension head 520. Other methods for simultaneously forming pillars 513, 514, and 515, and simultaneously forming the first extension head 519 and the second extension head 520, are within the scope of this example.
[0062] A capacitor dielectric layer 538 is formed above the second extension head 520, on the surface of the second extension head 520 opposite to the connection surface 503. The capacitor dielectric layer 538 may have a composition, and can be referenced... Figure 4C The capacitor dielectric layer 438 is formed using the method disclosed herein.
[0063] refer to Figure 5B A lead frame 524 is provided for a microelectronic device 500. The lead frame 524 includes a first lead 525 and a second lead 526. Leads 525 and 526 may include references. Figure 1FThe lead frame 124 may be made of any material disclosed herein. A first extension head 519 provides a bump pad for the microelectronic device 500. For example, the bump pad may be implemented as a solder bump pad or an adhesive bump pad. A first lead 525 is electrically coupled to the first extension head 519 via a solder connection 528. A second lead 526 is located above the second extension head 520 and is electrically isolated from the second extension head 520 via a capacitor dielectric layer 538.
[0064] refer to Figure 5C An encapsulation isolation structure 530 is formed on die 501, laterally surrounding pillars 513, 514, and 515, a first extension head 519, and a second extension head 520, and contacting leads 525 and 526. The encapsulation isolation structure 530 is non-conductive and may include a reference. Figure 1G The encapsulation isolation structure 130 is made of any material disclosed herein.
[0065] A second extension head 520 provides a first electrode 522 of the integrated capacitor 510. A second lead 526 provides a second electrode 509 of the integrated capacitor 510, facing the side of the first electrode 522 opposite to the connection surface 503. A capacitor dielectric layer 538 separating the first electrode 522 and the second electrode 509 advantageously provides a high capacitance value for the integrated capacitor 510 of this example. Figure 5C As shown, the encapsulation isolation structure 530 of this example may optionally extend between the first electrode 522 and the second electrode 509. Figure 5C The completed microelectronic device 500 is described.
[0066] The various features of the examples disclosed herein can be incorporated into other manifestations of microelectronic devices. For example, the first and second pillars of any microelectronic device can be based on references. Figures 1A to 1G , Figures 2A to 2F , Figures 3A to 3J or Figures 4A to 4G The methods disclosed are formed simultaneously as described. Similarly, the first and second extension heads of any microelectronic device can be formed according to reference. Figures 1A to 1G , Figures 2A to 2F , Figures 3A to 3J or Figures 4A to 4G The method disclosed is used to simultaneously form the capacitor. Any integrated capacitor can have the following characteristics: Figure 4C or Figure 5C The capacitor dielectric layer is shown. Any second extension of a microelectronic device can be like this... Figure 1G or Figure 3J It is electrically coupled to an external terminal as shown.
[0067] Although various embodiments of this disclosure have been described above, it should be understood that they are presented by way of example only and not by way of limitation. Many changes may be made to the disclosed embodiments in accordance with the disclosure herein without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of the invention should not be limited to any of the above-described embodiments. Rather, the scope of this disclosure should be defined by the appended claims and their equivalents.
Claims
1. A microelectronic device, comprising: The core tube has a connecting surface; A first pillar, which is mechanically coupled to the connecting surface, is conductive; A second pillar, which is mechanically coupled to the connecting surface, is conductive, wherein the first pillar and the second pillar are made of the same conductive material; A first extension head, electrically coupled to the first post, the first extension head being conductive, extends beyond the first post in a direction parallel to the connection surface. A second extension head, electrically coupled to the second post, the second extension head being conductive, extends beyond the second post in a direction parallel to the connection surface, wherein: The first extension head and the second extension head are made of conductive materials with the same composition; The first extension head provides solder bump pads; and The second extension head provides at least a portion of the first plate of the integrated capacitor of the microelectronic device; and The second plate of the integrated capacitor. The microelectronic device further includes a packaging isolation structure between the first electrode and the second electrode, the packaging isolation structure being non-conductive, wherein the packaging isolation structure laterally surrounds the first pillar and the second pillar.
2. The microelectronic device according to claim 1, wherein the second electrode is located in the die below the first electrode.
3. The microelectronic device according to claim 1, wherein the second electrode is located between the connecting surface and the first electrode.
4. The microelectronic device according to claim 3, wherein the second electrode and the first pillar are made of the same conductive material.
5. The microelectronic device according to claim 1, wherein the second electrode plate is located above the first electrode plate, facing the side of the first electrode plate opposite to the connecting surface.
6. The microelectronic device of claim 1, further comprising a lead frame, wherein the leads of the lead frame provide the second electrode plate.
7. The microelectronic device of claim 1, further comprising a lead frame, wherein the first electrode is electrically coupled to a lead of the lead frame via a conductive material.
8. The microelectronic device of claim 1, further comprising an isolation layer on the surface of the first electrode opposite to the connection surface, the isolation layer being non-conductive.
9. The microelectronic device of claim 1, wherein the first pillar is electrically coupled to a second terminal of the die, the second terminal being located at the connection surface and being conductive.
10. A method for forming a microelectronic device, comprising: Provides a die with a connecting surface; A first pillar and a second pillar are simultaneously formed on the connecting surface. The first pillar and the second pillar are conductive and are mechanically coupled to the connecting surface. as well as Simultaneously, a first extension head and a second extension head are formed, the first extension head being electrically coupled to the first post, and the second extension head being electrically coupled to the second post; wherein: The first extension head and the second extension head are conductive; The first extension head extends beyond the first post in a direction parallel to the connecting surface of the tube. The second extension head extends beyond the second post in a direction parallel to the connecting surface of the tube; The first extension head provides a bump pad; and The second extension head provides at least a portion of the first plate of the integrated capacitor. The method further includes: The second plate of the integrated capacitor is formed; and An encapsulation isolation structure is formed on the die, the encapsulation isolation structure being non-conductive, wherein the encapsulation isolation structure laterally surrounds the first post and the second post and extends between the first electrode and the second electrode.
11. The method of claim 10, wherein the second plate of the integrated capacitor is located in the die.
12. The method of claim 10, further comprising forming a second plate of the integrated capacitor above the connection surface prior to forming the second extension head.
13. The method of claim 12, wherein the second electrode plate is formed simultaneously with the first support and the second support.
14. The method of claim 10, further comprising: A dielectric layer is formed on the second electrode plate before the second extension head is formed.
15. The method of claim 10, further comprising electrically coupling the bump pad to a lead frame of the microelectronic device, wherein the lead frame provides a second plate of the integrated capacitor.
16. The method of claim 10, further comprising forming an insulating layer on the surface of the first electrode opposite to the connection surface, the insulating layer being non-conductive.
17. The method of claim 10, wherein the first pillar and the second pillar are formed by a plating process.
18. The method of claim 10, wherein the first extension head and the second extension head are formed by a plating process.