A flat panel detector and its driving method

Abstract

The present invention discloses a flat panel detector and a driving method thereof. By making the detection unit include: a first transistor, a second transistor, a storage capacitor, and a photoelectric detection device, since the material of the active layer of the second transistor is amorphous silicon semiconductor material, and the material of the active layer of the first transistor is low-temperature polycrystalline silicon semiconductor material or metal oxide semiconductor material, the transmission delay of the electrical signal generated by the photoelectric detection device can be reduced by controlling the conduction and cutoff of the first transistor and controlling the conduction and cutoff of the second transistor. When the flat panel detector is applied to an X-ray detection device, the accuracy of X-ray digital imaging can be improved.

Description

Technical Field

[0001] The present invention relates to the field of detection technology, and particularly to a flat panel detector and a driving method thereof. Background Art

[0002] X-ray detection devices usually adopt flat panel detectors to convert X-ray information into digital image information. Generally, a flat panel detector includes a plurality of grid lines and a plurality of detection lines SL arranged crosswise, and photosensitive pixels defined by the grid lines and the detection lines SL. Each photosensitive pixel may include a photodiode and a transistor coupled to the photodiode. Moreover, the transistor is also connected to the grid line and the detection line SL. During operation, the X-rays attenuated after passing through the human body are converted into visible light by a scintillator located on the surface of the flat panel detector. The photodiode converts the visible light into an electrical signal, and the gate scan signal transmitted through the grid line drives the transistor to turn on, so as to read out the electrical signal converted by the photodiode through the detection line SL connected to the transistor, thereby forming an X-ray digital image according to the signal line. Usually, the active layer of the transistor in the flat panel detector is formed of an amorphous silicon semiconductor material. However, as the refresh rate of the flat panel detector becomes higher and higher, the turn-on time of the transistor becomes shorter and shorter. Since the mobility of amorphous silicon is low, the delay in transmitting the electrical signal is large, which in turn leads to a reduction in the accuracy of the formed X-ray digital image. Summary of the Invention

[0003] Embodiments of the present invention provide a flat panel detector and a driving method thereof to improve the detection frame rate.

[0004] The flat panel detector provided by the embodiments of the present invention includes: a substrate, a plurality of scan lines and a plurality of detection lines located on the substrate, and a plurality of detection units defined by the plurality of scan lines and the plurality of detection lines; the plurality of scan lines include a plurality of first scan lines and a plurality of second scan lines;

[0005] Each of the detection units includes: a first transistor, a second transistor, a storage capacitor, and a photoelectric detection device; the material of the active layer of the second transistor is an amorphous silicon semiconductor material, and the material of the active layer of the first transistor is a low-temperature polycrystalline silicon semiconductor material or a metal oxide semiconductor material;

[0006] The gate of the first transistor is electrically connected to the first scan line, the first pole of the first transistor is electrically connected to the detection line, and the second pole of the first transistor is electrically connected to the first electrode plate of the storage capacitor and the first pole of the second transistor respectively;

[0007] The gate of the second transistor is electrically connected to the second scan line, and the second pole of the second transistor is electrically connected to the photoelectric detection device;

[0008] The second electrode plate of the storage capacitor is electrically connected to the reference signal terminal.

[0009] In some examples, the flat panel detector includes:

[0010] A first semiconductor layer located on the substrate; wherein, the first semiconductor layer includes the active layer of the first transistor;

[0011] A gate insulating layer located on the side of the first semiconductor layer away from the substrate;

[0012] A first conductive layer located on the side of the gate insulating layer away from the substrate; wherein, the first conductive layer includes the gate of the first transistor and the first scanning line; the first scanning line extends in a first direction;

[0013] An interlayer dielectric layer located on the side of the first conductive layer away from the substrate;

[0014] A second conductive layer located on the side of the interlayer dielectric layer away from the substrate; wherein, the second conductive layer includes the first and second poles of the first transistor and the detection line; the first and second poles of the first transistor are respectively electrically connected to the active layer of the first transistor through a first via hole penetrating the interlayer dielectric layer and the gate insulating layer; the detection line extends in a second direction;

[0015] The second transistor and the storage capacitor are respectively located on the side of the first semiconductor layer away from the substrate.

[0016] In some examples, the first conductive layer further includes: the gate of the second transistor and the second scanning line; wherein, the second scanning line extends in the first direction;

[0017] The flat panel detector further includes: a second semiconductor layer located between the interlayer dielectric layer and the second conductive layer; wherein, the second semiconductor layer includes the active layer of the second transistor;

[0018] The second conductive layer further includes the first and second poles of the second transistor; wherein, the first pole of the second transistor is in direct contact with the first end of the active layer of the second transistor, and the second pole of the second transistor is in direct contact with the second end of the active layer of the second transistor.

[0019] In some examples, the active layers of the first transistor and the second transistor in the same detection unit are located on the side of the detection unit close to the detection line;

[0020] The first scanning line and the second scanning line corresponding to the same detection unit are respectively located on both sides of the detection unit in the second direction.

[0021] In some examples, the interlayer dielectric layer includes a first interlayer dielectric layer located between the substrate and the second conductive layer, and a second interlayer dielectric layer located between the first interlayer dielectric layer and the second conductive layer;

[0022] The flat panel detector further includes: a third conductive layer located between the first interlayer dielectric layer and the second interlayer dielectric layer, and a second semiconductor layer located between the second interlayer dielectric layer and the second conductive layer; wherein, the third conductive layer includes: the gate of the second transistor and the second scan line; the second scan line extends along the first direction or the second direction;

[0023] The second semiconductor layer includes the active layer of the second transistor;

[0024] The second conductive layer further includes the first pole and the second pole of the second transistor; wherein, the first pole of the second transistor is in direct contact with the first end of the active layer of the second transistor, and the second pole of the second transistor is in direct contact with the second end of the active layer of the second transistor.

[0025] In some examples, the active layer of the first transistor and the active layer of the second transistor in the same detection unit are located at both ends of the diagonal of the detection unit;

[0026] The second scan line and the detection line corresponding to the same detection unit are respectively located on both sides of the detection unit in the first direction.

[0027] In some examples, the second conductive layer further includes the gate of the second transistor and the second scan line; wherein, the second scan line extends along the second direction;

[0028] The flat panel detector further includes: an interlayer insulating layer located on the side of the second conductive layer away from the substrate, a second semiconductor layer located on the side of the interlayer insulating layer away from the substrate, and a fourth conductive layer located on the side of the second semiconductor layer away from the substrate;

[0029] The second semiconductor layer includes the active layer of the second transistor;

[0030] The fourth conductive layer includes the first pole and the second pole of the second transistor; wherein, the first pole of the second transistor is in direct contact with the first end of the active layer of the second transistor, the second pole of the second transistor is in direct contact with the second end of the active layer of the second transistor, and the second pole of the second transistor is electrically connected to the first pole of the first transistor through a second via hole penetrating the interlayer insulating layer.

[0031] In some examples, the second conductive layer further includes a first electrode plate of the storage capacitor; wherein, the first electrode plate of the storage capacitor is electrically connected between a second pole of the first transistor and a first pole of the second transistor.

[0032] In some examples, when the second conductive layer further includes a first pole and a second pole of the second transistor, the first electrode plate of the storage capacitor, the second pole of the first transistor, and the first pole of the second transistor are integrally formed.

[0033] When the fourth conductive layer includes the first pole of the second transistor, the first electrode plate of the storage capacitor and the second pole of the first transistor are integrally formed, and the first pole of the second transistor is electrically connected to the first electrode plate of the storage capacitor through the second via hole.

[0034] In some examples, the first conductive layer further includes a second electrode plate of the storage capacitor; or,

[0035] The interlayer dielectric layer includes a first interlayer dielectric layer between the substrate and the second conductive layer, and a second interlayer dielectric layer between the first interlayer dielectric layer and the second conductive layer; the flat panel detector further includes: a third conductive layer between the first interlayer dielectric layer and the second interlayer dielectric layer; wherein, the third conductive layer includes: the second electrode plate of the storage capacitor.

[0036] The driving method of the flat panel detector provided by the embodiment of the present invention controls the detection units to enter the detection period row by row; wherein, there is at least one scanning duration between the detection periods of two adjacent rows of the detection units; the scanning duration is the maintaining duration when the first transistor is turned on.

[0037] Wherein, the detection period of each row of the detection units has an integration stage, a pre-transfer stage, and an output stage;

[0038] In the integration stage, a cut-off control signal is loaded onto the second scan line of the row to control the second transistor in the row to be cut off; and a cut-off control signal is loaded onto the first scan line of the row to control the first transistor in the row to be cut off; after the photodetector receives an optical signal, the optical signal is converted into an electrical signal.

[0039] In the pre-transfer stage, a conduction control signal is loaded onto the second scan line of the row to control the second transistor in the row to be turned on; and a cut-off control signal is loaded onto the first scan line of the row to control the first transistor in the row to be cut off.

[0040] In the output stage, a cut-off control signal is loaded onto the second scan line of the row to control the second transistor in the row to be cut off; and a conduction control signal is loaded onto the first scan line of the row to control the second transistor in the row to be conductive.

[0041] The beneficial effects of the present invention are as follows:

[0042] The flat panel detector and its driving method provided by the embodiments of the present invention enable the detection unit to include: a first transistor, a second transistor, a storage capacitor, and a photoelectric detection device. Since the material of the active layer of the second transistor is amorphous silicon semiconductor material, and the material of the active layer of the first transistor is low-temperature polycrystalline silicon semiconductor material or metal oxide semiconductor material, by controlling the conduction and cut-off of the first transistor and controlling the conduction and cut-off of the second transistor, the transmission delay of the electrical signal generated by the photoelectric detection device can be reduced. When the flat panel detector is applied to an X-ray detection device, the accuracy of X-ray digital imaging can be improved. Description of the Drawings

[0043] Figure 1 is a schematic structural diagram of the flat panel detector in the embodiments of the present invention;

[0044] Figure 2 is a flowchart of the driving method of the flat panel detector in the embodiments of the present invention;

[0045] Figure 3 is a signal timing diagram in the embodiments of the present invention;

[0046] Figure 4 is a schematic layout structure diagram of the flat panel detector in the embodiments of the present invention;

[0047] Figure 5 is Figure 4 a schematic cross-sectional structure diagram along the AA' direction in the schematic layout structure diagram of the flat panel detector shown;

[0048] Figure 6 is a schematic layout structure diagram of the flat panel detector in the embodiments of the present invention;

[0049] Figure 7 is Figure 6 a schematic cross-sectional structure diagram along the AA' direction in the schematic layout structure diagram of the flat panel detector shown;

[0050] Figure 8 is a schematic layout structure diagram of the flat panel detector in the embodiments of the present invention;

[0051] Figure 9 is Figure 8 a schematic cross-sectional structure diagram along the AA' direction in the schematic layout structure diagram of the flat panel detector shown. Detailed implementation mode

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. And without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0053] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention pertains. The "first", "second", and similar terms used in the present invention do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0054] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of the present invention. And the same or similar reference numerals throughout denote the same or similar elements or elements having the same or similar functions.

[0055] The embodiments of the present invention provide a flat panel detector, such as Figure 1As shown, it may include: a substrate substrate 100, a plurality of scan lines and a plurality of detection lines SL located on the substrate substrate 100, and a plurality of detection units 110 defined by the plurality of scan lines and the plurality of detection lines SL; wherein, the plurality of scan lines include a plurality of first scan lines GA1 and a plurality of second scan lines GA2; each detection unit 110 includes: a first transistor M1, a second transistor M2, a storage capacitor CST, and a photoelectric detection device GD0; the material of the active layer M2-A of the second transistor M2 is an amorphous silicon semiconductor material, and the material of the active layer M1-A of the first transistor M1 is a low-temperature polycrystalline silicon semiconductor material or a metal oxide semiconductor material; the gate M1-G of the first transistor M1 is electrically connected to the first scan line GA1, the first pole of the first transistor M1 is electrically connected to the detection line SL, and the second pole of the first transistor M1 is respectively electrically connected to the first electrode plate C1-1 of the storage capacitor CST and the first pole of the second transistor M2; the gate M2-G of the second transistor M2 is electrically connected to the second scan line GA2, the second pole of the second transistor M2 is electrically connected to the photoelectric detection device GD0; the second electrode plate C1-2 of the storage capacitor CST is electrically connected to the reference signal terminal.

[0056] In the flat panel detector provided by the embodiment of the present invention, by making the detection unit include: a first transistor, a second transistor, a storage capacitor, and a photoelectric detection device, since the material of the active layer of the second transistor is an amorphous silicon semiconductor material, and the material of the active layer of the first transistor is a low-temperature polycrystalline silicon semiconductor material or a metal oxide semiconductor material, the transmission delay of the electrical signal generated by the photoelectric detection device can be reduced by controlling the on and off of the first transistor and the on and off of the second transistor. When the flat panel detector is applied to an X-ray detection device, the accuracy of X-ray digital imaging can be improved.

[0057] In specific implementation, in the embodiment of the present invention, as Figure 1 shown, the detection units 110 may be arranged in an array on the substrate substrate 100. In this way, the detection units 110 can be periodically arranged in the row direction and the column direction. Exemplarily, one row of detection units 110 corresponds to one first scan line GA1 and one second scan line GA2, and one column of detection units 110 corresponds to one detection line SL. In the same row, the gates M1-G of the first transistors M1 in this row are all electrically connected to the corresponding first scan line GA1, and the gates M2-G of the second transistors M2 in this row are all electrically connected to the corresponding second scan line GA2. In the same column, the second poles of the second transistors M2 in this column are all electrically connected to the corresponding detection line SL.

[0058] In specific implementation, in the embodiment of the present invention, the second pole of the second transistor M2 may be electrically connected to the first electrode GD1 of the photodetector GD0, and the second electrode of the photodetector GD0 may be electrically connected to the bias voltage signal line. Wherein, the bias voltage signal line inputs a bias voltage to the photodetector GD0. When the photodetector GD0 receives an optical signal, an electrical signal can be generated through the photoelectric conversion effect, and this electrical signal can be transmitted to the first electrode of the photodetector GD0, and thus can be transmitted out through the second transistor M2. Exemplarily, the photodetector GD0 may be a photodiode (PIN) for example.

[0059] Exemplarily, the voltage of the reference signal terminal may be a fixed voltage. For example, the reference signal terminal may be a ground terminal.

[0060] The embodiment of the present invention also provides a driving method for a flat panel detector, which controls the detection units row by row to enter the detection period; wherein, there is at least one scanning duration interval between the detection periods of adjacent rows of detection units; the scanning duration is the maintaining duration when a first transistor is turned on;

[0061] Wherein, as Figure 2 shown, the detection period of each row of detection units has an integration stage, a pre-transfer stage, and an output stage;

[0062] S10. In the integration stage, a cut-off control signal is loaded onto the second scan line of the row to control the second transistor in the row to be cut off; and a cut-off control signal is loaded onto the first scan line of the row to control the first transistor in the row to be cut off; after the photodetector receives an optical signal, the optical signal is converted into an electrical signal;

[0063] S20. In the pre-transfer stage, a conduction control signal is loaded onto the second scan line of the row to control the second transistor in the row to be turned on; and a cut-off control signal is loaded onto the first scan line of the row to control the first transistor in the row to be cut off;

[0064] S30. In the output stage, a cut-off control signal is loaded onto the second scan line of the row to control the second transistor in the row to be cut off; and a conduction control signal is loaded onto the first scan line of the row to control the second transistor in the row to be turned on.

[0065] The following combines Figure 3 the signal timing diagram shown, Figure 1 the structure of the flat panel detector shown, to illustrate the above driving method for the flat panel detector.

[0066] Taking the flat panel detector having K rows of detection units 110 as an example, as Figure 3As shown, ga1-1 is the signal transmitted by the first scan line GA1 corresponding to the detection unit 110 in the first row, ga1-2 is the signal transmitted by the first scan line GA1 corresponding to the detection unit 110 in the second row, and ga1-K is the signal transmitted by the first scan line GA1 corresponding to the detection unit 110 in the Kth row. ga2-1 is the signal transmitted by the second scan line GA2 corresponding to the detection unit 110 in the first row, ga2-2 is the signal transmitted by the second scan line GA2 corresponding to the detection unit 110 in the second row, and ga2-K is the signal transmitted by the second scan line GA2 corresponding to the detection unit 110 in the Kth row. The specific value of K can be designed and determined according to actual applications and is not limited herein.

[0067] And, as Figure 3 shown, T10-1 represents the detection period when the detection unit in the first row enters, T10-2 represents the detection period when the detection unit in the second row enters, and T10-K represents the detection period when the detection unit in the Kth row enters. There is a scan duration interval between the detection periods of adjacent rows of detection units; wherein, the scan duration is the holding duration when a first transistor is turned on.

[0068] The detection period T10-1 when the detection unit in the first row enters may include an integration stage, a pre-transfer stage, and an output stage. In the integration stage, the first scan line GA1 corresponding to the detection unit 110 in the first row transmits the cut-off control signal (such as a low-level signal) in the signal ga1-1, and the second scan line GA2 corresponding to the detection unit 110 in the first row transmits the cut-off control signal (such as a low-level signal) in the signal ga2-1. Therefore, both the first transistor M1 and the second transistor M2 in the detection unit 110 in the first row are cut off. The photodetector GD0 can receive the optical signal and convert the received optical signal into an electrical signal.

[0069] In the pre-transfer stage, the first scan line GA1 corresponding to the detection unit 110 in the first row transmits the cut-off control signal (such as a low-level signal) in the signal ga1-1, and the second scan line GA2 corresponding to the detection unit 110 in the first row transmits the conduction control signal (such as a high-level signal) in the signal ga2-1. Therefore, the first transistor M1 in the detection unit 110 in the first row is cut off, and the second transistor M2 is turned on. After the photodetector GD0 receives the optical signal and converts it into an electrical signal, the storage capacitor CST can be charged through the turned-on second transistor M2 to store the electrical signal in the storage capacitor CST.

[0070] In the output stage, the conduction control signal (e.g., high-level signal) in the signal ga1-1 is transmitted through the first scan line GA1 corresponding to the first row detection unit 110, and the cut-off control signal (e.g., low-level signal) in the signal ga2-1 is transmitted through the second scan line GA2 corresponding to the first row detection unit 110. Therefore, the first transistor M1 in the first row detection unit 110 is turned on, and the second transistor M2 is turned off. In this way, the electrical signal stored in the storage capacitor CST can be input into the detection line SL through the turned-on first transistor M1, and then input into the detection circuit through the detection line SL, thereby forming an X-ray digital image.

[0071] The detection cycle T10-2 entered by the second row detection unit may include an integration stage, a pre-transmission stage, and an output stage. In the integration stage, the cut-off control signal (e.g., low-level signal) in the signal ga1-2 is transmitted through the first scan line GA1 corresponding to the second row detection unit 110, and the cut-off control signal (e.g., low-level signal) in the signal ga2-2 is transmitted through the second scan line GA2 corresponding to the second row detection unit 110. Therefore, both the first transistor M1 and the second transistor M2 in the second row detection unit 110 are turned off. The photoelectric detection device GD0 can receive the optical signal and convert the received optical signal into an electrical signal.

[0072] In the pre-transmission stage, the cut-off control signal (e.g., low-level signal) in the signal ga1-2 is transmitted through the first scan line GA1 corresponding to the second row detection unit 110, and the conduction control signal (e.g., high-level signal) in the signal ga2-2 is transmitted through the second scan line GA2 corresponding to the second row detection unit 110. Therefore, the first transistor M1 in the second row detection unit 110 is turned off, and the second transistor M2 is turned on. After the photoelectric detection device GD0 receives the optical signal and converts it into an electrical signal, the storage capacitor CST can be charged through the turned-on second transistor M2 to store the electrical signal into the storage capacitor CST.

[0073] In the output stage, the conduction control signal (e.g., high-level signal) in the signal ga1-2 is transmitted through the first scan line GA1 corresponding to the second row detection unit 110, and the cut-off control signal (e.g., low-level signal) in the signal ga2-2 is transmitted through the second scan line GA2 corresponding to the second row detection unit 110. Therefore, the first transistor M1 in the second row detection unit 110 is turned on, and the second transistor M2 is turned off. In this way, the electrical signal stored in the storage capacitor CST can be input into the detection line SL through the turned-on first transistor M1, and then input into the detection circuit through the detection line SL, thereby forming an X-ray digital image.

[0074] The rest can be deduced by analogy and will not be elaborated here.

[0075] Since the low-temperature polysilicon semiconductor material or the metal oxide semiconductor material has a higher mobility than the amorphous silicon semiconductor material. Therefore, in the flat panel detector provided by the embodiments of the present invention, by using the first transistor M1 as the output transistor and the second transistor M2 as the transfer transistor, the delay of the electrical signal output can be reduced, the electrical signal can be output quickly, the frame rate can be increased, and the imaging accuracy can be improved. Furthermore, a large-area flat panel detector can be realized. And by setting the second transistor M2 to control the light signal collection, the leakage current can be effectively reduced.

[0076] Moreover, for the flat panel detector provided by the embodiments of the present invention, only one first transistor M1 needs to be added to achieve the effect of reducing the delay of the electrical signal output. Its design structure is simple, has good compatibility with the manufacturing process, and is easy to perform the process preparation.

[0077] Exemplarily, the first transistor M1 can adopt a top-gate transistor, and the second transistor M2 can adopt a bottom-gate transistor.

[0078] Exemplarily, as Figure 4 As shown in Figure 5 the flat panel detector may include a substrate 100, a first semiconductor layer located on the substrate 100, a gate insulating layer 210 located on the side of the first semiconductor layer away from the substrate 100, a first conductive layer located on the side of the gate insulating layer 210 away from the substrate 100, an interlayer dielectric layer 220 located on the side of the first conductive layer away from the substrate 100, a second conductive layer located on the side of the interlayer dielectric layer 220 away from the substrate 100, and a second semiconductor layer located between the interlayer dielectric layer 220 and the second conductive layer. Among them, the second transistor M2 and the storage capacitor CST can be respectively located on the side of the first semiconductor layer away from the substrate 100.

[0079] Exemplarily, the material of the first semiconductor layer can be a low-temperature polysilicon semiconductor material. Or, the material of the first semiconductor layer can also be a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Exemplarily, as Figure 4 As shown in Figure 5 the first semiconductor layer may include the active layer M1-A of the first transistor M1. This can improve the mobility of the first transistor M1.

[0080] Exemplarily, as Figure 4 As shown in Figure 5As shown, the first conductive layer may include the gate M1-G of the first transistor M1 and the first scan line GA1; the first scan line GA1 extends along the first direction F1 and is arranged along the second direction F2. The first conductive layer may further include: the gate M2-G of the second transistor M2, the second electrode plate C1-2 of the storage capacitor CST, and the second scan line GA2; wherein, the second scan line GA2 extends along the first direction F1 and is arranged along the second direction F2. In this way, the gate M1-G of the first transistor M1, the first scan line GA1, the gate M2-G of the second transistor M2, the second electrode plate C1-2 of the storage capacitor CST, and the second scan line GA2 can be arranged in the same layer, that is, formed by a single lithography process.

[0081] Exemplarily, the first direction F1 may be a row direction or a column direction, which is not limited herein. Hereinafter, the first direction F1 is taken as an example of the row direction for illustration.

[0082] Exemplarily, as Figure 4 And Figure 5 As shown, the second semiconductor layer includes the active layer M2-A of the second transistor M2. Exemplarily, the material of the second semiconductor layer may be an amorphous silicon semiconductor material. For example, the material of the second semiconductor layer may be an amorphous silicon semiconductor material doped with H. In this way, the leakage current of the second transistor M2 can be reduced.

[0083] Exemplarily, as Figure 4 And Figure 5 As shown, the second conductive layer may include the first and second poles of the first transistor M1, the detection line SL, the first and second poles of the second transistor M2, and the first electrode plate C1-1 of the storage capacitor CST; the first and second poles of the first transistor M1 are respectively electrically connected to the active layer M1-A of the first transistor M1 through the first vias GK1 penetrating the interlayer dielectric layer 220 and the gate insulating layer 210. And, the first pole of the second transistor M2 is in direct contact with the first end of the active layer M2-A of the second transistor M2, and the second pole of the second transistor M2 is in direct contact with the second end of the active layer M2-A of the second transistor M2. And the detection line SL extends along the second direction F2 and is arranged along the first direction F1. And, the first electrode plate C1-1 of the storage capacitor CST is electrically connected between the second pole of the first transistor M1 and the first pole of the second transistor M2. In this way, the first and second poles of the first transistor M1, the detection line SL, the first and second poles of the second transistor M2, and the first electrode plate C1-1 of the storage capacitor CST can be formed by the same lithography process.

[0084] Exemplarily, the second direction F2 may be a row direction or a column direction, which is not limited herein. Hereinafter, the second direction F2 is taken as an example of the column direction for illustration.

[0085] Exemplarily, asFigure 4 As shown in Figure 5 Figure 5 , when the second conductive layer further includes the first and second poles of the second transistor M2, the first electrode plate C1-1 of the storage capacitor CST, the second pole of the first transistor M1, and the first pole of the second transistor M2 can be integrally structured.

[0086] Exemplarily, as Figure 4 shown in Figure 5 Figure 5 , the flat panel detector further includes: a planarization layer 230 on the side of the second conductive layer away from the substrate 100, a photoelectric detection device GD0 on the side of the planarization layer 230 away from the substrate 100, a photoelectric insulation layer on the side of the photoelectric detection device GD0 away from the substrate 100, a bias voltage signal line BL on the side of the photoelectric insulation layer away from the substrate 100, an adhesive layer on the side of the bias voltage signal line BL away from the substrate 100, and a protective cover plate GB on the side of the adhesive layer away from the substrate 100. Exemplarily, the second pole of the second transistor M2 is electrically connected to the first electrode GD1 of the photoelectric detection device GD0 through a via hole penetrating away from 230.

[0087] Exemplarily, as Figure 4 shown in Figure 5 Figure 5 , the photoelectric detection device GD0 may include a first electrode, a photoelectric conversion layer, and a second electrode stacked on the substrate 100. For example, the photoelectric conversion layer can be patterned so that an independent photoelectric conversion layer is provided in one detection unit 110. And, the first electrode is also patterned so that an independent first electrode is provided in one detection unit 110. And, the second electrode can cover the substrate 100 in a whole-layer manner.

[0088] Exemplarily, as Figure 4 shown in Figure 5 Figure 5 , the active layer M1-A of the first transistor M1 and the active layer M2-A of the second transistor M2 in the same detection unit 110 are located on the side of the detection unit 110 close to the detection line SL.

[0089] Exemplarily, as Figure 4 shown in Figure 5 Figure 5 , the first scan line GA1 and the second scan line GA2 corresponding to the same detection unit 110 are respectively located on both sides of the detection unit 110 in the second direction F2.

[0090] The embodiments of the present invention also provide some other flat panel detectors, as Figure 6 shown in Figure 7 Figure 7 , which are deformed from the implementation manners in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the same parts will not be elaborated here.

[0091] Exemplarily, as Figure 6 and Figure 7 shown, the flat panel detector may include a substrate 100, a first semiconductor layer located on the substrate 100, a gate insulating layer 210 located on a side of the first semiconductor layer away from the substrate 100, a first conductive layer located on a side of the gate insulating layer 210 away from the substrate 100, an interlayer dielectric layer 220 located on a side of the first conductive layer away from the substrate 100, and a second conductive layer located on a side of the interlayer dielectric layer 220 away from the substrate 100. Further, the interlayer dielectric layer 220 may include a first interlayer dielectric layer 220 located between the substrate 100 and the second conductive layer, and a second interlayer dielectric layer 220 located between the first interlayer dielectric layer 220 and the second conductive layer, that is, the second conductive layer is located on a side of the second interlayer dielectric layer 220 away from the substrate 100. Further, the flat panel detector may further include: a third conductive layer located between the first interlayer dielectric layer 220 and the second interlayer dielectric layer 220, and a second semiconductor layer located between the second interlayer dielectric layer 220 and the second conductive layer.

[0092] Exemplarily, as Figure 6 and Figure 7 shown, the first semiconductor layer may include an active layer M1-A of a first transistor M1. This can improve the mobility of the first transistor M1.

[0093] Exemplarily, as Figure 6 and Figure 7 shown, the first conductive layer may include a gate M1-G of the first transistor M1 and a first scan line GA1; the first scan line GA1 extends along a first direction F1 and is arranged along a second direction F2. This can make the gate M1-G of the first transistor M1 and the first scan line GA1 be arranged in the same layer, that is, formed by a single patterning process.

[0094] Exemplarily, as Figure 6 and Figure 7 shown, the third conductive layer includes: a gate M2-G of a second transistor M2 and a second scan line GA2; the second scan line GA2 may extend along the second direction F2 and be arranged along the first direction F1. Of course, the second scan line GA2 may also extend along the first direction F1 and be arranged along the second direction F2, which is not limited herein. This can make the gate M2-G of the second transistor M2 and the second scan line GA2 be arranged in the same layer, that is, formed by a single patterning process.

[0095] Exemplarily, as Figure 6 and Figure 7As shown, the third conductive layer may further include: the second electrode plate C1-2 of the storage capacitor CST. In this way, the gate M2-G of the second transistor M2, the second electrode plate C1-2 of the storage capacitor CST, and the second scan line GA2 can be arranged on the same layer, that is, formed by a single lithography process.

[0096] Exemplarily, as Figure 6 With Figure 7 As shown, the second semiconductor layer includes the active layer M2-A of the second transistor M2. Exemplarily, the material of the second semiconductor layer may be an amorphous silicon semiconductor material. For example, the material of the second semiconductor layer may be an amorphous silicon semiconductor material doped with H. This can reduce the leakage current of the second transistor M2.

[0097] Exemplarily, as Figure 6 With Figure 7 As shown, the second conductive layer may include the first pole and the second pole of the first transistor M1, the detection line SL, the first pole and the second pole of the second transistor M2, and the first electrode plate C1-1 of the storage capacitor CST; the first pole and the second pole of the first transistor M1 are respectively electrically connected to the active layer M1-A of the first transistor M1 through the first vias GK1 penetrating the interlayer dielectric layer 220 and the gate insulating layer 210. And, the first pole of the second transistor M2 is in direct contact with the first end of the active layer M2-A of the second transistor M2, and the second pole of the second transistor M2 is in direct contact with the second end of the active layer M2-A of the second transistor M2. And the detection line SL extends along the second direction F2 and is arranged along the first direction F1. And, the first electrode plate C1-1 of the storage capacitor CST is electrically connected between the second pole of the first transistor M1 and the first pole of the second transistor M2. In this way, the first pole and the second pole of the first transistor M1, the detection line SL, the first pole and the second pole of the second transistor M2, and the first electrode plate C1-1 of the storage capacitor CST can be formed by the same lithography process.

[0098] Exemplarily, as Figure 6 With Figure 7 As shown, the photodetector GD0 may include a first electrode, a photoelectric conversion layer, and a second electrode stacked on the substrate 100. For example, the photoelectric conversion layer can be arranged to cover the substrate 100 in a single layer, and the first electrode is patterned so that an independent first electrode is provided in one detection unit 110. And, the second electrode can be arranged to cover the substrate 100 in a single layer.

[0099] Exemplarily, as Figure 6 With Figure 7As shown, the active layer M1-A of the first transistor M1 and the active layer M2-A of the second transistor M2 in the same detection unit 110 are located at both ends of the diagonal of the detection unit 110. Exemplarily, the detection unit 110 may be rectangular, then the active layer M1-A of the first transistor M1 and the active layer M2-A of the second transistor M2 may be located at both ends of the diagonal in the rectangular detection unit 110.

[0100] Exemplarily, as Figure 6 With Figure 7 shown, the second scan line GA2 may extend along the second direction F2 and be arranged along the first direction F1. The second scan line GA2 and the detection line SL corresponding to the same detection unit 110 are respectively located on both sides of the detection unit 110 in the first direction F1.

[0101] Alternatively, the second scan line GA2 may extend along the first direction F1 and be arranged along the second direction F2. The first scan line GA1 and the second scan line GA2 corresponding to the same detection unit 110 are respectively located on both sides of the detection unit 110 in the second direction F2.

[0102] The embodiments of the present invention also provide some flat panel detectors, such as Figure 8 With Figure 9 shown, which is a deformation of the implementation manner in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the same parts will not be elaborated here.

[0103] Exemplarily, as Figure 8 With Figure 9 shown, the flat panel detector may include a substrate 100, a first semiconductor layer located on the substrate 100, a gate insulating layer 210 located on the side of the first semiconductor layer away from the substrate 100, a first conductive layer located on the side of the gate insulating layer 210 away from the substrate 100, an interlayer dielectric layer 220 located on the side of the first conductive layer away from the substrate 100, a second conductive layer located on the side of the interlayer dielectric layer 220 away from the substrate 100, an interlayer insulating layer located on the side of the second conductive layer away from the substrate 100, a second semiconductor layer located on the side of the interlayer insulating layer away from the substrate 100, and a fourth conductive layer located on the side of the second semiconductor layer away from the substrate 100.

[0104] Exemplarily, as Figure 8 With Figure 9 shown, the first semiconductor layer may include the active layer M1-A of the first transistor M1. This can improve the mobility of the first transistor M1.

[0105] Exemplarily, as Figure 8 With Figure 9As shown, the first conductive layer may include the gate M1-G of the first transistor M1 and the first scan line GA1; the first scan line GA1 extends along the first direction F1 and is arranged along the second direction F2. This enables the gate M1-G of the first transistor M1 and the first scan line GA1 to be formed on the same layer, that is, formed by a single lithography process.

[0106] Exemplarily, as Figure 8 shown in connection with Figure 9 the first conductive layer may further include: the second electrode plate C1-2 of the storage capacitor CST. This enables the gate M1-G of the first transistor M1, the first scan line GA1, and the second electrode plate C1-2 of the storage capacitor CST to be formed on the same layer, that is, formed by a single lithography process.

[0107] Exemplarily, as Figure 8 shown in connection with Figure 9 the second conductive layer may include the first and second poles of the first transistor M1, the detection line SL, the gate M2-G of the second transistor M2, and the second scan line GA2; wherein, the detection line SL may extend along the second direction F2 and be arranged along the first direction F1, and the second scan line GA2 extends along the second direction F2 and is arranged along the first direction F1.

[0108] Exemplarily, as Figure 8 shown in connection with Figure 9 the second conductive layer may further include the first electrode plate C1-1 of the storage capacitor CST. The first electrode plate C1-1 of the storage capacitor CST and the second pole of the first transistor M1 are integrally formed, and the first pole of the second transistor M2 is electrically connected to the first electrode plate C1-1 of the storage capacitor CST through a second via.

[0109] Exemplarily, as Figure 8 shown in connection with Figure 9 the second semiconductor layer includes the active layer M2-A of the second transistor M2. Exemplarily, the material of the second semiconductor layer may be an amorphous silicon semiconductor material. For example, the material of the second semiconductor layer may be an amorphous silicon semiconductor material doped with H. This can reduce the leakage current of the second transistor M2.

[0110] Exemplarily, as Figure 8 shown in connection with Figure 9As shown, the fourth conductive layer may include the first and second poles of the second transistor M2. Among them, the first pole of the second transistor M2 is in direct contact with the first end of the active layer M2-A of the second transistor M2, the second pole of the second transistor M2 is in direct contact with the second end of the active layer M2-A of the second transistor M2, and the second pole of the second transistor M2 is electrically connected to the first pole of the first transistor M1 through a second via hole penetrating the interlayer insulating layer. Exemplarily, the second pole of the second transistor M2 is electrically connected to the first electrode plate C1-1 of the storage capacitor CST through a second via hole penetrating the interlayer insulating layer.

[0111] Exemplarily, as Figure 8 and Figure 9 shown, the active layer M1-A of the first transistor M1 and the active layer M2-A of the second transistor M2 in the same detection unit 110 are located at both ends of the diagonal of the detection unit 110. Exemplarily, if the detection unit 110 is rectangular, then the active layer M1-A of the first transistor M1 and the active layer M2-A of the second transistor M2 may be located at both ends of the diagonal in the rectangular detection unit 110.

[0112] Exemplarily, as Figure 8 and Figure 9 shown, the second scan line GA2 may extend along the second direction F2 and be arranged along the first direction F1. The second scan line GA2 and the detection line SL corresponding to the same detection unit 110 are respectively located on both sides of the detection unit 110 in the first direction F1.

[0113] Alternatively, the second scan line GA2 may extend along the first direction F1 and be arranged along the second direction F2. The first scan line GA1 and the second scan line GA2 corresponding to the same detection unit 110 are respectively located on both sides of the detection unit 110 in the second direction F2.

[0114] It should be noted that the technical features in the above embodiments can be combined with each other, and the combined solutions will not be elaborated here.

[0115] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A flat panel detector, comprising: A substrate, a plurality of scan lines and a plurality of detection lines located on the substrate, and a plurality of detection units defined by the plurality of scan lines and the plurality of detection lines; characterized in that the plurality of scan lines include a plurality of first scan lines and a plurality of second scan lines; Each of the detection units includes: a first transistor, a second transistor, a storage capacitor, and a photodetector; the material of the active layer of the second transistor is amorphous silicon semiconductor material, and the material of the active layer of the first transistor is low-temperature polycrystalline silicon semiconductor material or metal oxide semiconductor material; The gate of the first transistor is electrically connected to the first scan line, the first pole of the first transistor is electrically connected to the detection line, and the second pole of the first transistor is respectively electrically connected to the first electrode plate of the storage capacitor and the first pole of the second transistor; The gate of the second transistor is electrically connected to the second scan line, and the second pole of the second transistor is electrically connected to the photodetector; The second electrode plate of the storage capacitor is electrically connected to the reference signal terminal; The flat panel detector includes: A first semiconductor layer located on the substrate; wherein, the first semiconductor layer includes the active layer of the first transistor; A gate insulating layer located on the side of the first semiconductor layer away from the substrate; A first conductive layer located on the side of the gate insulating layer away from the substrate; wherein, the first conductive layer includes the gate of the first transistor and the first scan line; the first scan line extends in a first direction; An interlayer dielectric layer located on the side of the first conductive layer away from the substrate; A second conductive layer located on the side of the interlayer dielectric layer away from the substrate; wherein, the second conductive layer includes the first and second poles of the first transistor and the detection line; the first and second poles of the first transistor are respectively electrically connected to the active layer of the first transistor through a first via hole penetrating the interlayer dielectric layer and the gate insulating layer; the detection line extends in a second direction; The second transistor and the storage capacitor are respectively located on the side of the first semiconductor layer away from the substrate.

2. The flat panel detector according to claim 1, wherein, The first conductive layer further includes: the gate of the second transistor and the second scan line; wherein, the second scan line extends in the first direction; The flat panel detector further includes: a second semiconductor layer located between the interlayer dielectric layer and the second conductive layer; wherein, the second semiconductor layer includes the active layer of the second transistor; The second conductive layer further includes the first and second poles of the second transistor; wherein, the first pole of the second transistor is in direct contact with the first end of the active layer of the second transistor, and the second pole of the second transistor is in direct contact with the second end of the active layer of the second transistor.

3. The flat panel detector according to claim 2, characterized in that, The active layers of the first transistor and the second transistor in the same detection unit are located on the side of the detection unit close to the detection line; The first scan line and the second scan line corresponding to the same detection unit are respectively located on both sides of the detection unit in the second direction.

4. The flat panel detector according to claim 1, characterized in that, The interlayer dielectric layer includes a first interlayer dielectric layer located between the substrate and the second conductive layer, and a second interlayer dielectric layer located between the first interlayer dielectric layer and the second conductive layer; The flat panel detector further includes: a third conductive layer located between the first interlayer dielectric layer and the second interlayer dielectric layer, and a second semiconductor layer located between the second interlayer dielectric layer and the second conductive layer; wherein, the third conductive layer includes: the gate of the second transistor and the second scan line; the second scan line extends along the first direction or the second direction; The second semiconductor layer includes the active layer of the second transistor; The second conductive layer further includes the first and second poles of the second transistor; wherein, the first pole of the second transistor is in direct contact with the first end of the active layer of the second transistor, and the second pole of the second transistor is in direct contact with the second end of the active layer of the second transistor.

5. The flat panel detector according to claim 4, wherein, The active layer of the first transistor and the active layer of the second transistor in the same detection unit are located at both ends of the diagonal of the detection unit; The second scan line and the detection line corresponding to the same detection unit are respectively located on both sides of the detection unit in the first direction.

6. The flat panel detector according to claim 1, wherein The second conductive layer further includes the gate of the second transistor and the second scan line; wherein, the second scan line extends along the second direction; The flat panel detector further includes: an interlayer insulating layer located on the side of the second conductive layer away from the substrate, a second semiconductor layer located on the side of the interlayer insulating layer away from the substrate, and a fourth conductive layer located on the side of the second semiconductor layer away from the substrate; The second semiconductor layer includes the active layer of the second transistor; The fourth conductive layer includes the first and second poles of the second transistor; wherein, the first pole of the second transistor is in direct contact with the first end of the active layer of the second transistor, the second pole of the second transistor is in direct contact with the second end of the active layer of the second transistor, and the second pole of the second transistor is electrically connected to the first pole of the first transistor through a second via hole penetrating the interlayer insulating layer.

7. The flat panel detector according to any one of claims 1-6, characterized in that, The second conductive layer further includes the first electrode plate of the storage capacitor; wherein, the first electrode plate of the storage capacitor is electrically connected between the second pole of the first transistor and the first pole of the second transistor.

8. The flat panel detector according to claim 6, characterized in that, The second conductive layer further includes the first electrode plate of the storage capacitor; wherein, the first electrode plate of the storage capacitor is electrically connected between the second pole of the first transistor and the first pole of the second transistor; When the second conductive layer further includes the first and second poles of the second transistor, the first electrode plate of the storage capacitor, the second pole of the first transistor, and the first pole of the second transistor are integrally structured; When the fourth conductive layer includes the first pole of the second transistor, the first electrode plate of the storage capacitor and the second pole of the first transistor are integrally structured, and the first pole of the second transistor is electrically connected to the first electrode plate of the storage capacitor through a second via hole.

9. The flat panel detector according to any one of claims 1-6, characterized in that, The first conductive layer further includes a second electrode plate of the storage capacitor; or, The interlayer dielectric layer includes a first interlayer dielectric layer between the substrate and the second conductive layer, and a second interlayer dielectric layer between the first interlayer dielectric layer and the second conductive layer; The flat panel detector further includes: a third conductive layer between the first interlayer dielectric layer and the second interlayer dielectric layer; wherein, the third conductive layer includes: a second electrode plate of the storage capacitor.

10. A driving method for a flat panel detector according to any one of claims 1-9, characterized in that, Controlling the detection units row by row to enter a detection period; wherein, there is at least one scan duration between the detection periods of adjacent rows of detection units; the scan duration is the holding duration when one of the first transistors is turned on; Wherein, the detection period of each row of detection units has an integration stage, a pre-transfer stage, and an output stage; In the integration stage, a cut-off control signal is loaded onto the second scan line of the row to control the second transistor in the row to be cut off; and a cut-off control signal is loaded onto the first scan line of the row to control the first transistor in the row to be cut off; after the photodetector receives an optical signal, the optical signal is converted into an electrical signal; In the pre-transfer stage, a conduction control signal is loaded onto the second scan line of the row to control the second transistor in the row to be turned on; and a cut-off control signal is loaded onto the first scan line of the row to control the first transistor in the row to be cut off; In the output stage, a cut-off control signal is loaded onto the second scan line of the row to control the second transistor in the row to be cut off; and a conduction control signal is loaded onto the first scan line of the row to control the second transistor in the row to be turned on.

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