A method, system and related components for hot reboot of a PCI device

Abstract

The application discloses a PCI device hot restart method, system and device and a computer readable storage medium. The PCI device hot restart method comprises the following steps: acquiring GPIO state values of PCI slots with different bandwidths for performing a hot restart operation; determining output state values of each GPIO signal interface according to the GPIO state values; controlling each GPIO signal interface to output a GPIO signal according to the corresponding output state value, and delaying for a preset time, so that a PCI device connected to the PCI slot with different bandwidths is hot restarted. The GPIO signal interface of the ARM processor is physically connected to the Reset signal interface of the PCI slot with x16 bandwidth, and the GPIO signal output by each GPIO signal interface can realize the hot restart of the PCI device with different bandwidths.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of servers, in particular to a PCI device hot restart method, system and related components. BACKGROUND

[0002] At present, the most commonly used in server products is the PCI (Peripheral Component Interconnect) bus, and the PCI devices mounted on the PCI bus include but are not limited to PCI standard network cards, PCI standard NVME (Non Volatile Memory Express) hard disks, PCIE (Peripheral Component Interconnect Express) standard storage cards, etc. These PCI devices need to perform corresponding hot restart operations when the system is hot restarted, so that the driver of the PCI device can be obtained again during the startup process of the server and can be normally used. In order to improve the hot restart efficiency of the PCI device, a systemReset signal is used by hardware engineers to support the hot restart function of all PCI devices when designing server products. However, in the design of emerging ARM (Advanced RISC Machine) server field chips, there is no such systemReset signal, and the hot restart function of the PCI device cannot be supported by the above-mentioned method.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. SUMMARY

[0004] The purpose of the present application is to provide a PCI device hot restart method, system, device and computer readable storage medium, which physically connects the GPIO signal interface of the ARM processor with the Reset signal interface of the x16 bandwidth PCI slot, and realizes the hot restart of the PCI device with different bandwidths through the GPIO signal output by each GPIO signal interface.

[0005] To solve the above technical problems, the present application provides a PCI device hot restart method applied to an ARM mainboard, wherein the ARM mainboard is provided with an ARM processor and PCI slots with multiple bandwidths, and a plurality of GPIO signal interfaces of the AMR processor are connected with the Reset signal interface of the PCI slot with x16 bandwidth. The PCI device hot restart method comprises the following steps:

[0006] acquiring the GPIO state value of the PCI slot of each bandwidth for performing the hot restart operation;

[0007] determining the output state value of each GPIO signal interface according to the GPIO state value;

[0008] controlling each GPIO signal interface to output a GPIO signal according to the corresponding output state value and delaying for a preset time so that the PCI device connected with the PCI slot of each bandwidth is hot restarted.

[0009] Optionally, the process of acquiring the GPIO state value of the PCI slot of each bandwidth for performing the hot restart operation comprises:

[0010] determining the GPIO state value of the PCI slot of each bandwidth for performing the hot restart operation according to the split state of the PCI slot of the x16 bandwidth and the ARM processor thereof.

[0011] Optionally, the process of determining the GPIO state value of the PCI slot of each bandwidth for performing the hot restart operation according to the split state of the PCI slot of the x16 bandwidth and the ARM processor thereof comprises:

[0012] selecting a preset state value table according to the split state of the PCI slot of the x16 bandwidth and the ARM processor thereof;

[0013] acquiring the GPIO state value of the PCI slot of each bandwidth for performing the hot restart operation in the preset state value table.

[0014] Optionally, the number of GPIO signal interfaces is four.

[0015] Optionally, after the preset time is delayed, the PCI device hot restart method further comprises:

[0016] controlling each GPIO signal interface to output a GPIO signal according to the high state value.

[0017] Optionally, before the GPIO state value of the PCI slot of each bandwidth for performing the hot restart operation is acquired, the PCI device hot restart method further comprises:

[0018] controlling each GPIO signal interface to output a GPIO signal according to the high state value when the ARM mainboard is powered on.

[0019] Optionally, the process of controlling each GPIO signal interface to output a GPIO signal according to the corresponding output state value comprises:

[0020] Simultaneously or sequentially control each of the GPIO signal interfaces to output a GPIO signal according to the corresponding output state value.

[0021] To solve the above technical problems, the application further provides a PCI device hot restart system applied to an ARM mainboard, wherein the ARM mainboard is provided with an ARM processor and PCI slots with various bandwidths, a plurality of GPIO signal interfaces of the AMR processor are connected with a Reset signal interface of the PCI slot with x16 bandwidth, and the PCI device hot restart system comprises:

[0022] An acquisition module is configured to acquire GPIO state values of the PCI slots with various bandwidths for performing a hot restart operation.

[0023] A determination module is configured to determine output state values of each of the GPIO signal interfaces according to the GPIO state values.

[0024] A control module is configured to control each of the GPIO signal interfaces to output a GPIO signal according to the corresponding output state value and delay for a preset time, so as to make a PCI device connected with the PCI slots with various bandwidths to be hot restarted.

[0025] To solve the above technical problems, the application further provides a PCI device hot restart device, which comprises:

[0026] A memory is configured to store a computer program.

[0027] A processor is configured to execute the computer program to realize the steps of the PCI device hot restart method according to any one of the above.

[0028] To solve the above technical problems, the application further provides a computer readable storage medium, wherein the computer readable storage medium is stored with a computer program, and the computer program is executed by a processor to realize the steps of the PCI device hot restart method according to any one of the above.

[0029] The application provides a PCI device hot restart method, wherein a GPIO signal interface of an ARM processor is physically connected with a Reset signal interface of a PCI slot with x16 bandwidth, the PCI slot with x16 bandwidth can be split into PCI slots with other bandwidths, GPIO state values required for performing a hot restart operation through the PCI slots with various bandwidths are acquired, output state values of each of the GPIO signal interfaces are set, each of the GPIO signal interfaces is controlled to output a GPIO signal corresponding to the output state value, and a preset time is delayed, so as to realize hot restart of PCI devices with different bandwidths. The application further provides a PCI device hot restart system, device and computer readable storage medium, which have the same beneficial effects as the PCI device hot restart method. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0031] Figure 1 A structure schematic diagram of an ARM mainboard provided by the present application;

[0032] Figure 2 A step flow chart of a PCI device hot restart method provided by the present application;

[0033] Figure 3 A structure schematic diagram of a PCI device hot restart system provided by the present application. DETAILED DESCRIPTION

[0034] The core of the present application is to provide a PCI device hot restart method, system, device and computer readable storage medium, physically connecting the GPIO signal interface of the ARM processor with the Reset signal interface of the x16 bandwidth PCI slot, and the GPIO signal output by each GPIO signal interface can realize the hot restart of the PCI device with different bandwidths.

[0035] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort are within the scope of protection of the present application.

[0036] In order to facilitate the understanding of the scheme of the present application, the ARM server to which the PCI device hot restart method is applied is described. The ARM server includes an ARM mainboard. The structure of the ARM mainboard refers to Figure 1 The ARM mainboard includes an ARM processor and PCI slots with various bandwidths, including x16 bandwidth PCI slots, x8 bandwidth PCI slots and x4 bandwidth PCI slots. The ARM processor includes a plurality of GPIO signal interfaces. In Figure 1 only four GPIO signal interfaces are shown, the x16 bandwidth PCI slot includes 16 Reset signal interfaces, the 16 Reset signal interfaces are divided into four groups, each group includes four Reset signal interfaces, and the four GPIO signal interfaces are respectively connected with the four groups of Reset signal interfaces, such as Figure 1As shown, the x16 bandwidth PCI slot can be split into two groups of x8 bandwidth PCI slots, can also be split into four groups of x4 bandwidth PCI slots, and can also be split into one group of x8 bandwidth PCI slots and two groups of x4 bandwidth PCI slots.

[0037] Please refer to Figure 2 , Figure 2 A step flowchart of a PCI device hot restart method provided by the present application is shown. The PCI device hot restart method comprises the following steps:

[0038] S101: Obtain the GPIO state value of each bandwidth PCI slot for performing a hot restart operation.

[0039] Specifically, the required GPIO state value for performing a hot restart operation is different for different bandwidth PCI slots. In order to implement the subsequent hot restart of the PCI device on each PCI slot, the GPIO state value required by each bandwidth PCI slot for performing a hot restart operation is first obtained.

[0040] It can be understood that the GPIO state value corresponding to each bandwidth PCI slot is adaptively adjusted according to the ARM server to which the x16 bandwidth PCI slot belongs and the split state thereof. Therefore, the operation of obtaining the ARM server to which the x16 bandwidth PCI slot belongs and the split state thereof is further included before the present step. Then, according to the split state of the x16 bandwidth PCI slot and the ARM processor to which it belongs, the GPIO state value of each bandwidth PCI slot for performing a hot restart operation under the current split state is determined.

[0041] Specifically, the GPIO state value of each bandwidth PCI slot for hot restart operation can be set in advance according to actual engineering needs. As an optional embodiment, a table of GPIO state values required by each bandwidth PCI slot corresponding to the x16 bandwidth PCI slot under different split states and different ARM servers to which it belongs can be created in advance. In this way, in subsequent actual applications, the target GPIO state value table can be determined according to the current ARM server to which the x16 bandwidth PCI slot belongs and the split state thereof, and the GPIO state value corresponding to each bandwidth PCI slot under the current split state can be determined according to the target GPIO state value table.

[0042] S102: Determine the output state value of each GPIO signal interface according to the GPIO state value.

[0043] S103: Control each GPIO signal interface to output a GPIO signal according to the output state value corresponding thereto, and delay for a preset time, so as to hot restart the PCI device connected to each bandwidth PCI slot.

[0044] Specifically, the output state value of each GPIO signal interface can be determined according to the GPIO state value, and each GPIO signal interface outputs a GPIO signal to the Reset signal interface of the corresponding bandwidth PCI slot according to the corresponding output state value, so that the PCI device on the bandwidth PCI slot is triggered to perform a hot restart operation. It can be understood that in the embodiment, each GPIO signal interface outputs a GPIO signal according to the corresponding output state value and delays for a preset time, so as to ensure that the PCI device can normally complete the hot restart operation. The preset time can be determined according to the time required for the complete hot restart of the PCI device, for example, it can be set to 100 ms.

[0045] For example, assuming that the GPIO state value required for the x16 bandwidth PCI slot to perform a hot restart operation is 0111, then the output state values of GPIO1, GPIO2, GPIO3 and GPIO4 in the GPIO state value are set to 0, 1, 1 and 1 respectively. Figure 1

[0046] Specifically, before performing the step, the operation of judging whether there is a PCI device on each bandwidth PCI slot in the current split state is further included. If there is no PCI device on a bandwidth PCI slot, the output state value of each GPIO signal interface corresponding to the bandwidth PCI slot is not set, and the output state value is maintained in the default state. It can be understood that when the ARM mainboard is powered on, the BIOS defaults to set the output state value of the four GPIOs to a high state value. Therefore, maintaining the default state means maintaining the high state value state.

[0047] As an optional embodiment, the process of controlling each GPIO signal interface to output a GPIO signal according to the corresponding output state value includes:

[0048] The GPIO signal interfaces are simultaneously or sequentially controlled to output a GPIO signal according to the corresponding output state value.

[0049] Specifically, the output state value of each GPIO signal interface in the embodiment can be set simultaneously or sequentially. Simultaneous pull-down setting can ensure signal synchronization and avoid hot restart loss of the PCI device.

[0050] It can be seen that in the embodiment, the GPIO signal interface of the ARM processor is physically connected to the Reset signal interface of the x16 bandwidth PCI slot. The x16 bandwidth PCI slot can be split into other bandwidth PCI slots. The GPIO state value required for the hot restart operation of each bandwidth PCI slot is set to the output state value of each GPIO signal interface, and each GPIO signal interface outputs a GPIO signal corresponding to the output state value and delays for a preset time, so that the hot restart of the PCI device with different bandwidths can be realized.​

[0051] On the basis of the above-mentioned embodiments,

[0052] As an optional embodiment, after the preset time is delayed, the PCI device hot restart method further comprises:

[0053] Controlling each GPIO signal interface to output the GPIO signal in the high state value.

[0054] Specifically, considering that the x16 bandwidth PCI slot can be split into PCI slots of various bandwidths, and the GPIO state values required for performing the hot restart operation by the PCI slots of different bandwidths are different, when the x16 bandwidth PCI slot is split into PCI slots of various bandwidths, such as x8x4x4, the steps of S102-S103 need to be performed multiple times in order to control the hot restart of the PCI device on the x8 bandwidth PCI slot and the hot restart of the PCI device on the x4 bandwidth PCI slot, respectively.

[0055] For example, the output state values of the four GPIO signal interfaces can be set to the GPIO state values required for the hot restart of the x8 bandwidth PCI slot, the four GPIO interfaces output the corresponding GPIO signals, and a preset time is delayed to complete the hot restart of the x8 bandwidth PCI device. In order to meet the hot restart function of the subsequent x4 bandwidth PCI slot, after the preset time is delayed, each GPIO signal interface is controlled to output the GPIO signal in the high state value, and then the output state values of the four GPIO signal interfaces are set to the GPIO state values required for the hot restart of the x4 bandwidth PCI slot, the four GPIO interfaces output the corresponding GPIO signals, and a preset time is delayed to complete the hot restart of the x4 bandwidth PCI device.

[0056] It can be understood that, since the GPIO state values required for the hot restart of the PCI slots of different bandwidths are different, the hot restart of the PCI device on the x4 bandwidth PCI slot will not affect the normal operation of the x8 bandwidth PCI device, and similarly, the hot restart of the x8 bandwidth PCI device will not affect the x4 bandwidth PCI device.

[0057] In summary, in the present application, the BIOS confirms the GPIO state value table used by the PCI slot by confirming the processor from which the different bandwidth PCI slot comes and whether there is a split condition and the like, the BIOS code realizes the hot restart function of the different bandwidth PCI slot device by simultaneously pulling down the four GPIO signals according to the state value table and delaying for 100 ms, ensures that the PCI device can still be normally used after the ARM server is hot restarted, effectively guarantees the large-scale deployment and application of the ARM server, and conforms to the future development trend of the ARM server technology.

[0058] Please refer to Figure 3 , Figure 3 The present application provides a structure diagram of a PCI device hot restart system, which is applied to an ARM mainboard, the ARM mainboard is provided with an ARM processor and PCI slots with multiple bandwidths, a plurality of GPIO signal interfaces of the ARM processor are connected with a Reset signal interface of the PCI slot with x16 bandwidth, and the PCI device hot restart system comprises:

[0059] An acquisition module 1 is configured to acquire GPIO state values of the PCI slots with multiple bandwidths for performing a hot restart operation;

[0060] A determination module 2 is configured to determine output state values of each GPIO signal interface according to the GPIO state values;

[0061] A control module 3 is configured to control each GPIO signal interface to output a GPIO signal according to the corresponding output state value and delay for a preset time, so that the PCI device connected with the PCI slot with multiple bandwidths is hot restarted.

[0062] It can be seen that in the embodiment, the GPIO signal interface of the ARM processor is physically connected with the Reset signal interface of the PCI slot with x16 bandwidth, the PCI slot with x16 bandwidth can be split into PCI slots with other bandwidths, the GPIO state values required for performing the hot restart operation through the PCI slots with multiple bandwidths are acquired, the output state values of each GPIO signal interface are set, each GPIO signal interface is controlled to output the GPIO signal corresponding to the output state value, and a preset time is delayed, so that the hot restart of the PCI device with different bandwidths is realized.

[0063] As an optional embodiment, the acquisition module 1 is specifically configured to:

[0064] Determine the GPIO state values of each PCI slot with multiple bandwidths for performing the hot restart operation according to the split state of the PCI slot with x16 bandwidth and the ARM processor to which the PCI slot belongs.

[0065] As an optional embodiment, the process of determining the GPIO state value of each bandwidth PCI slot for performing the hot restart operation according to the split state of the x16 bandwidth PCI slot and the ARM processor to which the x16 bandwidth PCI slot belongs comprises:

[0066] selecting a preset state value table according to the split state of the x16 bandwidth PCI slot and the ARM processor to which the x16 bandwidth PCI slot belongs;

[0067] obtaining the GPIO state value of each bandwidth PCI slot for performing the hot restart operation in the preset state value table.

[0068] As an optional embodiment, the number of GPIO signal interfaces is 4.

[0069] As an optional embodiment, the control module 3 is further configured to control each GPIO signal interface to output the GPIO signal in the high state value after delaying a preset time.

[0070] As an optional embodiment, the control module 3 is further configured to control each GPIO signal interface to output the GPIO signal in the high state value when the ARM mainboard is powered on.

[0071] As an optional embodiment, the process of controlling each GPIO signal interface to output the GPIO signal in the respective corresponding output state value comprises:

[0072] controlling each GPIO signal interface to output the GPIO signal in the respective corresponding output state value simultaneously or sequentially.

[0073] On the other hand, the present application also provides a PCI device hot restart device, comprising:

[0074] a memory for storing a computer program;

[0075] a processor for executing the computer program to implement the steps of the PCI device hot restart method described in any one of the above embodiments.

[0076] Specifically, the memory comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer readable instructions, and the internal memory provides an environment for the operating system and computer readable instructions in the non-volatile storage medium. When the processor executes the computer program stored in the memory, the following steps can be implemented: obtaining the GPIO state value of each bandwidth PCI slot for performing the hot restart operation; determining the output state value of each GPIO signal interface according to the GPIO state value; controlling each GPIO signal interface to output the GPIO signal in the respective corresponding output state value, and delaying a preset time to enable the PCI device connected to the bandwidth PCI slot to perform the hot restart.

[0077] It can be seen that in the embodiment, the GPIO signal interface of the ARM processor is physically connected with the Reset signal interface of the x16 bandwidth PCI slot, the x16 bandwidth PCI slot can be split into other bandwidth PCI slots, the output state value of each GPIO signal interface is set by the GPIO state value required for performing the hot restart operation through each bandwidth PCI slot, each GPIO signal interface outputs the GPIO signal corresponding to the output state value, and the GPIO signal is delayed for a preset time, so that the hot restart of the PCI device with different bandwidths is realized.

[0078] As an optional embodiment, when the processor executes the computer program stored in the memory, the following steps can be implemented: determining the GPIO state value of each bandwidth PCI slot for performing the hot restart operation according to the splitting state of the x16 bandwidth PCI slot and the ARM processor belonging to the x16 bandwidth PCI slot.

[0079] As an optional embodiment, when the processor executes the computer program stored in the memory, the following steps can be implemented: selecting a preset state value table according to the splitting state of the x16 bandwidth PCI slot and the ARM processor belonging to the x16 bandwidth PCI slot; and obtaining the GPIO state value of each bandwidth PCI slot for performing the hot restart operation in the preset state value table.

[0080] As an optional embodiment, when the processor executes the computer program stored in the memory, the following steps can be implemented: after delaying for a preset time, controlling each GPIO signal interface to output the GPIO signal in the high state value.

[0081] As an optional embodiment, when the processor executes the computer program stored in the memory, the following steps can be implemented: when the ARM mainboard is powered on, controlling each GPIO signal interface to output the GPIO signal in the high state value.

[0082] As an optional embodiment, when the processor executes the computer program stored in the memory, the following steps can be implemented: simultaneously or sequentially controlling each GPIO signal interface to output the GPIO signal in the corresponding output state value.

[0083] On the other hand, the application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of the PCI device hot restart method described in any one of the above embodiments are implemented.

[0084] The application further provides a computer readable storage medium, which can include a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk and various storage program code mediums. The storage medium stores a computer program, and the computer program is executed by a processor to implement the following steps: obtaining a GPIO state value of each bandwidth PCI slot for performing a hot restart operation; determining an output state value of each GPIO signal interface according to the GPIO state value; controlling each GPIO signal interface to output a GPIO signal according to the corresponding output state value, and delaying for a preset time to enable the PCI device connected to the PCI slot of each bandwidth to perform a hot restart.

[0085] It can be seen that, in the embodiment, the GPIO signal interface of the ARM processor is physically connected to the Reset signal interface of the x16 bandwidth PCI slot, the x16 bandwidth PCI slot can be split into other bandwidth PCI slots, the GPIO state value required for performing the hot restart operation through each bandwidth PCI slot is set to the output state value of each GPIO signal interface, and each GPIO signal interface outputs the GPIO signal corresponding to the output state value and delays for a preset time, so that the hot restart of the PCI device of different bandwidths is realized.

[0086] As an optional embodiment, when the computer program stored in the computer readable storage medium is executed by the processor, the following steps can be specifically implemented: determining the GPIO state value of each bandwidth PCI slot for performing the hot restart operation according to the splitting state of the x16 bandwidth PCI slot and the ARM processor.

[0087] As an optional embodiment, when the computer program stored in the computer readable storage medium is executed by the processor, the following steps can be specifically implemented: selecting a preset state value table according to the splitting state of the x16 bandwidth PCI slot and the ARM processor; and obtaining the GPIO state value of each bandwidth PCI slot for performing the hot restart operation in the preset state value table.

[0088] As an optional embodiment, when the computer program stored in the computer readable storage medium is executed by the processor, the following steps can be specifically implemented: after delaying for a preset time, controlling each GPIO signal interface to output a GPIO signal according to the high state value.

[0089] As an optional embodiment, when the computer program stored in the computer readable storage medium is executed by the processor, the following steps can be specifically implemented: when the ARM mainboard is powered on, controlling each GPIO signal interface to output a GPIO signal according to the high state value.

[0090] As an optional embodiment, the computer program stored in the computer readable storage medium is executed by the processor, and the following steps can be specifically implemented: the respective GPIO signal interfaces are controlled to output the GPIO signals according to the respective corresponding output state values simultaneously or sequentially.

[0091] It should also be noted that the terms such as first and second, etc., are merely used to distinguish one entity or operation from another, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. In addition, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0092] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for hot-rebooting a PCI device, characterized in that, This method is applied to ARM motherboards, which feature an ARM processor and PCI slots with varying bandwidths. The ARM processor includes four GPIO signal interfaces, and the x16 bandwidth PCI slots include 16 Reset signal interfaces. These 16 Reset signal interfaces are divided into four groups, each directly connected to one of the four GPIO interfaces. The PCI device hot-reboot method includes: Obtain the GPIO status values ​​of the PCI slots for each bandwidth used to perform a hot reboot operation; For each of the bandwidths mentioned, the following operations are performed: The output status value of each GPIO signal interface is determined according to the GPIO status value corresponding to the bandwidth, and each GPIO signal interface is controlled to output GPIO signal according to its corresponding output status value, and a preset time is delayed so that the PCI device connected to the PCI slot of each bandwidth can be hot-restarted. The PCI device hot-reboot method also includes: When a PCI slot with x16 bandwidth is split into multiple PCI slots with different bandwidths, after a preset delay, each of the GPIO signal interfaces is controlled to output a GPIO signal at a high state value so that the operation can be performed for the next bandwidth.

2. The PCI device hot restart method according to claim 1, characterized in that, The process of obtaining the GPIO status values ​​of the PCI slots for each bandwidth used to perform a hot reboot operation includes: The GPIO status value for performing a hot reboot operation for each PCI slot of the x16 bandwidth is determined based on the splitting status of the PCI slot and the ARM processor to which it belongs.

3. The PCI device hot restart method according to claim 2, characterized in that, The process of determining the GPIO status value for each bandwidth of the PCI slot used for performing a hot reboot operation based on the splitting status of the PCI slot with the x16 bandwidth and the ARM processor to which it belongs includes: Based on the split status of the PCI slot with the x16 bandwidth and the ARM processor to which it belongs, select a preset status value table; Obtain the GPIO status value for each bandwidth of the PCI slot used to perform a hot restart operation from the preset status value table.

4. The PCI device hot restart method according to claim 1, characterized in that, Before obtaining the GPIO status values ​​of the PCI slots for each bandwidth used to perform a hot restart operation, the PCI device hot restart method further includes: When the ARM motherboard is powered on, it controls each of the GPIO signal interfaces to output GPIO signals in a high state value.

5. The PCI device hot restart method according to any one of claims 1-4, characterized in that, The process of controlling each of the GPIO signal interfaces to output GPIO signals according to their respective corresponding output status values ​​includes: Simultaneously or sequentially, each of the GPIO signal interfaces is controlled to output GPIO signals according to its corresponding output state value.

6. A PCI device hot restart system, characterized in that, This system is applied to ARM motherboards, which feature an ARM processor and PCI slots with varying bandwidths. The ARM processor includes four GPIO signal interfaces, and the x14 bandwidth PCI slots include 14 Reset signal interfaces. These 14 Reset signal interfaces are divided into four groups, each directly connected to one of the four GPIO interfaces. The PCI device hot-reboot system includes: The acquisition module is used to acquire the GPIO status values ​​of the PCI slots for each bandwidth used to perform hot restart operations; A determination module is used to determine the output status value of each GPIO signal interface based on the GPIO status value for each bandwidth. The control module is used to control each of the GPIO signal interfaces to output GPIO signals according to their respective output status values ​​for each bandwidth, and delay for a preset time to enable the PCI device connected to the PCI slot of each bandwidth to hot restart. The PCI device warm restart system is also used for: When a PCI slot with x14 bandwidth is split into multiple PCI slots with different bandwidths, after a preset delay, each of the GPIO signal interfaces is controlled to output a GPIO signal at a high state value so that the operation can be performed for the next bandwidth.

7. A PCI device warm restart device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the PCI device hot restart method as described in any one of claims 1-5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the PCI device hot restart method as described in any one of claims 1-5.

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