Memory device, storage device, and method of operating a memory controller

Abstract

The present technology relates to an electronic device. More particularly, the present technology relates to a memory device, a storage device, and a method of operating a memory controller. According to an embodiment, a memory device outputs read data in response to a read enable signal provided from a memory controller, and the memory device includes: a plurality of memory cells configured to store data; a plurality of page buffers configured to sense data stored in the plurality of memory cells through a plurality of bit lines; and a data output controller configured to, when the read enable signal is input, select a target page buffer for outputting data from among the plurality of page buffers according to a page buffer address control signal provided from the memory controller, and control the selected target page buffer according to the read enable signal to output data stored in the selected target page buffer.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2020 - 0149734, filed on November 10, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a memory device, a storage device, and a method of operating a memory controller. Background Art

[0004] A storage device is a device that stores data under the control of a host device. The storage device may include a memory device that stores data and a memory controller that controls the memory device. The memory device may be classified into a volatile memory device and a non - volatile memory device.

[0005] A volatile memory device can store data only when receiving power from a power source. When the power supply is interrupted, the data stored in the volatile memory device may be lost. The volatile memory device may include a static random access memory (SRAM), a dynamic random access memory (DRAM), etc.

[0006] A non - volatile memory device is a device that does not lose data even when the power of the power source is interrupted. The non - volatile memory device may include a read - only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, etc. Summary of the Invention

[0007] Embodiments of the present disclosure provide a memory device, a storage device, and a method of operating a memory controller that improve the performance of a read operation.

[0008] According to an embodiment of the present disclosure, a memory device outputs read data in response to a read enable signal provided from a memory controller. The memory device may include: a plurality of memory cells configured to store data; a plurality of page buffers configured to sense data stored in the plurality of memory cells through a plurality of bit lines; and a data output controller configured to, when an input read enable signal is received, select a target page buffer for outputting data from among the plurality of page buffers according to a page buffer address control signal provided from the memory controller, and control the selected target page buffer according to the read enable signal to output data stored in the selected target page buffer.

[0009] According to another embodiment of the present disclosure, a storage device may include: a memory device including an input / output port, a read enable port, and a page buffer address port; and a memory controller configured to provide a read enable signal to the read enable port in response to a read request provided from a host, receive read data from the input / output port according to the read enable signal, temporarily store the read data received from the input / output port in a pre-allocated storage space, provide a page buffer address control signal to the page buffer address port according to whether there is available storage capacity in the storage space, the page buffer address control signal being for controlling the output of subsequent read data to be output immediately after the read data received from the input / output port, and provide the read data temporarily stored in the storage space to the host in response to the completion of the read operation of the memory device.

[0010] According to yet another embodiment of the present disclosure, a method of operating a memory controller, where the memory controller controls a memory device to perform a read operation, the method may include: providing a read enable signal to the memory device, the read enable signal indicating a timing for the memory device to output read data; receiving the read data sequentially output from the memory device according to the read enable signal; outputting a page buffer address control signal according to a result of monitoring whether there is available storage capacity in a data buffer; and temporarily storing the read data sequentially received from the memory device in the data buffer during a period when a voltage level of the page buffer address control signal is a first voltage level.

[0011] According to the present technology, there is provided a memory device, a storage device, and a method of operating a memory controller for improving the performance of a read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing a storage system according to an embodiment of the present disclosure.

[0013] Figure 2 is a diagram showing signals transmitted between a memory controller and a memory device according to an embodiment of the present disclosure.

[0014] Figure 3 and Figure 4 is a diagram showing a data buffer and an operation controller according to an embodiment of the present disclosure.

[0015] Figure 5 is a diagram showing a memory device according to an embodiment of the present disclosure.

[0016] Figure 6 is a waveform diagram showing a chip enable signal, a read enable signal, and data according to a comparative example.

[0017] Figure 7 is a waveform diagram showing a chip enable signal, a read enable signal, and data according to an embodiment of the present disclosure.

[0018] Figure 8 is a flowchart showing a method of operating a memory controller according to an embodiment of the present disclosure.

[0019] Figure 9 is a diagram showing a memory controller according to an embodiment of the present disclosure.

[0020] Figure 10 is a block diagram of a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0021] Figure 11 is a block diagram of a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0022] Figure 12 is a block diagram of a user system to which a storage device according to an embodiment of the present disclosure is applied. Detailed Description

[0023] Only specific structural or functional descriptions of embodiments according to the concepts disclosed in this specification or this application are shown to describe embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be implemented in various forms and are not limited to the embodiments in this specification or this application.

[0024] Figure 1 is a diagram showing a storage system according to an embodiment of the present disclosure.

[0025] Referring to Figure 1 , the storage system may be implemented as a personal computer (PC), a data center, an enterprise data storage system, a data processing system including direct attached storage (DAS), a data processing system including a storage area network (SAN), and a data processing system including network attached storage (NAS), etc.

[0026] The storage system may include a storage device 1000 and a host 500.

[0027] The storage device 1000 may be a device that stores data according to a request of a host 500 such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0028] Based on the host interface as a communication method with the host 500, the storage device 1000 can be manufactured as one of various types of storage devices. For example, the storage device 1000 can be configured as any one of various types of storage devices such as: SSD, multimedia cards in the form of MMC, eMMC, RS-MMC, and micro MMC, secure digital cards in the form of SD, mini SD, and micro SD, universal serial bus (USB) storage devices, universal flash storage (UFS) devices, Personal Computer Memory Card International Association (PCMCIA) card-type storage devices, Peripheral Component Interconnect (PCI) card-type storage devices, high-speed PCI (PCI-E) card-type storage devices, CompactFlash (CF) cards, SmartMedia cards, and Memory Sticks.

[0029] The storage device 1000 can be manufactured as any one of various types of packages. For example, the storage device 1000 can be manufactured as any one of various package types such as: Package on Package (POP), System in Package (SIP), System on Chip (SOC), Multi-Chip Package (MCP), Chip on Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0030] The storage device 1000 can include a memory device 100 and a memory controller 200.

[0031] The memory device 100 can operate in response to the control of the memory controller 200. Specifically, the memory device 100 can receive commands and addresses from the memory controller 200, and access the memory cells (not shown) selected by the address among the memory cells. The memory device 100 can perform the operation indicated by the command on the memory cells selected by the address.

[0032] For example, the command can be a programming command, a read command, or an erase command, and for example, the operation indicated by the command can be a programming operation (or write operation), a read operation, or an erase operation.

[0033] The programming operation can be an operation in which the memory device 100 stores the data provided from the host 500 in response to the control of the memory controller 200.

[0034] For example, the memory device 100 can receive a programming command, an address, and data, and program the data in the memory cells selected by the address. Here, the data to be programmed in the selected memory cells can be defined as write data. The write data can include the data provided from the host 500 (or user data) and the metadata of the data.

[0035] A read operation may be an operation in which the memory device 100 reads read data stored in the memory device 100 in response to the control of the memory controller 200.

[0036] For example, the memory device 100 may receive a read command and an address, and read data from a region selected by the address in a memory cell array (not shown). The data to be read from the selected region among the data stored in the memory device 100 may be defined as read data. The memory device 100 may provide the read data to the memory controller 200.

[0037] An erase operation may be an operation in which the memory device 100 erases data stored in the memory device in response to the control of the memory controller 200.

[0038] For example, the memory device 100 may receive an erase command and an address, and erase the data stored in the region selected by the address.

[0039] The memory device 100 may be implemented using a volatile memory device or a non-volatile memory device.

[0040] For example, volatile memory devices may include: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4th Generation (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM). Non-volatile memory devices may include: Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory, Spin Transfer Torque Random Access Memory, etc.

[0041] For example, non-volatile memory devices may include flash memory. For example, flash memory may include NAND flash memory, Vertical NAND flash memory (Vertical NAND), NOR flash memory, etc.

[0042] In this specification, for ease of description, the memory device 100 is a NAND flash memory.

[0043] The memory device 100 may store write data under the control of the memory controller 200, or read the stored data under the control of the memory controller 200 and provide the read data to the memory controller 200.

[0044] The memory device 100 may include a plurality of dies (not shown). One die may include at least one plane. One plane may include a memory cell array 101, and the memory cell array 101 includes memory cells that store data.

[0045] The memory cell array 101 may include a plurality of memory blocks (not shown). A memory block may be a unit that performs an erase operation for erasing data.

[0046] A memory block may include a plurality of pages (not shown). A page may be a unit that performs a programming operation for storing written data or a read operation for reading stored data.

[0047] A memory cell may be configured as any one of the following: a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, and a four-level cell (QLC) that stores four data bits. However, the present disclosure is not limited thereto, and a memory cell may store five or more data bits.

[0048] The memory device 100 may include a page buffer bank 102.

[0049] The page buffer bank 102 may be a bank including a plurality of page buffers. The page buffer bank 102 may be electrically connected to the memory cell array 101. Each page buffer included in the page buffer bank 102 may sense data stored in the memory cell array 101. Each page buffer included in the page buffer bank 102 may temporarily store the sensed data.

[0050] The memory device 100 may include a data output controller 103.

[0051] The data output controller 103 may select a target page buffer for outputting data from the page buffer bank 102 under the control of the memory controller 200. The target page buffer may be a page buffer selected from among the plurality of page buffers. The data output controller 103 may control the target page buffer to provide data from the target page buffer to the memory controller 200.

[0052] The memory controller 200 may control all operations of the storage device 1000.

[0053] When power is supplied to the storage device 1000, the memory controller 200 may run firmware. When the memory device 100 is a flash memory device, the firmware may include a host interface layer, a flash translation layer, and a flash interface layer. Here, the power may be, for example, power supplied from the outside.

[0054] The host interface layer can control the operations between the host 500 and the memory controller 200.

[0055] The flash translation layer can convert the logical address provided from the host 500 into a physical address.

[0056] The flash interface layer can control the communication between the memory controller 200 and the memory device 100.

[0057] The memory controller 200 can control the memory device 100 to perform a programming operation, a read operation, and an erase operation respectively in response to a write request, a read request, and an erase request of the host 500.

[0058] During the programming operation, the memory controller 200 can provide a programming command, a physical address, and write data to the memory device 100.

[0059] During the read operation, the memory controller 200 can provide a read command and a physical address to the memory device 100. The memory controller 200 can receive read data from the memory controller 100.

[0060] Specifically, after the memory controller 200 provides a read command and a physical address to the memory device 100, the memory controller 200 can receive read data from the memory device 100. The memory controller 200 can temporarily store the received read data in a pre-allocated storage space (not shown). In this case, an error may occur in the read data. The memory controller 200 can perform error correction decoding on the read data. The error bits of the read data can be corrected through error correction decoding. At this time, according to the error correction decoding, the time delay for providing a response to the read request of the host 500 can be caused.

[0061] For this purpose, the memory controller 200 can control the memory device 100 to output subsequent read data according to whether there is available storage capacity in the storage space. When the read operation of the memory device 100 is completed, the memory controller 200 can provide the read data temporarily stored in the storage space to the host 500 in response to the completion of the read operation.

[0062] In an embodiment, the memory controller 200 can include a data buffer 210 and an operation controller 220.

[0063] The data buffer 210 can temporarily store data. For example, the data buffer 210 can store data only when receiving power from an external power source. The data buffer 210 can have a storage space with a certain storage capacity.

[0064] For example, data buffer 210 may be a buffer memory. For example, buffer memory 210 may be implemented as any one of the following: double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4th generation (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory, and spin transfer torque random access memory.

[0065] In an embodiment, when the storage capacity is full of data, data buffer 210 may provide a flag signal (not shown) indicating insufficient storage space to operation controller 220.

[0066] Although Figure 1 the illustrated data buffer 210 may be included in memory controller 200, it is not limited thereto, and Figure 1 the illustrated data buffer 210 may exist separately outside memory controller 200.

[0067] Operation controller 220 may store the read data received from memory device 100 in data buffer 210.

[0068] In an embodiment, operation controller 220 may monitor the storage capacity of data buffer 210 regardless of whether a flag signal indicating insufficient storage space is provided from data buffer 210 to operation controller 220. Specifically, operation controller 220 may monitor whether there is available storage capacity in the storage capacity of data buffer 210. Operation controller 220 may still store the read data received from memory device 100 in data buffer 210 having available storage capacity. When there is no available storage capacity in the storage capacity of data buffer 210, that is, when the storage capacity of data buffer 210 becomes full of read data, operation controller 220 may not store any more read data received from memory device 100 in data buffer 210 until data buffer 210 ensures available storage capacity again.

[0069] In an embodiment, when data buffer 210 provides a flag signal indicating insufficient storage space to operation controller 220, operation controller 220 may monitor whether there is available storage capacity in the storage capacity of data buffer 210 according to whether the flag signal is received.

[0070] Operation controller 220 may control whether memory device 100 outputs the same read data that has been output or outputs subsequent read data according to the monitoring result.

[0071] For example, when there is available storage capacity in the data buffer 210, the operation controller 220 may control the memory device 100 to output subsequent read data. When the storage capacity of the data buffer 210 is insufficient, the operation controller 220 may control the memory device 100 to output the same read data that has been output.

[0072] The operation controller 220 may control the data buffer 210 to provide the read data temporarily stored in the storage space to the host 500 in response to the completion of the read operation of the memory device 100.

[0073] During an erase operation, the memory controller 200 may provide an erase command and a physical address to the memory device 100.

[0074] The memory controller 200 may autonomously generate commands, addresses, and data regardless of requests provided from the host 500. The memory controller 200 may transmit the autonomously generated commands, addresses, and data to the memory device 100.

[0075] For example, the memory controller 200 may generate commands, addresses, and data for performing background operations. Additionally, the memory controller 200 may provide the commands, addresses, and data to the memory device 100.

[0076] The background operation may be at least one of wear leveling, read recovery, or garbage collection.

[0077] For example, wear leveling may refer to static wear leveling, dynamic wear leveling, etc. Static wear leveling may refer to an operation of storing the number of times a storage block is erased and moving cold data that hardly undergoes an erase operation or a write operation to a storage block having the maximum number of erase times. Dynamic wear leveling may refer to an operation of storing the number of times a storage block is erased and programming data in a storage block having the minimum number of erase times.

[0078] Read recovery may refer to an operation of moving data stored in a storage block to another storage block before an uncorrectable error occurs in the data stored in the storage block.

[0079] Garbage collection may refer to an operation of copying valid data included in a bad block among storage blocks to a free block and erasing invalid data included in the bad block. Here, copying valid data included in a bad block to a free block may refer to moving valid data included in the bad block to a free block.

[0080] The memory controller 200 may control two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operation performance.

[0081] The interleaving method may be a method of controlling the overlapping operation of two or more memory devices 100.

[0082] The host 500 may communicate with the storage device 1000 through an interface (not shown).

[0083] The interface may be implemented using a Serial Advanced Technology Attachment (SATA) interface, a High-Speed SATA interface, a Serial Small Computer System Interface (SAS) interface, a High-Speed Peripheral Component Interconnect (PCIe) interface, a High-Speed Non-Volatile Memory (NVMe) interface, an Advanced Host Controller Interface (AHCI), or a Multimedia Card interface. However, the interface is not limited thereto.

[0084] The host 500 may store data in the storage device 1000 or communicate with the storage device 1000 to obtain the data stored in the storage device 1000.

[0085] In an embodiment, the host 500 may provide a write request to the storage device 1000, the write request being for requesting to store data in the storage device 1000. Additionally, the host 500 may provide the write request, the data, and a logical address for identifying the data to the storage device 1000.

[0086] In response to the write request provided by the host 500, the storage device 1000 may store the write data including metadata and data provided from the host 500 in the memory device 100, and provide a response indicating the completion of storage to the host 500.

[0087] In an embodiment, the host 500 may provide a read request to the storage device 1000, the read request being for requesting to provide the data stored in the storage device 1000 to the host 500. Additionally, the host 500 may provide the read request and a read address to the storage device 1000.

[0088] In response to the read request provided from the host 500, the storage device 1000 may read the read data corresponding to the read address provided by the host 500 from the memory device 100, and may provide the read data to the host 500 as a response to the read request.

[0089] Figure 2 is a diagram showing signals transmitted between a memory controller and a memory device according to an embodiment of the present disclosure.

[0090] Refer to Figure 2, the memory device 100 may include: input / output ports DQ[7:0], chip enable port CE#, read enable port RE#, address latch enable port ALE, command latch enable port CLE, write enable port WE#, write protection port WP#, page buffer address port PBAC, and ready / busy port R / B.

[0091] The input / output ports DQ[7:0] may be ports for transmitting commands, addresses, and data. The input / output ports DQ[7:0] may be eight-bit bidirectional ports, but are not limited thereto.

[0092] In an embodiment, the memory controller 200 may provide commands, addresses, and write data to the memory device 100 through the input / output ports DQ[7:0].

[0093] In an embodiment, the memory device 100 may provide read data to the memory controller 200 through the input / output ports DQ[7:0].

[0094] The chip enable port CE# may be a port for transmitting a chip enable signal CE_SIG. The chip enable signal CE_SIG may be a signal for selecting a target memory device. Specifically, the chip enable signal CE_SIG may be a signal for enabling or disabling the memory device 100. For example, when the voltage level of the chip enable signal CE_SIG is a first voltage level, the memory device 100 may be enabled, and when the voltage level of the chip enable signal CE_SIG is a second voltage level different from the first voltage level, the memory device 100 may be disabled. Here, the disabling of the memory device 100 may refer to the memory device 100 being in a ready state and the memory device 100 entering a low-power waiting state. The enabling of the memory device 100 may refer to the memory device 100 being in an operable state.

[0095] In an embodiment, the memory controller 200 may provide the chip enable signal CE_SIG to the memory device 100 through the chip enable port CE#.

[0096] In an embodiment, when the voltage level of the chip enable signal CE_SIG is a first voltage level (e.g., logic low), the memory device 100 may be enabled. When the voltage level of the chip enable signal CE_SIG is a second voltage level (e.g., logic high), the memory device 100 may be disabled.

[0097] The read enable port RE# can be a port for transmitting a read enable signal RE_SIG. The read enable signal RE_SIG can be a signal for outputting serial data. The read enable signal RE_SIG can be a clock signal that toggles with a constant pulse width and period. When the data transfer method is a double data rate (DDR) method, a DDR2 method, or a DDR3 method, serial data can be provided to the memory controller 200 in synchronization with the falling edge or the rising edge of the read enable signal RE_SIG.

[0098] In an embodiment, in response to a read request provided from the host 500, the memory controller 200 can provide a read enable signal RE_SIG to the memory device 100 through the read enable port RE#.

[0099] In an embodiment, in response to the falling edge or the rising edge of the read enable signal RE_SIG, the memory device 100 can sequentially transfer read data to the memory controller 200 through the input / output port DQ[7:0]. The memory controller 200 can receive the read data from the input / output port DQ[7:0] according to the read enable signal RE_SIG.

[0100] The address latch enable port ALE can be a port for transmitting an address latch enable signal ALE_SIG. The address latch enable signal ALE_SIG can be a signal indicating that the signal transmitted through the input / output port DQ[7:0] is an address.

[0101] The command latch enable port CLE can be a port for transmitting a command latch enable signal CLE_SIG. The command latch enable signal CLE_SIG can be a signal indicating that the signal transmitted through the input / output port DQ[7:0] is a command.

[0102] In an embodiment, the memory controller 200 can provide a command latch enable signal CLE_SIG to the memory device 100 through the command latch enable port CLE.

[0103] The write enable port WE# can be a port for transmitting a write enable signal WE_SIG. The write enable signal WE_SIG can be a signal for controlling the latching of commands, addresses, and data transmitted through the input / output port DQ[7:0].

[0104] In an embodiment, when the voltage level of each of the address latch enable signal ALE_SIG and the write enable signal WE_SIG is a first voltage level and the voltage level of each of the command latch enable signal CLE_SIG and the read enable signal RE_SIG is a second voltage level different from the first voltage level, a command can be provided to the memory controller 200 through the input / output port DQ[7:0].

[0105] In an embodiment, when the voltage level of each of the command latch enable signal CLE_SIG and the write enable signal WE_SIG is a first voltage level and the voltage level of each of the address latch enable signal ALE_SIG and the read enable signal RE_SIG is a second voltage level different from the first voltage level, an address can be provided to the memory controller 200 through the input / output port DQ[7:0].

[0106] In an embodiment, when the voltage level of each of the address latch enable signal ALE_SIG, the command latch enable signal CLE_SIG, and the write enable signal WE_SIG is a first voltage level and the voltage level of the read enable signal RE_SIG is a second voltage level different from the first voltage level, read data can be provided to the memory controller 200 through the input / output port DQ[7:0].

[0107] In an embodiment, when the voltage level of each of the address latch enable signal ALE_SIG, the command latch enable signal CLE_SIG, and the read enable signal RE_SIG is a first voltage level and the voltage level of the write enable signal WE_SIG is a second voltage level different from the first voltage level, write data can be provided to the memory device 100 through the input / output port DQ[7:0].

[0108] The write protection port WP# can be a port for transmitting the write protection signal WP_SIG. The write protection signal WP_SIG can be a signal for deactivating programming operations and erase operations.

[0109] The page buffer address port PBAC may be a port for transmitting a page buffer address control signal PBAC_SIG. The page buffer address control signal PBAC_SIG may be a signal for controlling the output of subsequent read data to be output, which is immediately received from the input / output port DQ[7:0], according to whether there is available storage capacity in the storage space allocated to the memory controller 200. The page buffer address control signal PBAC_SIG may be a signal having a first voltage level or a second voltage level according to whether there is available storage capacity in the storage space allocated to the memory controller 200. For example, the page buffer address control signal PBAC_SIG may be a signal having a logic low level or a logic high level according to whether there is available storage capacity in the data buffer 210 included in the memory controller 200. Here, when the first voltage level is a logic low level, the second voltage level may be a logic high level. However, the present disclosure is not limited thereto.

[0110] In an embodiment, when the page buffer address control signal PBAC_SIG having the first voltage level is provided to the memory device 100 through the page buffer address port PBAC, the read data may be sequentially provided to the memory controller 200 through the input / output port DQ[7:0].

[0111] Specifically, when there is available storage capacity, the memory controller 200 may output the page buffer address control signal PBAC_SIG having the first voltage level. When the page buffer address control signal PBAC_SIG having the first voltage level is provided to the memory device 100, the memory controller 200 may receive subsequent read data.

[0112] In an embodiment, when the page buffer address control signal PBAC_SIG having the second voltage level is provided to the memory device 100 through the page buffer address port PBAC, the same read data that has been provided may be provided to the memory controller 200 again through the input / output port DQ[7:0].

[0113] Specifically, when the storage capacity of the storage space is full, the memory controller 200 may output the page buffer address control signal PBAC_SIG having the second voltage level, which is different from the first voltage level. When the page buffer address control signal PBAC_SIG having the second voltage level is provided to the memory device 100, the previous read data may be received from the memory device 100. The previous read data may be the read data output from the memory device 100 immediately before the storage capacity of the storage space was full.

[0114] The ready / busy port R / B can be a port for the transmit ready / busy signal R / B_SIG. The ready / busy signal R / B_SIG can indicate the ready state or the busy state of the memory device 100. The ready state can be a state in which the memory device 100 can receive a command without performing an operation. The busy state can be a state in which the memory device 100 performs at least one operation.

[0115] According to the above embodiments, when providing the page buffer address control signal PBAC_SIG having a first voltage level, the memory controller 200 can receive subsequent read data, and when providing the page buffer address control signal PBAC_SIG having a second voltage level, the memory controller 200 can receive previous read data. However, the present disclosure is not limited thereto. According to the design method, when providing the page buffer address control signal PBAC_SIG having a second voltage level, the memory controller 200 can receive subsequent read data, and when providing the page buffer address control signal PBAC_SIG having a first voltage level, the memory controller 200 can receive previous read data.

[0116] In this specification, "port", "pad", "node", etc. can have the same meaning.

[0117] In addition to the above ports DQ [7:0], CE#, RE#, ALE, CLE, WE#, WP#, PBAC, and RB, the memory device 100 can further include other ports.

[0118] Figure 3 and Figure 4 is a diagram showing a data buffer and an operation controller according to an embodiment of the present disclosure.

[0119] In the description Figure 3 and Figure 4 In the illustrated embodiment, the first to third data DATA1, DATA2, and DATA3 are read data provided in response to a read request of the current host 500, the first voltage level of the page buffer address control signal PBAC_SIG is a logic low level, and the second voltage level of the page buffer address control signal PBAC_SIG is a logic high level.

[0120] Referring to Figure 3 , the data buffer 210 can include a storage space 211. The data DATA can be stored in the storage space 211 of the data buffer 210. When the data DATA is stored in the storage space 211 provided in the data buffer 210, there may be an available storage space 212 having an available storage capacity other than the size of the data DATA in the storage space 211 of the data buffer 210.

[0121] The operation controller 220 can monitor whether there is available storage capacity in the storage capacity of the data buffer 210. Additionally, the operation controller 220 can change the voltage level of the page buffer address control signal PBAC_SIG to a logic high level different from the logic low level according to the monitoring result.

[0122] Because there is available storage space 212, the operation controller 220 can provide the page buffer address control signal PBAC_SIG with a logic low level to the page buffer address port PBAC.

[0123] The first data DATA1 can be provided to the operation controller 220 through the input / output port DQ[7:0]. The operation controller 220 can temporarily store the first data DATA1 in the data buffer 210. Since the first data DATA1 is stored in the available storage space 212 of the data buffer 210, the storage capacity of the storage space 211 may be full. In this case, even if the second data DATA2 to be output after the first data DATA1 is provided to the operation controller 220 through the input / output port DQ[7:0], because the second data DATA2 cannot be stored in the data buffer 210, it may cause a time delay (latency) for providing a response to the read request.

[0124] When the storage capacity of the storage space 211 is full, the operation controller 220 can output the page buffer address control signal PBAC_SIG with a logic high level. That is to say, the voltage level of the page buffer address control signal PBAC_SIG can be changed from the logic low level to the logic high level.

[0125] When the page buffer address control signal PBAC_SIG with a logic high level is provided to the page buffer address port PBAC, the operation controller 220 can receive the previously read data from the input / output port DQ[7:0]. Here, the previously read data can be the read data output from the input / output port DQ[7:0] before the voltage level of the page buffer address control signal PBAC_SIG is changed from the logic low level to the logic high level. Refer to Figure 3 , for example, the previously read data can be the first data DATA1. When the page buffer address control signal PBAC_SIG with a logic high level is provided to the page buffer address port PBAC, the second data DATA2 may not be output.

[0126] Since the previously read data may have been stored in the storage space allocated to the memory controller 200, for example, in the storage space 211 of the data buffer 210, the operation controller 220 may discard the previously read data received after providing the page buffer address control signal to the memory device 100.

[0127] Referring to Figure 3 and Figure 4 , when the storage capacity of the storage space 211 is full, the operation controller 220 may perform a data buffer clear operation on the data buffer 210 to generate an available storage capacity. Specifically, the operation controller 220 may provide a command for instructing to clear the data DATA stored in the data buffer 210 to the data buffer 210. The cleared data DATA may be deleted or provided to the host 500. However, the present disclosure is not limited thereto.

[0128] Referring to Figure 4 , after performing the data buffer clear operation, the operation controller 220 may provide a page buffer address control signal PBAC_SIG having a logic low level to the page buffer address port PBAC. That is, the voltage level of the page buffer address control signal PBAC_SIG may change from a logic high level to a logic low level.

[0129] When the page buffer address control signal PBAC_SIG having a logic low level is provided to the page buffer address port PBAC, the operation controller 220 may receive subsequent read data from the input / output port DQ [7:0]. Here, referring to Figure 4 , the subsequent read data may be, for example, a second data DATA2 or a third data DATA3.

[0130] The operation controller 220 may temporarily store the subsequent read data in the data buffer 210.

[0131] Figure 5 is a diagram showing a memory device according to an embodiment of the present disclosure.

[0132] Referring to Figure 5 , the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control logic 130.

[0133] The memory cell array 110 may perform the same functions as the memory cell array 101 described with reference to Figure 1 .

[0134] The memory cell array 110 may include a plurality of memory blocks MB1 to MBk (k is a positive integer). Here, the number of the plurality of memory blocks MB1 to MBk is only an example for describing embodiments of the present disclosure, but is not limited thereto.

[0135] Each of the memory blocks MB1 to MBk may be connected to a local line LL and bit lines BL1 to BLn (n is a positive integer).

[0136] The local line LL may be connected to the row decoder 122.

[0137] The local line LL may be connected to each of the memory blocks MB1 to MBk.

[0138] Although not shown, the local line LL may include a first selection line, a second selection line, and a plurality of word lines disposed between the first selection line and the second selection line.

[0139] Although not shown, the local line LL may further include dummy lines disposed between the first selection line and the word lines, dummy lines disposed between the second selection line and the word lines, and pipeline lines.

[0140] The bit lines BL1 to BLn may be commonly connected to the memory blocks MB1 to MBk.

[0141] The memory blocks MB1 to MBk may be implemented as a two-dimensional structure or a three-dimensional structure.

[0142] For example, in the two-dimensional structured memory blocks MB1 to MBk, memory cells may be arranged in a direction parallel to the substrate.

[0143] For example, in the three-dimensional structured memory blocks MB1 to MBk, memory cells may be stacked on the substrate in a vertical direction.

[0144] The peripheral circuit 120 may include a voltage generator 121, a row decoder 122, a page buffer bank 123, a column decoder 124, an input / output circuit 125, and a sense circuit 126.

[0145] The voltage generator 121 may generate various operation voltages Vop for programming operations, read operations, and erase operations in response to an operation command OP_CMD. Additionally, the voltage generator 121 may selectively discharge the local line LL in response to the operation command OP_CMD. For example, the voltage generator 121 may generate a programming voltage, a verification voltage, a pass voltage, a turn-on voltage, a read voltage, an erase voltage, a source line voltage, etc. under the control of the control logic 130.

[0146] In an embodiment, the voltage generator 121 may generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 121 is used as an operating voltage of the memory device 100.

[0147] In an embodiment, the voltage generator 121 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 121 may include a plurality of pumping capacitors that receive the internal power supply voltage, and generate a plurality of voltages by selectively enabling the plurality of pumping capacitors in response to the control of the control logic 130. The generated voltages may be supplied to the memory cell array 110 through the row decoder 122.

[0148] The row decoder 122 may transfer the operation voltage Vop to the local line LL in response to the row address RADD. The operation voltage Vop may be transferred to the selected memory blocks MB1 to MBk through the local line LL.

[0149] For example, during a programming operation, the row decoder 122 may apply a programming voltage to the selected word line, and apply a programming pass voltage to the unselected word lines, where the level of the programming pass voltage is lower than the level of the programming voltage. During a programming verification operation, the row decoder 122 may apply a verification voltage to the selected word line, and apply a verification pass voltage to the unselected word lines, where the verification pass voltage is higher than the verification voltage.

[0150] During a read operation, the row decoder 122 may apply a read voltage to the selected word line, and apply a read pass voltage to the unselected word lines, where the read pass voltage is higher than the read voltage.

[0151] During an erase operation, the row decoder 122 may select one memory block according to the decoded address. During an erase operation, the row decoder 122 may apply a ground voltage to the word lines connected to the selected memory block.

[0152] The page buffer group 123 may perform the same functions as the page buffer group 102 described with reference to Figure 1 description.

[0153] The page buffer group 123 may include first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn may be respectively connected to the memory cell array 110 through first to nth bit lines BL1 to BLn. The first to nth page buffers PB1 to PBn may operate in response to the control of the control logic 130.

[0154] Specifically, the first to nth page buffers PB1 to PBn can operate in response to page buffer control signals PBSIGNALS. For example, during a read operation or a verify operation, the first to nth page buffers PB1 to PBn can temporarily store data received through the first to nth bit lines BL1 to BLn, or can sense the voltage or current of the bit lines BL1 to BLn.

[0155] During a programming operation, when a programming voltage is applied to the selected word line, the first to nth page buffers PB1 to PBn can transfer the data DATA received through the column decoder 124 and the input / output circuit 125 to the selected memory cells through the first to nth bit lines BL1 to BLn. According to the transferred data DATA, the memory cells of the selected page are programmed. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming inhibit voltage (e.g., power supply voltage) is applied can be maintained.

[0156] During a verify operation, the first to nth page buffers PB1 to PBn can sense the data stored in the selected memory cells from the selected memory cells through the first to nth bit lines BL1 to BLn.

[0157] During a read operation, the first to nth page buffers PB1 to PBn can, under the control of the column decoder 124, sense the data DATA from the memory cells of the selected page through the first to nth bit lines BL1 to BLn, and output the sensed data DATA to the input / output circuit 125.

[0158] During an erase operation, the first to nth page buffers PB1 to PBn can float the first to nth bit lines BL1 to BLn.

[0159] The column decoder 124 can transfer data between the input / output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 can exchange data with the first to nth page buffers PB1 to PBn through data lines DL, or can exchange data with the input / output circuit 125 through column lines CL.

[0160] The input / output circuit 125 can transfer a command CMD and an address ADD received from the memory controller 200 to the control logic 130, or can exchange data DATA with the column decoder 124.

[0161] During a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to an enable bit signal VRY_BIT <#>, and compare a sensed voltage VPB received from the page buffer bank 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0162] The control logic 130 may output an operation command OP_CMD, a row address RADD, page buffer control signals PBSIGNALS, and an enable bit signal VRY_BIT <#> in response to a command CMD and an address ADD to control the peripheral circuit 120.

[0163] In an embodiment, the control logic 130 may include a data output controller 131.

[0164] The data output controller 131 may perform the same functions as the data output controller 103 described with reference to Figure 1 description.

[0165] When an input read enable signal RE_SIG is received, the data output controller 131 may select a target page buffer for output data from the first to the nth page buffers PB1 to PBn according to a page buffer address control signal PBAC_SIG.

[0166] In an embodiment, during a period when the voltage level of the page buffer address control signal PBAC_SIG is a first voltage level, the data output controller 131 may sequentially select the target page buffer according to the address of the page buffer. For example, during a period when the voltage level of the page buffer address control signal PBAC_SIG is a logic low level, the data output controller 131 may sequentially select the target page buffer from the first page buffer PB1 to the nth page buffer PBn. As another example, during a period when the voltage level of the page buffer address control signal PBAC_SIG is a logic low level, the data output controller 131 may sequentially select the target page buffer from the nth page buffer PBn to the first page buffer PB1.

[0167] In an embodiment, during a period when the voltage level of the page buffer address control signal PBAC_SIG is a second voltage level different from the first voltage level, the data output controller 131 may maintain the target page buffer. For example, during a period when the voltage level of the page buffer address control signal PBAC_SIG is a logic high level, the data output controller 131 may select one of the first to nth page buffers PB1 to PBn as the target page buffer and maintain the target page buffer. For example, the target page buffer selected during a period when the voltage level of the page buffer address control signal PBAC_SIG is a logic high level may be the page buffer selected before the voltage level of the page buffer address control signal PBAC_SIG changes from a logic low level to a logic high level.

[0168] The data output controller 131 may control the selected target page buffer according to the read enable signal RE_SIG to output the data stored in the selected target page buffer.

[0169] In an embodiment, when the data transfer method is a DDR method, a DDR2 method, or a DDR3 method, the data output controller 131 may output the data stored in the selected target page buffer to the input / output circuit 125 in synchronization with the falling edge or the rising edge of the read enable signal RE_SIG.

[0170] Figure 6 is a waveform diagram showing a chip enable signal, a read enable signal, and data according to a comparative example, and Figure 7 is a waveform diagram showing a chip enable signal, a read enable signal, and data according to an embodiment of the present disclosure.

[0171] According to Figure 6 The waveform diagram of the comparative example shown in is a diagram showing a notification signal BF_SIG, a chip enable signal CE_SIG, a read enable signal RE_SIG, and data output from the memory device when the storage capacity of the storage space allocated to the memory controller according to the comparative example is full in a case where the memory device does not include a page buffer address port PBAC.

[0172] According to Figure 7 The waveform diagram of the present embodiment shown in is a diagram showing a notification signal BF_SIG, a chip enable signal CE_SIG, a read enable signal RE_SIG, a page buffer address control signal PBAC_SIG, and data output from the memory device 100 when the storage capacity of the storage space allocated to the memory controller is full in a case where the memory device 100 includes a page buffer address port PBAC.

[0173] In the descriptionFigure 6 the comparative examples shown and Figure 7 the embodiments of the present disclosure shown, a logic low level Low is a first voltage level, a logic high level High is a second voltage level, and the data transmission method is a DDR method, a DDR2 method, or a DDR3 method.

[0174] Referring to Figure 6 , before a first time point t1, the voltage level of the chip enable signal CE_SIG may be a logic low level Low. Additionally, when there is available storage capacity in the storage space allocated to the memory controller according to the comparative example, the voltage level of the notification signal BF_SIG may be a logic low level Low. Here, the notification signal BF_SIG may be generated internally in the memory controller according to the comparative example. The read enable signal RE_SIG may be switched to a clock signal having a logic high level High or a logic low level Low.

[0175] Before the first time point t1, data DATA may be output synchronously with the falling edge or the rising edge of the read enable signal RE_SIG. For example, a first read data D1 may be output synchronously with the falling edge of the read enable signal RE_SIG. A second read data D2 may be output synchronously with the rising edge of the read enable signal RE_SIG. By this method, third to seventh read data D3, D4, D5, D6, and D7 may be sequentially output synchronously with the falling edge or the rising edge of the read enable signal RE_SIG.

[0176] At the first time point t1, when the storage capacity of the storage space allocated to the memory controller according to the comparative example is full, the voltage level of the notification signal BF_SIG may be a logic high level High. In this case, the read operation of the memory device according to the comparative example may be stopped. This may be the same as the state where the read operation ends. At this time, a postamble time TRPST and an additionally generated postamble hold time TRPSTH, which are delay times that basically accompany after the read operation ends, may occur. The sum of the postamble time TRPST and the postamble hold time TRPSTH may be a period corresponding to the time period from the first time point t1 to the fourth time point t4. After the first time point t1, according to the postamble time TRPST and the postamble hold time TRPSTH, the voltage level of the chip enable signal CE_SIG may change from a logic low level Low to a logic high level High.

[0177] From the first time point t1, it may not switch the read enable signal RE_SIG. That is, the voltage level of the read enable signal RE_SIG may be the logic low level Low. Since the read enable signal RE_SIG is not switched, data DATA may not be output from the first time point t1.

[0178] At the second time point t2, when there is available storage capacity in the storage space allocated to the memory controller according to the comparative example, the voltage level of the notification signal BF_SIG may be the logic low level Low.

[0179] At the third time point t3, the voltage level of the chip enable signal CE_SIG may change from the logic low level Low to the logic high level High.

[0180] At the fifth time point t5, the read operation may be resumed. A read preamble time TRPREST, which is a delay time that generally accompanies the start of the read operation, may occur. The read preamble time TRPREST may be the time period from the fifth time point t5 to the seventh time point t7. After the fifth time point t5, according to the read preamble time TRPREST, the voltage level of the chip enable signal CE_SIG may change from the logic high level High to the logic low level Low.

[0181] At the sixth time point t6, the voltage level of the chip enable signal CE_SIG may change from the logic high level High to the logic low level Low.

[0182] From the seventh time point t7, the read enable signal RE_SIG may be switched again. In this case, data DATA consecutive to the data (e.g., read data D7) whose output has been stopped may be output synchronously with the falling edge or rising edge of the read enable signal RE_SIG. For example, the eighth read data D8 may be output synchronously with the rising edge of the read enable signal RE_SIG. The ninth read data D9 may be output synchronously with the falling edge of the read enable signal RE_SIG. In this way, the tenth to thirteenth read data D10, D11, D12, and D13 may be output synchronously with the falling edge or rising edge of the read enable signal RE_SIG.

[0183] As referred to above Figure 6 As described above, when the memory device does not include the page buffer address port PBAC, the read operation is stopped due to the read postamble time TRPST, the read postamble hold time TRPSTH, and the read preamble time TRPREST, so a delay may occur. Therefore, due to the delay, the read operation performance of the storage device according to the comparative example may be reduced.

[0184] On the other hand, according to an embodiment of the present disclosure, since the data DATA is sequentially output or the output data DATA is not changed and is maintained by the page buffer address control signal PBAC_SIG, the read operation can be not stopped. Therefore, the delay caused by the stop of the read operation can be significantly reduced or may not occur.

[0185] Referring to Figure 7 , before the first time point t1, the voltage level of the chip enable signal CE_SIG can be a logic low level Low. When there is available storage capacity in the storage space allocated to the memory controller 200 according to an embodiment of the present disclosure, the voltage level of the notification signal BF_SIG can be a logic low level Low. For example, the storage space allocated to the memory controller 200 can be the storage space of the data buffer 210. At the same time, the read enable signal RE_SIG may be switched.

[0186] Before the first time point t1, the voltage level of the page buffer address control signal PBAC_SIG can be a logic low level Low. In this case, the first to seventh read data D1, D2, D3, D4, D5, D6, and D7 can be sequentially output in synchronization with the falling edge or rising edge of the read enable signal RE_SIG.

[0187] Referring to Figure 1 , Figure 2 and Figure 7 , for example, when there is available storage capacity, the memory controller 200 can output the page buffer address control signal PBAC_SIG having a logic low level Low to the memory device 100. The memory device 100 can sequentially provide the first to seventh read data D1, D2, D3, D4, D5, D6, and D7 to the memory controller 200 through the input / output port DQ [7:0] in response to the falling edge or rising edge of the read enable signal RE_SIG provided by the memory controller 200. The memory controller 200 can sequentially receive the first to seventh read data D1, D2, D3, D4, D5, D6, and D7 from the input / output port DQ [7:0]. In addition, the memory controller 200 can temporarily store the sequentially received first to seventh read data D1, D2, D3, D4, D5, D6, and D7.

[0188] Referring to Figure 3 , Figure 4 , Figure 5 and Figure 7, specifically, for example, during a period before the first time point t1, the data output controller 131 may select the first to nth page buffers PB1 to PBn as target page buffers in ascending order of the addresses of the page buffers. At this time, when the first page buffer PB1 to the seventh page buffer (not shown) output the first to seventh read data D1, D2, D3, D4, D5, D6, and D7 respectively, the data output controller 131 may sequentially select the first page buffer PB1 to the seventh page buffer (not shown) as the target page buffer. The data output controller 131 may control the selected target page buffer to output the first to seventh read data D1, D2, D3, D4, D5, D6, and D7 according to the falling edge or rising edge of the read enable signal RE_SIG. The operation controller 220 may sequentially receive the first to seventh read data D1, D2, D3, D4, D5, D6, and D7, and store the first to seventh read data D1, D2, D3, D4, D5, D6, and D7 in the data buffer 210.

[0189] At the first time point t1, when the storage capacity of the storage space allocated to the memory controller 200 according to an embodiment of the present disclosure is full, the voltage level of the notification signal BF_SIG may be logic high level High. In this case, the voltage level of the page buffer address control signal PBAC_SIG may change from logic low level Low to logic high level High. In this case, the seventh read data D7, which is the read data output before the voltage level of the page buffer address control signal PBAC_SIG changes from logic low level Low to logic high level High, may be output synchronously with the falling edge or rising edge of the read enable signal RE_SIG.

[0190] Refer to Figure 1 , Figure 2 and Figure 7 , for example, when the storage capacity of the storage space is full, the memory controller 200 may output the page buffer address control signal PBAC_SIG having a logic high level High to the memory device 100. In response to the falling edge or rising edge of the read enable signal RE_SIG provided by the memory controller 200, the memory device 100 may provide the seventh read data D7, which is the previous read data, to the memory controller 200 through the input / output port DQ [7:0]. The memory controller 200 may receive the seventh read data D7 from the input / output port DQ [7:0]. The memory controller 200 may discard the seventh read data D7 received after the first time point t1.

[0191] Refer to Figure 3 , Figure 4 , Figure 5 andFigure 7 Specifically, for example, when the seventh page buffer outputs the seventh read data D7, the seventh page buffer that outputs the seventh read data D7 before the page buffer address control signal PBAC_SIG changes from the logic low level Low to the logic high level High can be maintained as the target page buffer. During the period from the first time point t1 to the third time point t3, the data output controller 131 can maintain the seventh page buffer as the target page buffer. The operation controller 220 can receive the seventh read data D7.

[0192] At the second time point t2, when there is available storage capacity in the storage space allocated to the memory controller 200 according to an embodiment of the present disclosure, the voltage level of the notification signal BF_SIG can be the logic low level Low.

[0193] At the third time point t3, the page buffer address control signal PBAC_SIG can change from the logic high level High to the logic low level Low. In response to the falling edge or rising edge of the read enable signal RE_SIG, the eighth to thirteenth read data D8, D9, D10, D11, D12, and D13 can be sequentially output.

[0194] Refer to Figure 3 、 Figure 4 、 Figure 5 and Figure 7 Specifically, for example, after the third time point t3, the operation controller 220 can sequentially receive the eighth to thirteenth read data D8, D9, D10, D11, D12, and D13. In addition, the operation controller 220 can store the eighth to thirteenth read data D8, D9, D10, D11, D12, and D13 in the data buffer 210.

[0195] When providing the page buffer address control signal PBAC_SIG, the read enable signal RE_SIG shown in Figure 7 may be switched.

[0196] As described above, since the read operation is maintained by the page buffer address control signal PBAC_SIG, there is the following effect: the delay caused by the stop of the read operation is significantly reduced.

[0197] Figure 8 is a flowchart showing a method of operating a memory controller according to an embodiment of the present disclosure.

[0198] Refer to Figure 1 、 Figure 2 and Figure 8 The memory controller 200 receives a read request and a logical address from the host 500 (S110).

[0199] The memory controller 200 generates a read command in response to a read request from the host 500, generates a physical address corresponding to the logical address provided from the host 500, and provides the read command and the physical address to the memory device 100 (S120).

[0200] The memory controller 200 provides a read enable signal to the memory device 100 (S130). Here, the read enable signal RE_SIG may be a signal indicating the timing for the memory device 100 to output read data.

[0201] The memory controller 200 receives the read data sequentially output from the memory device 100 according to the read enable signal RE_SIG (S140). In this case, the read data and subsequent read data may be output sequentially. Alternatively, the same previously provided read data may be output.

[0202] The memory controller 200 monitors whether there is available storage capacity in the data buffer 210 (S150).

[0203] When there is available storage capacity in the data buffer 210 (S150, Yes), the memory controller 200 provides a page buffer address control signal PBAC_SIG having a first voltage level to the memory device 100 (S160). The page buffer address control signal PBAC_SIG having a first voltage level may be a signal indicating the sequential output of the read data.

[0204] The memory controller 200 may store the read data sequentially received from the memory device 100 in the data buffer 210 (S170).

[0205] The memory controller 200 checks whether the read operation of the memory device 100 is completed (S180).

[0206] When the read operation is completed (S180, Yes), the memory controller 200 provides the read data stored in the data buffer 210 to the host 500 (S190).

[0207] When the read operation is not completed (S180, No), step S140 is executed.

[0208] When the storage capacity of the data buffer 210 is full (S150, No), the memory controller 200 provides a page buffer address control signal PBAC_SIG having a second voltage level to the memory device 100 (S200). The page buffer address control signal PBAC_SIG having a second voltage level may be a signal indicating output of the same read data or previous read data. The previous read data may be read data output from the memory device 100 before the voltage level of the page buffer address control signal PBAC_SIG changes from a first voltage level (e.g., logic low level) to a second voltage level (e.g., logic high level).

[0209] While providing the page buffer address control signal PBAC_SIG having a second voltage level to the memory device 100, the memory controller 200 discards the read data received from the memory device 100 (S210).

[0210] The memory controller 200 performs a data buffer clearing operation (S220) and performs operation S140. The data buffer clearing operation may be an operation in which the memory controller 200 clears the data buffer 210 to generate available storage capacity. Then, the process may return to operation S140.

[0211] Figure 9 is a diagram showing a memory controller according to an embodiment of the present disclosure.

[0212] Referring to Figure 9 , the memory controller 200 may include a processor 201, a RAM 202, an error correction circuit 203, a host interface 204, a ROM 205, and a flash memory interface 206.

[0213] The processor 201 may control all operations of the memory controller 200.

[0214] The RAM 202 may be used as a buffer memory, a cache memory, an operation memory, etc. of the memory controller 200. For example, the RAM 202 may be a buffer memory.

[0215] The error correction circuit 203 may generate an error correction code (ECC) for correcting a failed bit or an error bit of data received from the memory device 100.

[0216] The error correction circuit 203 may perform error correction encoding on the data provided to the memory device 100 to generate data with added parity bits. The parity bits (not shown) may be stored in the memory device 100.

[0217] The error correction circuit 203 can perform error correction decoding on the data output from the memory device 100, and at this time, the error correction circuit 203 can use parity check to correct errors.

[0218] For example, the error correction circuit 203 can use various coding modulations such as the following to correct errors: LDPC code, BCH code, turbo code, Reed-Solomon code, convolutional code, RSC, TCM, and BCM.

[0219] In a programming operation, the error correction circuit 203 can calculate the error correction code value of the data to be programmed into the memory device 100.

[0220] In a read operation, the error correction circuit 203 can perform an error correction operation on the data read from the memory device 100 based on the error correction code value.

[0221] In a recovery operation of failed data, the error correction circuit 203 can perform an error correction operation on the data recovered from the memory device 100.

[0222] The memory controller 200 can communicate with an external device (e.g., host 500, application processor, etc.) through the host interface 204.

[0223] The ROM 205 can store each piece of information required to operate the memory controller 200 in the form of firmware.

[0224] The memory controller 200 can communicate with the memory device 100 through the flash interface 206. The memory controller 200 can transmit a command CMD, an address ADDR, a control signal CTRL, etc. to the memory device 100 through the flash interface 206 and receive data.

[0225] For example, the flash interface 206 can include a NAND interface.

[0226] Figure 10 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0227] Refer to Figure 10 , the memory card system 2000 includes a memory device 2100, a memory controller 2200, and a connector 2300.

[0228] For example, the memory device 2100 can be configured by various non-volatile memory elements such as: electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetoresistive RAM (STT-MRAM).

[0229] The memory controller 2200 is connected to the memory device 2100. The memory controller 2200 is configured to access the memory device 2100. For example, the memory controller 2200 may be configured to control read operations, write operations, erase operations, and background operations of the memory device 2100. The memory controller 2200 is configured to provide an interface between the memory device 2100 and the host 500. The memory controller 2200 is configured to drive firmware for controlling the memory device 2100. The memory controller 2200 may be implemented in the same manner as the memory controller 200 described with reference to Figure 1 The memory controller 2200 may be implemented in the same manner as the memory controller 200 described with reference to

[0230] For example, the memory controller 2200 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error correction circuit.

[0231] The memory controller 2200 may communicate with an external device through the connector 2300. The memory controller 2200 may communicate with an external device (e.g., the host 500) according to a specific communication standard. For example, the memory controller 2200 is configured to communicate with an external device through at least one of various communication standards such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 may be defined by at least one of the above various communication standards.

[0232] The memory device 2100 and the memory controller 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2200 and the memory device 2100 may be integrated into one semiconductor device to configure a memory card such as: PC Card (Personal Computer Memory Card International Association (PCMCIA)), CompactFlash card, SmartMedia card (SM or SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, microMMC, or eMMC), SD card (SD, miniSD, microSD, or SDHC), and Universal Flash Storage (UFS).

[0233] Figure 11 FIG. is a block diagram of a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0234] With reference to Figure 11, the SSD system includes a host 500 and an SSD 3000.

[0235] The SSD 3000 exchanges signals SIG with the host 500 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3000 includes an SSD controller 3200, a plurality of flash memories 3100_1, 3100_2, and 3100_n, an auxiliary power supply device 3300, and a buffer memory 3400.

[0236] According to an embodiment of the present disclosure, the SSD controller 3200 may perform the functions of the memory controller 200 described with reference to Figure 1 description.

[0237] The SSD controller 3200 may control the plurality of flash memories 3100_1, 3100_2, and 3100_n in response to the signal SIG received from the host 500. For example, the signal SIG may be a signal based on the interface between the host 500 and the SSD 3000. For example, the signal SIG may be a signal defined through at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0238] The auxiliary power supply device 3300 is connected to the host 500 through the power connector 3002. The auxiliary power supply device 3300 may receive power PWR from the host 500 and may charge using the power PWR. When the power supply from the host 500 is unstable, the auxiliary power supply device 3300 may supply power to the SSD 3000. For example, the auxiliary power supply device 3300 may be located in the SSD 3200 or may be located outside the SSD 3000. For example, the auxiliary power supply device 3300 may be located on the main board and may supply auxiliary power to the SSD 3000.

[0239] The buffer memory 3400 can temporarily store data. For example, the buffer memory 3400 can temporarily store data received from the host 500 or data received from the plurality of flash memories 3100_1, 3100_2, and 3100_n, or can temporarily store metadata (e.g., a mapping table) of the flash memories 3100_1, 3100_2, and 3100_n. The buffer memory 3400 can include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0240] Figure 12 is a block diagram of a user system to which a storage device according to an embodiment of the present disclosure is applied.

[0241] Referring to Figure 12 , the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0242] The application processor 4100 can drive components, an operating system (OS), user programs, etc. included in the user system 4000. For example, the application processor 4100 can include a controller, an interface, a graphics engine, etc. that control components included in the user system 4000. The application processor 4100 can be configured as a system-on-chip (SoC).

[0243] The memory module 4200 can operate as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 can include volatile random access memories such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memories such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 can be packaged based on a package-on-package (POP) and configured as one semiconductor package.

[0244] The network module 4300 can communicate with an external device. For example, the network module 4300 can support wireless communications such as the following: code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 can be included in the application processor 4100.

[0245] The storage module 4400 can store data. For example, the storage module 4400 can store the data received from the application processor 4100. Optionally, the storage module 4400 can transfer the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 can be implemented using non-volatile semiconductor memory elements such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and 3D NAND flash memory. For example, the storage module 4400 can be set as a removable storage device (removable drive) such as a memory card and an external drive of the user system 4000.

[0246] For example, the storage module 4400 can operate in the same manner as the storage device 1000 described with reference to Figure 8 The storage module 4400 can include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices can operate in the same manner as the memory device 100 described with reference to Figure 1 The storage module 4400 can operate in the same manner as the storage device 1000 described with reference to

[0247] The user interface 4500 can include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 can include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touchpad, trackball, camera, microphone, gyro sensor, vibration sensor, and piezoelectric element. The user interface 4500 can include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0248] Although specific embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Therefore, the memory system should not be limited based on the described embodiments. Instead, when combined with the above description and the drawings, the memory system described herein should be limited only by the appended claims.

Claims

1. A memory device that outputs read data in response to a read enable signal provided from a memory controller, the memory device comprises: a plurality of memory cells that store data; a plurality of page buffers that sense the data stored in the plurality of memory cells through a plurality of bit lines; and a data output controller: when the read enable signal is input, selects a target page buffer for outputting data from among the plurality of page buffers according to a page buffer address control signal provided from the memory controller, and controls the selected target page buffer according to the read enable signal to output the data stored in the selected target page buffer, wherein the page buffer address control signal indicates whether there is available storage capacity in the storage space allocated to the memory controller.

2. The memory device according to claim 1, wherein the data output controller sequentially selects the target page buffer from among the plurality of page buffers according to the address of the page buffer during a period when the voltage level of the page buffer address control signal is a first voltage level, and the data output controller maintains the target page buffer during a period when the voltage level of the page buffer address control signal is a second voltage level, the second voltage level being different from the first voltage level.

3. The memory device according to claim 2, wherein the data output controller maintains, as the target page buffer, a page buffer among the plurality of page buffers that outputs data before the voltage level of the page buffer address control signal changes from the first voltage level to the second voltage level.

4. The memory device according to claim 3, wherein the page buffer address control signal is a signal having the first voltage level or a signal having the second voltage level according to whether there is the available storage capacity in the storage space allocated to the memory controller.

5. The memory device according to claim 4, wherein the page buffer address control signal has the first voltage level when there is the available storage capacity, and has the second voltage level when the storage capacity of the storage space is full.

6. The memory device according to claim 1, wherein the read enable signal is a clock signal that is switched when the page buffer address control signal is provided.

7. A storage device, comprises: a memory device including an input / output port, a read enable port, and a page buffer address port; and a memory controller: provides a read enable signal to the read enable port in response to a read request provided from a host, receives read data from the input / output port according to the read enable signal, temporarily stores the read data received from the input / output port in a pre-allocated storage space, Provide a page buffer address control signal to the page buffer address port according to whether there is available storage capacity in the storage space, the page buffer address control signal being used to control the output of subsequent read data, the subsequent read data being to be output immediately after the read data received from the input / output port, and In response to the completion of the read operation of the memory device, provide the host with the read data temporarily stored in the storage space.

8. The storage device according to claim 7, wherein when there is the available storage capacity, the memory controller provides a page buffer address control signal having a first voltage level, and wherein when the page buffer address control signal having the first voltage level is provided to the page buffer address port, the memory controller further receives the subsequent read data from the input / output port.

9. The storage device according to claim 8, wherein when the storage capacity of the storage space is full, the memory controller provides a page buffer address control signal having a second voltage level, the second voltage level being different from the first voltage level, and wherein when the page buffer address control signal having the second voltage level is provided to the page buffer address port, the memory controller further receives previously read data from the input / output port.

10. The storage device according to claim 9, wherein the previously read data is the read data output from the input / output port before the voltage level of the page buffer address control signal changes from the first voltage level to the second voltage level.

11. The storage device according to claim 10, wherein when the page buffer address control signal having the second voltage level is provided to the page buffer address port, the memory controller further discards the previously read data provided from the input / output port.

12. The storage device according to claim 10, wherein when the storage capacity of the storage space is full, the memory controller further performs a data buffer clearing operation, the data buffer clearing operation clearing the storage space to generate the available storage capacity.

13. The storage device according to claim 7, wherein the memory controller comprises: a data buffer having the storage space; and an operation controller: store the read data received from the input / output port in the data buffer, monitor whether there is the available storage capacity in the storage capacity of the data buffer, and according to the monitoring result, change the voltage level of the page buffer address control signal to a second voltage level, the second voltage level being different from the first voltage level.

14. The storage device according to claim 13, wherein during a period when the voltage level of the page buffer address control signal is the first voltage level, the operation controller further stores the subsequent read data in the data buffer.

15. The storage device according to claim 13, wherein during a period when the voltage level of the page buffer address control signal is the second voltage level, the operation controller receives the read data output from the input / output port before the voltage level of the page buffer address control signal changes from the first voltage level to the second voltage level.

16. The storage device according to claim 7, wherein the read enable signal is a clock signal that is switched when the page buffer address control signal is provided.

17. A method of operating a memory controller, the memory controller controlling a memory device to perform a read operation, the method comprising: providing a read enable signal to the memory device, the read enable signal indicating a timing for the memory device to output read data; receiving the read data sequentially output from the memory device according to the read enable signal; outputting a page buffer address control signal according to a result of monitoring whether there is available storage capacity in a data buffer; and temporarily storing the read data sequentially received from the memory device in the data buffer during a period when the voltage level of the page buffer address control signal is a first voltage level.

18. The method according to claim 17, wherein outputting the page buffer address control signal comprises: outputting a page buffer address control signal having the first voltage level in response to a result of monitoring the presence of the available storage capacity; and outputting a page buffer address control signal having a second voltage level different from the first voltage level in response to a result of monitoring that the storage capacity of the data buffer is full.

19. The method according to claim 18, further comprising: discarding the read data received from the memory device when the voltage level of the page buffer address control signal is the second voltage level.

20. The method according to claim 19, further comprising: providing the read data stored in the data buffer to a host in response to completion of the read operation.

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