Semiconductor device and method of forming a semiconductor device

Abstract

Methods for forming under bump metal (UBM) structures having different surface profiles and semiconductor devices formed by the methods are disclosed. In embodiments, a semiconductor device includes a first redistribution line and a second redistribution line located over a semiconductor substrate; a first passivation layer located over the first redistribution line and the second redistribution line; a first under bump metal (UBM) structure located over the first redistribution line and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure located over the second redistribution line and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being planar or convex.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for forming semiconductor devices. Background Technology

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. They are typically formed by depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material sequentially on a semiconductor substrate, and by using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is constantly increasing the integration density of individual electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest components, which allows more components to be integrated into a given area. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor device comprising: a first redistribution line and a second redistribution line located above a semiconductor substrate; a first passivation layer located above the first redistribution line and the second redistribution line; a first under-bump metal (UBM) structure located above the first redistribution line and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, wherein the top surface of the first UBM structure is concave; and a second UBM structure located above the second redistribution line and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, wherein the top surface of the second UBM structure is flat or convex.

[0005] Other embodiments of the present invention provide another semiconductor device, comprising: a first redistribution line and a second redistribution line, located above a semiconductor substrate; a first under-bump metal (UBM) structure, located above the first redistribution line and electrically coupled to the first redistribution line, wherein the top surface of the first UBM structure is concave, and wherein the first UBM structure has a first width; and a second UBM structure, located above the second redistribution line and electrically coupled to the second redistribution line, wherein the bottom surface of the second UBM structure is flush with the bottom surface of the first UBM structure, wherein the second UBM structure has a second width less than the first width, and wherein the top surface of the second UBM structure is less concave than the top surface of the first UBM structure.

[0006] Some embodiments of the present invention provide a method comprising: forming a first conductive component and a second conductive component over a semiconductor substrate; depositing a passivation structure over the first conductive component and the second conductive component; forming a patterned photoresist over the passivation structure, the patterned photoresist including a first opening over the first conductive component and a second opening over the second conductive component; and simultaneously electroplating a first under-bump metal (UBM) structure in the first opening and a second UBM structure in the second opening, wherein the first UBM structure is electrically coupled to the first conductive component, wherein the second UBM structure is electrically coupled to the second conductive component, and wherein the surface profile of the first UBM structure is different from the surface profile of the second UBM structure. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figures 1 to 15 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor device according to some embodiments. Detailed Implementation

[0009] The following disclosure provides numerous different embodiments or examples of various components for implementing the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0011] Various embodiments provide methods for forming under-bump metal (UBM) and conductive bumps of different sizes with improved coplanarity, and semiconductor devices formed by such methods. UBMs and conductive bumps of different widths can be used to provide different types of interconnects between semiconductor devices. However, forming UBMs and conductive bumps of different widths may result in the upper limits of the top surfaces of the conductive bumps being set at different levels. For example, if conductive material for forming conductive bumps of the same thickness is deposited over two UBMs having the same height but different widths, after the conductive material is reflowed, the top surface of the conductive bump formed over the wider UBM may be positioned above the top surface of the conductive bump formed over the narrower UBM.

[0012] To improve the coplanarity of the top surfaces of conductive bumps, a first UBM with a relatively large width can be formed with a concave upper surface, while a second UBM with a relatively small width can be formed with a flat or convex upper surface. The conductive connector formed above the first UBM has a larger fill volume than the conductive connector formed above the second UBM, thus lowering the upper limit of the top surface of the conductive connector formed above the first UBM compared to the conductive connector formed above the second UBM. The first and second UBMs can be formed using a plating process, and the shape of the top surfaces of the first and second UBMs can be controlled based on the concentration of the leveling agent used in the plating solution and the current density applied during the plating process. This method for improving the coplanarity of conductive bumps reduces yield losses caused by cold soldering, solder bridges, etc. This reduces device defects and increases yield. Furthermore, the first and second UBMs can be formed simultaneously, and the conductive connectors formed on them are formed simultaneously, reducing production time and cost.

[0013] Figures 1 to 14 A cross-sectional view of an intermediate stage in the formation of a device is shown according to some embodiments of the present invention. It should be understood that although device wafers and device dies are used as examples, embodiments of the present invention can also be applied to the formation of conductive components in other devices (e.g., package elements), which include, but are not limited to, package substrates, interposers, packages, etc.

[0014] Figure 1 A cross-sectional view of a semiconductor device 100 is shown. In some embodiments, the semiconductor device 100 is a device wafer containing active and / or passive devices, referred to as an integrated circuit device 104. The semiconductor device 100 can be diced to thereby form a plurality of chips / dies 106. Figure 1The diagram illustrates a single die 106. In some embodiments, the semiconductor device 100 is an interposer wafer that has no active devices and may contain passive devices. In some embodiments, the semiconductor device 100 is a package substrate strip that includes a coreless package substrate or a cored package substrate having a core therein. In the following discussion, a device wafer is used as an example of the semiconductor device 100, and the semiconductor device 100 may be referred to as a wafer. Embodiments of the invention can also be applied to interposer wafers, package substrates, packages, etc.

[0015] In some embodiments, die 106 is a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, application-specific integrated circuit (ASIC) die, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high bandwidth memory (HBM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die, etc.), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0016] In some embodiments, the semiconductor device 100 includes a semiconductor substrate 102 and components formed on the top surface of the semiconductor substrate 102. The semiconductor substrate 102 may be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and may be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor substrate 102 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 102 may include silicon; germanium; compound semiconductors comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium; or combinations thereof. Shallow trench isolation (STI) regions (not shown separately) may be formed in the semiconductor substrate 102 to isolate active regions in the semiconductor substrate 102. Through-holes (not shown separately) may be formed extending into or through the semiconductor substrate 102 (e.g., vias), and may be used for electrical interconnection of components on opposite sides of the semiconductor device 100.

[0017] In some embodiments, the semiconductor device 100 includes an integrated circuit device 104 formed on the top surface of a semiconductor substrate 102. The integrated circuit device 104 may include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of the integrated circuit device 104 are not shown herein. In some embodiments, the semiconductor device 100 is used to form an interposer (which has no active devices), and the semiconductor substrate 102 may be a semiconductor substrate or a dielectric substrate.

[0018] An interlayer dielectric (ILD) 108 is formed over a semiconductor substrate 102 and fills the gaps between the gate stacks (not shown separately) of transistors in the integrated circuit device 104. In some embodiments, the ILD 108 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, combinations thereof, or multilayers thereof. The ILD 108 can be formed using spin coating, flowable chemical vapor deposition (FCVD), or the like. In some embodiments, the ILD 108 is formed using deposition methods such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD).

[0019] Contact plugs 110 are formed in the ILD 108 and electrically couple the integrated circuit device 104 to metal lines and / or vias thereon. In some embodiments, the contact plugs 110 are formed of conductive materials such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), alloys thereof, or multilayers thereof. Forming the contact plugs 110 may include forming contact openings in the ILD 108, filling the contact openings with conductive material, and performing planarization processes (such as chemical mechanical polishing (CMP), mechanical polishing, etch-back, etc.) to make the top surface of the contact plugs 110 flush with the top surface of the ILD 108.

[0020] An interconnect structure 112 is formed above the ILD 108 and the contact plug 110. The interconnect structure 112 includes metal lines 114 and metal vias 116 formed in a dielectric layer 118 (also referred to as an intermetallic dielectric (IMD)). The metal lines 114 formed at the same level are collectively referred to as metal layers. In some embodiments, the interconnect structure 112 includes multiple metal layers comprising metal lines 114 interconnected through the metal vias 116. The metal lines 114 and metal vias 116 may be formed of copper, copper alloys, other metals, etc.

[0021] In some embodiments, dielectric layer 118 is formed of a low-k dielectric material. The dielectric constant (k value) of the low-k dielectric material may be less than about 3.0. Dielectric layer 118 may include carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), combinations thereof, or multilayers thereof. In some embodiments, dielectric layer 118 may comprise phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, dielectric layer 118 may include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), combinations thereof, etc. Dielectric layer 118 may be formed by FCVD, PECVD, LPCVD, etc. In some embodiments, forming dielectric layer 118 includes depositing a dielectric material containing a pore-forming agent in dielectric layer 118, and then performing a curing process to remove the pore-forming agent. Thus, dielectric layer 118 may be porous.

[0022] Forming metal lines 114 and metal vias 116 in the dielectric layer 118 can include single damascene and / or dual damascene processes. In a single damascene process, a trench or via opening is formed in one of the dielectric layers 118, and the trench or via opening is filled with a conductive material. A planarization process, such as CMP, is then performed to remove excess conductive material, which may be above the top surface of the dielectric layer 118, thereby leaving metal lines 114 or metal vias 116 in the corresponding trench or via opening. In a dual damascene process, both trenches and via openings are formed in the dielectric layer 118, wherein the via opening is located below the trench and connected to the trench. Conductive material is filled into the trench and via opening to form metal lines 114 and metal vias 116, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0023] A top metal component 120 can be formed in the top dielectric layer 121. The top metal component 120 can be formed of the same or similar material as the metal lines 114 and metal vias 116 and through the same or similar processes as the metal lines 114 and metal vias 116, and the top dielectric layer 121 can be formed of the same or similar material as the dielectric layer 118 and through the same or similar processes as the dielectric layer 118. The top metal component 120 can be referred to as the topmost metallization layer in the interconnect structure 112. Although... Figure 1 The interconnect structure 112 is shown to have a specific number of metallization layers, but in other embodiments it may contain any number of metal layers. The top dielectric layer 121 and the dielectric layer 118 directly below the top dielectric layer 121 may be formed as a single continuous dielectric layer, or they may be formed as different dielectric layers using different processes, and / or formed from different materials.

[0024] A first passivation layer 122 and a second passivation layer 124 may be formed over the interconnect structure 112. The first passivation layer 122 and the second passivation layer 124 may be collectively referred to as the first passivation structure. In some embodiments, the first passivation layer 122 and the second passivation layer 124 may comprise phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, the first passivation layer 122 and the second passivation layer 124 may comprise an inorganic dielectric material, which may comprise materials selected from silicon nitride (SiN). x ), silicon dioxide (SiO2), silicon oxynitride (SiON) x ), silicon dioxide (SiOC) x Materials such as silicon carbide (SiC), combinations thereof, or multilayers thereof. The first passivation layer 122 and the second passivation layer 124 can be formed of different materials. For example, the first passivation layer 122 may include silicon nitride (SiN), while the second passivation layer 124 may include undoped silicate glass (USG). In some embodiments, the first passivation layer 122 may include a single layer, and the second passivation layer 124 may be omitted. In some embodiments, the top surface of the top dielectric layer 121 is coplanar with the top surface of the top metal component 120 (e.g., flush with each other). Therefore, the first passivation layer 122 and the second passivation layer 124 may be coplanar layers. In some embodiments, the top metal component 120 protrudes above the top surface of the top dielectric layer 121, and the first passivation layer 122 and the second passivation layer 124 are not coplanar. The first passivation layer 122 and the second passivation layer 124 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0025] exist Figure 2 An opening 126 is formed in the first passivation layer 122 and the second passivation layer 124. The opening 126 can be formed using an etching process, which may include a dry etching process. The etching process may include forming a patterned etch mask (not shown separately), such as a patterned photoresist, and then using the patterned photoresist as a mask to etch the first passivation layer 122 and the second passivation layer 124. The patterned etch mask is then removed. The opening 126 can be patterned through the first passivation layer 122 and the second passivation layer 124, and the opening 126 can expose the top metal part 120.

[0026] exist Figure 3In this process, a seed layer 128 is formed over the second passivation layer 124, the first passivation layer 122, and the top metal component 120, and in the opening 126. The seed layer 128 may include a titanium layer and a copper layer above the titanium layer. In some embodiments, the seed layer 128 includes a copper layer in contact with the second passivation layer 124, the first passivation layer 122, and the top metal component 120. The seed layer 128 may be formed by a deposition process such as PVD.

[0027] exist Figure 4 In this process, a patterned photoresist 130 is formed above the seed layer 128. The patterned photoresist 130 can be formed by depositing a photosensitive layer above the seed layer 128 using spin coating or the like. The photosensitive layer can then be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions, thereby forming the patterned photoresist 130. An opening 132 is formed in the exposed seed layer 128 to extend through the patterned photoresist 130. The pattern of the patterned photoresist 130 corresponds to the redistribution layer (RDL) to be formed in the patterned photoresist 130, as will be discussed below. Figure 5 The subject of discussion.

[0028] exist Figure 5 In this process, a conductive material 134 is formed above the exposed portion of the seed layer 128, and the conductive material 134 fills the openings 126 and 132. The conductive material 134 can be formed by plating, such as electroplating or electroless plating. The conductive material 134 may include metals such as copper, titanium, tungsten, aluminum, combinations thereof, or alloys thereof. The combination of the conductive material 134 with portions of the underlying seed layer 128 forms RDL 136A and RDL 136B (collectively referred to as RDL 136). Each RDL in RDL 136 may include a via portion extending through the second passivation layer 124 and the first passivation layer 122, and a trace / line portion above the second passivation layer 124. Although in Figure 5 Only two RDLs of RDL 136 are shown in the diagram, but any number of RDLs 136 can be formed above each die in die 106.

[0029] exist Figure 6 In this process, the patterned photoresist 130 and portions of the seed layer 128 on which the conductive material 134 is not formed are removed. The patterned photoresist 130 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the patterned photoresist 130 has been removed, the exposed portions of the seed layer 128 are removed using an acceptable etching process, such as wet etching or dry etching. One or more optional cleaning processes may also be performed.

[0030] exist Figure 7In this structure, a third passivation layer 138, a fourth passivation layer 140, and a protective layer 142 are formed above the second passivation layer 124 and above and along the sidewalls and top surface of the RDL 136. The third passivation layer 138 and the fourth passivation layer 140 may be collectively referred to as the second passivation structure. The third passivation layer 138 and the fourth passivation layer 140 may be formed of the same or different materials as the first passivation layer 122 and the second passivation layer 124. In some embodiments, the third passivation layer 138 and the fourth passivation layer 140 may be formed of an inorganic dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbide, combinations thereof, or multiple layers thereof. In some embodiments, the third passivation layer 138 may include silicon oxide, and the fourth passivation layer 140 may include silicon nitride. The third passivation layer 138 may be made of a material with high etch selectivity relative to the material of the fourth passivation layer 140, thereby enabling the third passivation layer 138 to serve as an etch stop layer for the process of etching the fourth passivation layer 140. In some embodiments, the third passivation layer 138 may be a single layer, and the fourth passivation layer 140 may be omitted. The third passivation layer 138 and the fourth passivation layer 140 may be deposited by CVD, ALD, or the like. The combined thickness T1 of the third passivation layer 138 and the fourth passivation layer 140 may range from about 0.5 μm to about 5.0 μm or from about 1.0 μm to about 2.5 μm.

[0031] A protective layer 142 is then formed over the fourth passivation layer 140. In some embodiments, the protective layer 142 is formed from a polymeric material such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc. (which may be photosensitive). The protective layer 142 can be formed by CVD, PECVD, spin coating, etc. In some embodiments, forming the protective layer 142 includes coating the protective layer 142 in a flowable form and then baking to harden the protective layer 142. A planarization process such as CMP or mechanical polishing can be performed to make the top surface of the protective layer 142 flush. The protective layer 142 over RDL 136 may have a height H1 in the range of about 1.0 μm to about 10 μm. The protective layer 142 over the second passivation layer 124 between RDL 136 may also have a height H2 in the range of about 2 μm to about 40 μm or about 4.5 μm to about 20 μm.

[0032] exist Figure 8In this embodiment, a first opening 144 and a second opening 146 are formed over RDL 136A and RDL 136B, respectively, through the protective layer 142, the fourth passivation layer 140, and the third passivation layer 138. In an embodiment where the protective layer 142 comprises a photosensitive material, the protective layer 142 can be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions, thereby forming the first opening 144 and the second opening 146. The first opening 144 and the second opening 146 can then extend through the fourth passivation layer 140 and the third passivation layer 138 to expose RDL 136A and RDL 136B, respectively, using the protective layer 142 as a mask. The fourth passivation layer 140 and the third passivation layer 138 can be etched using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching process can be anisotropic.

[0033] like Figure 8 As shown, the first opening 144 and the second opening 146 may have tapered sidewalls that narrow in the direction toward the semiconductor substrate 102. In some embodiments, the sidewalls of the first opening 144 and the second opening 146 may be substantially vertical or may be tapered and widen in the direction toward the semiconductor substrate 102. The first opening 144 may have a width W1 that is flush with the top surface of the protective layer 142 and ranges from about 5 μm to about 80 μm or from about 10 μm to about 50 μm, and a width W2 that is flush with the bottom surface of the third passivation layer 138 above the RDL 136A and ranges from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. The second opening 146 may have a width W3 ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm, flush with the top surface of the protective layer 142, and a width W4 ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm, flush with the bottom surface of the third passivation layer 138 above the RDL 136B. The ratio of width W3 to width W1 and the ratio of width W4 to width W2 may range from about 1.0 to about 8.0. The first opening 144 and the second opening 146 may have a height H3 ranging from about 2 μm to about 40 μm or from about 4.5 μm to about 20 μm. In some embodiments, the first opening 144 is larger (e.g., wider) than the second opening 146. For example, the width W1 of the first opening 144 may be greater than the width W3 of the second opening 146, and the width W2 of the first opening 144 may also be greater than the width W4 of the second opening 146.

[0034] The protective layer 142 can then be cured using a curing process. The curing process may include heating the protective layer 142 to a predetermined temperature for a predetermined time period using an annealing process or other heating process. The curing process may also include ultraviolet (UV) light exposure, infrared (IR) energy exposure, combinations thereof, or combinations thereof with heating processes. Optionally, other methods may be used to cure the protective layer 142. In some embodiments, no curing process is included, or the curing process is performed before the formation of the first opening 144 and the second opening 146.

[0035] exist Figure 9 In this process, a seed layer 148 is formed over RDL 136, the third passivation layer 138, the fourth passivation layer 140, and the protective layer 142, and within the first opening 144 and the second opening 146. The seed layer 148 may include a titanium layer and a copper layer above the titanium layer. In some embodiments, the seed layer 148 includes a copper layer in contact with RDL 136, the third passivation layer 138, the fourth passivation layer 140, and the protective layer 142. The seed layer 148 can be formed by a deposition process such as PVD. Figure 9 As shown, the bottom surface of the seed layer 148 in the first opening 144 can be flush with the bottom surface of the seed layer 148 in the second opening 146. The seed layer 148 includes a horizontal portion extending along the top surface of the protective layer 142, a diagonal portion extending along the sidewalls of the third passivation layer 138, the fourth passivation layer 140 and the protective layer 142, and a horizontal portion extending along the top surface of the RDL 136.

[0036] exist Figure 10 In this process, a patterned photoresist 150 is formed above a seed layer 148. The patterned photoresist 150 can be formed by depositing a photosensitive layer above the seed layer 148 using a spin coating or similar method. The photosensitive layer can then be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions, thereby forming the patterned photoresist 150. A first opening 152A and a second opening 152B of the seed layer 148 exposed above RDL 136A and exposed above RDL 136B respectively extend through the patterned photoresist 150. The first opening 152A and the second opening 152B can be collectively referred to as opening 152. The pattern of the patterned photoresist 150 corresponds to the under-bump metal (UBM) to be formed in the patterned photoresist 150, as will be discussed below. Figure 11A and Figure 11B The discussion.

[0037] The first opening 152A may have a width W5 ranging from about 10 μm to about 90 μm, and the second opening 152B may have a width W6 ranging from about 5 μm to about 80 μm. The ratio of the width W5 of the first opening 152A to the width W6 of the second opening 152B may be in the range of about 1.5 to about 10 or about 2 to about 5. In some embodiments, the first opening 152A is larger (e.g., wider) than the second opening 152B. For example, the width W5 of the first opening 152A may be greater than the width W6 of the second opening 152B. In a top view (not shown separately), the ratio of the area of ​​the first opening 152A to the area of ​​the second opening 152B may be in the range of about 2.5 to about 16. Different types of UBMs may subsequently be formed in the first opening 152A and the second opening 152B, and the dimensions of the first opening 152A and the second opening 152B may be based on the type of UBM to be formed therein. In some embodiments, a controlled-collapse chip connection (C4) bump can be formed in a first opening 152A, and a microbump (μbump) can be formed in a second opening 152B. Simultaneously forming the first opening 152A and the second opening 152B, and subsequently simultaneously forming the UBM and the conductive contact, reduces the mask required to form the UBM and the conductive contact and lowers the cost.

[0038] exist Figure 11A and Figure 11B In this process, conductive material 154 is deposited in the first opening 152A and the second opening 152B. The conductive material 154 can be deposited by plating, such as electroplating. The conductive material 154 can include metals such as copper (Cu), nickel (Ni), silver (Ag), combinations thereof, etc. The combination of the conductive material 154 and the lower portion of the seed layer 148 forms a first UBM 156A in the first opening 152A and a second UBM 156B in the second opening 152B (collectively referred to as UBM 156). Conductive connectors (such as those referenced below) can then be formed on the UBM 156. Figure 13 The conductive connector 160 discussed provides an external connection to the semiconductor device 100. The UBM 156 may include a bump portion extending along the top surface of the protective layer 142. The UBM 156 may also include via portions in the first opening 144 and the second opening 146 (e.g., extending through the protective layer 142, the fourth passivation layer 140, and the third passivation layer 138), which are physically and electrically coupled to the RDL 136. As a result, the UBM 156 is electrically coupled to a device (e.g., an integrated circuit device 104 on the semiconductor substrate 102).

[0039] In embodiments where the conductive material 154 is formed by a plating process, the die 106 may be immersed in a plating solution. A direct current may be applied to the semiconductor substrate 102. In embodiments where the conductive material 154 comprises copper, the plating solution may include copper sulfate (CuSO4), sulfuric acid (H2SO4), and hydrochloric acid (HCl). The plating solution may also contain additives such as accelerators, inhibitors, leveling agents, combinations thereof. In some embodiments, the plating solution may include copper sulfate at a concentration ranging from about 20 g / L to about 175 g / L, sulfuric acid at a concentration ranging from about 50 g / L to about 300 g / L, hydrochloric acid at a concentration ranging from about 10 ppm to about 100 ppm, a leveling agent at a concentration ranging from about 5 cc / L to about 30 cc / L, an accelerator at a concentration ranging from about 5 cc / L to about 30 cc / L, and an inhibitor at a concentration ranging from about 5 cc / L to about 30 cc / L.

[0040] As the conductive material 154 is deposited, a leveling agent can be adsorbed onto the surface of the conductive material 154. The leveling agent can prevent the conductive material 154 from being deposited with a top surface having a raised profile; a higher concentration of leveling agent results in the conductive material 154 being deposited with a less raised profile. For example, if the conductive material 154 is deposited with a plating solution that does not contain a leveling agent, the conductive material 154 can have a raised top surface. As the concentration of the leveling agent present in the opening 152 increases, the conductive material 154 can be deposited with a less raised top surface, such as a flat top surface or a concave top surface.

[0041] In some embodiments, the leveling agent may include polar molecules. For example, the leveling agent may contain one or more halogen groups, such as chlorine groups. Because the leveling agent contains polar molecules, it can be attracted to the first opening 152A and the second opening 152B based on the electric fields applied through RDL 136A and RDL 136B, respectively. The electric fields applied through RDL 136A and RDL 136B are the result of applying a direct current to the semiconductor substrate 102 during electroplating. The magnitude of the electric fields applied through RDL 136A and RDL 136B depends on the areas of RDL 136A and RDL 136B and the applied current density. The first opening 152A has a larger area than the second opening 152B, resulting in a greater electric field applied in the first opening 152A than the electric field applied in the second opening 152B. This results in a higher concentration of leveling agent present in the first opening 152A compared to the second opening 152B. Therefore, compared to the second opening 152B, more leveling agent is adsorbed onto the conductive material 154 in the first opening 152A, and compared to the second UBM 156B, the first UBM 156A forms a less protruding surface. This is achieved through... Figure 11A and Figure 11BIn the illustrated embodiment, the first UBM 156A has a concave surface, and the second UBM 156B has a more convex surface (e.g., Figure 11A The flat surface of the embodiment shown and Figure 11B The raised surface in the illustrated embodiment is used for illustration. A range of approximately 1 amp / dm can be used. 2 The conductive material 154 is plated at a current density of approximately 15 ASD to approximately 15 ASD. The area of ​​the first opening 152A is approximately 5 to approximately 16 times larger than the area of ​​the second opening 152B (e.g., in a top view), such that the current applied to the first opening 152A can be approximately 5 to approximately 16 times larger than the current applied to the second opening 152B.

[0042] Figure 11A and Figure 11B The surface profile of UBM 156 shown can be the result of containing different concentrations of leveling agent in the plating solution, applying different current densities, or combinations thereof. For example, relative to Figure 11B The embodiment shown, Figure 11A The surface profile shown can be achieved by including a higher concentration of leveling agent and / or using a higher current density. For Figure 11A In the illustrated embodiment, the concentration of the leveling agent in the plating solution can be in the range of about 5 cc / L to about 30 cc / L, and a current density in the range of about 1 ASD to about 15 ASD can be applied to the die 106. Figure 11B In the illustrated embodiment, the concentration of the leveling agent in the plating solution can be in the range of about 5 cc / L to about 30 cc / L, and a current density in the range of about 1 ASD to about 15 ASD can be applied to the die 106. The current density can be adjusted by changing the DC current applied to the semiconductor substrate 102.

[0043] exist Figure 11AIn the illustrated embodiment, the first UBM 156A has a width W5 ranging from about 10 μm to about 90 μm above the protective layer 142, a width W1 ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm flush with the top surface of the protective layer 142, and a bottom surface of the first UBM 156A having a width W2 ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. The first UBM 156A has a height H4 ranging from about 5 μm to about 18 μm above the protective layer 142. The top surface of the first UBM 156A is concave, such that the distance D1 between the upper limit of the first UBM 156A and the lower limit of the top surface of the first UBM 156A is in the range of about 0.1 μm to about 10 μm or about 0.5 μm to about 6 μm. The second UBM 156B has a width W6 ranging from about 5 μm to about 50 μm above the protective layer 142, a width W3 ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm flush with the top surface of the protective layer 142, and a bottom surface of the second UBM 156B having a width W4 ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. The second UBM 156B has a height H5 ranging from about 5 μm to about 18 μm above the protective layer 142. The top surface of the second UBM 156B may be substantially planar. In some embodiments, the height H5 of the second UBM 156B may be equal to the height H4 of the first UBM 156A. In some embodiments, the height H5 of the second UBM 156B is greater than the height H4 of the first UBM 156A, and the height H4 of the first UBM 156A is within about 3 μm or about 6 μm of the height H5 of the second UBM 156B. Figure 11A In the illustrated embodiment, the top surface of the second UBM 156B may be flush with the top surface of the first UBM 156A or above the upper limit of the top surface of the first UBM 156A and above the lower limit of the top surface of the first UBM 156A. Providing the first UBM 156A and the second UBM 156B with heights within a specified range helps ensure the subsequent deposition of conductive connectors (such as those referenced below). Figure 13 The upper limit of the conductive connectors (160) discussed is within the expected range of each other, which helps to improve the coplanarity of the conductive connectors; reduce the risk of cold soldering, solder bridging, etc.; and reduce device defects and yield loss.

[0044] exist Figure 11BIn the illustrated embodiment, the first UBM 156A has a width W5 ranging from about 10 μm to about 90 μm above the protective layer 142, a width W1 ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm flush with the top surface of the protective layer 142, and a bottom surface of the first UBM 156A having a width W2 ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. The first UBM 156A has a height H6 ranging from about 5 μm to about 18 μm above the protective layer 142. The top surface of the first UBM 156A is concave, such that the distance D2 between the upper limit of the first UBM 156A and the lower limit of the top surface of the first UBM 156A is in the range of about 0.1 μm to about 10 μm or about 0.5 μm to about 6 μm. The second UBM 156B has a width W6 ranging from about 5 μm to about 80 μm above the protective layer 142, a width W3 ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm flush with the top surface of the protective layer 142, and a bottom surface of the second UBM 156B having a width W4 ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. The second UBM 156B has a height H7 ranging from about 5 μm to about 18 μm above the protective layer 142. The top surface of the second UBM 156B may be convex. The top surface of the second UBM 156B is convex such that the distance D4 between the upper limit of the second UBM 156B and the lower limit of the top surface of the second UBM 156B is less than about 0.1 μm. The height H7 of the second UBM 156B may be greater than the height H6 of the first UBM 156A. In some embodiments, the top surface of the second UBM 156B may extend over the top surface of the first UBM 156A by a distance D3 ranging from about 0.01 μm to about 3 μm. Figure 11B In the illustrated embodiment, the upper limit of the top surface of the second UBM 156B may be above the upper limit of the top surface of the first UBM 156A, and the lower limit of the top surface of the second UBM 156B may be flush with or above the upper limit of the top surface of the first UBM 156A. Furthermore, the lower limit of the top surface of the second UBM 156B may be above the lower limit of the top surface of the first UBM 156A. Although the first UBM 156A is shown as having angled surfaces and transitions between surfaces, the top surface of the first UBM 156A may be... Figure 11A and Figure 11B The cross-sectional view has a circular outline.

[0045] A conductive material (e.g., solder material) can then be deposited and reflowed over UBM 156 to form a conductive connector. Due to the greater width of the first UBM 156A relative to the second UBM 156B, reflowing conductive material to form the conductive connector may result in a conductive connector formed over the first UBM 156A tending to have a greater height than the conductive connector formed over the second UBM 156B. However, this height difference is corrected by forming the first UBM 156A with a concave top surface and the second UBM 156B with a flat or convex top surface, and a conductive connector with an upper limit at or near the same level can then be formed. Specifically, the more concave profile of the first UBM 156A provides a larger fill volume for the conductive connector formed above the first UBM 156A compared to the conductive connector formed above the second UBM 156B. This lowers the top surface of the conductive connector formed above the first UBM 156A compared to the conductive connector formed above the second UBM 156B. This results in the top surfaces of the conductive connectors being closer to coplanarity, reducing yield losses due to cold soldering and solder bridging, and reducing device defects. Furthermore, because the first UBM 156A and the second UBM 156B are formed simultaneously, fewer masks are required compared to other methods used to improve the coplanarity of conductive connectors, reducing production time and cost.

[0046] exist Figure 12 In this process, a first conductive material 158A and a second conductive material 158B (collectively referred to as conductive material 158) are deposited over a first UBM 156A in a first opening 152A and a second UBM 156B in a second opening 152B, respectively. In some embodiments, the conductive material 158 is formed by evaporation, electroplating, printing, solder transfer, solder ball placement, etc. The conductive material 158 may comprise conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, multilayers, or combinations thereof. The conductive material 158 can be deposited simultaneously in the first opening 152A and the second opening 152B, and the conductive material 158 can be deposited to a thickness ranging from about 3 μm to about 20 μm.

[0047] like Figure 12As shown, conductive material 158 can be conformally deposited such that the top surface of the first conductive material 158A has a similar profile to the top surface of the first UBM 156A, and the top surface of the second solder material 158B has a similar profile to the top surface of the second UBM 156B. Therefore, the first conductive material 158A can have a concave top surface, and the second conductive material 158B can have a flat or convex top surface. Due to the larger width of the first UBM 156A relative to the second UBM 156B, reflowing conductive material 158 may result in the first conductive material 158A tending to have a greater height than the second conductive material 158B. However, by forming the first UBM 156A with a concave top surface and the second UBM 156B with a flat or convex top surface, this height difference is corrected, and conductive material 158 can be reflowed to form conductive connectors with upper limits of top surfaces at or near the same level (as discussed below). Figure 13 The conductive connector 160 under discussion. Specifically, the more concave profile of the first UBM 156A, relative to the second conductive material 158B, provides a larger fill volume for the conductive material 158A during reflow. This lowers the upper limit top surface of the conductive connector formed above the first UBM 156A relative to the conductive connector formed above the second UBM 156B. This results in the upper limit of the top surface of the conductive connector being closer to coplanar, reducing yield losses due to cold soldering and solder bridging, and reducing device defects. Furthermore, the simultaneous formation of the first conductive material 158A and the second conductive material 158B reduces production time and cost.

[0048] exist Figure 13 In the process, the portions of the patterned photoresist 150 and seed layer 148 where the conductive material 154 is not formed are removed, and the first conductive material 158A and the second conductive material 158B are also removed. Figure 12 (Not shown in the image) Reflow is performed. The patterned photoresist 150 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the patterned photoresist 150 has been removed, the exposed portion of the seed layer 148 is removed using an acceptable etching process, such as wet etching or dry etching.

[0049] Reflow can be used to form the first conductive material 158A and the second conductive material 158B into the first conductive connector 160A and the second conductive connector 160B (collectively referred to as conductive connector 160). For example... Figure 13As shown, the conductive connector 160 may have a spherical shape. The conductive connector 160 may be a ball grid array (BGA) connector, solder ball, controlled collapse chip connection (C4) bump, microbump, etc. In some embodiments, the first conductive connector 160A may be a C4 bump, and the second conductive connector 160B may be a microbump.

[0050] Because the first UBM 156A has a larger width relative to the second UBM 156B, reflowing the conductive material 158 may cause the first conductive connector 160A to tend to have a higher height than the second conductive connector 160B. However, this height difference is corrected by forming the first UBM 156A with a concave top surface and the second UBM 156B with a flat or convex top surface, and the conductive material 158 can be reflowed to form the first conductive connector 160A and the second conductive connector 160B with upper limits at the same level or closer to the same level. Although the upper limits of the top surfaces of the first conductive connector 160A and the second conductive connector 160B are at... Figure 13 The top surfaces of the first conductive connector 160A and the second conductive connector 160B are shown as flush, but the range of the upper limit difference between their top surfaces can be from approximately 3 μm above the first conductive connector 160A to approximately 3 μm above the second conductive connector 160B, or from approximately 8 μm above the first conductive connector 160A to approximately 5 μm above the second conductive connector 160B. Maintaining the upper limits of the top surfaces of the first conductive connector 160A and the second conductive connector 160B within this range significantly improves their coplanarity, reducing solder bridges, cold solder joints, etc. This reduces device defects, reduces device yield losses, and improves device performance. Furthermore, the simultaneous formation of the first conductive material 158A and the second conductive material 158B reduces production time and cost.

[0051] Figure 14 An embodiment omitting the protective layer 142 is shown. (As shown) Figure 14 As shown, the seed layer 148 of UBM 156 can be formed directly on the top surface of the fourth passivation layer 140. UBM 156 may include a horizontal portion extending along the top surface of the fourth passivation layer 140. The steps for forming UBM 156 and conductive connector 160 can be the same as those discussed above, except that the steps of depositing and patterning the protective layer 142 are omitted. Omitting the protective layer 142 can provide better contact resistance between UBM 156 and the underlying RDL 136 and reduce the cost associated with forming the protective layer 142.

[0052] Figure 15 An embodiment is shown in which the through-hole portions of UBM 156 have the same width. This can be achieved by forming... Figure 8 The first opening 144 and the second opening 146, which have the same width, are shown, and then... Figures 9 to 13 The steps shown are to form Figure 15 The UBM 156 shown is an example. Figure 15 As shown, the via portion of UBM 156 may have a width W7 of about 5 μm to about 80 μm or about 10 μm to about 50 μm that is flush with the top surface of the protective layer 142 and a width W8 of about 5 μm to about 80 μm or about 10 μm to about 50 μm that is flush with the bottom surface of the third passivation layer 138 located above RDL 136A.

[0053] As previously discussed, the shape and profile of the concave portion of the first UBM 156A are determined by the width W5 of the first opening 152A. Figure 10 As shown), the concentration of the leveling agent present during the formation of the first UBM 156A and the current applied during the formation of the first UBM 156A cause this. Thus, the shape and contour of the concave portion of the first UBM 156A can be controlled independently of the shape and contour of the through-hole portion of the first UBM 156A. For example... Figure 15 As shown, the center line of the through-hole portion C1 of the first UBM 156A may be offset from or misaligned with the center line of the protrusion portion C2 of the first UBM 156A. The center line of the concave portion C3 of the first UBM 156A may be aligned with the center line of the protrusion portion C2 of the first UBM 156A, but offset from or misaligned with the center line of the through-hole portion C1 of the first UBM 156A. Furthermore, in Figure 15 In the illustrated embodiment, the concave portion of the first UBM 156A may have a width greater than the width of the through-hole portion of the first UBM 156A. Forming the first UBM 156A according to the above embodiment allows the shape and profile of the concave portion of the first UBM 156A to be set independently of the shape and profile of the underlying through-hole portion of the first UBM 156A, which provides greater flexibility in forming the first UBM 156A.

[0054] The embodiments can achieve various advantages. For example, forming different UBMs with different widths and surface profiles improves the coplanarity of the conductive connections subsequently formed on top of the UBMs. This helps prevent solder bridging, cold solder joints, etc., increases yield, and reduces device defects. Furthermore, UBMs and conductive connections can be formed simultaneously, which reduces production time and costs.

[0055] According to an embodiment, the semiconductor device includes: a first redistribution line and a second redistribution line located above a semiconductor substrate; a first passivation layer located above the first redistribution line and the second redistribution line; a first under-bump metal (UBM) structure located above the first redistribution line and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, the top surface of the first UBM structure being concave; and a second UBM structure located above the second redistribution line and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, the top surface of the second UBM structure being either flat or convex. In an embodiment, a first width of the first UBM structure is greater than a second width of the second UBM structure. In an embodiment, the first UBM includes a via portion extending through the first passivation layer, and the centerline of the via portion is not aligned with the centerline of the concave portion of the top surface of the first UBM structure. In an embodiment, the first UBM includes a via portion extending through the first passivation layer, and the width of the via portion is less than the width of the concave portion of the top surface of the first UBM structure. In one embodiment, the semiconductor device further includes a polymer layer located above a first passivation layer, a first UBM structure and a second UBM structure extending through the polymer layer, the first UBM structure having a first height above the polymer layer, and the second UBM structure having a second height above the polymer layer, with the difference between the first height and the second height being less than 3 μm. In another embodiment, the semiconductor device further includes a first conductive connector located above the first UBM structure, the upper limit of the top surface of the first UBM structure being disposed at a first distance above the top surface of the first passivation layer; and a second conductive connector located above the second UBM structure, the upper limit of the top surface of the second UBM structure being disposed at a second distance above the top surface of the first passivation layer, with the difference between the first distance and the second distance being less than 4 μm. In another embodiment, the upper limit of the top surface of the first UBM structure is flush with the upper limit of the top surface of the second UBM structure.

[0056] According to another embodiment, the semiconductor device includes a first redistribution line and a second redistribution line located above a semiconductor substrate; a first under-bump metal (UBM) structure located above and electrically coupled to the first redistribution line, the top surface of the first UBM structure being concave and having a first width; and a second UBM structure located above and electrically coupled to the second redistribution line, the bottom surface of the second UBM structure being flush with the bottom surface of the first UBM structure, the second UBM structure having a second width less than the first width, and the top surface of the second UBM structure being less concave than the top surface of the first UBM structure. In one embodiment, the top surface of the second UBM structure is flat. In another embodiment, the top surface of the second UBM structure is convex. In another embodiment, the semiconductor device further includes a first passivation layer located above the first and second redistribution lines, the first UBM structure and the second UBM structure extending through the first passivation layer, the first UBM structure and the second UBM structure including horizontal portions extending along the top surface of the first passivation layer. In one embodiment, the semiconductor device further includes a first passivation layer located above the first redistribution line and the second redistribution line; and a polymer layer located above the first passivation layer. A first UBM structure and a second UBM structure extend through the polymer layer and the first passivation layer, and the first and second UBM structures include horizontal portions extending along the top surface of the polymer layer. In another embodiment, the upper limit of the top surface of the first UBM structure is flush with the upper limit of the top surface of the second UBM structure.

[0057] According to yet another embodiment, the method includes: forming a first conductive component and a second conductive component over a semiconductor substrate; depositing a passivation structure over the first and second conductive components; forming a patterned photoresist over the passivation structure, the patterned photoresist including a first opening over the first conductive component and a second opening over the second conductive component; and simultaneously electroplating a first under-bump metallization (UBM) structure in the first opening and a second UBM structure in the second opening, the first UBM structure being electrically coupled to the first conductive component, the second UBM structure being electrically coupled to the second conductive component, and the surface profile of the first UBM structure being different from the surface profile of the second UBM structure. In an embodiment, the first UBM structure is electroplated with a concave surface profile, and the second UBM structure is electroplated with a flat or convex surface profile. In an embodiment, in a top view, a first area of ​​the first opening is larger than a second area of ​​the second opening. In an embodiment, electroplating the first and second UBM structures involves applying a current with a density of 1 ASD to 15 ASD. In an embodiment, electroplating the first UBM structure and the second UBM structure includes applying an electroplating solution into the first and second openings. The electroplating solution contains a leveling agent, and the concentration of the leveling agent adsorbed on the surface of the first UBM structure is greater than that on the surface of the second UBM structure. In an embodiment, the method further includes simultaneously depositing a conductive material over the first and second UBM structures; and reflowing the conductive material to form a first conductive connector over the first UBM structure and a second conductive connector over the second UBM structure. In an embodiment, electroplating the first and second UBM structures includes applying an electroplating solution into the first and second openings. The electroplating solution contains a leveling agent, which includes chlorine, and the concentration of the leveling agent in the electroplating solution ranges from 5 cc / L to 30 cc / L.

[0058] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under bump metal structure over and electrically coupled to the first redistribution line, the first under bump metal structure extending through the first passivation layer, wherein a top surface of the first under bump metal structure is concave; and a second under bump metal structure over and electrically coupled to the second redistribution line, the second under bump metal structure extending through the first passivation layer, wherein a top surface of the second under bump metal structure is planar or convex; wherein the first under bump metal structure includes a first via portion extending through the first passivation layer, and wherein a centerline of the first via portion is misaligned with a centerline of a concave portion of the top surface of the first under bump metal structure.

2. The semiconductor device of claim 1, wherein, a first width of the first under bump metal structure is greater than a second width of the second under bump metal structure.

3. The semiconductor device of claim 1, wherein, the first passivation layer is a layer of inorganic dielectric material.

4. The semiconductor device of claim 1, wherein, a width of the first via portion is less than a width of the concave portion of the top surface of the first under bump metal structure.

5. The semiconductor device of claim 1, further comprising a polymer layer over the first passivation layer, the first bump- under metal structure and the second bump- under metal structure extending through the polymer layer, wherein, the first under bump metal structure has a first height over the polymer layer, wherein the second under bump metal structure has a second height over the polymer layer, and wherein a difference between the first height and the second height is less than 3 pm.

6. The semiconductor device of claim 1, further comprising: a first conductive connection over the first under bump metal structure, wherein an upper extent of a top surface of the first under bump metal structure is disposed at a first distance above a top surface of the first passivation layer; and a second conductive connection over the second under bump metal structure, wherein an upper extent of a top surface of the second under bump metal structure is disposed at a second distance above the top surface of the first passivation layer, and wherein a difference between the first distance and the second distance is less than 4 pm.

7. The semiconductor device of claim 1, wherein, the upper extent of the top surface of the first under bump metal structure is flush with the upper extent of the top surface of the second under bump metal structure.

8. A semiconductor device, comprising: a first redistribution line and a second redistribution line over a semiconductor substrate; a first under bump metal structure over and electrically coupled to the first redistribution line, wherein a top surface of the first under bump metal structure is concave, and wherein the first under bump metal structure has a first width; and a second under bump metal structure over and electrically coupled to the second redistribution line, wherein a bottom surface of the second under bump metal structure is flush with a bottom surface of the first under bump metal structure, wherein the second under bump metal structure has a second width that is less than the first width, and wherein a top surface of the second under bump metal structure is less concave than the top surface of the first under bump metal structure. a first passivation layer over the first redistribution line and the second redistribution line, the first under bump metallurgy structure and the second under bump metallurgy structure extending through the first passivation layer; wherein the first under bump metallurgy structure includes a first via portion extending through the first passivation layer, and wherein a centerline of the first via portion is misaligned with a centerline of a concave portion of the top surface of the first under bump metallurgy structure.

9. The semiconductor device of claim 8, wherein, the top surface of the second under bump metallurgy structure is planar.

10. The semiconductor device of claim 8, wherein, the top surface of the second under bump metallurgy structure is convex.

11. The semiconductor device of claim 8, wherein, the first under bump metallurgy structure and the second under bump metallurgy structure include horizontal portions extending along a top surface of the first passivation layer.

12. The semiconductor device of claim 8, further comprising: a polymer layer over the first passivation layer, wherein the first under bump metallurgy structure and the second under bump metallurgy structure extend through the polymer layer and the first passivation layer, and wherein the first under bump metallurgy structure and the second under bump metallurgy structure include horizontal portions extending along a top surface of the polymer layer.

13. The semiconductor device of claim 8, wherein, an upper extent of the top surface of the first under bump metallurgy structure is flush with an upper extent of the top surface of the second under bump metallurgy structure.

14. A method of forming a semiconductor device, comprising: forming first and second conductive features over a semiconductor substrate; depositing a passivation structure over the first and second conductive features; forming a patterned photoresist over the passivation structure, the patterned photoresist including a first opening over the first conductive feature and a second opening over the second conductive feature; and electroplating a first under bump metallurgy structure in the first opening and a second under bump metallurgy structure in the second opening simultaneously, wherein the first under bump metallurgy structure is electrically coupled to the first conductive feature, wherein the second under bump metallurgy structure is electrically coupled to the second conductive feature, and wherein a surface profile of the first under bump metallurgy structure is different than a surface profile of the second under bump metallurgy structure; wherein the first under bump metallurgy structure includes a first via portion extending through the passivation structure, and wherein a centerline of the first via portion is misaligned with a centerline of a concave portion of a top surface of the first under bump metallurgy structure.

15. The method of claim 14, wherein, the first under bump metallurgy structure is electroplated with a concave surface profile, and wherein the second under bump metallurgy structure is electroplated with a planar or convex surface profile.

16. The method of claim 15, wherein, in a top view, a first area of the first opening is greater than a second area of the second opening.

17. The method of claim 16, wherein, electroplating the first under bump metallurgy structure and the second under bump metallurgy structure includes applying a current having a density of 1 ASD to 15 ASD.

18. The method of claim 15, wherein, Electroplating the first and second under bump metallization structures includes applying an electroplating solution in the first and second openings, the electroplating solution including a leveling agent, wherein a concentration of the leveling agent adsorbed on a surface of the first under bump metallization structure is greater than a concentration of the leveling agent adsorbed on a surface of the second under bump metallization structure.

19. The method of claim 14, further comprising: simultaneously depositing a conductive material over the first and second under bump metallization structures; and reflowing the conductive material to form a first conductive connection over the first under bump metallization structure and a second conductive connection over the second under bump metallization structure.

20. The method of claim 14, wherein, Electroplating the first and second under bump metallization structures includes applying an electroplating solution in the first and second openings, the electroplating solution including a leveling agent, the leveling agent including chlorine, a concentration of the leveling agent in the electroplating solution ranging from 5 cc / L to 30 cc / L.

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