Dual-mode ultra-wideband high-efficiency power amplification circuit
By employing a single-pole double-throw switch and a dual-mode ultra-wideband output matching circuit in the RF microwave system, the loss problem caused by switch switching is solved, achieving efficient power mode conversion and bandwidth expansion, which is suitable for RF microwave systems.
Patent Information
- Application Number
- CN202111577553.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-22
- Publication Date
- 2025-10-24
- Estimated Expiration
- 2041-12-22
AI Technical Summary
In existing multi-mode RF microwave systems, the losses caused by switching are superimposed, making it difficult to improve system efficiency. Furthermore, the integration is not high, which cannot meet the different operating modes of communication and target detection.
A single-pole double-throw switch and a dual-mode ultra-wideband output matching circuit are used to achieve power mode conversion by switching the switch in different states. The circuit is combined with a multi-stage inductor-capacitor low-pass network for matching, which reduces losses and widens the bandwidth.
It achieves high-efficiency power output in communication and detection modes, improves system efficiency, reduces output matching circuit losses, and widens the bandwidth, making it suitable for radio frequency microwave systems.
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Figure CN114465584B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a dual-mode ultra-wideband high-efficiency power amplifier circuit, and belongs to the technical field of radio frequency microwave and millimeter wave circuits. BACKGROUND
[0002] Modern electronic systems have changed from single function to systematization, especially communication and detection integrated systems. With the ability to realize signal amplification, ultra-wideband power amplifiers have become essential core devices in the system. However, communication and target detection often require different working modes. Target detection requires higher output power and hopes that the power consumption of the whole machine is small and the efficiency is high. The communication system generally hopes to have good linearity, but the output power does not need to be too large. At present, most of the systems working in multiple modes use cascaded switching. The system is relatively cumbersome and has low integration. In the traditional mode of realizing multi-mode through switching, the switch and the power amplifier are designed separately and then cascaded. The loss of the switch is directly added to the output end of the power amplifier, so that the efficiency of the system is difficult to improve. SUMMARY
[0003] In order to solve the technical problems mentioned in the background art, the present application provides a dual-mode ultra-wideband high-efficiency power amplifier circuit.
[0004] In order to achieve the above technical purpose, the technical scheme of the present application is as follows:
[0005] A dual-mode ultra-wideband high-efficiency power amplifier circuit, comprising a single-pole double-throw switch, a first mode branch, a second mode branch and a dual-mode ultra-wideband output matching circuit; the movable end of the single-pole double-throw switch is used as the input end of the power amplifier circuit, the two fixed ends are connected with the input ends of the first mode branch and the second mode branch respectively, the output terminals of the first mode branch and the second mode branch are connected with the two input terminals of the dual-mode ultra-wideband output matching circuit, and the output terminal of the dual-mode ultra-wideband output matching circuit is used as the output end of the power amplifier circuit.
[0006] Preferably, the first mode branch comprises an input matching network, n transistors and n-1 inter-stage matching networks, n is an integer greater than or equal to 1, the n transistors are connected in series, when n is greater than or equal to 2, an inter-stage matching network is connected in series between adjacent two transistors, the gate of the first transistor is connected with the output terminal of the input matching network, the drain of the last transistor is used as the output terminal of the first mode branch, and the sources of all the transistors are connected with the ground.
[0007] Preferably, the second mode branch includes an input matching network, m transistors, and m-1 inter-stage matching networks, m is an integer greater than or equal to 1, the m transistors are connected in series, when m is greater than or equal to 2, an inter-stage matching network is connected in series between adjacent two transistors, the gate of the first transistor is connected to the output terminal of the input matching network, the drain of the last transistor is the output terminal of the second mode branch, and the source of all the transistors is connected to the ground.
[0008] Preferably, the type of the transistor is a junction field effect transistor, a metal-oxide-semiconductor field effect transistor, a heterojunction field effect transistor, a bipolar junction transistor, or a heterojunction bipolar transistor.
[0009] Preferably, the dual-mode ultra-wideband output matching circuit includes a first microstrip line, a first bias branch, a third microstrip line, a second capacitor, a fourth microstrip line, a multiplexing branch, a sixth capacitor, and a ninth microstrip line, a second bias branch; the first microstrip line, the third microstrip line, the fourth microstrip line, the multiplexing branch, the sixth capacitor, and the ninth microstrip line are connected in series, the input terminal of the first microstrip line and the output terminal of the ninth microstrip line are the two input terminals of the dual-mode ultra-wideband output matching circuit, one end of the second capacitor is connected to the common terminal of the third microstrip line and the fourth microstrip line, and the other end is connected to the ground of the reference potential of the dual-mode ultra-wideband output matching circuit, the first bias branch is connected to the common terminal of the first microstrip line and the third microstrip line, and the second bias branch is connected to the common terminal of the output terminal of the sixth capacitor and the ninth microstrip line.
[0010] Preferably, the first bias branch includes a first capacitor and a second microstrip line, one end of the second microstrip line is connected to the common terminal of the first microstrip line and the third microstrip line, and the other end is connected to a first bias voltage source, one end of the first capacitor is connected to the common terminal of the second microstrip line and the first bias voltage source, and the other end is connected to the ground of the reference potential of the dual-mode ultra-wideband output matching circuit.
[0011] Preferably, the multiplexing branch comprises a third capacitor, a first transistor, a fourth capacitor, a fifth capacitor, a fifth microstrip line, a second transistor, a sixth microstrip line, a seventh microstrip line, a third transistor and a fourth transistor; the drain of the first transistor is connected to the output end of the fourth microstrip line in series with the third capacitor, the source is connected to the ground for setting the reference potential of the dual-mode ultra-wideband output matching circuit, and the gate is connected to the first control voltage source; one end of the fourth capacitor is connected to the output end of the fourth microstrip line, and the other end is connected to the sixth capacitor in series with the fifth microstrip line, the sixth microstrip line and the seventh microstrip line in turn; one end of the fifth capacitor is connected to the common end of the fourth capacitor and the fifth microstrip line, and the other end is used as the output end of the dual-mode ultra-wideband output matching circuit; the drain of the second transistor is connected to the common end of the fifth microstrip line and the sixth microstrip line, the source is connected to the common end of the sixth microstrip line and the seventh microstrip line, and the gate is connected to the second control voltage source; the drains of the third transistor and the fourth transistor are commonly connected to the common end of the seventh microstrip line and the sixth capacitor, the sources are commonly connected to the ground for setting the reference potential of the dual-mode ultra-wideband output matching circuit, and the gates are respectively connected to the third control voltage source and the fourth control voltage source.
[0012] Preferably, the second bias branch comprises a seventh capacitor and an eighth microstrip line; one end of the eighth microstrip line is connected to the common end of the sixth capacitor and the ninth microstrip line, and the other end is connected to the second bias voltage source; one end of the seventh capacitor is connected to the common end of the eighth microstrip line and the second bias voltage source, and the other end is connected to the ground for setting the reference potential of the dual-mode ultra-wideband output matching circuit.
[0013] Preferably, the dual-mode ultra-wideband high-efficiency power amplification circuit is implemented in the form of a monolithic integrated circuit or a hybrid integrated circuit.
[0014] The above technical scheme has the following beneficial effects:
[0015] The application realizes the switching between large and small power modes of the ultra-wideband power amplifier circuit through the two different states of the on and off of the switch, and realizes the application requirements of different power modes for communication and detection.
[0016] The application integrates the switch into the output matching circuit to serve as a circuit matching branch, which greatly reduces the loss of the output matching circuit compared with the traditional power amplifier cascaded switch, and adopts a multi-stage inductance-capacitance low-pass network plus a parallel inductance to ground for matching, and the inductance value can be changed according to the switching of the switch for different modes, thereby improving the efficiency of the ultra-wideband power amplifier.
[0017] The application has the advantages of reasonable design, easy implementation, scalability and good practical value. BRIEF DESCRIPTION OF DRAWINGS
[0018] Figure 1The present invention is a dual-mode ultra-wideband high-efficiency power amplifier circuit;
[0019] Figure 2 The invention provides a dual-mode ultra-wideband output matching circuit;
[0020] Figure 3 is a simulation result of the dual-mode ultra-wideband output matching circuit in the embodiment;
[0021] Figure 4 1 is a graph showing the test results of the large and small output powers of the power amplifier circuit in dual-mode operation in the embodiment, wherein (a) is a graph showing the test results of the high-power output and (b) is a graph showing the test results of the low-power output. DETAILED DESCRIPTION
[0022] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.
[0023] The dual-mode ultra-wideband high-efficiency power amplifier circuit of the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0024] like Figure 1 The figure shows a dual-mode ultra-wideband high-efficiency power amplifier circuit according to the present invention, comprising a single-pole double-throw switch, a first mode branch, a second mode branch, and a dual-mode ultra-wideband output matching circuit. The first mode branch further comprises an input matching network, a pre-stage transistor, multiple intermediate-stage transistors, an inter-stage matching network, and a final-stage transistor. The second mode branch similarly comprises an input matching network, a pre-stage transistor, multiple intermediate-stage transistors, an inter-stage matching network, and a final-stage transistor. The power amplifier provides DC power to the drains of the final-stage transistors of the first mode branch and the second mode branch respectively through the first bias branch and the second bias branch of the dual-mode ultra-wideband output matching circuit.
[0025] like Figure 2 As shown, in the dual-mode ultra-wideband output matching circuit, the first microstrip line TL1, the third microstrip line TL3, the fourth microstrip line TL4, the multiplexing branch, the sixth capacitor C6, and the ninth microstrip line TL9 are connected in series in sequence. The input terminal of the first microstrip line TL1 and the output terminal of the ninth microstrip line TL9 serve as the two input terminals P1 and P9 of the dual-mode ultra-wideband output matching circuit. One end of the second capacitor C2 is connected to the terminal where the third microstrip line TL3 and the fourth microstrip line TL4 are connected, and the other end is connected to the ground point G1 for setting the reference potential of the dual-mode ultra-wideband output matching circuit. The first bias branch is connected between the output terminal of the first microstrip line TL1 and the first bias voltage source P2, and the second bias branch is connected between the output terminal of the sixth capacitor C6 and the second bias voltage source P8.
[0026] In the multiplexing branch, the drain of the first transistor K1 is connected in series with the third capacitor C3 and the output terminal of the fourth microstrip line TL4, the source is connected to the ground G1 for setting the reference potential of the dual-mode ultra-wideband output matching circuit, and the gate is connected to the first control voltage source P3. One end of the fourth capacitor C4 is connected to the output terminal of the fourth microstrip line TL4, and the other end is connected in series with the fifth microstrip line TL5, the sixth microstrip line TL6, and the seventh microstrip line TL7, and then connected to the input terminal of the sixth capacitor C6. The fifth capacitor C5 is connected between the terminal where the fourth capacitor C4 is connected to the fifth microstrip line TL5 and the output terminal P4 of the dual-mode ultra-wideband output matching circuit. The drain of the second transistor K2 is connected to the terminal where the fifth microstrip line TL5 is connected to the sixth microstrip line TL6, the source is connected to the terminal where the sixth microstrip line TL6 is connected to the seventh microstrip line TL7, and the gate is connected to the second control voltage source P5. The drains of the third transistor K3 and the fourth transistor K4 are commonly connected to the output terminal of the seventh microstrip line TL7, the sources are both connected to the ground G1 for setting the reference potential of the dual-mode ultra-wideband output matching circuit, and the gates are respectively connected to the third control voltage source P6 and the fourth control voltage source P7.
[0027] In the first biasing branch, the second microstrip line TL2 is connected between the output terminal of the first microstrip line TL1 and the first biasing voltage source P2, and the first capacitor C1 is connected between the terminal where the second microstrip line TL2 is connected to the first biasing voltage source P2 and the ground G1 for setting the reference potential of the dual-mode ultra-wideband output matching circuit.
[0028] In the second biasing branch, the eighth microstrip line TL8 is connected between the output terminal of the sixth capacitor C6 and the second biasing voltage source P8, and the seventh capacitor C7 is connected between the terminal where the eighth microstrip line TL8 is connected to the second biasing voltage source P8 and the ground G1 for setting the reference potential of the dual-mode ultra-wideband output matching circuit.
[0029] The physical structure type of the above-mentioned pre-stage transistor, multiple intermediate-stage transistors, and final-stage transistor can be a junction field effect transistor, a metal-oxide-semiconductor field effect transistor, a heterojunction field effect transistor, a bipolar junction transistor, or a heterojunction bipolar transistor.
[0030] The power amplification circuit is implemented in the form of a monolithic integrated circuit or a hybrid integrated circuit. Embodiment
[0031] As Figure 1As shown, it is a dual-mode ultra-wideband high-efficiency power amplifier circuit. Its frequency range is 5-13GHz, including a single-pole double-throw switch, a first mode branch, a second mode branch and a dual-mode ultra-wideband output matching circuit. The common terminal of the switch is the input terminal of the power amplifier circuit, and the other two terminals are connected to the input terminals of the first mode branch and the second mode branch respectively. The output terminals of the first mode branch and the second mode branch are connected to the two input terminals of the dual-mode ultra-wideband output matching circuit. The first mode branch includes an input matching network, a transistor Q1, a first-to-second inter-stage matching network, a transistor Q2, a second-to-third inter-stage matching network and a transistor Q3. The gate of the transistor Q1 is connected to the output terminal of the input matching network. The first-to-second inter-stage matching network is connected between the drain of the transistor Q1 and the gate of the transistor Q2. The second-to-third inter-stage matching network is connected between the drain of the transistor Q2 and the gate of the transistor Q3. The drain of the transistor Q3 is connected to one input terminal P1 of the dual-mode ultra-wideband output matching circuit. The second mode branch includes an input matching network, a transistor Q4, a first-to-second inter-stage matching network and a transistor Q5. The gate of the transistor Q4 is connected to the output terminal of the input matching network. The first-to-second inter-stage matching network is connected between the drain of the transistor Q4 and the gate of the transistor Q5. The drain of the transistor Q5 is connected to the other input terminal P9 of the dual-mode ultra-wideband output matching circuit. The first bias branch and the second bias branch of the dual-mode ultra-wideband output matching circuit provide DC power for the drain of the transistor Q3 of the first mode branch and the drain of the transistor Q5 of the second mode branch respectively. In the above, the input matching network and the first-to-second inter-stage matching network in the first mode branch and the second mode branch can be different in circuit structure. The sources of the transistors in the branches are all connected to ground.
[0032] Figure 1 When the single-pole double-throw switch is turned on in the first mode branch, and Figure 2 When the single-pole double-throw switch is turned on in the second mode branch, and the gates of the transistors K1 and K2 of the dual-mode ultra-wideband output matching circuit are connected to 0V, and the gates of the transistors K3 and K4 are applied with negative voltage, the dual-mode ultra-wideband output matching circuit participates in the matching of the second mode branch to realize a small power output of 0.5W.
[0033] Figure 3 is Figure 2 The matching result of the dual-mode ultra-wideband output matching circuit in the high-power mode is shown in the figure. It can be seen from the matching result that the output matching network has good matching result in the ultra-wideband range of 5-13GHz. It can also be explained that the structure is suitable for the application occasions of ultra-wideband impedance matching.
[0034] Figure 4 is Figure 1 The test result chart of output power and efficiency of the dual-mode power amplification circuit in the medium power amplification circuit, wherein (a) is a high power output test result chart, and (b) is a low power output test result chart. It can be seen that the dual-mode power amplification circuit of the application has a power output of 12W in a high power working mode and an additional efficiency of 35% in a frequency range of 5-13GHz. The dual-mode power amplification circuit has a power output of 0.5W in a low power working mode, and the flatness is better than ±1dB. The dual-mode ultra-wideband high-efficiency matching circuit of the application is suitable for application occasions of radio frequency microwave millimeter wave ultra-wideband dual-mode.
[0035] The embodiments are only used to illustrate the technical idea of the application, and cannot limit the protection scope of the application. Any modification made according to the technical idea of the application on the basis of the technical scheme falls within the protection scope of the application.
Claims
1. A dual mode ultra-wideband high efficiency power amplification circuit, characterized by, The single-pole double-throw switch, the first mode branch, the second mode branch and the dual-mode ultra-wideband output matching circuit are included; the movable end of the single-pole double-throw switch is used as the input end of the power amplifier circuit, the two fixed ends are connected with the input ends of the first mode branch and the second mode branch respectively, the output terminals of the first mode branch and the second mode branch are connected with the two input terminals of the dual-mode ultra-wideband output matching circuit respectively, and the output terminal of the dual-mode ultra-wideband output matching circuit is used as the output end of the power amplifier circuit; The dual-mode ultra-wideband output matching circuit includes a first microstrip line, a first bias branch, a third microstrip line, a second capacitor, a fourth microstrip line, a multiplexing branch, a sixth capacitor and a ninth microstrip line, and a second bias branch. The first microstrip line, the third microstrip line, the fourth microstrip line, the multiplexing branch, the sixth capacitor and the ninth microstrip line are connected in series, the input terminal of the first microstrip line and the output terminal of the ninth microstrip line are used as the two input terminals of the dual-mode ultra-wideband output matching circuit, one end of the second capacitor is connected to the common end of the third microstrip line and the fourth microstrip line, the other end is connected to the grounding point for setting the reference potential of the dual-mode ultra-wideband output matching circuit, the first bias branch is connected to the common end of the first microstrip line and the third microstrip line, and the second bias branch is connected to the common end of the output terminal of the sixth capacitor and the ninth microstrip line. The multiplexing branch includes a third capacitor, a first transistor, a fourth capacitor, a fifth capacitor, a fifth microstrip line, a second transistor, a sixth microstrip line, a seventh microstrip line, a third transistor and a fourth transistor; the drain of the first transistor is connected with the output end of the fourth microstrip line in series through the third capacitor, the source is connected to the grounding point for setting the reference potential of the dual-mode ultra-wideband output matching circuit, and the gate is connected to the first control voltage source; one end of the fourth capacitor is connected to the output end of the fourth microstrip line, and the other end is connected to the sixth capacitor in series through the fifth microstrip line, the sixth microstrip line and the seventh microstrip line in sequence; one end of the fifth capacitor is connected to the common end of the fourth capacitor and the fifth microstrip line, and the other end is used as the output end of the dual-mode ultra-wideband output matching circuit; the drain of the second transistor is connected to the common end of the fifth microstrip line and the sixth microstrip line, the source is connected to the common end of the sixth microstrip line and the seventh microstrip line, the gate is connected to the second control voltage source, the drains of the third transistor and the fourth transistor are commonly connected to the common end of the seventh microstrip line and the sixth capacitor, the sources are commonly connected to the grounding point for setting the reference potential of the dual-mode ultra-wideband output matching circuit, and the gates are respectively connected to the third control voltage source and the fourth control voltage source.
2. The dual mode ultra-wideband high efficiency power amplification circuit of claim 1, wherein, The first mode branch includes an input matching network, n transistors and n-1 inter-stage matching networks, n is an integer greater than or equal to 1, the n transistors are connected in series, when n is greater than or equal to 2, one inter-stage matching network is connected between two adjacent transistors, the gate of the first transistor is connected to the output terminal of the input matching network, the drain of the last transistor is used as the output terminal of the first mode branch, and the sources of all the transistors are connected to the ground.
3. The dual mode ultra-wideband high efficiency power amplification circuit of claim 1, wherein, The second mode branch includes an input matching network, m transistors and m-1 inter-stage matching networks, m is an integer greater than or equal to 1, the m transistors are connected in series, when m is greater than or equal to 2, an inter-stage matching network is connected in series between two adjacent transistors, the gate of the first transistor is connected to the output terminal of the input matching network, the drain of the last transistor is the output terminal of the second mode branch, and the sources of all the transistors are connected to the ground.
4. The dual-mode ultra-wideband high-efficiency power amplifying circuit according to claim 2 or 3, characterized in that, The type of the transistor is a junction field effect transistor, a metal-oxide-semiconductor field effect transistor, a heterojunction field effect transistor, a bipolar junction transistor or a heterojunction bipolar transistor.
5. The dual mode ultra-wideband high efficiency power amplification circuit of claim 1, wherein, The first bias branch includes a first capacitor and a second microstrip line, one end of the second microstrip line is connected to the common end of the first microstrip line and the third microstrip line, the other end is connected to the first bias voltage source, one end of the first capacitor is connected to the common end of the second microstrip line and the first bias voltage source, and the other end is connected to the grounding point of the reference potential of the dual-mode ultra-wideband output matching circuit.
6. The dual mode ultra-wideband high efficiency power amplification circuit of claim 1, wherein, The second bias branch includes a seventh capacitor and an eighth microstrip line; one end of the eighth microstrip line is connected to the common end of the sixth capacitor and the ninth microstrip line, the other end is connected to the second bias voltage source, one end of the seventh capacitor is connected to the common end of the eighth microstrip line and the second bias voltage source, and the other end is connected to the grounding point of the reference potential of the dual-mode ultra-wideband output matching circuit.
7. The dual mode ultra-wideband high efficiency power amplification circuit of claim 1, wherein, The dual-mode ultra-wideband high-efficiency power amplification circuit is implemented in the form of a monolithic integrated circuit or a hybrid integrated circuit.
Citation Information
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