A random number generator for stochastic computing

Abstract

The patent discloses a random number generator for random calculation, comprising: an excitation unit, a first random unit, a second random unit and a sensing unit, wherein under the excitation of the excitation unit, the first random unit transforms from a high resistance state to a low resistance state with a first probability; under the excitation of the excitation unit, the second random unit transforms from a high resistance state to a low resistance state with a second probability; the second random unit randomly outputs a first or second or third or fourth response current according to the combined relationship between the resistance states of the first and second random units; and the sensing unit is used for sensing the first or second or third or fourth response current randomly output by the second random unit and generating a random number 1 or 0 according to the sensing result.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the field of information security, and particularly relates to a random number generator for random computing. BACKGROUND

[0002] Random computing is a new form of computing, which encodes a numerical value by the probability of '1' in a random bit stream composed of '0' and '1'. It has low computing cost and strong error tolerance to soft errors, and has attracted widespread attention in the field of information technology in recent years.

[0003] Compared with traditional binary counting, random computing can use simple logic gate circuits to implement some complex operations, thereby reducing the computing cost. For example, a single AND gate can implement multiplication, and a single multiplexer can implement proportional addition and subtraction. At the same time, random computing has strong error tolerance to soft errors. If some bits are flipped during the operation, the impact of these error flips on the operation result is small because all bits in the random bit stream have equal weights. In traditional binary counting, the flipping of some bits has a large impact on the operation result.

[0004] Traditional random computing circuits are usually composed of a random number generator and a logic operation unit. The random number generator has problems such as circuit complexity and area. For example, the widely used linear feedback shift register (LFSR) is composed of multiple registers and multiple XOR gates, which has a large circuit area and high hardware cost, which has offset the cost benefits brought by random computing. The separate logic operation unit (such as the logic AND gate for multiplication) also introduces new area and energy consumption problems. With the development of technology, the natural random characteristics of the resistance change process of emerging non-volatile memory and volatile gate can be used to provide a random bit stream for random computing, thereby reducing the cost of random computing. SUMMARY

[0005] In view of the deficiencies in the prior art, the purpose of the present disclosure is to provide a random number generator for random computing, which reduces the cost of generating a random bit stream by connecting a non-volatile memory and a volatile gate in series as a random source, and can output a random bit stream of any length. Moreover, the multiplication operation can be performed without additional logic gate circuits.

[0006] To achieve the above purpose, the present disclosure provides the following technical solutions:

[0007] A random number generator for random computing comprises an excitation unit, a first random unit, a second random unit and a sensing unit, wherein,

[0008] Under the excitation of the excitation unit, the first random unit transitions from a high resistance state to a low resistance state with a first probability;

[0009] Under the excitation of the excitation unit, the second random unit transforms from a high resistance state to a low resistance state with a second probability;

[0010] The second random unit randomly outputs a first or second or third or fourth response current according to a combination relationship between the resistance states of the first and second random units;

[0011] The sensing unit is used for sensing the first or second or third or fourth response current randomly output by the second random unit, and generating a random number 1 or 0 according to the sensing result.

[0012] Preferably, the first random unit adopts a non-volatile memory, including any one of a magnetic random memory, a resistive random memory, a phase change random memory and a ferroelectric random memory;

[0013] Preferably, the second random unit adopts a volatile switch, including any one of a bidirectional threshold switch, a metal-insulator phase change switch, a hybrid ion-electron conductor switch, a field-assisted super-linear threshold switch, a Schottky diode switch, a tunnel barrier switch and a metal wire threshold switch.

[0014] Preferably, the first random unit and the second random unit are connected in series.

[0015] Preferably, the excitation of the excitation unit is voltage excitation or current excitation.

[0016] Preferably, the first probability of the first random unit transforming from a high resistance state to a low resistance state is regulated by adjusting the pulse amplitude or pulse width of the voltage excitation or current excitation;

[0017] The second probability of the second random unit transforming from a high resistance state to a low resistance state is regulated by adjusting the pulse amplitude or pulse width of the voltage excitation or current excitation.

[0018] Preferably, the pulse width of the voltage excitation is 100 ps to 10 ms, and the pulse amplitude is 1 mV to 10 V;

[0019] The pulse width of the current excitation is 100 ps to 10 ms, and the pulse amplitude is 1 nA to 10 mA.

[0020] Preferably, the waveform of the voltage excitation or current excitation includes any one of a square wave, a sine wave, a triangular wave, a trapezoidal wave, a truncated sine wave, a ladder wave, a sawtooth wave and a hybrid wave.

[0021] Preferably, the sensing unit includes a current comparator and a sampling circuit.

[0022] The present disclosure also provides a random computing method of a random number generator, comprising the following steps:

[0023] S100: the excitation unit excites the first random unit to transition from a high resistance state to a low resistance state with a first probability;

[0024] S200: the excitation unit excites the second random unit to transition from a high resistance state to a low resistance state with a second probability;

[0025] S300: adjust the pulse amplitude or pulse width of the excitation unit to regulate the first probability and the second probability to realize random computing.

[0026] The present disclosure also provides a method for applying a random number generator in random computing, comprising the following steps:

[0027] S1000: connect the first random unit and the second random unit in series, and under the excitation of the excitation unit, the first random unit is initialized to a high resistance state;

[0028] S2000: under the excitation of the excitation unit, the first random unit transitions from a high resistance state to a low resistance state with a first probability, and the first probability is denoted as P1;

[0029] S3000: under the excitation of the excitation unit, the second random unit transitions from a high resistance state to a low resistance state with a second probability, and the second probability is denoted as P2;

[0030] S4000: if the first random unit is in a low resistance state and the second random unit is in a low resistance state, the second random unit responds to output a first current; if the first random unit is in a low resistance state and the second random unit is in a high resistance state, the second random unit responds to output a second current; if the first random unit is in a high resistance state and the second random unit is in a low resistance state, the second random unit responds to output a third current; if the first random unit is in a high resistance state and the second random unit is in a high resistance state, the second random unit responds to output a fourth current; wherein the output probability of the first current is P1*P2;

[0031] S5000: sense the first or second or third or fourth response current by the sensing unit and compare it with the reference current, wherein the reference current is set to be between the first current and the second current, if the response current is greater than the reference current, the first current is sensed, at this time, a random number 1 is generated; if the response current is less than the reference current, the second current or the third current or the fourth current is sensed, at this time, a random number 0 is generated;

[0032] S6000: repeat steps S1000-S5000 for N times to generate a random bit stream of N bits, wherein the probability of the occurrence of the digital bit "1" is P1*P2, that is, the multiplication operation of the probability P1 and the probability P2 is completed.

[0033] Compared with the prior art, the beneficial effects brought by the present disclosure are:

[0034] 1. Compared with the traditional CMOS circuit, the present disclosure utilizes the randomness of the volatile gate and the non-volatile memory in the resistance change process as a random bit source, reduces the circuit area, and greatly reduces the cost of random bit stream generation; and can output random bit stream of any length without limitation.

[0035] 2. Multiplication operation in traditional random calculation is realized by a logical AND gate, which needs to input two independent random bit streams at both ends of the AND gate to generate a new random bit stream. The volatile gate and the non-volatile memory are connected in series in the present disclosure, so that the multiplication operation can be directly performed without the logical AND gate circuit, thereby reducing the energy consumption of random calculation.

[0036] 3. The emerging volatile gate and non-volatile memory are subject to changes in manufacturing parameters, and there is a problem of device uniformity, that is, two (or more) devices designed the same will have a deviation in the probability value represented by the output random bit stream under the same operating conditions. Using the traditional multiplication method, two devices need to be connected in parallel to input two independent random bit streams to the logical AND gate. Due to the influence of device uniformity, the probability value represented by the bit stream generated by the device is deviated, which affects the accuracy of multiplication operation; the present disclosure adopts the series connection of volatile gate and non-volatile memory, which avoids the influence of device uniformity on the accuracy of multiplication operation.

[0037] 4. The random number generator provided by the present disclosure has small size, simple structure, high reliability, and can be easily integrated on a large scale, and has good application prospect in the field of information technology such as digital filtering, image signal processing and neural network. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 A structural schematic diagram of a random number generator for random calculation is provided for an embodiment of the present disclosure;

[0039] Figure 2 A flowchart for multiplication operation using a random number generator to generate a random bit stream;

[0040] Figure 3 A voltage waveform applied for multiplication operation using a random number generator;

[0041] Figure 4 A waveform diagram for outputting a first current I1 or a second current I2 or a third current I3 or a fourth current I4 according to the resistance state of the first random unit and the second random unit;

[0042] Figure 5 for comparing the first current I1 with the reference current I ref After comparison, the comparator output level V out and the waveform of the sampling clock V sample ;

[0043] Figure 6 for comparing the second current I2 or the third current I3 or the fourth current I4 with the reference current I ref After comparison, the comparator output level V out and the waveform of the sampling clock V sample ;

[0044] Figures 7(a) to 7(d) for the simulation result of multiplication operation using random number generator, wherein Fig. 7(a) is the distribution of values represented by 16-bit bit stream; Fig. 7(b) is the distribution of values represented by 32-bit bit stream; Fig. 7(c) is the distribution of values represented by 64-bit bit stream; Fig. 7(d) is the distribution of values represented by 128-bit bit stream. DETAILED DESCRIPTION

[0045] Specific embodiments of the present disclosure will be described in detail hereinafter with reference to the drawings, but the present disclosure can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Figures 1 to 7(d) The specific embodiments of the present disclosure will be described in detail hereinafter with reference to the drawings, but the present disclosure can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0046] It should be noted that some terms are used in the specification and claims to refer to certain components. Those skilled in the art will understand that the same component can be referred to by different names. The specification and claims should not be construed as being limited by the names of the components. Rather, the criterion for distinguishing components is their functions. As used throughout the specification and claims, "comprise" or "include" is an open term, which should be interpreted as "including but not limited to". The subsequent description is provided for the purpose of illustrating the preferred embodiments of the present disclosure, and is intended to serve as a general principle for the specification, and not to limit the scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

[0047] For the convenience of understanding the embodiments of the present disclosure, the following will be further explained with specific examples in conjunction with the accompanying drawings, and each drawing does not constitute a limitation on the embodiments of the present disclosure.

[0048] In one embodiment, as shown in Figure 1 the present disclosure provides a random number generator for random computing, comprising: an excitation unit, a first random unit, a second random unit and a sensing unit, wherein,

[0049] under the excitation of the excitation unit, the first random unit transforms from the high resistance state to the low resistance state with a first probability;

[0050] under the excitation of the excitation unit, the second random unit transforms from the high resistance state to the low resistance state with a second probability;

[0051] the second random unit randomly outputs a first or second or third or fourth response current according to a combination relationship between the resistance states of the first and second random units;

[0052] the sensing unit is used for sensing the first or second or third or fourth response current randomly output by the second random unit and generating a random number 1 or 0 according to the sensing result.

[0053] In the embodiment, the initial resistance states of the first and second random units are both high resistance states, under the excitation of one voltage pulse, the first random unit transforms from the high resistance state to the low resistance state with a first probability P1, and at the same time, the second random unit also transforms from the high resistance state to the low resistance state with a second probability P2. If the first random unit is in the low resistance state and the second random unit is in the low resistance state, a first current is output; if the first random unit is in the high resistance state and the second random unit is in the low resistance state, a second current is output; if the first random unit is in the low resistance state and the second random unit is in the high resistance state, a third current is output; if the first random unit is in the high resistance state and the second random unit is in the high resistance state, a fourth current is output. Further, when the current signal sensed by the sensing unit is the first current, a random number 1 is output; when the current signal sensed by the sensing unit is the second current or the third current or the fourth current, a random number 0 is output. After one voltage pulse ends, the first random unit is reset to the high resistance state, and the second random unit automatically recovers from the low resistance state to the high resistance state, thereby entering the next random number generation period. Through the circulation of multiple periods, the sensing unit senses either the first current or the second current or the third current or the fourth current, thereby cyclically outputting the random number 1 or 0, and finally generating a random bit stream including the random number 1 or 0.

[0054] The embodiment utilizes the randomness of the resistance state changes of the first and second random units under pulse excitation to randomly generate a random bit stream, which can be used as a new random bit source. Compared with a traditional CMOS circuit, the random bit stream generation cost is greatly reduced.

[0055] In another embodiment, the first random unit adopts a non-volatile memory.

[0056] In the embodiment, the non-volatile memory will randomly change from the high resistance state to the low resistance state under the action of the voltage pulse or the current pulse. Unlike the volatile switch, the non-volatile memory will not automatically restore to the high resistance state from the low resistance state after the voltage pulse disappears, and needs to be reset to restore to the high resistance state. The embodiment utilizes the characteristic that the resistance state of the non-volatile memory will change under the voltage pulse excitation, thereby taking the non-volatile memory as one of the elements for generating random numbers.

[0057] In addition, the non-volatile memory includes, but is not limited to, a magnetic random access memory (MRAM), a resistive random access memory (RRAM), a phase change random access memory (PCM), a ferroelectric random access memory (FeRAM), and the like, and the magnetic memory is preferably used in the embodiment. The magnetic memory has a typical sandwich structure, which includes a free layer, a pinned layer, and a tunneling layer between the free layer and the pinned layer. The free layer and the pinned layer are composed of ferromagnetic materials, including but not limited to NiFe, CoFe, CoFeB, and the like. The tunneling layer is composed of non-magnetic insulating materials, including but not limited to MgO, Al2O3, Al2MgO4, ZnO, HfO2, TaO2, and the like. In the embodiment, the low resistance state of the magnetic memory is 3kΩ, the high resistance state is 6kΩ, and the device diameter is 60nm.

[0058] In another embodiment, the second random unit uses a volatile switch.

[0059] In the embodiment, the volatile switch will randomly change from the high resistance state to the low resistance state under the action of the voltage pulse or the current pulse, and will automatically restore to the high resistance state from the low resistance state after the voltage pulse disappears. The embodiment also utilizes the characteristic that the resistance state of the volatile switch will change under the voltage pulse excitation, and generates different random numbers by cooperating with the non-volatile memory.

[0060] In addition, the volatile switch includes, but is not limited to, a bidirectional threshold switch (OTS) switch, a metal-insulator phase change (MIT) switch, a mixed ionic-electronic conductor (MIEC) switch, a field-assisted super-linear threshold switching (FAST) switch, a Schottky diode switch, a tunneling barrier switch, a metal wire threshold switch (TS) switch, and the like, and the bidirectional threshold switch is preferably used in the embodiment. The bidirectional threshold switch is composed of chalcogenide materials, including one or more of sulfur group elements such as Se and Te, and one or more of elements such as C, B, N, Ge, Sn, Sb, As, Al, Zn, Mg, Si, and the like. In the embodiment, the low resistance state of the bidirectional threshold switch is 1kΩ, the high resistance state is 100kΩ, and the device diameter is 60nm.

[0061] It is noted that the voltage pulse (or current pulse) amplitude required for the non-volatile memory resistance state change is higher than the voltage pulse (or current pulse) amplitude required for the volatile switch resistance state change. It is understood that the various types, materials and structures of the non-volatile memory and the volatile switch described above are known in the art, and the present application is not limited to the above-described embodiments, but covers various modifications thereof.

[0062] In another embodiment, as shown in FIG. 1C, the first random unit and the second random unit are connected in series. Figure 1

[0063] A conventional random computing circuit is usually composed of a random number generator and a logic operation unit. The random number generator has problems of circuit complexity, large area and high energy consumption. The separate logic operation unit (such as an AND gate required for multiplication operation) also introduces new area and energy consumption. New memory devices such as MRAM, RRAM and PCRAM have outstanding characteristics of small area, high speed and low power consumption based on new mechanisms, new materials and new structures, and are considered as strong candidate devices for the next generation of memory. The above new memory devices are usually prepared in a cross array due to their unique two-terminal structure, which introduces the problem of sneak current and causes read / write errors. To solve this problem, a volatile switch with good nonlinearity is usually used in series with the cross array to suppress the sneak current. Therefore, the series combination of the non-volatile memory and the volatile switch has become a common form of new memory. On the other hand, since the resistance change processes of the non-volatile memory and the volatile switch both have natural random characteristics, the series combination thereof can be used to realize the function of random computing inside the memory array, without the need for an additional random number generator or logic operation unit, which can reduce the circuit design cost and chip area.

[0064] In another embodiment, the excitation of the excitation unit is voltage excitation or current excitation.

[0065] ​In the embodiment, the excitation unit applies an excitation signal to the first random unit and the second random unit, which can be a voltage excitation signal or a current excitation signal. The excitation unit can change the amplitude and pulse width of the excitation signal, and change the first probability of the first random unit from the high resistance state to the low resistance state and the second probability of the second random unit from the high resistance state to the low resistance state by adjusting the amplitude and pulse width of the excitation signal. In the embodiment, the first random unit preferably uses voltage excitation as the excitation signal, the pulse width is 10 ns, and the pulse amplitude is 2 V. Under the action of the voltage excitation, the first probability of the first random unit from the high resistance state to the low resistance state is 50%, the first probability of the first random unit from the high resistance state to the low resistance state is increased by increasing the voltage amplitude, and when the voltage amplitude is increased to 2.3 V, the first probability is increased to 100%; the first probability of the first random unit from the high resistance state to the low resistance state is reduced by reducing the voltage amplitude, and when the voltage amplitude is reduced to 1.7 V, the first probability is reduced to 0. The second random unit preferably uses voltage excitation as the excitation signal, the pulse width is 10 ns, and the pulse amplitude is 1.2 V. Under the action of the voltage excitation, the second probability of the second random unit from the high resistance state to the low resistance state is 50%, the second probability of the second random unit from the high resistance state to the low resistance state is increased by increasing the voltage amplitude, and when the voltage amplitude is increased to 1.5 V, the second probability is increased to 100%; the second probability of the second random unit from the high resistance state to the low resistance state is reduced by reducing the voltage amplitude, and when the voltage amplitude is reduced to 1 V, the first probability is reduced to 0. It should be understood that increasing the pulse width can also increase the first probability of the first random unit from the high resistance state to the low resistance state and the second probability of the second random unit from the high resistance state to the low resistance state. It should be understood that for different types and different process parameters of the non-volatile memory and the volatile gate, the probabilities of the high resistance state to the low resistance state under the action of the above excitation voltage will be different.

[0066] In the embodiment, the applied voltage excitation has a pulse width in the range of 100 ps to 10 ms and a pulse amplitude in the range of 1 mV to 10 V, and the first random unit and the second random unit can realize resistance transition in the voltage range. The applied current excitation has a pulse width in the range of 100 ps to 10 ms and a pulse amplitude in the range of 1 nA to 10 mA, and the first random unit and the second random unit can realize resistance transition in the current range. It should be understood that the range of the working voltage and the working current of the non-volatile memory and the volatile gate described above is known in the art, and the present application is not limited to the above-described voltage range and current range.

[0067] In addition, it should be noted that the waveform of the voltage excitation or the current excitation includes, but is not limited to, any one of a square wave, a sine wave, a triangular wave, a trapezoidal wave, a truncated sine wave, a ladder wave, a sawtooth wave, and a hybrid wave.

[0068] In another embodiment, the sensing unit includes a current comparator and a sampling circuit.

[0069] In this embodiment, the sensing unit is used to sense the first or second or third or fourth response current, and compare the sensed response current with a reference current set in the comparator. If the response current is greater than the reference current, the comparator outputs a high level V out , at this time, the first current is sensed; if the response current is less than the reference current, the comparator outputs a low level V out , at this time, any one of the second response current, the third response current, and the fourth response current is sensed. Through the sampling circuit, a sampling clock signal V sample of a specific frequency is input, and the V OUT value in a specific time period is selected. If the V OUT value is high, a random number "1" is generated; if the V OUT value is low, a random number "0" is generated.

[0070] In another embodiment, the present disclosure also provides a random calculation method of a random number generator, including the following steps:

[0071] S100: The excitation unit excites the first random unit to transition from a high resistance state to a low resistance state with a first probability;

[0072] S200: The excitation unit excites the second random unit to transition from a high resistance state to a low resistance state with a second probability;

[0073] S300: Adjust the pulse amplitude or pulse width of the excitation unit to control the first probability and the second probability to realize random calculation.

[0074] In this embodiment, the first probability and the second probability are controlled to realize logical operations such as bitwise AND and bitwise XOR, and on this basis, numerical calculations such as multiplication operations and complex function operations are realized in a random calculation manner.

[0075] In another embodiment, as shown in Figure 2 , the present disclosure also provides an application method of a random number generator in random calculation, including the following steps:

[0076] S1000: Connect the first random unit and the second random unit in series, and under the excitation of the excitation unit, initialize the first random unit to a high resistance state;

[0077] S2000: Under the excitation of the excitation unit, the first random unit changes from the high resistance state to the low resistance state with a first probability, which is denoted as P1;

[0078] S3000: Under the excitation of the excitation unit, the second random unit changes from the high-resistance state to the low-resistance state with a second probability, which is denoted as P2;

[0079] In the above three steps, the voltage pulse waveform is as follows: Figure 3 As shown, it includes reset voltage, load voltage, and read voltage. The reset voltage amplitude is slightly higher than the voltage amplitude V during the memory's transition from a low-resistance state to a high-resistance state. low-＞high The input voltage amplitude is slightly lower than the transition voltage amplitude V of the memory from a high-resistance state to a low-resistance state. high-＞low At this point, the non-volatile memory will randomly transition from a high-resistance state to a low-resistance state; the read voltage will cause the volatile selector to randomly transition from a high-resistance state to a low-resistance state, and since the read voltage amplitude is low, it will not change the resistance state of the non-volatile memory. Applying a reset voltage initializes the first random cell to a high-resistance state, and applying a latch voltage causes the first random cell to randomly transition from a high-resistance state to a low-resistance state, with a transition probability of P1; applying a read voltage causes the second random cell to randomly transition from a high-resistance state to a low-resistance state, with a transition probability of P2.

[0080] S4000: Based on the changes in the resistance state of the first and second random units, it will generate different current responses. For example... Figure 4 As shown, if the first random unit is in a low-resistance state and the second random unit is in a low-resistance state, a first response current is output; if the first random unit is in a high-resistance state and the second random unit is in a low-resistance state, a second response current is output; if the first random unit is in a low-resistance state and the second random unit is in a high-resistance state, a third response current is output; if the first random unit is in a high-resistance state and the second random unit is in a high-resistance state, a fourth response current is output.

[0081] The output probability of the first current is P1*P2;

[0082] S5000: The sensing unit senses the first, second, third, or fourth response current and compares it with the reference current. The reference current is set to be between the first and second currents. If the response current is greater than the reference current, the first current is sensed, and a random number 1 is generated. If the response current is less than the reference current, the second, third, or fourth current is sensed, and a random number 0 is generated.

[0083] In this step, the first response current I1, the second response current I2, the third response current I3, or the fourth response current I4 obtained in step S4000 is compared with the reference current I built into the sensing unit. refComparison is made, as shown in Figure 5 and Figure 6 In the reset voltage phase, I1, I2, I3 and I4 are all less than I ref , the comparator output is low V out , and no random number is generated in this phase; in the set voltage phase, I1, I2, I3 and I4 are all greater than I ref , the comparator output is high V out , and no random number is generated in this phase; in the read voltage phase, when the non-volatile storage and the volatile gate are both in a low resistance state, the first current I1 is output, and I1 is greater than I ref , the comparator output is high V out ; when any one of the volatile gate and the non-volatile storage is in a high resistance state, the second current I2 or the third current I3 or the fourth current I4 is output, I2, I3 and I4 are all less than I ref , the comparator output is low V out .

[0084] The sampling clock V sample and the output level V out are input into the sampling circuit for sampling, as shown in Figure 5 and Figure 6 , the value of V out in the read voltage phase is selected, if V out is higher, a random number "1" is generated; if V out is lower, a random number "0" is generated.

[0085] S6000: Steps S1000-S5000 are repeated N times to generate an N-bit random bit stream, wherein the probability of occurrence of the digital bit "1" is P1*P2, that is, the multiplication operation of the completion probability P1 and the probability P2 is completed.

[0086] In random calculation, the accuracy of calculation is determined by the length of the random bit stream, and the higher the length of the random bit stream, the higher the accuracy. Based on the CMOS circuit, the length of the generated random bit stream is limited, for example, 8-bit linear feedback shift register (LFSR) is required to generate an 8-bit random bit stream, and 16-bit linear feedback shift register (LFSR) is required to generate a 16-bit random bit stream. The present disclosure utilizes the randomness of the non-volatile storage and the volatile gate in the resistance change process as a random bit source, and the length of the generated random bit stream can be unlimited. Figures 7(a) to 7(d)The simulation result of multiplication operation by the random number generator for the present disclosure is shown. The memory performs resistance transition with a probability of 0.5, the volatile gate performs resistance transition with a probability of 0.5, the arithmetic result value of multiplication operation is 0.25, the random number generator is used to multiply the two probabilities, and 8, 16, 32, and 64-bit random bit streams are generated, respectively. The distribution of the values obtained by multiplication operation is counted for 100 times, and compared with the arithmetic result value. In which, Fig. 7(a) is the distribution of the values represented by 8-bit bit stream, Fig. 7(b) is the distribution of the values represented by 16-bit bit stream, Fig. 7(c) is the distribution of the values represented by 32-bit bit stream, and Fig. 7(d) is the distribution of the values represented by 64-bit bit stream. From the result, we can see that the results of random calculation are distributed near the arithmetic result value 0.25, and with the increase of the length of random bit stream, the values obtained by random calculation are more and more concentrated near the arithmetic result.

[0087] It should be understood that the random number generator described in the present disclosure is not limited to multiplication operation. By designing and combining multiple random units, other operation forms in random calculation can be realized, including addition operation, and even complex function operation.

[0088] Table 1 shows the circuit area required for multiplication operation using 8bit-LFSR and the circuit area of the random number generator proposed in the present example, as shown below:

[0089] Table 1

[0090] Device Circuit area (μm 2 )]]> 8 bit-LSFR 12.5 The present example random number generator 0.0036

[0091] The linear feedback shift register (LFSR) is composed of multiple registers and multiple XOR gates, and the circuit area of LFSR is large and the cost is high. The random number generator proposed in the present disclosure has a circuit area depending on the device size of the volatile gate and the non-volatile memory, and the device size of the volatile gate and the non-volatile memory is nanometer level, which greatly reduces the circuit area and greatly reduces the cost of random bit stream generation.

[0092] Although the present application is described above with reference to exemplary embodiments, the scope of the present application is not limited to the above-described embodiments. It is obvious to those skilled in the art that various changes and modifications can be made in form and details without departing from the scope and spirit of the present application. The scope of the present application is defined only by the appended claims and their equivalents.

Claims

1. A random number generator for random calculation, comprising: The system comprises an excitation unit, a first random unit, a second random unit, and a sensing unit, wherein... Under the excitation of the excitation unit, the first random unit changes from a high-resistance state to a low-resistance state with a first probability; Under the excitation of the excitation unit, the second random unit transitions from a high-resistance state to a low-resistance state with a second probability; The second random unit randomly outputs a first, second, third, or fourth response current based on the combination relationship between the resistance states of the first and second random units. The sensing unit is used to sense the first, second, third, or fourth response current randomly output by the second random unit, and generate a random number 1 or 0 based on the sensing result; The first random unit employs a non-volatile memory, including any one of magnetic random access memory, resistive random access memory, phase-change random access memory, and ferroelectric random access memory. The second random unit employs a volatile selector, including any one of the following: a bidirectional threshold switch selector, a metal-insulator phase transition selector, a hybrid ion-electron conductor selector, a field-assisted superlinear threshold conversion selector, a Schottky diode selector, a tunneling barrier selector, and a wire threshold switch selector; The first random unit and the second random unit are connected in series.

2. The random number generator according to claim 1, wherein, The excitation unit is excited by voltage or current.

3. The random number generator according to claim 2, wherein, By adjusting the pulse amplitude or pulse width of the voltage excitation or the current excitation, the first probability of the first random unit transitioning from a high-resistivity state to a low-resistivity state can be controlled. By adjusting the pulse amplitude or pulse width of the voltage excitation or the current excitation, the second probability of the second random unit transitioning from a high-resistivity state to a low-resistivity state can be controlled.

4. The random number generator according to claim 3, wherein, The voltage excitation pulse width is 100ps to 10ms, and the pulse amplitude is 1mV to 10V; The pulse width of the current excitation is 100ps to 10ms, and the pulse amplitude is 1nA to 10mA.

5. The random number generator according to claim 3 or 4, wherein, The waveform of the voltage excitation or current excitation includes any one of the following: square wave, sine wave, triangular wave, trapezoidal wave, truncated sine wave, stepped wave, sawtooth wave, and mixed waveform.

6. The random number generator according to claim 1, wherein, The sensing unit includes a current comparator and a sampling circuit.

7. A random number generator method as described in claim 1, comprising the following steps: S100: The excitation unit excites the first random unit to change from a high-resistance state to a low-resistance state with a first probability; S200: The excitation unit excites the second random unit to change from a high-resistance state to a low-resistance state with a second probability; S300: Adjust the pulse amplitude or pulse width of the excitation unit to control the first probability and the second probability to achieve random calculation.

8. A method for applying the random number generator as described in claim 1 in random computation, comprising the following steps: S1000: Connect the first random unit and the second random unit in series. Under the excitation of the excitation unit, initialize the first random unit to a high-resistance state. S2000: Under the excitation of the excitation unit, the first random unit changes from the high resistance state to the low resistance state with a first probability, which is denoted as P1; S3000: Under the excitation of the excitation unit, the second random unit changes from the high-resistance state to the low-resistance state with a second probability, which is denoted as P2; S4000: If both the first random unit and the second random unit are in a low-resistance state, the second random unit outputs a first current; if both are in a low-resistance state, the second random unit outputs a second current; if both are in a high-resistance state, the second random unit outputs a third current; if both are in a high-resistance state, the second random unit outputs a fourth current. The output probability of the first current is P1*P2; S5000: The sensing unit senses the first, second, third, or fourth response current and compares it with the reference current. The reference current is set to be between the first and second currents. If the response current is greater than the reference current, the first current is sensed, and a random number 1 is generated. If the response current is less than the reference current, the second, third, or fourth current is sensed, and a random number 0 is generated. S6000: Repeat steps S1000-S5000 N times to generate an N-bit random bit stream, where the probability of the digit "1" appearing is P1*P2, that is, the multiplication operation of probability P1 and probability P2 is completed.

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