A high-performance, low-power eSIM card chip system

Abstract

The present invention discloses a high-performance, low-power eSIM card chip system, including a CPU, an MMU memory management module, an eflash module, an ILM_RAM module, a DLM_RAM module, a PMU power consumption control module, a CLK clock control module, an AHB_DMA module, a UCAA operation module, a HASH operation module, a DMA direct access module, an SM1 operation module, a DES operation module, an SM4 operation module, and a configurable vector interrupt controller. The advantages are: compared with other eSIM card chips on the market, the system has higher Java card execution efficiency and lower power consumption control at the same CPU frequency, and can better serve as a carrier for payment application communication of mobile devices such as mobile phones and POS machines.

Description

Technical Field

[0001] The present invention relates to the technical field of eSIM card chips, and in particular to a high-performance and low-power eSIM card chip system. Background Art

[0002] The eSIM card is a SIM card with two interface functions, ISO7816 and SWP. The eSIM card chips on the market are mainly for mobile payment applications and are used in mobile devices such as mobile phones. The eSIM card chips widely used in the current market use a 32-bit ARM series RISC processor in its chip design, with 40KB SRAM and 1MB FLASH for data storage. eSIM card chips mostly use AHB and APB bus structures. In today's market, there are more and more eSIM card applications, and more and more scenarios use the functions of the encryption and decryption modules in the chip. Therefore, for the battery standby time of mobile devices such as mobile phones, eSIM card chips with both high performance and low power consumption are the trend of the future mobile phone market.

[0003] There are two mainstream eSIM card chips on the market:

[0004] 1. The bus structure used by the second type of eSIM card chip is: the AHB bus is connected to peripheral modules with frequent system interactions, large data throughput, and high performance requirements, including memory system, system control module, DES, AES, SM1, SM3, SM4, PKE, CRC, etc. The memory security management mechanism can provide a high level of security protection for the algorithm. The target algorithm is implemented by calling the software library. The APB bus of this chip is connected to modules with fewer system interactions, small data volume, and low performance requirements, including 7816, GPIO, SWP, SPI, RNG, Timer, WDT, etc.

[0005] The main features of the on-chip NVM (specifically Flash) interface of this eSIM card chip are: page size is 512B, supporting page / block erase, page write, page write verification, page erase, page erase verification, and BUF clear operations. NVM write operations are based on pages as the smallest unit, so before executing various NVM page write commands, the software must ensure that the entire page of data is written. For addresses that have never been written in the page, all Fs can be written, otherwise the validity of the data read from the unwritten addresses cannot be guaranteed.

[0006] Power consumption management of this eSIM card chip: After executing the WFE instruction to enter the Standby state, all interrupt signals can wake up the chip. Standby mode is a low-power mode actively entered by the system. The system can enter standby mode only when the 7816 interface and the SWP interface are not in working state. During the process of the chip entering standby, the activity of any interface will directly wake up the chip to exit the standby state. In this chip, its ISO7816 interface can enter low-power mode only when the card reader stops the external clock. Its SWP interface is in the SUSPENDED state when the C6 pin is in the SUSPENDED state. When the UICC receives the response information of the SHDLC layer to the UICC request that it no longer communicates, and the SWP interface is in the SUSPENDED state, the SWP interface can enter low-power mode.

[0007] The CPU Hold mode of this chip includes PKE low power mode and FLASH operation low power mode. The PKE low power mode is as follows: In order to prevent excessive system power consumption during PKE operation, the low power mode can be selected by setting the corresponding parameters of the power control register. When the PKE low power mode is selected, the CPU clock will stop after the CPU starts the coprocessor operation to reduce system power consumption. After the coprocessor operation is completed, the CPU clock will be automatically restored to exit the coprocessor low power mode. The FLASH operation low power mode is as follows: In order to reduce system power consumption during FLASH Erase and Program operations, the FLASH operation low power mode can be selected by setting the FLASHLPMode parameter of the power control register. When FLASHLPMode=1, the CPU clock will stop after the CPU starts FLASH Erase or Program to reduce system power consumption. After Erase / Program is completed, the CPU automatically wakes up the clock to exit the FLASH operation low power mode.

[0008] From the CPU Hold mode operation flow of this chip, we can see that for PKE, the high-power operation of FLASH only stops the CPU clock to reduce system power consumption, which is equivalent to working in a channeling manner.

[0009] The LLC layer ACT and SHDLC frame parsing of this chip is completely completed by the upper layer software, and SWP only completes the MAC layer and LLC layer CLT frame protocol parsing at the hardware layer. Therefore, its function is not powerful enough on the SWP interface, because the software needs to do a lot of work such as packet assembly and unpacking and control communication according to the protocol, so its execution efficiency on the SWP interface is very low.

[0010] 2. The bus structure used by the second type of eSIM card chip is: only common modules such as NVM memory, SRAM, and CPU are mounted on its AHB bus; its hardware encryption coprocessor and security encryption module are mounted on the APB bus. Since the access performance of the APB bus is lower than that of the AHB bus, it takes multiple clock cycles to clear the interrupt of the APB peripheral interrupt, so its performance is not high enough and the protection provided to the algorithm is not high enough. The SWP interface function of its chip supporting the ETSI TS 102613 specification is not powerful enough. It provides DMA function inside the SWP hardware module to move data, but requires the user's own program to parse the data packet and implement the SHDLC protocol from the software layer. Therefore, the communication management function of the chip's SWP interface will consume a lot of system resources, so the function on the SWP interface is not powerful enough.

[0011] The chip uses DMA function inside the SWP and 7816 modules to send and receive data on the interface. However, there is no DMA IP controller mounted on the AHB bus.

[0012] The low power consumption management of the chip includes the control of interface sleep and sleep wake-up. When the system enters deep sleep, all interfaces must be in sleep state.

[0013] For high power consumption operations such as NVM erase and PKE algorithm, the CPU of this eSIM chip should be in a light sleep state. When the operation is completed, the corresponding event will wake up the CPU. Then, the CPU will directly execute the command after WFE without jumping to ISR. The process of waking up the light sleep CPU by an event can be found in Figure 1 .

[0014] The total RAM capacity of this eSIM chip is 40KB, which is accessible to the CPU, 32KB of general RAM, and 8KB of specific buffers for each communication interface. The NVM page size is 512B, and each page includes 2 half pages of 256B.

[0015] The page erase operation of this eSIM chip is to erase all 512B pages at one time; the write operation of this eSIM chip uses the specified double word programming within half a page, that is, by writing the data to be written to the specified position in the buffer, marking the address and data to be written. The written data must be a number of double words (N*8 bytes). After the programming action is started, the data of these marked double words will be programmed at one time. Post-programming status: the read value is the written value. NVM programming time: TFP = 100μs + 53μs * N, where N represents the number of double word data. The time required for programming the NVM page 512B of this chip is 2*(100μs + 53μs * 32) = 3592μs. The specific process of the write operation is: set the chip NVM control register - write the data to be programmed to the NVM target address, the starting address must be a double-word aligned address, and the number of writes must be an integer multiple of double words (8 bytes) - set the chip NVM control register - write 0xFFFFFFFF to any address of the NVM target page - the user program sets the CPU to sleep (WFE / WFI) - query whether SFR NVMSTS is ended and whether NVMSTS1 has an error - clear SFR NVMSTS and SFRNVMSTS1.

[0016] Javacard applications are called Applets, which must comply with the Java Card specification. The basic structure of a Java Card Applet is:

[0017] 1. install() method: When the Applet is downloaded to the JAVA card, the install() method will be started to install the Applet and pass in the parameters required for the Applet installation.

[0018] 2. register() method: After the Applet is installed, call the register() method to register the Applet with JCRE.

[0019] 3. select() method: Before running an Applet, JCVM must first call the select() method to select the Applet.

[0020] 4. Process() method: This method is the core method of Applet. After the terminal sends the command APDU to the card, COS first receives the APDU, and then passes the APDU to JCRE. JCRE sends the APDU to the process method of the currently selected Applet for processing. The process method is generally designed as a branch selection structure. Different processing methods are executed according to different command APDUs, and the processing results are sent back to JCRE until they are returned to the terminal. When we develop and design an Applet, the main work is to write the process method according to the requirements.

[0021] The main responsibilities of the GlobalPlatform environment (hereinafter referred to as OPEN) are to provide API, command distribution, application selection, logical channel management (MANAGE CHANNEL command is only processed by OPEN and will not be distributed to applications) and card content management for applications.

[0022] OPEN performs the loading of AP code and related card content management.

[0023] OPEN is also responsible for the installation of applications loaded onto the card. OPEN is responsible for implementing the security principles defined for application loading and installation. These principles include the verification of the application code and the authorization for application loading and / or installation provided by the card issuer.

[0024] Another important responsibility of OPEN is the distribution of APDU commands and the selection of applications. When OPEN receives a SELECT command, it sets the application specified in the SELECT command as the selected application, and subsequent application commands should be distributed to this selected application.

[0025] Except for the MANAGE CHANNEL command and the SELECT command, all other commands are directly distributed to the currently selected application on the basic logical channel.

[0026] Figure 2The system framework diagram of the existing Java Card shows that the bottom layer of Java Card is Hardware, i.e., the chip. The operating system OS (Operating System) on the hardware is usually a customized micro-operating system (RTOS), and the Java Card runtime environment JCRE (Java Card Runtime Environment) on the operating system includes the Java Card virtual machine JCVM (Java Card Virtual Machine), which can parse and execute Java Card bytecodes, so that Java Card applications can run normally on the card. The Global Platform runtime environment OPEN provides applications with functions such as command distribution, application selection, logical channel management, and card content management. Applications can use these services by calling the GP API located on OPEN. The Issuer Security Domain ISD (Issuer Security Domain) can manage card content, card life cycle, and application life cycle. It is the basis of other security domains and is the representative of the card manager in the card; while the Supplementary Security Domain SSD (Supplementary Security Domain) can provide security domains for application providers and is the representative of application providers in the card. JCAPI (Java Card application programming interface) is the application programming interface of Java Card. Applications App1 and App2 running on Java Card can use the services provided by JCRE through JC API.

[0027] Currently, eSIM cards are basically implemented based on the Java card platform. In the Java platform, there are multiple Flash writes to back up data and other Flash write requirements, and each APDU instruction guarantees the atomicity of writing and erasing Flash through the transaction mechanism. Therefore, it is very important to improve the parsing speed of APDU instructions and the writing speed of Flash.

[0028] From a market perspective, under the premise that the chip hardware performance of the eSIM card manufacturer is fixed, on the one hand, it is possible to optimize the writing method of the Java Applet source code, use a more scientific algorithm design method, optimize the code execution process, make it more regular, and plan the execution of time-consuming operations, etc., which can directly improve the execution efficiency of the application. However, because the developer of the Applet in the Java card environment is uncontrollable, it seems infeasible to propose optimization requirements from the perspective of Applet writing. This design invention improves performance from the perspective of Java virtual machine execution and DMA parallelism. A general Java virtual machine needs to load a method form and load the corresponding Java virtual machine machine code according to the offset position to complete the method call. The contents of the data structure in the form format of each component of the Java card are stored in the Flash storage unit, and the reading and parsing work requires multiple Flash read and write operations.

[0029] When the target application is selected for execution by the Java virtual machine, the Java virtual machine will find the Flash storage location corresponding to the Java virtual machine machine code of the application, and load it into the Java virtual machine for parsing and execution. For stack operations, since the cached data is operated in the chip's RAM, and the RAM read and write speed is much faster than the Flash storage domain, the execution speed of stack operations will be very fast. However, due to the limitations of the existing Java card chip hardware level and chip cost considerations, it is impossible to place all data in RAM for operation, so most of the data can only be stored in the Flash memory, and the operating speed of the Flash memory is much lower than that of the RAM storage. Therefore, under certain hardware conditions, the key factor affecting the execution efficiency of the Java API is the slow read and write speed of the Flash memory.

[0030] Judging from the mainstream eSIM card chip data on the market, the CPU is in a stopped state when writing Flash, and the WFE and FEI instructions will turn off the CPU clock. That is, for the program in the NVM, after the erase and write operations are executed, the subsequent instructions will be suspended until the erase and programming operations are completed. The program can continue to be executed, which is equivalent to a run-through operation, which will affect the execution performance of the Java card. These eSIM card chips do not have a DMA controller mounted on the AHB bus. Their functions on the SWP interface are not efficient enough, and the program needs to manage and control the SHDLC protocol by itself, including assembling data packets, parsing data packets, communication timing, etc., which is bound to increase the power consumption of the chip. In addition, these chips can only enter low-power mode when the communication is completed. From the perspective of Java card technology, its power consumption control is based on application transactions, so the CPU working time will be longer, which will increase the power consumption of the chip. Summary of the invention

[0031] The purpose of the present invention is to provide a high-performance and low-power eSIM card chip system, so as to solve the above-mentioned problems existing in the prior art.

[0032] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0033] A high-performance, low-power eSIM card chip system, including a CPU, an MMU memory management module, an eflash module, an ILM_RAM module, a DLM_RAM module, a PMU power consumption control module, a CLK clock control module, an AHB_DMA module, a UCAA operation module, a HASH operation module, a DMA direct access module, an SM1 operation module, a DES operation module, an SM4 operation module and a configurable vector interrupt controller;

[0034] The CPU is connected to the MMU memory management module via the I_AHB bus, and the MMU memory management module is connected to the eflash module and the ILM_RAM module via the FLASH_Ctrl interface and the RAM_CTRL interface respectively; the CPU is connected to the AHB_DMA module, the UCAA module, the HASH module, the DMA direct access module, the SM1 operation module, the DES operation module and the SM4 operation module via the SYS_AHB bus; the AHB_DMA module is connected to the eFLASH module via the FLASH_CTRL interface, and the AHB_DMA module is connected to the ILM_RAM module and the DLM_RAM module via the RAM_CTRL interface;

[0035] The SYS_AHB bus is connected to the AHB2APB control line, and the AHB2APB control line is connected with a watchdog, a counter, a cyclic redundancy check module, a pure digital true random number generator, a programmable IO module, an IIC interface module, an SPI interface module, a UART interface module, a SWP interface module and a 7816 interface module;

[0036] The MMU memory management module is connected to the AHB2SFR control line via the SFR bus, and the CLK clock control module and the PMU power consumption control module are both connected to the AHB2SFR control line; the CLK clock management module is connected to the OSC_HF clock and the OSC_LF clock;

[0037] The CPU is connected to a configurable vector interrupt controller via a tightly coupled IP that supports single CPU clock cycle access;

[0038] The RAM_CTRL interface is a control interface of the SRAM, used to control the read and write operations of the SRAM;

[0039] The FLASH_CTRL interface is a FLASH control interface, used to control the read and write operations of FLASH;

[0040] The OSC_HF clock is the source clock or provides the normal working clock for the system after frequency division;

[0041] The OSC_LF clock is a wake-up clock for waking up the CPU.

[0042] Preferably, for the application selected by OPEN, the virtual machine performs the Remap operation of the MMU memory management module on the process method of the selected Applet application, that is, by means of the DMA direct access module, the corresponding execution code is copied from the Flash address corresponding to the process method of the application to the space of the ILM_RAM module, so that the corresponding code is executed in the RAM memory, thereby improving the execution efficiency;

[0043] The specific process of the Remap operation is as follows:

[0044] Move the program at address n1KB~n2KB in Flash to the space n3KB~n4KB in ILM_RAM module;

[0045] Remap source address register, remap destination address register, remap length register;

[0046] Remap the enable register to start the acceleration mechanism. After the enable register is remapped, when accessing the n1KB~n2KB address space of the Flash, the n3KB~n4KB space of the SRAM is actually accessed.

[0047] After the register remapping configuration is completed, the DMA direct access module starts the migration work, and the CPU runs the Java virtual machine code at the same time.

[0048] Preferably, for each new application selected by the Java virtual machine, as much content as possible in the Flash is moved to the memory for execution according to the source address and the number of bytes of the Process form, thereby improving the execution performance of the Applet.

[0049] Preferably, when the content of a Page needs to be read from the Flash, the page read function of the DMA direct access module is used; when the content of a Page in the Flash needs to be modified, the page erase and write function of the DMA direct access module is used.

[0050] Preferably, the Java main loop in the system is driven by the interrupt on the interface to drive the firmware, and the firmware enters the WAIT mode after parsing the APDU instruction. When the system sends a response data packet to the host to complete the interrupt generation, the CPU is awakened from the WAIT mode and then enters a deeper low-power Stop mode;

[0051] If the Flash needs to be erased, the DMA direct access module is used to erase the Flash page by page, and the program runs in the ILM_RAM module; in this case, the CPU is awakened twice from the WAIT mode, once by the DMA Burst PageWrite completion interrupt, and the other by the interface transmission completion interrupt; and then enters the STOP mode;

[0052] The system provides the Burst write function, which limits the maximum length of each Burst write to 64 words.

[0053] Preferably, the system comprises,

[0054] Instruction low power mode: The CPU enters a low power mode when executing instructions, which is divided into STOP mode and WAIT mode;

[0055] The STOP mode is specifically: set the STOP instruction of the CPU. In the STOP mode, except for some circuits in the communication interface that are directly driven by the external clock and the internal OSCLF, the clocks of other parts of the system are all stopped, and the analog module enters the STOP state to reduce the power consumption of the system; after the communication interface receives data / commands or receives a reset signal, it exits the STOP mode and the system clock returns to its original value;

[0056] The specific details of the WAIT mode are: setting the CPU's WAIT instruction, the CPU enters the WAIT state, at which time the CPU clock stops to reduce power consumption. When an interrupt occurs, the CPU exits the WAIT state;

[0057] UCAA low power mode; when Applet uses the UCAA algorithm, it completes the algorithm by calling the UCAA APIs function provided by the system, sets registers in the UCAA APIs function, and selects the UCAA low power mode; in the UCAA low power mode, after the CPU starts the UCAA operation module, the clocks of other parts of the system will stop to reduce system power consumption; after the operation is completed, the system clock will be automatically restored to exit the low power state;

[0058] In UCAA low power mode, when the RSA algorithm starts to operate, the CLK clock management module, eFlash module, DES operation module, and SM1 operation module will all stop;

[0059] NVM erase low power mode; when Applet wants to erase Flash, it can be done by calling the WriteFlash APIs function provided by the system. The WriteFlash APIs function sets the register according to the actual erase, write or move function, and selects the NVM erase low power mode; in the NVM erase low power mode, after the CPU starts Flash Erase or Program, the clocks of other parts of the system will stop to reduce system power consumption; after the Erase / Program is completed, the system clock will be automatically restored to exit the low power state;

[0060] In the NVM erase low power mode, during Flash Erase / Program, the CLK clock management module, UCAA operation module, DES operation module, and SM1 operation module will all stop.

[0061] Preferably, the workflow of the Java virtual machine of the system is:

[0062] S1. After the system is powered on, the CPU execution environment is initialized and the DMA direct access module migration function is used to copy the 7816 interface, SWP interface, ISR interface, WriteFlash API, and Java_Loop from the Flash to the ILM_RAM module to obtain the starting address that can be used for Remap in the system: 0x00A01000.

[0063] S2, system Java virtual machine initialization;

[0064] S3. According to the interface hardware detection result, register configuration is performed on the 7816 interface and the SWP interface, and the corresponding interface interrupt of the register is enabled; Sys_WaitingCnt is set, and Sys_JobCnt is set to 0; and the virtual machine main loop Java_Loop API is entered from step S4, which is an IRAM program;

[0065] S4. If Sys_WaitingCnt is not equal to 0, call the assembly instruction to make the system enter the WAIT mode, and repeat step S4 until it is awakened by an interrupt; if Sys_WaitingCnt is equal to 0, go to step S5;

[0066] S5, call the assembly instruction to make the system enter the lowest power consumption STOP mode;

[0067] S6. The system receives the APDU instruction and exits the STOP mode. If the currently activated interface is the 7816 interface, the APDU data buffer pointer is set to the data buffer of the 7816 interface; if the currently activated interface is the SWP interface, the APDU data buffer pointer is set to the data buffer of the SWP interface; Sys_JobCnt decreases by 1;

[0068] S7, the Java virtual machine checks the APDU instruction. If the current instruction is not a MANAGE CHANNE command or a SELECT command, the process proceeds to step S9; if the current instruction is a MANAGE CHANNEL command, the Java virtual machine performs corresponding processing, writes the return data to the APDU data buffer, and then proceeds to step S10; if the current instruction is a SELECT command, the process proceeds to step S8;

[0069] S8. After the current target application is selected by OPEN, the Remap operation of the MMU memory management module is performed on the process method of the application, that is, the Flash page address corresponding to the Process method form byte code of the application is copied to the space of the ILM_RAM module from the Flash address corresponding to the process method of the application, with the help of the move function of the DMA direct access module, and the form byte number RemapSize of the method is obtained and aligned to the integer K byte number. If RemapSize is greater than 12KB, RemapSize is set to 12KB, and the source address of the remapped original address register is the integer K byte address of the form Flash, and the target address of the remapped target address register is 0x00A01000. The length of the remap length register is RemapSize, and the register is enabled to perform the remapping function. At this time, with the help of the characteristics of the DMA direct access module and the CPU executing in parallel, the Remap Flash content is copied to the ILM_RAM module, with a maximum of 12KB; the Java virtual machine writes the return data to the APDU data buffer, and then enters step S10;

[0070] S9, the Java virtual machine calls the currently selected application and parses the APDU instruction. Since the bytecode corresponding to the 12KB process method operation is remapped to the ILM_RAM module, the execution efficiency of Java parsing APDU instructions can be improved; if the Applet process needs to write to Flash, the system WrtFlash API is called to write 512B of data back to Flash, and the data is written to the target Flash address with the help of DMA BurstWrite function. Sys_WaitingCnt is set to increase by 1 in WrtFlash API, and the DMA direct access module completes the interrupt. In the interrupt service program, Sys_WaitingCnt will be set to decrease by 1; write the returned data to the APDU data buffer, and then enter step S10;

[0071] S10, for the current interface, call the system sending API to send the data in the APDU data buffer to the host, set Sys_WaitingCnt to increase by 1 in the sending API, and enable the DMA direct access module to send the completion interrupt, and set Sys_WaitingCnt to decrease by 1 in the interrupt service program;

[0072] S11. If Sys_JobCnt is not equal to 0, return to step S6; otherwise, return to step S4.

[0073] Preferably, the UCAA operation module includes an RSA algorithm, an SM2 algorithm, and an ECC algorithm; and the HASH operation module includes a SHA1 algorithm, an SM3 algorithm, and a SHA256 algorithm.

[0074] Preferably, the ILM_RAM module is a 16KB single-port SRAM; and the DLM_RAM module is a 24KB single-port SRAM.

[0075] The beneficial effects of the present invention are as follows: 1. The system mounts a DMA direct access module on the AHB bus, so that the execution of the program can be parallelized to the greatest extent, thereby greatly improving the execution efficiency of the Java card, reducing the chip working time, and reducing the overall power consumption of the eSIM chip. 2. The ILM_RAM module is mounted on the SYS_AHB bus and connected to the CPU through the I_AHB bus. During use, the code that needs to be accelerated is placed in the ILM_RAM module for execution to the greatest extent, thereby greatly improving the execution efficiency of the Java card, reducing the chip working time, and reducing the overall power consumption of the eSIM chip. 3. The 7816 interface interrupt service program, SWP interface interrupt service program, DMA interrupt service program, WriteFlash API and other key function firmware codes are defined as programs that are logically on the ILM_RAM module, physically on the FLASH, and executed in the ILM_RAM module to improve the instruction processing performance of the entire chip. 4. When the host sends the APDU SELECT command, the Java Card virtual machine receives and parses it to select a different new Applet. The Java Card virtual machine further processes the selected Applet's Procees method form to obtain the FLASH page address and the byte size of the form, and performs MMURemap on the FLASH content of this section. This remapping design is dynamic, that is, when switching Applets, the MMU Remap operation will be performed for the new Applet, and the key code will be accelerated, thereby improving the performance of the Java Card virtual machine. 5. Use the DMA transfer function to write Flash pages, which realizes parallel processing of instructions and improves chip execution performance; WriteFlash API is an ILM_RAM program, and the Applet's Procees method also runs in the ILM_RAM module. Therefore, the Procees method can be run normally while programming the FLASH page. Writing Flash pages is a frequently used operation in Java Card applications, which can greatly improve the performance of Java Cards. 6. All Flash programming operations are performed through the DMA direct access module, so they can be processed in parallel with the CPU running firmware. In this chip, the minimum programming unit of FLASH is a WORD, i.e., 4 bytes. It takes 25 microseconds to write four bytes into FLASH. The programming time of Flash page 512B of this system is twice as fast as the programming time of Flash page 512B of the mainstream eSIM chip on the market. When the Java card application uses the DMA Burst read and write function designed by the present invention, the execution performance of the Java card application is higher. Since the programming time of Flash is greatly reduced, the power consumption of the entire chip can be greatly reduced.When the FLASH page is almost full, it is necessary to use the DMA Burst write function to erase the FLASH page and rewrite the data. Under such a strategy, the power consumption of the eSIM card on the FLASH will be greatly reduced. 7. The system low-power control architecture actively enters the low-power mode based on the interface receiving and sending data packets; the interface IP's transceiver buffer makes the CPU in Wait mode, and the interface automatically sends data packets to the host, thereby reducing the CPU processing time on the interface to a minimum, thereby reducing the overall power consumption of the eSIM chip. 8. The SWP interface supports the communication control of the SHDLC protocol at the hardware level. The received data packet is the data of the HCI layer, and the program does not need to spend a lot of instructions to perform SHDLC packet assembly and SHDLC communication protocol control. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 This is a flowchart of waking up a shallow sleep CPU using an existing eSIM chip event;

[0077] Figure 2 This is the existing Java Card system framework diagram;

[0078] Figure 3 is a schematic diagram of the structure of the system in an embodiment of the present invention;

[0079] Figure 4 It is a schematic diagram of the principle of the system providing the Burst write function in an embodiment of the present invention. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation methods described herein are only used to explain the present invention and are not used to limit the present invention.

[0081] like Figure 3 As shown, in this embodiment, a high-performance and low-power eSIM card chip system is provided, including a CPU, an MMU memory management module, an eflash module, an ILM_RAM module, a DLM_RAM module, a PMU power consumption control module, a CLK clock control module, an AHB_DMA module, a UCAA operation module, a HASH operation module, a DMA direct access module, an SM1 operation module, a DES operation module, an SM4 operation module and a configurable vector interrupt controller;

[0082] The CPU is connected to the MMU memory management module via the I_AHB bus, and the MMU memory management module is connected to the eflash module and the ILM_RAM module via the FLASH_Ctrl interface and the RAM_CTRL interface respectively; the CPU is connected to the AHB_DMA module, the UCAA module, the HASH module, the DMA direct access module, the SM1 operation module, the DES operation module and the SM4 operation module via the SYS_AHB bus; the AHB_DMA module is connected to the eFLASH module via the FLASH_CTRL interface, and the AHB_DMA module is connected to the ILM_RAM module and the DLM_RAM module via the RAM_CTRL interface;

[0083] The SYS_AHB bus is connected to the AHB2APB control line, and the AHB2APB control line is connected with a watchdog, a counter, a cyclic redundancy check module, a pure digital true random number generator, a programmable IO module, an IIC interface module, an SPI interface module, a UART interface module, a SWP interface module and a 7816 interface module;

[0084] The MMU memory management module is connected to the AHB2SFR control line via the SFR bus, and the CLK clock control module and the PMU power consumption control module are both connected to the AHB2SFR control line; the CLK clock management module is connected to the OSC_HF clock and the OSC_LF clock;

[0085] The CPU is connected to a configurable vector interrupt controller via a tightly coupled IP that supports single CPU clock cycle access;

[0086] The UCAA operation module includes RSA algorithm, SM2 algorithm and ECC algorithm; the specific algorithms included can be selected according to actual conditions.

[0087] The HASH operation module includes SHA1 algorithm, SM3 algorithm and SHA256 algorithm; the specific algorithms included can be selected according to actual conditions.

[0088] The ILM_RAM module is a 16KB single-port SRAM; instruction RAM, which can be used for code remapping. Starting address: 0x00A00000

[0089] The DLM_RAM module is a 24KB single-port SRAM; data RAM;

[0090] The RAM_CTRL interface is a control interface of the SRAM, used to control the read and write operations of the SRAM;

[0091] The FLASH_CTRL interface is a FLASH control interface, used to control the read and write operations of FLASH;

[0092] The CLK clock management module includes OSCHF and OSCLF;

[0093] The OSC_HF clock is the source clock or provides the normal working clock for the system after frequency division;

[0094] The OSC_LF clock is a wake-up clock for waking up the CPU.

[0095] The detailed explanation of each component module in the system is shown in Table 1.

[0096] Table 1 Brief description of each module of the system

[0097]

[0098]

[0099]

[0100] In this embodiment, the system adopts a domestically produced 32-bit RISC security CPU core with independent intellectual property rights. The chip has built-in SM1, SM4, AES, DES and other commonly used cryptographic algorithm hard cores, and has the characteristics of powerful functions, multiple interfaces and low power consumption.

[0101] The CPU implements central control, and the program storage space is in the on-chip FLASH (1MB). The system SRAM size is 16KB+24KB, and in this system 16KB is used for the Remap function. The CPU can access and control the corresponding registers through the system AHB bus, thereby scheduling each IP to complete a specific task. The system provides interrupt and DMA services to achieve fast response to IP requests and fast data transfer. The system block diagram is shown in the figure. Figure 3 shown.

[0102] The CPU uses a domestically produced 32-bit secure RISC processor, which is connected to the MMU through the I_AHB bus and to the AHB bus through the SYS-AHB control line. The CPU can execute programs in the ILM_RAM module (instruction local memory bus) through the I_AHB bus and access the DLM_RAM module (data local memory bus) through the SYS_AHB control line.

[0103] In this embodiment, for the application selected by OPEN, the virtual machine executes the Remap operation of the MMU memory management module on the process method of the selected Applet application, that is, with the help of the DMA direct access module, the corresponding execution code is copied from the Flash address corresponding to the process method of the application to the space of the ILM_RAM module, so that the corresponding code can be executed in the RAM memory, thereby improving the execution efficiency.

[0104] In this embodiment, since the read and write speed of Flash is slow, but the read speed of RAM can reach up to 40MHz, the program in Flash can be moved to the ILM_RAM module to run, so as to improve the execution speed of the program. The location and size of the program can be configured (the location can be configured arbitrarily, and the size can only be up to 16KB).

[0105] When the user wants to accelerate the program, move the program to be accelerated to the ILM_RAM module to speed up the program. The software configures the Remap length, start address and destination address, and turns on the remapping function (REMAP_EN), which can achieve program acceleration.

[0106] The specific process of the Remap operation is as follows:

[0107] Move the program at address n1KB~n2KB in Flash to the space n3KB~n4KB in ILM_RAM module;

[0108] Remap source address register, remap destination address register, remap length register;

[0109] Remap the enable register to start the acceleration mechanism. After the enable register is remapped, when accessing the n1KB~n2KB address space of the Flash, the n3KB~n4KB space of the SRAM is actually accessed.

[0110] After remapping and configuring the relevant registers, the DMA direct access module starts the transfer work, and the CPU runs the Java virtual machine code at the same time. The DMA direct access module of this system only takes 8 microseconds to move 512 bytes of data from Flash to memory, and it takes milliseconds from the host side sending the SELECT APDU instruction to the next APDU instruction being received by the chip. Therefore, when the next instruction is parsed, the Process method of the target application is executed in memory.

[0111] The DMA direct access module supports data exchange between memory and memory, and between memory and IO devices. The CPU does not need to be involved in the data transmission process, which improves the execution efficiency of the system. Its functions are: to increase the data transfer speed between instruction RAM, data RAM, peripheral RAM, and Flash; to release the CPU conveniently and improve the execution efficiency of the system; to cooperate with the remapping function to increase the speed of CPU execution instructions; to cooperate with the Flash page write operation.

[0112] In this embodiment, in actual user applications, the content in the Flash is often modified. After reading out a page (Page=512B), i.e., 64 words, and partially modifying it, the entire page is written back to the Flash. Since the minimum unit of the chip Flash programming in this design is a word (4B), the entire page write-back function required by each application can only be written back one word at a time.

[0113] In this system, a burst write function is proposed for the continuous writing method, which limits the maximum length of each burst write to 64 words. The purpose is to speed up the writing speed. The time comparison is as follows: it takes 25us to write a word at a time, and the time to write 64 words = 64*25(us) = 1600us; using burst writing, it takes 15us, and the time to write 64 words = 27+63*15+5(us) = 977us; in comparison, the writing speed of this system can be increased by nearly 40% compared with the original.

[0114] The requirements for the system to provide the Burst write function are as follows: 1. Analyzing from the actual operation of the application, before modifying the entire page, the entire page content will be read out first, and the software overhead storage will be cached. After the modification, it will be slowly written back. If hardware design is used, a full page of 512B DRAM cache is first required. 2. At the same time, in order to be compatible with the conventional word write function, a register is added to indicate whether it is a Burst write or a word write. 3. If the Burst full page write function is used, the logical address sent by the application must be the starting address of a page. 4. The hardware will also add a flag that the full page read and write is completed or interrupt the application for the next step of processing.

[0115] The principle flow structure of the system's Burst write function is as follows: Figure 4 As shown. The implementation of this function is based on the DMA direct access module. The main reason is that the DMA direct access module itself needs to have the read and write transfer function between RAM and Flash. The DMA direct access module involves the Flash operation. After the software is started, it is not necessary to query the completion status of the DMA direct access module, and then the software can perform other parallel operations at the same time.

[0116] The Burst write function uses the Word mode to program the Flash page 512B. The time required to program a single word is 25us. The time to program 64 words = 64*25(us) = 1600us, which is twice as fast as the Flash page programming time of the mainstream eSIM chip on the market. The NVM page size is 512B, and the programming time required is 2*(100μs+53μs*32=3592μs.

[0117] In this embodiment, for each new application selected by the Java virtual machine, as much content as possible in the Flash is moved to the memory for execution according to the source address and the number of bytes of the Process form, thereby improving the execution performance of the Applet.

[0118] In this system, when the page content needs to be read from the Flash, the page read function of the DMA direct access module is used; when the page content in the Flash needs to be modified, the page erase and write function of the DMA direct access module is used. Because the function of the DMA direct access module is used, it can be processed in parallel with the CPU running firmware, which can greatly improve the performance of the system. In this system, the minimum programming unit of the chip FLash is a word, that is, 4 bytes. By writing a small amount of words, relevant information can be stored, so the Flash programming power consumption of the entire eSIM card chip can be better reduced.

[0119] From the perspective of the eSIM card chips currently on the market, there is a situation where the NVM is read again during NVM erasure or programming, and subsequent instructions will be suspended. In view of this problem of the current eSIM card chips, in the design of the present invention, the program is placed in the ILM_RAM module to run, and the erase and write operations are performed. The program can continue to run, that is, the CPU fetches instructions from the ILM_RAM module and runs, while the Flash is in the erase or programming state, thereby improving the operating efficiency of the Java card.

[0120] Judging from the current existing technology of Java Card, most of them use customized micro operating system (RTOS). Under such architecture, the power consumption control of the chip is not very good. These chips can only enter low power consumption mode when the interface communication is completed. From the perspective of Java Card technology, its power consumption control is based on application transactions, so the CPU working time will be longer, which will increase the power consumption of the chip.

[0121] The system of the present invention does not use a customized micro-operating system (RTOS). The Java main loop is driven by the interrupt on the interface to drive the firmware. After the firmware parses the APDU instruction, it enters the WAIT mode. When the chip completes sending the response data packet to the host and the interrupt is generated, the CPU is awakened from the WAIT mode and then enters a deeper low-power Stop mode. If the Flash needs to be erased, because the DMA direct access module is used to erase the Flash page by page, and the program is run in the ILM_RAM module, in this case, the CPU is awakened from the WAIT mode twice, once by the DMA Burst PageWrite completion interrupt, and the other time by the interface sending completion interrupt; then enters the STOP mode. Such a system architecture design can achieve the lowest power consumption state during the instruction interaction process of the eSIM card.

[0122] Under the system architecture of this design, the 7816 interface IP of the chip can provide a 255-byte receive and send buffer. The SWP interface IP supports the SHDLC protocol from the hardware layer. The data received by the firmware is the original upper layer data packet stripped of the SHDLC protocol layer. It can provide a 128B receive and send buffer, and can receive and send up to 4 SHDLC data packets. The receive and send buffers on the 7816 interface and SWP interface designed in this system can meet the parallelism of the chip core. When the interface sends a response data packet, the CPU enters the WAIT mode, and after the transmission is completed, the CPU enters the STOP mode.

[0123] In this embodiment, in order to reduce the power consumption of the chip, the designed PMU power consumption management module well realizes the low power consumption management of the chip from the system level, and replaces the original clock with the gated clock in the circuit structure. When the UCAA and NVM modules with large erase power consumption are working, other irrelevant working modules will be turned off. In the chip Stop mode, digital modules such as the CPU, DMA direct access module, and SWP interface will be turned off, and analog modules such as the OSC_HF clock, voltage regulator, and chip sensor (the voltage regulator and chip sensor are basic functions of the system and are not drawn in the system structure diagram) will also be turned off step by step. In the chip Wait mode, the CPU clock, ISO7816, and SWP interface are turned off, and the DMA direct access module and eFLASH module can continue to work.

[0124] The PMU power consumption control module implements low-power consumption control and management of the system, including entry and exit of low-power consumption mode, low-power consumption wake-up source configuration, etc., in accordance with the internal SFR bus interface timing.

[0125] The system provides a variety of low-power control modes to meet the power consumption requirements of various occasions. The details are as follows:

[0126] 1. Instruction low power mode: The CPU executes instructions to enter low power mode, which is divided into STOP mode and WAIT mode;

[0127] The STOP mode is specifically: set the STOP instruction of the CPU. In the STOP mode, except for some circuits in the communication interface that are directly driven by the external clock and the internal OSCLF, the clocks of other parts of the system are all stopped, and the analog module enters the STOP state to reduce the power consumption of the system; after the communication interface receives data / commands or receives a reset signal, it exits the STOP mode and the system clock returns to its original value;

[0128] The specific details of the WAIT mode are: setting the CPU's WAIT instruction, the CPU enters the WAIT state, at which time the CPU clock stops to reduce power consumption. When an interrupt occurs, the CPU exits the WAIT state;

[0129] 2. UCAA low power mode: When Applet uses the UCAA algorithm, it completes the algorithm by calling the UCAA APIs function provided by the system, sets registers in the UCAA APIs function, and selects the UCAA low power mode. In the UCAA low power mode, after the CPU starts the UCAA operation module, the clocks of other parts of the system will stop to reduce system power consumption. After the operation is completed, the system clock will be automatically restored to exit the low power state.

[0130] In UCAA low power mode, when the RSA algorithm starts to operate, the CLK clock management module, eFlash module, DES operation module, and SM1 operation module will all stop;

[0131] 3. NVM erase low power mode; When Applet wants to erase Flash, it is done by calling the WriteFlash APIs function provided by the system. The WriteFlash APIs function sets the register according to the actual erase, write or move function. The target address at this time is the address in the Flash. After configuring the DMA register and remapping the enable register to complete the interrupt, this WriteFlash APIs returns immediately without waiting; Select NVM erase low power mode; In NVM erase low power mode, after the CPU starts Flash Erase or Program, the clocks of other parts of the system will stop to reduce system power consumption; After Erase / Program ends, the system clock is automatically restored and exits the low power state;

[0132] In the NVM erase low power mode, during Flash Erase / Program, the CLK clock management module, UCAA operation module, DES operation module, and SM1 operation module will all stop.

[0133] The system supports multiple wake-up methods and wake-up source software configuration. The wake-up sources are: 1. GPIO wake-up, supporting all GPIOs (GPIO0--GPIO10); 2. Timed wake-up; 3. Interface wake-up (7816 interface, SWP interface, IIC interface, SPI interface, UART interface); 4. Interrupt wake-up.

[0134] In the system of the present invention, STOP low power consumption is the state with the lowest power consumption of the chip. In the stop state, analog modules such as OSC_HF clock, voltage regulator, chip sensor, etc. are all in the stop low power consumption state, and RAM and digital circuit clocks are all turned off. The entry and exit of the STOP state adopt a step-by-step control strategy to reduce the impact of current changes on the voltage regulator. When entering the STOP process, the circuit must be shut down step by step, and when exiting the STOP process, the circuit must be opened step by step.

[0135] Compared with existing chips, this system provides more low-power control clocks, so the power consumption of the entire chip can be lower.

[0136] In this embodiment, since the system mounts a DMA controller (ie, a DMA direct access module) and an ILM_RAM module on the AHB bus, the speed of parallel data processing can be greatly improved, and the eSIM card can have the characteristics of high performance and low power consumption.

[0137] IRAM programs are stored in IRAM. Different from REMAP remapping program execution, the logical address of IRAM programs is in ILM_RAM space, and CPU can directly access and execute the programs in it. IRAM programs are directly compiled and generated by the compiler and stored in Flash. In actual chip use, a certain IRAM program stored in Flash can be moved to IRAM by the management program or user program after the chip is powered on.

[0138] In the present invention, the important key codes such as communication interface ISO7816 / SWP ISR, WriteFlash API, Java_Loop, etc. are set to have logical addresses in the ILM_RAM space and physical addresses in the segments in the Flash space by modifying the link file in the project, that is, compiling and generating IRAM programs.

[0139] The system mainly uses 7816 interface and SWP interface. It supports dynamic detection of external interface by hardware, i.e. dynamic detection of 7816 interface and SWP interface. The detection result of 7816 interface will be notified to the software in the form of 7816 reset interrupt, and the detection result of SWP interface will be notified to the software in the form of interface detection interrupt.

[0140] The entire process of the Java virtual machine of the system is divided into three stages: initial configuration, application activation, and application completion. The initial configuration stage mainly consists of software configuring the parameters of the SWP IP and detecting whether the external SWP interface is supported to decide whether to enable the SWP interface. After the initial configuration is completed, the application activation stage begins. Since each IP in the chip supports interrupts, the software can implement applications based on interface interrupts, thereby enabling parallel processing of multi-interface applications.

[0141] Initialize and set Sys_JobCnt to 0. When receiving APDU instruction in 7816_ISR or SWP_ISR, Sys_JobCnt will increase by 1, and in Java_Loop, Sys_JobCnt will decrease by 1. When Sys_JobCnt is not 0, APDU instruction parsing is then performed, and Sys_JobCnt is used to control the processing flow of the virtual machine, so that the 7816 interface and SWP interface can work in parallel, thus eliminating the need for RTOS and better reducing system power consumption.

[0142] Initialize and set Sys_WaitingCnt to 0. When Applet calls the 7816 interface to send API, Sys_WaitingCnt will increase by 1. In 7816_ISR, when the sending is completed, Sys_WaitingCnt will decrease by 1. If the system uses the SWP interface, Sys_WaitingCnt will increase by 1 when Applet calls the SWP send API, and Sys_WaitingCnt will decrease by 1 in SWP_ISR when the sending is completed. In Java_Loop, it will enter Wait mode or Stop mode depending on whether Sys_WaitingCnt is 0. When Applet calls WriteFlash APIs, Sys_WaitingCnt will increase by 1, and Sys_WaitingCnt will decrease by 1 in DMA_ISR when the sending is completed.

[0143] The workflow of the system's Java_Loop virtual machine is:

[0144] S1. After the system is powered on, the CPU execution environment is initialized and the DMA direct access module migration function is used to copy the 7816 interface, SWP interface, ISR interface, WriteFlash API, and Java_Loop from the Flash to the ILM_RAM module to obtain the starting address that can be used for Remap in the system: 0x00A01000.

[0145] S2, system Java virtual machine initialization;

[0146] S3. According to the interface hardware detection result, register configuration is performed on the 7816 interface and the SWP interface, and the corresponding interface interrupt of the register is enabled; Sys_WaitingCnt is set, and Sys_JobCnt is set to 0; and the virtual machine main loop Java_Loop API is entered from step S4, which is an IRAM program;

[0147] S4. If Sys_WaitingCnt is not equal to 0, call the assembly instruction to make the system enter the WAIT mode, and repeat step S4 until it is awakened by an interrupt; if Sys_WaitingCnt is equal to 0, go to step S5;

[0148] S5, call the assembly instruction to make the system enter the lowest power consumption STOP mode;

[0149] S6. The system receives the APDU instruction and exits the STOP mode. If the currently activated interface is the 7816 interface, the APDU data buffer pointer is set to the data buffer of the 7816 interface; if the currently activated interface is the SWP interface, the APDU data buffer pointer is set to the data buffer of the SWP interface; Sys_JobCnt decreases by 1;

[0150] S7, the Java virtual machine checks the APDU instruction. If the current instruction is not a MANAGE CHANNE command or a SELECT command, the process proceeds to step S9; if the current instruction is a MANAGE CHANNEL command, the Java virtual machine performs corresponding processing, writes the return data to the APDU data buffer, and then proceeds to step S10; if the current instruction is a SELECT command, the process proceeds to step S8;

[0151] S8. After the current target application is selected by OPEN, the Remap operation of the MMU memory management module is performed on the process method of the application, that is, the Flash page address corresponding to the Process method form byte code of the application is copied to the space of the ILM_RAM module from the Flash address corresponding to the process method of the application, with the help of the move function of the DMA direct access module, and the form byte number RemapSize of the method is obtained and aligned to the integer K byte number. If RemapSize is greater than 12KB, RemapSize is set to 12KB, and the source address of the remapped original address register is the integer K byte address of the form Flash, and the target address of the remapped target address register is 0x00A01000. The length of the remap length register is RemapSize, and the register is enabled to perform the remapping function. At this time, with the help of the characteristics of the DMA direct access module and the CPU executing in parallel, the Remap Flash content is copied to the ILM_RAM module, with a maximum of 12KB; the Java virtual machine writes the return data to the APDU data buffer, and then enters step S10;

[0152] S9, the Java virtual machine calls the currently selected application and parses the APDU instruction. Since the bytecode corresponding to the 12KB process method operation is remapped to the ILM_RAM module, the execution efficiency of Java parsing APDU instructions can be improved; if the Applet process needs to write to Flash, the system WrtFlash API is called to write 512B of data back to Flash, and the data is written to the target Flash address with the help of DMA BurstWrite function. Sys_WaitingCnt is set to increase by 1 in WrtFlash API, and the DMA direct access module completes the interrupt. In the interrupt service program, Sys_WaitingCnt will be set to decrease by 1; write the returned data to the APDU data buffer, and then enter step S10;

[0153] S10, for the current interface, call the system sending API to send the data in the APDU data buffer to the host, set Sys_WaitingCnt to increase by 1 in the sending API, and enable the DMA direct access module to send the completion interrupt, and set Sys_WaitingCnt to decrease by 1 in the interrupt service program;

[0154] S11. If Sys_JobCnt is not equal to 0, return to step S6; otherwise, return to step S4.

[0155] By adopting the above technical solution disclosed in the present invention, the following beneficial effects are obtained:

[0156] The present invention provides a high-performance, low-power eSIM card chip system. The system mounts a DMA direct access module on the AHB bus, so that the execution of the program can be parallelized to the greatest extent, thereby greatly improving the execution efficiency of the Java card, reducing the chip working time, and reducing the overall power consumption of the eSIM chip. The system mounts an ILM_RAM module on the SYS_AHB bus and is connected to the CPU through the I_AHB bus. During use, the code that needs to be accelerated is placed in the ILM_RAM module for execution, which can be parallelized to the greatest extent, thereby greatly improving the execution efficiency of the Java card, reducing the chip working time, and reducing the overall power consumption of the eSIM chip. The system defines the key function firmware codes such as the 7816 interface interrupt service program, the SWP interface interrupt service program, the DMA interrupt service program, and the WriteFlash API as programs that are logically on the ILM_RAM module, physically on the FLASH, and executed in the ILM_RAM module to improve the instruction processing performance of the entire chip. The system sends APDUSELECT instruction on the host side. When the Java card virtual machine receives and parses it to select a different new Applet, the Java card virtual machine further processes and obtains the FLASH page address and the byte size of the selected Applet's Procees method form, and performs MMU Remap on the FLASH content of this section. This remapping design is dynamic, that is, when switching Applets, the MMU Remap operation will be performed for the new Applet, and the key code will be accelerated, thereby improving the performance of the Java card virtual machine. The system uses the DMA transfer function to write Flash pages, which realizes parallel processing of instructions and improves chip execution performance; WriteFlash API is an ILM_RAM program, and the Applet's Procees method also runs in the ILM_RAM module, so the Procees method can be run normally while programming the FLASH page. Writing Flash pages is a frequently used operation in Java card applications, which can greatly improve the performance of Java cards. The system's programming operations on Flash are all performed through the DMA direct access module, so it can be processed in parallel with the CPU running firmware. In this chip, the minimum programming unit of FLASH is a WORD, i.e., 4 bytes. It takes 25 microseconds to write four bytes into FLASH. The programming time of Flash page 512B of this system is twice as fast as the programming time of Flash page 512B of the mainstream eSIM chip on the market. When the Java card application uses the DMA Burst read and write function designed by the present invention, the execution performance of the Java card application is higher. Since the programming time of Flash is greatly reduced, the power consumption of the entire chip can be greatly reduced.When the FLASH page is almost full, the DMA Burst write function is needed to erase the FLASH page and rewrite the data. Under such a strategy, the power consumption of the eSIM card on the FLASH will be greatly reduced. The system low-power control architecture actively enters the low-power mode based on the interface receiving and sending data packets; the interface IP's transceiver buffer makes the CPU in Wait mode, and the interface automatically sends data packets to the host, thereby reducing the CPU processing time on the interface to a minimum, thereby reducing the overall power consumption of the eSIM chip. The SWP interface supports the communication control of the SHDLC protocol at the hardware level. The received data packet is the data of the HCI layer, and the program does not need to spend a lot of instructions to perform SHDLC packet assembly and SHDLC communication protocol control.

[0157] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be considered as the scope of protection of the present invention.

Claims

1. A high-performance, low-power eSIM card chip system, characterized by: Including CPU, MMU memory management module, eflash module, ILM_RAM module, DLM_RAM module, PMU power consumption control module, CLK clock control module, AHB_DMA module, UCAA operation module, HASH operation module, DMA direct access module, SM1 operation module, DES operation module, SM4 operation module and configurable vector interrupt controller; The CPU is connected to the MMU memory management module via the I_AHB bus, and the MMU memory management module is connected to the eflash module and the ILM_RAM module via the FLASH_Ctrl interface and the RAM_CTRL interface respectively; the CPU is connected to the AHB_DMA module, the UCAA module, the HASH module, the DMA direct access module, the SM1 operation module, the DES operation module and the SM4 operation module via the SYS_AHB bus; the AHB_DMA module is connected to the eFLASH module via the FLASH_CTRL interface, and the AHB_DMA module is connected to the ILM_RAM module and the DLM_RAM module via the RAM_CTRL interface; The SYS_AHB bus is connected to the AHB2APB control line, and the AHB2APB control line is connected with a watchdog, a counter, a cyclic redundancy check module, a pure digital true random number generator, a programmable IO module, an IIC interface module, an SPI interface module, a UART interface module, a SWP interface module and a 7816 interface module; The MMU memory management module is connected to the AHB2SFR control line via the SFR bus, and the CLK clock control module and the PMU power consumption control module are both connected to the AHB2SFR control line; the CLK clock management module is connected to the OSC_HF clock and the OSC_LF clock; The CPU is connected to a configurable vector interrupt controller via a tightly coupled IP that supports single CPU clock cycle access; The RAM_CTRL interface is a control interface of the SRAM, used to control the read and write operations of the SRAM; The FLASH_CTRL interface is a FLASH control interface, used to control the read and write operations of FLASH; The OSC_HF clock is the source clock or provides the normal working clock for the system after frequency division; The OSC_LF clock is a wake-up clock for waking up the CPU; For the application selected by OPEN, the virtual machine performs the Remap operation of the MMU memory management module on the process method of the selected Applet application, that is, with the help of the DMA direct access module, the corresponding execution code is copied from the Flash address corresponding to the process method of the application to the space of the ILM_RAM module, so that the corresponding code can be executed in the RAM memory, thereby improving the execution efficiency; The specific process of the Remap operation is as follows: Move the program at address n1KB~n2KB in Flash to the space n3KB~n4KB in ILM_RAM module; Remap source address register, remap destination address register, remap length register; Remap the enable register to start the acceleration mechanism. After the enable register is remapped, when accessing the n1 KB to n2KB address space of the Flash, the n3KB to n4KB space of the SRAM is actually accessed. After the register remapping configuration is completed, the DMA direct access module starts the migration work, and the CPU runs the Java virtual machine code at the same time.

2. The high-performance, low-power eSIM card chip system according to claim 1, characterized in that: For each new application selected by the Java virtual machine, as much content as possible in Flash will be moved to the memory for execution based on its Process form source address and form byte number, thereby improving the execution performance of the Applet.

3. The high-performance, low-power eSIM card chip system according to claim 2, characterized in that: When you need to read the page content from the Flash, use the page read function of the DMA direct access module; when you need to modify the page content in the Flash, use the page erase and write function of the DMA direct access module.

4. The high-performance, low-power eSIM card chip system according to claim 3, characterized in that: The Java main loop in the system is driven by the interrupt on the interface to drive the firmware. After parsing the APDU instruction, the firmware enters the WAIT mode. When the system sends a response data packet to the host and the interrupt is generated, the CPU is woken up from the WAIT mode and then enters the deeper low-power Stop mode. If the Flash needs to be erased, the DMA direct access module is used to erase the Flash page by page, and the program runs in the ILM_RAM module; in this case, the CPU is awakened twice from the WAIT mode, once by the DMA Burst PageWrite completion interrupt, and the other by the interface transmission completion interrupt; and then enters the STOP mode; The system provides the Burst write function, which limits the maximum length of each Burst write to 64 words.

5. The high-performance, low-power eSIM card chip system according to claim 4, characterized in that: The system includes, Instruction low power mode: The CPU enters a low power mode when executing instructions, which is divided into STOP mode and WAIT mode; The STOP mode is specifically: set the STOP instruction of the CPU. In the STOP mode, except for some circuits in the communication interface that are directly driven by the external clock and the internal OSCLF, the clocks of other parts of the system are all stopped, and the analog module enters the STOP state to reduce the power consumption of the system; after the communication interface receives data / commands or receives a reset signal, it exits the STOP mode and the system clock returns to its original value; The specific details of the WAIT mode are: setting the CPU's WAIT instruction, the CPU enters the WAIT state, at which time the CPU clock stops to reduce power consumption. When an interrupt occurs, the CPU exits the WAIT state; UCAA low power mode; when Applet uses the UCAA algorithm, it completes the algorithm by calling the UCAA APIs function provided by the system, sets registers in the UCAA APIs function, and selects the UCAA low power mode; in the UCAA low power mode, after the CPU starts the UCAA operation module, the clocks of other parts of the system will stop to reduce system power consumption; after the operation is completed, the system clock will be automatically restored to exit the low power state; In UCAA low power mode, when the RSA algorithm starts to operate, the CLK clock management module, eFlash module, DES operation module, and SM1 operation module will all stop; NVM erase low power mode; when Applet wants to erase Flash, it can be done by calling the WriteFlashAPIs function provided by the system. The WriteFlash APIs function sets the register according to the actual erase, write or move function, and selects the NVM erase low power mode; in the NVM erase low power mode, after the CPU starts Flash Erase or Program, the clocks of other parts of the system will stop to reduce system power consumption; after the Erase / Program is completed, the system clock will be automatically restored to exit the low power state; In the NVM erase low power mode, during Flash Erase / Program, the CLK clock management module, UCAA operation module, DES operation module, and SM1 operation module will all stop.

6. The high-performance, low-power eSIM card chip system according to claim 5, characterized in that: The workflow of the system's Java virtual machine is: S1. After the system is powered on, the CPU execution environment is initialized and the DMA direct access module migration function is used to copy the 7816 interface, SWP interface, ISR interface, WriteFlash API, and Java_Loop from the Flash to the ILM_RAM module to obtain the starting address that can be used for Remap in the system: 0x00A01000. S2, system Java virtual machine initialization; S3. According to the interface hardware detection result, register configuration is performed on the 7816 interface and the SWP interface, and the corresponding interface interrupt of the register is enabled; Sys_WaitingCnt is set, and Sys_JobCnt is set to 0; and the virtual machine main loop Java_Loop API is entered from step S4, which is an IRAM program; S4. If Sys_WaitingCnt is not equal to 0, call the assembly instruction to make the system enter the WAIT mode, and repeat step S4 until it is awakened by an interrupt; if Sys_WaitingCnt is equal to 0, go to step S5; S5, call the assembly instruction to make the system enter the lowest power consumption STOP mode; S6. The system receives the APDU instruction and exits the STOP mode. If the currently activated interface is the 7816 interface, the APDU data buffer pointer is set to the data buffer of the 7816 interface; if the currently activated interface is the SWP interface, the APDU data buffer pointer is set to the data buffer of the SWP interface; Sys_JobCnt decreases by 1; S7, the Java virtual machine checks the APDU instruction. If the current instruction is not a MANAGE CHANNE command or a SELECT command, the process proceeds to step S9; if the current instruction is a MANAGE CHANNEL command, the Java virtual machine performs corresponding processing, writes the return data to the APDU data buffer, and then proceeds to step S10; if the current instruction is a SELECT command, the process proceeds to step S8; S8. After the current target application is selected by OPEN, the Remap operation of the MMU memory management module is performed on the process method of the application, that is, the Flash page address corresponding to the Process method form byte code of the application is copied to the space of the ILM_RAM module from the Flash address corresponding to the process method of the application, with the help of the move function of the DMA direct access module, and the form byte number RemapSize of the method is obtained and aligned to the integer K byte number. If RemapSize is greater than 12KB, RemapSize is set to 12KB, and the source address of the remapped original address register is the integer K byte address of the form Flash, and the target address of the remapped target address register is 0x00A01000. The length of the remap length register is RemapSize, and the register is enabled to perform the remapping function. At this time, with the help of the characteristics of the DMA direct access module and the CPU executing in parallel, the Remap Flash content is copied to the ILM_RAM module, with a maximum of 12KB; the Java virtual machine writes the return data to the APDU data buffer, and then enters step S10; S9, the Java virtual machine calls the currently selected application and parses the APDU instruction. Since the bytecode corresponding to the 12KB process method operation is remapped to the ILM_RAM module, the execution efficiency of Java parsing APDU instructions can be improved; if the Applet process needs to write to Flash, the system WrtFlash API is called to write 512B of data back to Flash, and the data is written to the target Flash address with the help of DMA BurstWrite function. Sys_WaitingCnt is set to increase by 1 in WrtFlash API, and the DMA direct access module completes the interrupt. In the interrupt service program, Sys_WaitingCnt will be set to decrease by 1; write the returned data to the APDU data buffer, and then enter step S10; S10, for the current interface, call the system sending API to send the data in the APDU data buffer to the host, set Sys_WaitingCnt to increase by 1 in the sending API, and enable the DMA direct access module to send the completion interrupt, and set Sys_WaitingCnt to decrease by 1 in the interrupt service program; S11. If Sys_JobCnt is not equal to 0, return to step S6; otherwise, return to step S4.

7. The high-performance, low-power eSIM card chip system according to claim 1, characterized in that: The UCAA operation module includes the RSA algorithm, the SM2 algorithm, and the ECC algorithm; the HASH operation module includes the SHA1 algorithm, the SM3 algorithm, and the SHA256 algorithm.

8. The high-performance, low-power eSIM card chip system according to claim 1, characterized in that: The ILM_RAM module is a 16KB single-port SRAM; the DLM_RAM module is a 24KB single-port SRAM.

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