Gate driving unit, gate driving circuit and display device

Abstract

The application provides a gate driving unit, a gate driving circuit and a display device. The application provides a gate driving unit, which comprises a pull-up node denoising circuit and a pull-up control circuit; the pull-up node denoising circuit is electrically connected with an input end, a pull-down node and a pull-up node respectively, and is used for controlling the pull-up node and the input end to be in communication or disconnected under the control of the potential of the pull-down node; the pull-up control circuit is electrically connected with the pull-up node and the input end respectively, and is used for controlling the pull-up node and the input end to be in communication in an input stage. The application solves the problem of insufficient charging capacity of the pull-up node in the input stage in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving unit, a gate driving circuit and a display device. BACKGROUND

[0002] In the existing gate driving unit, the pull-up node and the pull-down node are in a competitive connection relationship, the input signal provided by the input end charges the pull-up node, and the pull-up node pulls down the potential of the pull-down node through the pull-down TFT (Thin Film Transistor), but the pull-down node simultaneously pulls down the potential of the pull-up node through the noise reduction TFT. When the potential of the pull-down node is high in the input stage, the pull-up node cannot be charged, so that no gate driving signal is output. SUMMARY

[0003] The main purpose of the present application is to provide a gate driving unit, a gate driving circuit and a display device to solve the problem of insufficient charging capacity of the pull-up node in the input stage in the prior art.

[0004] In order to achieve the above purpose, the present application provides a gate driving unit, comprising a pull-up node noise reduction circuit and a pull-up control circuit.

[0005] The pull-up node noise reduction circuit is electrically connected with the input end, the pull-down node and the pull-up node respectively, and is used to control the communication or disconnection between the pull-up node and the input end under the control of the potential of the pull-down node.

[0006] The pull-up control circuit is electrically connected with the pull-up node and the input end respectively, and is used to control the communication between the pull-up node and the input end in the input stage.

[0007] The present application further provides a gate driving circuit comprising a plurality of the above-mentioned gate driving units.

[0008] The present application further provides a display device comprising the above-mentioned gate driving circuit.

[0009] The gate driving unit, the gate driving circuit and the display device according to the present application can charge the pull-up node in the input stage through the pull-up control circuit to control the communication between the pull-up node and the input end, so as to improve the potential of the pull-up node in the input stage. Even if the potential of the pull-down node is high in the input stage, the pull-up node noise reduction circuit can control the communication between the pull-up node and the input end under the control of the potential of the pull-down node, so as to avoid the problem of insufficient charging capacity of the pull-up node caused by the competition between the pull-up node and the pull-down node, and better charge the pull-up node in the input stage. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1This is a structural diagram of the gate driving unit according to an embodiment of the present invention;

[0011] Figure 2 This is a structural diagram of the gate driving unit according to another embodiment of the present invention;

[0012] Figure 3 This is a circuit diagram of a first specific embodiment of the gate driving unit described in this invention;

[0013] Figure 4 This is a timing diagram of the operation of a first specific embodiment of the gate driving unit described in this invention;

[0014] Figure 5 This is a simulation timing diagram of a first specific embodiment of the gate driving unit described in this invention;

[0015] Figure 6 This is a circuit diagram of a second specific embodiment of the gate driving unit described in this invention;

[0016] Figure 7 This is a timing diagram of the operation of a second specific embodiment of the gate driving unit described in this invention;

[0017] Figure 8 This is a structural diagram of the gate driving unit according to an embodiment of the present invention;

[0018] Figure 9 This is a circuit diagram of the gate driving unit according to an embodiment of the present invention;

[0019] Figure 10 This invention is as follows Figure 9 The timing diagram of the gate driving unit. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] like Figure 1 As shown, the gate driving unit in this embodiment of the invention includes a pull-up node noise reduction circuit 11 and a pull-up control circuit 12;

[0022] The pull-up node noise reduction circuit 11 is electrically connected to the input terminal INPUT, the pull-down node PD, and the pull-up node PU0, respectively, and is used to control the connection or disconnection between the pull-up node PU0 and the input terminal INPUT under the control of the potential of the pull-down node PD.

[0023] The pull-up control circuit 12 is electrically connected with the pull-up node PU0 and the input terminal INPUT respectively, and is used for controlling the communication between the pull-up node PU0 and the input terminal INPUT in the input stage.

[0024] In the input stage, the pull-up control circuit 12 controls the communication between the pull-up node PU0 and the input terminal INPUT to charge the pull-up node PU0, so as to raise the potential of the pull-up node PU0 in the input stage. Even if the potential of the pull-down node PD is high in the input stage, the potential of the pull-up node PU0 will not be pulled down due to the control of the pull-up node noise elimination circuit 11 on the potential of the pull-down node PD, so as to avoid the problem of insufficient charging capacity of the pull-up node caused by the competition between the pull-up node and the pull-down node, and better charge the pull-up node PU0 in the input stage.

[0025] In the specific implementation, the gate drive unit can further include an energy storage circuit electrically connected with the pull-up node, and used for storing energy to maintain the potential of the pull-up node.

[0026] The gate drive unit can be based on the Oxide technology, and can also be based on the a-si (Amorphous Silicon) and LTPS (Low Temperature Ploy Silicon) technology, but is not limited thereto.

[0027] Optionally, the pull-up node noise elimination circuit is electrically connected with a pull-down node, and includes a pull-up node noise elimination transistor; a control electrode of the pull-up node noise elimination transistor is electrically connected with the pull-down node; a first electrode of the pull-up node noise elimination transistor is electrically connected with the pull-up node; and a second electrode of the pull-up node noise elimination transistor is electrically connected with the input terminal.

[0028] The pull-down node includes a first pull-down node and a second pull-down node; the pull-up node noise elimination circuit includes a first pull-up node noise elimination transistor and a second pull-up node noise elimination transistor; a control electrode of the first pull-up node noise elimination transistor is electrically connected with the first pull-down node; a first electrode of the first pull-up node noise elimination transistor is electrically connected with the pull-up node; and a second electrode of the first pull-up node noise elimination transistor is electrically connected with the input terminal; a control electrode of the second pull-up node noise elimination transistor is electrically connected with the second pull-down node; a first electrode of the second pull-up node noise elimination transistor is electrically connected with the pull-up node; and a second electrode of the second pull-up node noise elimination transistor is electrically connected with the input terminal.

[0029] In a specific implementation, the pull-up control circuit is further configured to reset the potential of the pull-up node to pull down the potential of the pull-up node in a reset stage.

[0030] Optionally, the pull-up control circuit comprises a pull-up control transistor.

[0031] The control electrode of the pull-up control transistor is electrically connected to the first clock signal terminal, the first electrode of the pull-up control transistor is electrically connected to the pull-up node, and the second electrode of the pull-up control transistor is electrically connected to the input terminal.

[0032] Optionally, the pull-up control circuit comprises an input transistor and a reset transistor.

[0033] The control electrode and the first electrode of the input transistor are both electrically connected to the input terminal, and the second electrode of the input transistor is electrically connected to the pull-up node.

[0034] The control electrode of the reset transistor is electrically connected to the reset terminal, the first electrode of the reset transistor is electrically connected to the pull-up node, and the second electrode of the reset transistor is electrically connected to the first low-voltage terminal or the input terminal.

[0035] In the embodiment of the present application, as shown in Figure 2 As shown in the embodiment of the gate drive unit, Figure 1 Based on the embodiment of the gate drive unit shown in

[0036] The pull-down node control circuit 21 is electrically connected to the pull-up node PU0, the pull-down node PD and the first low-voltage terminal, respectively, and is configured to control the communication between the pull-down node and the control voltage terminal under the control of the control voltage provided by the control voltage terminal, and is configured to control the communication or disconnection between the pull-down node and the first low-voltage terminal under the control of the potential of the pull-up node; the first low-voltage terminal is configured to provide a first low voltage LVGL.

[0037] The energy storage circuit 24 is electrically connected to the pull-up node PU0 and is configured to maintain the potential of the pull-up node PU0.

[0038] The carry signal output circuit 22 is electrically connected with the carry signal output end OUT_C, the pull-up node PU0, the pull-down node PD, a second clock signal end and a first low voltage end respectively, for controlling the communication between the carry signal output end OUT_C and the second clock signal end under the control of the potential of the pull-up node PU0, and for controlling the communication between the carry signal output end OUT_C and the first low voltage end under the control of the potential of the pull-down node PD; the second clock signal end is used for providing a second clock signal CLK; and the first low voltage end is used for providing a first low voltage LVGL.

[0039] The gate drive signal output circuit 23 is electrically connected with the gate drive signal output end OUT1, the pull-up node PU0, the pull-down node PD, the second clock signal end and a second low voltage end respectively, for controlling the communication between the gate drive signal output end OUT1 and the second clock signal end under the control of the potential of the pull-up node PU0, and for controlling the communication between the gate drive signal output end OUT1 and the second low voltage end under the control of the potential of the pull-down node PD; and the second low voltage end is used for providing a second low voltage VGL.

[0040] In a specific implementation, the pull-down node control circuit 21 is used for controlling the potential of the pull-down node PD under the control of the control voltage and the potential of the pull-up node PU0, the energy storage circuit 24 maintains the potential of the pull-up node PU0, the carry signal output circuit 22 controls the carry signal output end OUT_C to output a carry signal under the control of the potential of the pull-up node PU0 and the potential of the pull-down node PD, so as to provide an input signal and a reset signal for an adjacent stage gate drive unit, and the gate drive signal output circuit 23 controls the gate drive signal output end OUT1 to output a gate drive signal under the control of the potential of the pull-up node PU0 and the potential of the pull-down node PD.

[0041] In a preferred case, the first low voltage provided by the first low voltage end is less than the second low voltage provided by the second low voltage end, so as to compensate the stress of a first gate drive output transistor included in the gate drive signal output circuit for outputting a gate drive signal in a non-output stage, and to reduce the threshold voltage drift of the first gate drive output transistor.

[0042] Optionally, the pull-down node includes a first pull-down node and a second pull-down node; and the control voltage end includes a first control voltage end and a second control voltage end.

[0043] The pull-down node control circuit is configured to control the potential of the first pull-down node under the control of a first control voltage provided by the first control voltage terminal, and to control the communication or disconnection between the first pull-down node and the first low voltage terminal under the control of the pull-up node, and to control the potential of the second pull-down node under the control of a second control voltage provided by the second control voltage terminal, and to control the electrical connection between the second pull-down node and the first low voltage terminal under the control of the pull-up node.

[0044] In a specific implementation, when the gate drive unit includes the first pull-down node and the second pull-down node, the gate drive unit uses the first control voltage terminal and the second control voltage terminal, and when the first control voltage provided by the first control voltage terminal is a high voltage, the second control voltage provided by the second control voltage terminal is a low voltage; when the first control voltage is a low voltage, the second control voltage is a high voltage; in this way, the transistor controlled by the first control voltage terminal and the transistor controlled by the second control voltage terminal can work alternately, and threshold voltage drift caused by the transistor controlled by the first control voltage terminal and the transistor controlled by the second control voltage terminal being turned on for a long time is prevented.

[0045] In the embodiment of the present application, the first control voltage terminal and the second control voltage terminal alternately provide a high voltage at a predetermined time interval (the predetermined time interval can be less than one frame of picture display time, or can be greater than one frame of picture display time, and the predetermined time interval can be selected according to actual conditions). That is, when the first control voltage terminal provides a high voltage, the second control voltage terminal provides a low voltage; when the first control voltage terminal provides a low voltage, the second control voltage terminal provides a high voltage.

[0046] Optionally, the pull-down node control circuit includes a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor, wherein,

[0047] The control electrode of the first pull-down control transistor and the first electrode of the first pull-down control transistor are electrically connected to the first control voltage terminal, and the second electrode of the first pull-down control transistor is electrically connected to the first pull-down node;

[0048] The control electrode of the second pull-down control transistor is electrically connected to the pull-up node, the first electrode of the second pull-down control transistor is electrically connected to the first pull-down node, and the second electrode of the second pull-down control transistor is electrically connected to the first low voltage terminal;

[0049] The control electrode of the third pull-down control transistor and the first electrode of the third pull-down control transistor are electrically connected to the second control voltage terminal, and the second electrode of the third pull-down control transistor is electrically connected to the second pull-down node;

[0050] The control electrode of the fourth pull-down control transistor is electrically connected with the pull-up node, the first electrode of the fourth pull-down control transistor is electrically connected with the second pull-down node, and the second electrode of the fourth pull-down control transistor is electrically connected with the first low-voltage terminal.

[0051] In the embodiment of the present application, the pull-down node can include a first pull-down node and a second pull-down node; the carry signal output circuit includes a first carry signal output transistor, a second carry signal output transistor and a third carry signal output transistor, and the gate drive signal output circuit includes a first gate drive output transistor, a second gate drive output transistor and a third gate drive output transistor.

[0052] The control electrode of the first carry signal output transistor is electrically connected with the pull-up node, the first electrode of the first carry signal output transistor is electrically connected with the second clock signal terminal, and the second electrode of the first carry signal output transistor is electrically connected with the carry signal output terminal.

[0053] The control electrode of the second carry signal output transistor is electrically connected with the first pull-down node, the first electrode of the second carry signal output transistor is electrically connected with the carry signal output terminal, and the second electrode of the second carry signal output transistor is electrically connected with the first low-voltage terminal.

[0054] The control electrode of the third carry signal output transistor is electrically connected with the second pull-down node, the first electrode of the third carry signal output transistor is electrically connected with the carry signal output terminal, and the second electrode of the third carry signal output transistor is electrically connected with the first low-voltage terminal.

[0055] The control electrode of the first gate drive output transistor is electrically connected with the pull-up node, the first electrode of the first gate drive output transistor is electrically connected with the second clock signal terminal, and the second electrode of the first gate drive output transistor is electrically connected with the gate drive signal output terminal.

[0056] The control electrode of the second gate drive output transistor is electrically connected with the first pull-down node, the first electrode of the second gate drive output transistor is electrically connected with the gate drive signal output terminal, and the second electrode of the second gate drive output transistor is electrically connected with the second low-voltage terminal.

[0057] The control electrode of the third gate drive output transistor is electrically connected with the second pull-down node, the first electrode of the third gate drive output transistor is electrically connected with the gate drive signal output terminal, and the second electrode of the third gate drive output transistor is electrically connected with the second low-voltage terminal.

[0058] As Figure 3As shown, the first embodiment of the gate drive unit of the present application comprises a pull-up node denoising circuit 11, a pull-up control circuit 12, a pull-down node control circuit 21, a carry signal output circuit 22, a gate drive signal output circuit 23 and an energy storage circuit 24;

[0059] The pull-down node comprises a first pull-down node PD_A and a second pull-down node PD_B, and the control voltage end comprises a first control voltage end VDD_A and a second control voltage end VDD_B;

[0060] The pull-up node denoising circuit 11 comprises a first pull-up node denoising transistor M7A and a second pull-up node denoising transistor M7B;

[0061] The gate of the first pull-up node denoising transistor M7A is electrically connected with the first pull-down node PD_A, the drain of the first pull-up node denoising transistor M7A is electrically connected with the pull-up node PU0, and the source of the first pull-up node denoising transistor M7A is electrically connected with the input end INPUT;

[0062] The gate of the second pull-up node denoising transistor M7B is electrically connected with the second pull-down node PD_B, the drain of the second pull-up node denoising transistor M7B is electrically connected with the pull-up node PU0, and the source of the second pull-up node denoising transistor M7B is electrically connected with the input end INPUT;

[0063] The pull-up control circuit 12 comprises a pull-up control transistor M2;

[0064] The gate of the pull-up control transistor M2 is electrically connected with a first clock signal end, the drain of the pull-up control transistor M2 is electrically connected with the pull-up node PU0, and the source of the pull-up control transistor M2 is electrically connected with the input end INPUT; the first clock signal end is used for providing a first clock signal CLKB;

[0065] The pull-down node control circuit 21 comprises a first pull-down control transistor M5A, a second pull-down control transistor M6A, a third pull-down control transistor M5B and a fourth pull-down control transistor M6B, wherein,

[0066] The gate of the first pull-down control transistor M5A and the drain of the first pull-down control transistor M5A are both electrically connected with the first control voltage end VDD_A, and the source of the first pull-down control transistor M5A is electrically connected with the first pull-down node PD_A;

[0067] The gate of the second pull-down control transistor M6A is electrically connected with the pull-up node PU0, the drain of the second pull-down control transistor M6A is electrically connected with the first pull-down node PD_A, and the source of the second pull-down control transistor M6A is electrically connected with the first low voltage end; the first low voltage end is used for providing a first low voltage LVGL;

[0068] The gate of the third pull-down control transistor M5B and the drain of the third pull-down control transistor M5B are both electrically connected with the second control voltage end VDD_B, and the source of the third pull-down control transistor M5B is electrically connected with the second pull-down node PD_B;

[0069] The gate of the fourth pull-down control transistor M6B is electrically connected with the pull-up node PU0, the drain of the fourth pull-down control transistor M6B is electrically connected with the second pull-down node PD_B, and the source of the fourth pull-down control transistor M6B is electrically connected with the first low voltage end;

[0070] The carry signal output circuit 22 includes a first carry signal output transistor M4, a second carry signal output transistor M8A and a third carry signal output transistor M8B, and the gate drive signal output circuit 23 includes a first gate drive output transistor M3, a second gate drive output transistor M9A and a third gate drive output transistor M9B;

[0071] The gate of the first carry signal output transistor M4 is electrically connected with the pull-up node PU0, the drain of the first carry signal output transistor M4 is electrically connected with the second clock signal end, and the source of the first carry signal output transistor M4 is electrically connected with the carry signal output end OUT_C; the second clock signal end is used for providing a second clock signal CLK;

[0072] The gate of the second carry signal output transistor M8A is electrically connected with the first pull-down node PD_A, the drain of the second carry signal output transistor M8A is electrically connected with the carry signal output end OUT_C, and the source of the second carry signal output transistor M8A is electrically connected with the first low voltage end; the first low voltage end is used for providing a first low voltage LVGL;

[0073] The gate of the third carry signal output transistor M8B is electrically connected with the second pull-down node PD_B, the drain of the third carry signal output transistor M8B is electrically connected with the carry signal output end OUT_C, and the source of the third carry signal output transistor M8B is electrically connected with the first low voltage end;

[0074] The gate of the first gate drive output transistor M3 is electrically connected to the pull-up node PU0, the drain of the first gate drive output transistor M3 is electrically connected to the second clock signal terminal, and the source of the first gate drive output transistor M3 is electrically connected to the gate drive signal output terminal OUT1.

[0075] The gate of the second gate drive output transistor M9A is electrically connected to the first pull-down node PD_A, the drain of the second gate drive output transistor M9A is electrically connected to the gate drive signal output terminal OUT1, and the source of the second gate drive output transistor M9A is electrically connected to the second low voltage terminal; the second low voltage terminal is used to provide the second low voltage VGL.

[0076] The gate of the third gate drive output transistor M9B is electrically connected to the second pull-down node PD_B, the drain of the third gate drive output transistor M9B is electrically connected to the gate drive signal output terminal OUT1, and the source of the third gate drive output transistor M9B is electrically connected to the second low voltage terminal.

[0077] The energy storage circuit 24 includes a storage capacitor C1;

[0078] The first terminal of C1 is electrically connected to the pull-up node PU0, and the second terminal of C1 is electrically connected to the gate drive signal output terminal OUT1.

[0079] exist Figure 3 In the first specific embodiment of the gate drive unit shown, all transistors are NMOS transistors (N-type metal-oxide-semiconductor transistors), but this is not a limitation.

[0080] like Figure 4 As shown, in operation, the first specific embodiment of the gate driving unit of the present invention,

[0081] During the input phase S1, CLKB is at a high voltage, CLK is at a low voltage, VDD_A provides a high voltage, VDD_B provides a low voltage, INPUT provides a high voltage, M2 is on, PU and INPUT are connected, INPUT charges C1, PU's potential is high, M6A and M6B are both on, and PD_A and PD_B's potentials are both low. Since the sources of M7A and M7B are electrically connected to INPUT, even if the potentials of PD_A and PD_B cannot be quickly pulled low during the input phase S1, the on-state of M7A and M7B, connecting PU and INPUT, promotes charging of PU, eliminating the risk of competition between PD and PU during the input phase in the prior art.

[0082] In the output stage S2, CLKB is low voltage, CLK is high voltage, VDD_A provides high voltage, VDD_B provides low voltage, INPUT provides low voltage, the potential of PU is pulled up by C1, so that M3 and M4 are fully opened, CLK is transmitted to OUT_C and OUT1, at this time, M6A and M6B are fully opened, the potential of PD is low voltage, and the noise elimination related transistors are all closed.

[0083] In the reset stage S3, CLKB is high voltage, CLK is low voltage, VDD_A provides high voltage, VDD_B provides low voltage, INPUT provides low voltage, M2 is opened, the potential of PU is pulled low to low voltage, M5A is opened, M5B, M6A and M6B are closed, the potential of PD_A is pulled to high voltage, the potential of PD_B is low voltage, M7A is opened, and PU is communicated with INPUT.

[0084] After the reset stage S3 ends for a period of time, before the next frame signal arrives or after a few frame display times, VDD_A becomes to provide low voltage, VDD_B becomes to provide high voltage, the noise elimination function is maintained to be normal, and M7A, M7B, M8A, M8B, M9A and M8B are not subjected to positive stress for a long time, so that the threshold voltage is not positively biased to cause the gate drive unit to fail.

[0085] Figure 5 It is a simulation working timing diagram of the first specific embodiment of the gate drive unit described in the application.

[0086] The first specific embodiment of the gate drive unit described in the embodiment of the application works as follows: when the duty cycle of the clock signal used by the gate drive unit is less than 0.5, there is a first time period between the input stage and the output stage, and there is a second time period between the output stage and the reset stage, OUT1 outputs LVGL (the potential of CLK in the first time period and the second time period is LVGL) in the first time period and the second time period.

[0087] Figure 6 The second specific embodiment of the gate drive unit shown is different from the first specific embodiment of the gate drive unit shown in that: Figure 3

[0088] The pull-up control circuit 12 includes an input transistor M1 and a reset transistor M0.

[0089] The gate of M1 and the drain of M1 are electrically connected with the input end INPUT, and the source of M1 is connected with the pull-up node PU0.

[0090] The gate of M0 is electrically connected with the reset end RST, the drain of M0 is electrically connected with PU, and the source of M0 is electrically connected with the input end INPUT. ​

[0091] In Figure 6 In the embodiment shown, the source of M0 can also access the first low voltage LVGL.

[0092] In Figure 6 In the embodiment shown, M1 and M0 can both be NMOS tubes, but are not limited thereto.

[0093] As Figure 7 shown, the application is as Figure 6 The second specific embodiment of the gate drive unit shown in the application works as follows:

[0094] In the input stage S1, INPUT provides a high voltage, M1 is turned on, PU is connected with INPUT, RST provides a low voltage, and M0 is turned off.

[0095] In the output stage S2, INPUT and RST both provide low voltages, and M1 and M0 are both turned off.

[0096] In the reset stage S3, INPUT provides a low voltage, RST provides a high voltage, M1 is turned off, and M0 is turned on to pull the potential of PU low.

[0097] In the specific implementation, the pull-up node includes a first pull-up node and a second pull-up node; the gate drive unit of the embodiment of the application further includes a pull-up node control circuit.

[0098] The pull-up node control circuit is electrically connected with the control voltage end, the first pull-up node and the second pull-up node, respectively, for controlling the first pull-up node and the second pull-up node to be connected or disconnected under the control of the control voltage provided by the control voltage end, and for maintaining the potential of the second pull-up node.

[0099] The pull-up node de-noising circuit is electrically connected with the first pull-up node, for controlling the first pull-up node and the input end to be connected under the control of the potential of the pull-down node PD.

[0100] The pull-up control circuit is electrically connected with the first pull-up node, for controlling the first pull-up node and the input end to be connected in the input stage.

[0101] In the gate driving unit of this embodiment, during the input phase, the pull-up node control circuit, under the control of the control voltage, controls the connection between the first pull-up node and the second pull-up node to charge the energy storage circuit until the potential of the second pull-up node rises to a certain value. Then, the pull-up node control circuit controls the connection between the first pull-up node and the second pull-up node to complete the charging of the second pull-up node. Furthermore, during the time interval between the input and output phases (in this embodiment, when the duty cycle of the clock signal used by the gate driving unit is not equal to 0.5, there will be a time interval between the input and output phases), the pull-up node control circuit, under the control of the control voltage, can prevent the potential of the second pull-up node from decreasing due to leakage, thus preventing the inability to control the pull-down node's potential from dropping.

[0102] Optionally, the pull-up node control circuit includes a pull-up control transistor;

[0103] The control electrode of the pull-up control transistor is electrically connected to the control voltage terminal, the first electrode of the pull-up control transistor is electrically connected to the second pull-up node, and the second electrode of the pull-up control transistor is electrically connected to the first pull-up node.

[0104] like Figure 8 As shown, in Figure 1 Based on the embodiment of the gate driving unit shown, the pull-up node may include a first pull-up node PU and a second pull-up node PU_1; the control voltage terminal may include a first control voltage terminal VDD_A and a second control voltage terminal VDD_B; the gate driving unit of the embodiment of the present invention further includes a pull-up node control circuit 90; the pull-down node includes a first pull-down node PD_A and a second pull-down node PD_B;

[0105] The pull-up node control circuit 90 is electrically connected to the first control voltage terminal VDD_A, the second control voltage terminal VDD_B, the first pull-up node PU, and the second pull-up node PU_1, respectively. It is used to control the connection or disconnection between the first pull-up node PU and the second pull-up node PU_1 under the control of the first control voltage provided by the first control voltage terminal VDD_A, and to control the connection or disconnection between the first pull-up node PU and the second pull-up node PU_1 under the control of the second control voltage provided by the second control voltage terminal VDD_B, and to maintain the potential of the second pull-up node PU_1.

[0106] The pull-up node noise reduction circuit 11 is electrically connected to the first pull-up node PU, and is used to control the connection between the first pull-up node PU and the input terminal INPUT under the control of the potential of the pull-down node PD;

[0107] The pull-up control circuit 12 is electrically connected with the first pull-up node PU, and is configured to control the first pull-up node PU to be in communication with the input terminal INPUT in the input stage.

[0108] The gate driving unit shown in the embodiment of the present application works as follows. Figure 8 In the input stage, the pull-up node control circuit 90 controls the first pull-up node PU to be in communication with the second pull-up node PU_1 under the control of the first control voltage provided by VDD_A or the second control voltage provided by VDD_B, so as to charge the energy storage circuit until the potential of the second pull-up node PU_1 rises to a certain value, and then the pull-up node control circuit 90 controls the first pull-up node PU to be disconnected from the second pull-up node PU_1, thereby completing the charging of the second pull-up node PU_1; and in the period between the input stage and the output stage (in the embodiment of the present application, when the duty cycle of the clock signal used by the gate driving unit is not equal to 0.5, the input stage and the output stage will be separated by a period of time), the pull-up node control circuit 90 can prevent the potential of the second pull-up node PU_1 from being reduced due to leakage, which may result in the failure to control the potential of the pull-down node to be lowered.

[0109] Optionally, the pull-up node control circuit comprises a first pull-up control transistor and a second pull-up control transistor.

[0110] The control electrode of the first pull-up control transistor is electrically connected with the first control voltage terminal, the first electrode of the first pull-up control transistor is electrically connected with the second pull-up node, and the second electrode of the first pull-up control transistor is electrically connected with the first pull-up node.

[0111] The control electrode of the second pull-up control transistor is electrically connected with the second control voltage terminal, the first electrode of the second pull-up control transistor is electrically connected with the second pull-up node, and the second electrode of the second pull-up control transistor is electrically connected with the first pull-up node.

[0112] In the embodiment of the present application, the gate driving unit can further comprise a pull-down node control circuit, a carry signal output circuit, a gate driving signal output circuit and an energy storage circuit.

[0113] The pull-down node control circuit is electrically connected with the second pull-up node, the pull-down node and the first low voltage end respectively, and is used for controlling the communication between the pull-down node and the control voltage end under the control of the control voltage provided by the control voltage end, and is used for controlling the communication or disconnection between the pull-down node and the first low voltage end under the control of the potential of the second pull-up node; the pull-down node control circuit controls the potential of the pull-down node under the control of the control voltage and the potential of the second pull-up node.

[0114] The energy storage circuit is electrically connected with the second pull-up node, and is used for maintaining the potential of the second pull-up node.

[0115] The carry signal output circuit is electrically connected with the carry signal output end, the second pull-up node, the pull-down node, the second clock signal end and the first low voltage end respectively, and is used for controlling the communication between the carry signal output end and the second clock signal end under the control of the potential of the second pull-up node, and is used for controlling the communication between the carry signal output end and the first low voltage end under the control of the potential of the pull-down node; the carry signal output circuit controls the carry signal output end to output the carry signal under the control of the potential of the pull-down node and the potential of the second pull-up node.

[0116] The gate drive signal output circuit is electrically connected with the gate drive signal output end, the second pull-up node, the pull-down node, the second clock signal end and the second low voltage end respectively, and is used for controlling the communication between the gate drive signal output end and the second clock signal end under the control of the potential of the second pull-up node, and is used for controlling the communication between the gate drive signal output end and the second low voltage end under the control of the potential of the pull-down node; the gate drive signal output circuit controls the gate drive signal output end to output the gate drive signal under the control of the potential of the pull-down node and the potential of the second pull-up node.

[0117] Optionally, the pull-down node includes a first pull-down node and a second pull-down node; the control voltage end includes a first control voltage end and a second control voltage end.

[0118] The pull-down node control circuit is used for controlling the potential of the first pull-down node under the control of the first control voltage provided by the first control voltage end, and is used for controlling the communication or disconnection between the first pull-down node and the first low voltage end under the control of the second pull-up node, and is used for controlling the potential of the second pull-down node under the control of the second control voltage provided by the second control voltage end, and is used for controlling the electrical connection between the second pull-down node and the first low voltage end under the control of the second pull-up node.

[0119] Optionally, the pull-down node control circuit comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor and a fourth pull-down control transistor, wherein,

[0120] the control electrode of the first pull-down control transistor and the first electrode of the first pull-down control transistor are electrically connected with the first control voltage terminal, and the second electrode of the first pull-down control transistor is electrically connected with the first pull-down node;

[0121] the control electrode of the second pull-down control transistor is electrically connected with the second pull-up node, the first electrode of the second pull-down control transistor is electrically connected with the first pull-down node, and the second electrode of the second pull-down control transistor is electrically connected with the first low voltage terminal;

[0122] the control electrode of the third pull-down control transistor and the first electrode of the third pull-down control transistor are electrically connected with the second control voltage terminal, and the second electrode of the third pull-down control transistor is electrically connected with the second pull-down node;

[0123] the control electrode of the fourth pull-down control transistor is electrically connected with the second pull-up node, the first electrode of the fourth pull-down control transistor is electrically connected with the second pull-down node, and the second electrode of the fourth pull-down control transistor is electrically connected with the first low voltage terminal.

[0124] In specific implementation,

[0125] the carry signal output circuit can comprise a first carry signal output transistor, a second carry signal output transistor and a third carry signal output transistor, and the gate drive signal output circuit can comprise a first gate drive output transistor, a second gate drive output transistor and a third gate drive output transistor;

[0126] the control electrode of the first carry signal output transistor is electrically connected with the second pull-up node, the first electrode of the first carry signal output transistor is electrically connected with the second clock signal terminal, and the second electrode of the first carry signal output transistor is electrically connected with the carry signal output terminal;

[0127] the control electrode of the second carry signal output transistor is electrically connected with the first pull-down node, the first electrode of the second carry signal output transistor is electrically connected with the carry signal output terminal, and the second electrode of the second carry signal output transistor is electrically connected with the first low voltage terminal;

[0128] the control electrode of the third carry signal output transistor is electrically connected with the second pull-down node, the first electrode of the third carry signal output transistor is electrically connected with the carry signal output terminal, and the second electrode of the third carry signal output transistor is electrically connected with the first low voltage terminal.

[0129] The control electrode of the first gate drive output transistor is electrically connected with the second pull-up node, the first electrode of the first gate drive output transistor is electrically connected with the second clock signal end, and the second electrode of the first gate drive output transistor is electrically connected with the gate drive signal output end;

[0130] The control electrode of the second gate drive output transistor is electrically connected with the first pull-down node, the first electrode of the second gate drive output transistor is electrically connected with the gate drive signal output end, and the second electrode of the second gate drive output transistor is electrically connected with the second low voltage end;

[0131] The control electrode of the third gate drive output transistor is electrically connected with the second pull-down node, the first electrode of the third gate drive output transistor is electrically connected with the gate drive signal output end, and the second electrode of the third gate drive output transistor is electrically connected with the second low voltage end.

[0132] As shown in Figure 9 The gate drive unit includes a pull-up node control circuit 90, a pull-up node denoising circuit 11, a pull-up control circuit 12, a pull-down node control circuit, a carry signal output circuit 22, a gate drive signal output circuit 23 and an energy storage circuit 24.

[0133] The pull-down node includes a first pull-down node PD_A and a second pull-down node PD_B, and the control voltage end includes a first control voltage end VDD_A and a second control voltage end VDD_B.

[0134] The pull-up node control circuit 90 includes a first pull-up control transistor M2A and a second pull-up control transistor M2B.

[0135] The gate of the first pull-up control transistor M2A is electrically connected with the first control voltage end VDD_A, the drain of the first pull-up control transistor M2A is electrically connected with the second pull-up node PU_1, and the source of the first pull-up control transistor M2A is electrically connected with the first pull-up node PU.

[0136] The gate of the second pull-up control transistor M2B is electrically connected with the second control voltage end VDD_B, the drain of the second pull-up control transistor M2B is electrically connected with the second pull-up node PU_1, and the source of the second pull-up control transistor M2B is electrically connected with the first pull-up node PU.

[0137] The pull-up node denoising circuit 11 includes a first pull-up node denoising transistor M7A and a second pull-up node denoising transistor M7B.

[0138] The gate of the first pull-up node denoising transistor M7A is electrically connected with the first pull-down node PD_A, the drain of the first pull-up node denoising transistor M7A is electrically connected with the second pull-up node PU_1, and the source of the first pull-up node denoising transistor M7A is electrically connected with the input terminal INPUT;

[0139] The gate of the second pull-up node denoising transistor M7B is electrically connected with the second pull-down node PD_B, the drain of the second pull-up node denoising transistor M7B is electrically connected with the second pull-up node PU_1, and the source of the second pull-up node denoising transistor M7B is electrically connected with the input terminal INPUT;

[0140] The pull-up control circuit 12 comprises a pull-up control transistor M2;

[0141] The gate of the pull-up control transistor M2 is electrically connected with a first clock signal terminal, the drain of the pull-up control transistor M2 is electrically connected with the pull-up node PU, and the source of the pull-up control transistor M2 is electrically connected with the input terminal INPUT; the first clock signal terminal is used for providing a first clock signal CLKB;

[0142] The pull-down node control circuit comprises a first pull-down control transistor M5A, a second pull-down control transistor M6A, a third pull-down control transistor M5B and a fourth pull-down control transistor M6B, wherein,

[0143] The gate of the first pull-down control transistor M5A and the drain of the first pull-down control transistor M5A are both electrically connected with the first control voltage terminal VDD_A, and the source of the first pull-down control transistor M5A is electrically connected with the first pull-down node PD_A;

[0144] The gate of the second pull-down control transistor M6A is electrically connected with the second pull-up node PU_1, the drain of the second pull-down control transistor M6A is electrically connected with the first pull-down node PD_A, and the source of the second pull-down control transistor M6A is electrically connected with the first low voltage terminal; the first low voltage terminal is used for providing a first low voltage LVGL;

[0145] The gate of the third pull-down control transistor M5B and the drain of the third pull-down control transistor M5B are both electrically connected with the second control voltage terminal VDD_B, and the source of the third pull-down control transistor M5B is electrically connected with the second pull-down node PD_B;

[0146] A gate of the fourth pull-down control transistor M6B is electrically connected with the second pull-up node PU_1, a drain of the fourth pull-down control transistor M6B is electrically connected with the second pull-down node PD_B, and a source of the fourth pull-down control transistor M6B is electrically connected with the first low voltage end;

[0147] The carry signal output circuit 22 comprises a first carry signal output transistor M4, a second carry signal output transistor M8A and a third carry signal output transistor M8B, and the gate drive signal output circuit 23 comprises a first gate drive output transistor M3, a second gate drive output transistor M9A and a third gate drive output transistor M9B;

[0148] A gate of the first carry signal output transistor M4 is electrically connected with the second pull-up node PU_1, a drain of the first carry signal output transistor M4 is electrically connected with the second clock signal end, and a source of the first carry signal output transistor M4 is electrically connected with the carry signal output end OUT_C; the second clock signal end is used for providing a second clock signal CLK;

[0149] A gate of the second carry signal output transistor M8A is electrically connected with the first pull-down node PD_A, a drain of the second carry signal output transistor M8A is electrically connected with the carry signal output end OUT_C, and a source of the second carry signal output transistor M8A is electrically connected with the first low voltage end; the first low voltage end is used for providing a first low voltage LVGL;

[0150] A gate of the third carry signal output transistor M8B is electrically connected with the second pull-down node PD_B, a drain of the third carry signal output transistor M8B is electrically connected with the carry signal output end OUT_C, and a source of the third carry signal output transistor M8B is electrically connected with the first low voltage end;

[0151] A gate of the first gate drive output transistor M3 is electrically connected with the second pull-up node PU_1, a drain of the first gate drive output transistor M3 is electrically connected with the second clock signal end, and a source of the first gate drive output transistor M3 is electrically connected with the gate drive signal output end OUT1;

[0152] A gate of the second gate drive output transistor M9A is electrically connected with the first pull-down node PD_A, a drain of the second gate drive output transistor M9A is electrically connected with the gate drive signal output end OUT1, and a source of the second gate drive output transistor M9A is electrically connected with the second low voltage end; the second low voltage end is used for providing a second low voltage VGL;

[0153] The gate of the third gate drive output transistor M9B is electrically connected with the second pull-down node PD_B, the drain of the third gate drive output transistor M9B is electrically connected with the gate drive signal output end OUT1, and the source of the third gate drive output transistor M9B is electrically connected with the second low voltage end;

[0154] The energy storage circuit 24 comprises a storage capacitor C1;

[0155] The first end of C1 is electrically connected with the second pull-up node PU_1, and the second end of C1 is electrically connected with the gate drive signal output end OUT1.

[0156] In Figure 9 In the embodiment of the gate drive unit shown in the figure, all the transistors are NMOS tubes, but are not limited thereto.

[0157] As Figure 10 The embodiment of the gate drive unit of the present application as Figure 9 The embodiment of the gate drive unit of the present application as

[0158] In the input stage S1, in the input stage S1, CLK is low voltage, CLKB is high voltage, VDD_A provides high voltage, VDD_B provides low voltage, INPUT provides high voltage, M2 is opened, the potential of PU is high voltage, M5A is opened, M2A is opened at the beginning of S1 to make PU communicate with PU_1 to charge C1 to raise the potential of PU_1, when the potential of PU_1 reaches a predetermined potential, M2A is closed; M6A and M6B are both opened, the potential of PD_A and the potential of PD_B are both low voltage, OUT1 and OUT_C both output low voltage; and since the source of M7A and the source of M7B are both electrically connected with INPUT, even if the potential of PD_A and the potential of PD_B cannot be quickly pulled down in the input stage S1, M7A and M7B are opened, PU communicates with INPUT, which promotes charging of PU and eliminates the risk of competition between PD and PU in the prior art in the input stage;

[0159] In the output stage S2, CLK is high voltage, CLKB is low voltage, VDD_A provides high voltage, VDD_B provides low voltage, INPUT provides low voltage, M2 is closed, M4 and M3 are opened, OUT1 and OUT_C both output high voltage, the potential of PU_1 is pulled up by C1, M6A and M6B are opened to make the potential of PD_A and the potential of PD_B be pulled down;

[0160] In the output stage S2, the gate potential of M2A is the high voltage provided by VDD_A, the source potential of M2A is the potential of PU, the drain potential of M2A is the potential of PU_1 (the potential of PU_1 is higher than the potential of PU), thus M2A is turned off, the potential of PU_1 can be further maintained, and M6A and M6B are fully turned on, the potential of PD_A and the potential of PD_B are low voltages, so that M7A, M7B, M8A, M8B, M9A and M9B are all turned off;

[0161] In the reset stage S3, CLK is a low voltage, CLKB is a high voltage, VDD_A provides a high voltage, VDD_B provides a low voltage, INPUT provides a low voltage, M2 is turned on, so that the potential of PU becomes a low voltage, M2A is turned on, so that the potential of PU_1 becomes a low voltage, M5A is turned on, M6A and M6B are turned off, M5B is turned off, the potential of PD_A is a high voltage, the potential of PD_B is a low voltage, M8A and M9A are turned on, M8B and M9B are turned off, M3 and M4 are turned off, OUT_C outputs LVGL, and OUT1 outputs VGL;

[0162] Before the next frame signal arrives, or, after a few frame display times, the first control voltage provided by VDD_A and the second control voltage provided by VDD_B are converted between high and low voltages, so that the denoising function is maintained to be normal, and the denoising transistors controlled by PD_A and the denoising transistors controlled by PD_B will not be subjected to positive stress for a long time to cause threshold voltage deviation and lead to failure of the gate driving unit.

[0163] The gate driving unit shown in the embodiment of the present application works as follows. Figure 9 When the duty cycle of CLK and the duty cycle of CLKB are not 0.5, there is a time period between the input stage and the output stage, and in this time period, the potential of PU_1 will not be pulled too low due to the existence of M2A and M2B.

[0164] The gate driving circuit in the embodiment of the present application comprises a plurality of the above-described gate driving units.

[0165] In a specific implementation, the gate driving unit can comprise an input end and a carry signal output end.

[0166] The input end of the gate driving unit is electrically connected with the carry signal output end of an adjacent upper gate driving unit.

[0167] The display device in the embodiment of the present application comprises the above-described gate driving circuit.

[0168] The display device provided in the embodiment of the present application can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0169] The above describes the preferred embodiments of the present application. It should be noted that, for those skilled in the art, several improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements should also be considered as falling within the scope of the present application.

Claims

1. A gate drive unit characterized by, The pull-up node denoising circuit and the pull-up control circuit are included. The pull-up node denoising circuit is electrically connected with the input end, the pull-down node and the pull-up node respectively, and is used for controlling the pull-up node and the input end to be in communication or disconnected under the control of the potential of the pull-down node. The pull-up control circuit is electrically connected with the pull-up node and the input end respectively, and is used for controlling the pull-up node and the input end to be in communication in the input stage. The pull-up node includes a first pull-up node and a second pull-up node, and the gate drive unit further includes a pull-up node control circuit. The pull-up node control circuit is electrically connected with the control voltage end, the first pull-up node and the second pull-up node respectively, and is used for controlling the first pull-up node and the second pull-up node to be in communication or disconnected under the control of the control voltage provided by the control voltage end, and is used for maintaining the potential of the second pull-up node. The gate drive unit further includes an energy storage circuit, the energy storage circuit is electrically connected with the pull-up node, and is used for maintaining the potential of the pull-up node; the pull-up node control circuit is electrically connected with the first control voltage end, the second control voltage end, the first pull-up node and the second pull-up node respectively, and is used for controlling the first pull-up node and the second pull-up node to be in communication or disconnected under the control of the first control voltage provided by the first control voltage end, and is used for controlling the first pull-up node and the second pull-up node to be in communication or disconnected under the control of the second control voltage provided by the second control voltage end, and is used for maintaining the potential of the second pull-up node. The pull-up node control circuit is used for controlling the first pull-up node and the second pull-up node to be in communication under the control of the first control voltage or the second control voltage in the input stage, so as to charge the energy storage circuit, to increase the potential of the second pull-up node, and to control the first pull-up node and the second pull-up node to be disconnected until the charging of the second pull-up node is completed. When the duty cycle of the clock signal used by the gate drive unit is not equal to 0.5, a time period is arranged between the input stage and the output stage, and the pull-up node control circuit is used for preventing the potential of the second pull-up node from being reduced due to leakage under the control of the first control voltage or the second control voltage in the time period.

2. The gate drive unit of claim 1, wherein, The pull-up node denoising circuit is electrically connected with a pull-down node, and the pull-up node denoising circuit includes a pull-up node denoising transistor; the control electrode of the pull-up node denoising transistor is electrically connected with the pull-down node, the first electrode of the pull-up node denoising transistor is electrically connected with the pull-up node, and the second electrode of the pull-up node denoising transistor is electrically connected with the input end; or The pull-down nodes comprise a first pull-down node and a second pull-down node; the pull-up node noise elimination circuit comprises a first pull-up node noise elimination transistor and a second pull-up node noise elimination transistor; a control electrode of the first pull-up node noise elimination transistor is electrically connected with the first pull-down node, a first electrode of the first pull-up node noise elimination transistor is electrically connected with the pull-up node, and a second electrode of the first pull-up node noise elimination transistor is electrically connected with the input terminal; a control electrode of the second pull-up node noise elimination transistor is electrically connected with the second pull-down node, a first electrode of the second pull-up node noise elimination transistor is electrically connected with the pull-up node, and a second electrode of the second pull-up node noise elimination transistor is electrically connected with the input terminal.

3. The gate drive unit according to claim 1 or 2, characterized in that The pull-up control circuit is further configured to reset the potential of the pull-up node in a reset stage.

4. The gate drive unit of claim 3, wherein, The pull-up control circuit comprises a pull-up control transistor; a control electrode of the pull-up control transistor is electrically connected with a first clock signal terminal, a first electrode of the pull-up control transistor is electrically connected with the pull-up node, and a second electrode of the pull-up control transistor is electrically connected with the input terminal.

5. The gate drive unit of claim 3, wherein, The pull-up control circuit comprises an input transistor and a reset transistor; a control electrode of the input transistor and a first electrode of the input transistor are both electrically connected with an input terminal, and a second electrode of the input transistor is electrically connected with the pull-up node; a control electrode of the reset transistor is electrically connected with a reset terminal, a first electrode of the reset transistor is electrically connected with the pull-up node, and a second electrode of the reset transistor is electrically connected with a first low-voltage terminal or the input terminal.

6. The gate drive unit of claim 1 or 2, wherein The circuit further comprises a pull-down node control circuit, a carry signal output circuit and a gate drive signal output circuit. The pull-down node control circuit is electrically connected with a control voltage terminal, the pull-up node, the pull-down node and a first low-voltage terminal respectively, and is configured to control the communication between the pull-down node and the control voltage terminal under the control of a control voltage provided by the control voltage terminal, and is configured to control the communication or disconnection between the pull-down node and the first low-voltage terminal under the control of the potential of the pull-up node; The carry signal output circuit is electrically connected with a carry signal output terminal, the pull-up node, the pull-down node, a second clock signal terminal and a first low-voltage terminal respectively, and is configured to control the communication between the carry signal output terminal and the second clock signal terminal under the control of the potential of the pull-up node, and is configured to control the communication between the carry signal output terminal and the first low-voltage terminal under the control of the potential of the pull-down node; The gate drive signal output circuit is electrically connected with a gate drive signal output terminal, the pull-up node, the pull-down node, the second clock signal terminal and a second low-voltage terminal respectively, and is configured to control the communication between the gate drive signal output terminal and the second clock signal terminal under the control of the potential of the pull-up node, and is configured to control the communication between the gate drive signal output terminal and the second low-voltage terminal under the control of the potential of the pull-down node; The first low voltage provided by the first low-voltage terminal is less than the second low voltage provided by the second low-voltage terminal.

7. The gate drive unit of claim 6, wherein, The pull-down nodes comprise a first pull-down node and a second pull-down node; the control voltage terminals comprise a first control voltage terminal and a second control voltage terminal; The pull-down node control circuit is configured to control the potential of the first pull-down node under the control of a first control voltage provided by the first control voltage terminal, and to control the communication or disconnection between the first pull-down node and the first low-voltage terminal under the control of the pull-up node, and to control the potential of the second pull-down node under the control of a second control voltage provided by the second control voltage terminal, and to control the electrical connection between the second pull-down node and the first low-voltage terminal under the control of the pull-up node.

8. The gate drive unit of claim 1 or 2, wherein The pull-up node de-noising circuit is electrically connected to the first pull-up node and is configured to control the communication between the first pull-up node and the input terminal under the control of the potential of the pull-down node. The pull-up control circuit is electrically connected to the first pull-up node and is configured to control the communication between the first pull-up node and the input terminal in the input stage.

9. The gate drive unit of claim 8, wherein, The pull-down node control circuit, the carry signal output circuit, the gate drive signal output circuit, and the energy storage circuit are further included. The pull-down node control circuit is electrically connected to the control voltage terminal, the second pull-up node, the pull-down node, and the first low-voltage terminal, respectively, and is configured to control the communication between the pull-down node and the control voltage terminal under the control of a control voltage provided by the control voltage terminal, and to control the communication or disconnection between the pull-down node and the first low-voltage terminal under the control of the potential of the second pull-up node. The energy storage circuit is electrically connected to the second pull-up node and is configured to maintain the potential of the second pull-up node. The carry signal output circuit is electrically connected to the carry signal output terminal, the second pull-up node, the pull-down node, the second clock signal terminal, and the first low-voltage terminal, respectively, and is configured to control the communication between the carry signal output terminal and the second clock signal terminal under the control of the potential of the second pull-up node, and to control the communication between the carry signal output terminal and the first low-voltage terminal under the control of the potential of the pull-down node. The gate drive signal output circuit is electrically connected to the gate drive signal output terminal, the second pull-up node, the pull-down node, the second clock signal terminal, and the second low-voltage terminal, respectively, and is configured to control the communication between the gate drive signal output terminal and the second clock signal terminal under the control of the potential of the second pull-up node, and to control the communication between the gate drive signal output terminal and the second low-voltage terminal under the control of the potential of the pull-down node.

10. The gate drive unit of claim 9, wherein, The pull-down nodes comprise a first pull-down node and a second pull-down node; the control voltage terminals comprise a first control voltage terminal and a second control voltage terminal; The pull-down node control circuit is configured to control the potential of the first pull-down node under the control of a first control voltage provided by the first control voltage terminal, and control the first pull-down node to be in communication or disconnected with the first low voltage terminal under the control of the second pull-up node, and control the potential of the second pull-down node under the control of a second control voltage provided by the second control voltage terminal, and control the second pull-down node to be electrically connected with the first low voltage terminal under the control of the second pull-up node.

11. A gate drive circuit, characterized by comprising: A gate drive unit comprising a plurality of stages as claimed in any one of claims 1 to 10.

12. A display device comprising: A gate drive unit as claimed in any one of claims 1 to 10.

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