Apparatus and method for controlling a display panel

Abstract

The display driver includes an internal oscillator circuit, a timing controller circuit, and a panel interface circuit. The internal oscillator circuit is disposed internal to the display driver and is configured to generate an internal oscillation signal. The timing controller circuit is configured to generate a resultant synchronization signal using an external synchronization input received from an entity external to the display driver during a first period of a frame period. The timing controller circuit is further configured to generate the resultant synchronization signal using the internal oscillation signal during a second period of the frame period, the second period being subsequent to the first period. The panel interface circuit is configured to generate a firing control signal based on the resultant synchronization signal, the firing control signal controlling a firing scan driver circuit configured to drive a plurality of firing scan lines of a display panel.

Description

Technical Field

[0001] The disclosed technologies generally relate to display drivers, display devices, and methods for controlling display panels. Background Technology

[0002] Display systems configured to display images on display panels can consume considerable power to control or drive the display panels. There is a need for technologies to reduce the power consumption of the display panels used to control or drive these systems. Summary of the Invention

[0003] The present invention is provided to present, in a simplified form, the selection of concepts further described below in the detailed embodiments. The present invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0004] In one or more embodiments, a display driver is provided. The display driver includes an internal oscillator circuit, a timing controller circuit, and a panel interface circuit. The internal oscillator circuit is disposed within the display driver and configured to generate an internal oscillation signal. The timing controller circuit is configured to generate a result synchronization signal during a first period of a frame time using an external synchronization input received from an entity outside the display driver. The timing controller circuit is also configured to generate the result synchronization signal using the internal oscillation signal during a second period of the frame time, after the first period. The panel interface circuit is configured to generate a transmit control signal based on the result synchronization signal, the transmit control signal controlling a transmit scan driver circuit configured to drive a plurality of transmit scan lines of a display panel.

[0005] In one or more embodiments, a display system is provided. The display system includes a display panel, a display driver, and a control device. The display panel includes a plurality of transmit scan lines and a transmit scan driver circuit configured to drive the plurality of transmit scan lines. The display driver includes an internal oscillator circuit disposed within the display driver and configured to generate an internal oscillation signal. The control device is configured to supply an external synchronization input during a first period of a frame time interval. The display driver is configured to generate a result synchronization signal during the first period of the frame time interval using the external synchronization input received from the control device. The display driver is also configured to generate the result synchronization signal using the internal oscillation signal during a second period of the frame time interval, after the first period of the frame time interval. The display driver is further configured to generate a transmit control signal for controlling the transmit scan driver circuit based on the result synchronization signal.

[0006] In one or more embodiments, a method for driving a display panel is provided. The method includes generating an internal oscillation signal in a display driver. The method also includes supplying an external synchronization input from an entity located outside the display driver during a first time period of a frame time interval. The method further includes generating a resulting synchronization signal by the display driver using the external synchronization input during the first time period, and generating the resulting synchronization signal by the display driver using the internal oscillation signal during a second time period of the frame time interval after the first time period. The method also generates a transmission control signal based on the resulting synchronization signal, the transmission control signal controlling transmission scan driver circuitry configured to drive a plurality of transmission scan lines of the display panel.

[0007] Other aspects of the embodiments will become apparent from the following description and the appended claims. Attached Figure Description

[0008] To enable a more detailed understanding of the foregoing features of this disclosure, a more specific description of the disclosure briefly outlined above can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate exemplary embodiments only and should therefore not be considered as limiting the scope of the invention, as other equally effective embodiments are permissible with respect to this disclosure.

[0009] Figure 1 An example configuration of a display system according to one or more embodiments is illustrated.

[0010] Figure 2 The illustration shows an example operation of a display system in normal mode according to one or more embodiments.

[0011] Figure 3 The illustration shows an example operation of a display system according to one or more embodiments in a low frame rate mode.

[0012] Figure 4 The illustration shows an example operation of a display driver in a low frame rate mode according to one or more embodiments.

[0013] Figure 5 The illustration shows an example operation of a display driver in a low frame rate mode according to one or more embodiments.

[0014] Figure 6 An example method for controlling a display panel is illustrated according to one or more embodiments.

[0015] For ease of understanding, where possible, the same reference numerals have been used to designate the same elements common to the figures. Elements disclosed in one embodiment are expected to be advantageously used in other embodiments without specific description. Suffixes may be attached to the reference numerals to distinguish the same elements from one another. The figures mentioned herein should not be construed as being drawn to scale unless specifically indicated. Furthermore, for clarity of presentation and explanation, the figures are generally simplified and details or parts are omitted. The figures and discussion are used to explain the principles discussed below, wherein the same reference numerals denote the same elements. Detailed Implementation

[0016] The following detailed description is exemplary in nature only and is not intended to limit this disclosure or its application and use. Furthermore, it is not intended to be bound by any express or implied theory presented in the foregoing background, summary of the invention, or the following detailed description.

[0017] Controlling or driving a display panel can require considerable power, so power consumption reduction is one of the issues in display systems configured to display images on the display panel.

[0018] One way to reduce the power consumption of a display system is to reduce the frequency at which the pixel circuitry in the display panel is updated. Less frequent updates to the pixel circuitry effectively reduce power consumption. The frequency at which the pixel circuitry in the display panel is updated can be measured as the frame rate. The display system can be configured such that the frame rate is variable and can be reduced when power consumption is reduced.

[0019] One issue with reducing power consumption in display systems is that a display panel containing pixel circuitry configured to emit light can be configured to continuously receive control signals to maintain an image displayed on the display panel. More specifically, the display panel may include a plurality of emission scan lines configured to control light emission from the pixel circuitry and emission scan driver circuitry configured to drive the emission scan lines.

[0020] Display panels configured in this way (such as organic light-emitting diode (OLED) display panels, micro light-emitting diode (LED) display panels, and other self-emissive display panels) can be configured to continuously receive one or more emission control signals to control emission scan driver circuitry. The generation of the emission control signals may require a timing reference. The display system can be configured to continuously supply a synchronization input as a timing reference to the display driver that drives the display panel. However, continuously supplying a synchronization input to the display driver may increase the power consumption of the display system.

[0021] This disclosure provides various techniques for reducing power consumption in a display system configured to display an image on a display panel, the display panel including a plurality of emission scan lines and emission scan driver circuitry configured to drive the plurality of emission scan lines. In one or more embodiments, the display system includes a display panel, a display driver, and a control device. The display panel includes emission scan lines and emission scan driver circuitry configured to drive the emission scan lines. The display driver includes an internal oscillator circuitry disposed within the display driver and configured to generate an internal oscillation signal. The control device is configured to supply an external synchronization input during a first period of a frame time interval. The display driver is configured to generate a result synchronization signal using the external synchronization input received from the control device during the first period of the frame time interval. The display driver is also configured to generate the result synchronization signal using the internal oscillation signal during a second period of the frame time interval, after the first period of the frame time interval. The display driver is also configured to generate a transmit control signal for controlling the emission scan driver circuitry based on the result synchronization signal. By using the internal oscillator circuitry, it is possible to mitigate (if not completely eliminate) the need to supply external synchronization input from the control device to the display driver during at least a portion of the second period of the frame time interval, thereby effectively reducing the power consumption of the control device.

[0022] Figure 1 An example configuration of a display system 1000 according to one or more embodiments is illustrated. In the illustrated embodiment, the display system 1000 includes a display module 100 and a control device 200, which is an entity disposed outside the display module 100. Examples of the control device 200 include a host, an application processor, a CPU (central processing unit), and other types of processors.

[0023] The display module 100 includes a display panel 10 and a display driver 20. The display panel 10 may include a self-emissive display panel, such as an organic light-emitting diode (OLED) display panel and a micro light-emitting diode (LED) display panel. The display driver 20 is configured to display a desired image under the control of the control device 200.

[0024] In the illustrated embodiment, the display panel 10 includes a display area 11, a gate scan driver circuit 12, and an emission scan driver circuit 13. In the illustrated embodiment, the display area 11 includes pixel circuits 14, M data lines D[1] to D[M], N gate scan lines SC[1] to SC[N], and N emission scan lines EM[1] to EM[N]. Each pixel circuit 14 is coupled to a corresponding gate scan line SC, emission scan line EM, and data line D.

[0025] Each pixel circuit 14 is configured to be programmed or updated using an output voltage received from the display driver 20. In one or more embodiments, programming or updating the pixel circuit 14 connected to the gate scan line SC [i], the emission scan line EM [i], and the data line D [j] can be achieved by asserting the gate scan line SC [i] in a state where the emission scan line EM [i] is deasserted and a gamma voltage is supplied to the data line D [j]. Each pixel circuit 14 is also configured to emit light with a luminance level corresponding to the output voltage from the display driver 20. The light emission from the pixel circuit 14 is controlled by the emission scan lines EM [1] to EM [N]. The pixel circuit 14 connected to the emission scan line EM [i] is configured to emit light when the emission scan line EM [i] is active and not emit light when the emission scan line EM [i] is deasserted.

[0026] Gate scan driver circuit 12 is configured to scan gate scan lines SC[1] to SC[N] (e.g., sequentially activating gate scan lines SC[1] to SC[N]) to select pixel circuit 14 to be programmed or updated. Gate scan driver circuit 12 is configured to activate gate scan line SC[i] when pixel circuit 14 connected to gate scan line SC[i] is programmed or updated. The assertion and deassertion of gate scan lines SC[1] to SC[N] can be controlled based on a gate start pulse signal GSTV synchronized with the gate clock GCK, wherein the gate start pulse signal GSTV and the gate clock GCK are received from display driver 20. The gate clock GCK may include a multi-phase (e.g., two-phase) clock signal. The gate start pulse signal GSTV controls the start timing of scanning the gate scan lines SC[1] to SC[N].

[0027] The emission scan driver circuit 13 is configured to scan emission scan lines EM[1] to EM[N] to control light emission from pixel circuits 14 connected to the emission scan lines EM[1] to EM[N]. The emission scan driver circuit 13 is configured to receive one or more emission control signals that control the operation of the emission scan driver circuit 13. In one or more embodiments, the emission control signals include an emission clock ECK and an emission start pulse signal ESTV. When displaying an image, a selected emission scan line among the emission scan lines EM[1] to EM[N] is made active to allow the pixel circuits 14 connected thereto to emit light, and the selection of the active emission scan line EM is sequentially shifted on the array of emission scan lines EM in sync with the emission clock ECK received from the display driver 20. The emission clock ECK may include a multiphase (e.g., two-phase) clock signal. The emission start pulse signal ESTV controls the start timing of the shift of the active emission scan line EM. The emission start pulse signal ESTV may be generated as a pulse width modulated signal, and the display brightness level of the display module 100 is controlled by the duty cycle of the emission start pulse signal ESTV. The duty cycle of the transmit start pulse signal ESTV can correspond to the ratio of a time period (during which the transmit start pulse signal ESTV is valid) to a cycle of the transmit start pulse signal ESTV. In one or more embodiments, as the duty cycle of the transmit start pulse signal ESTV increases, the ratio of the number of valid transmit scan lines EM to the total number of transmit scan lines EM increases, and the ratio of the number of light-emitting pixel circuits 14 to the total number of pixel circuits 14 also increases, thereby resulting in an increase in the display brightness level of the display module 100.

[0028] The display driver 20 is configured to receive pixel data and external synchronization input from the control device 200, and to control the display panel 10 based on the received pixel data and external synchronization input. The pixel data may include grayscale levels defined for the pixel circuitry 14. The external synchronization input serves as a timing reference to achieve timing synchronization between signals generated in the display module 100. In one or more embodiments, the external synchronization input includes a vertical synchronization (Vsync) packet defining a frame period (or a vertical synchronization period) and a horizontal synchronization (Hsync) packet defining a horizontal synchronization period. In other embodiments, the external synchronization input may include a vertical synchronization signal defining a frame period and a horizontal synchronization signal defining a horizontal synchronization period. The display driver 20 is also configured to receive a frame rate instruction specifying a frame rate from the control device 200, and to display an image on the display panel 10 at the specified frame rate.

[0029] In the illustrated embodiment, the display driver 20 includes an interface (I / F) circuit 21, an image processing circuit 22, a data driver circuit 23, an internal oscillator (OSC) circuit 24, a timing controller circuit 25, and a panel interface circuit 26.

[0030] Interface circuit 21 is configured to receive pixel data, external synchronization input, and frame rate commands from control device 200. Interface circuit 21 can also be configured to forward pixel data to image processing circuit 22 and forward external synchronization input and frame rate commands to timing controller circuit 25. In other embodiments, interface circuit 21 can be configured to process pixel data and send the processed pixel data to image processing circuit 22. In one implementation, interface circuit 21 can be configured to send a tearing effect signal TE to control device 200 under the control of timing controller circuit 25. The tearing effect signal TE can be used to notify control device 200 that display driver 20 is ready to receive pixel data and to request the start of transmitting external synchronization input.

[0031] Image processing circuit 22 is configured to process pixel data received from interface circuit 21 to generate output voltage data. The output voltage data may include a voltage value specifying the voltage level of the output voltage, which the corresponding pixel circuit 14 of display panel 10 will use for programming or updating. Processes performed by image processing circuit 22 may include color adjustment, image scaling, gamma transformation, subpixel rendering, or other processing.

[0032] The data driver circuit 23 is configured to generate an output voltage for the corresponding pixel circuit 14 provided to the display panel 10 based on the output voltage data received from the image processing circuit 22. The output voltage may have a voltage level specified by the output voltage data. The pixel circuit 14 is updated or programmed using the output voltage data provided to it.

[0033] The internal oscillation circuit 24 is configured to generate an internal oscillation signal OSC, which can be used as an internal timing reference in the display driver 20. The internal oscillation circuit 24 is located inside the display driver 20. The internal oscillation signal OSC can be a periodic square wave signal. The internal oscillation circuit 24 may include a phase-locked loop (PLL) or a digital-locked loop (DLL).

[0034] The timing controller circuit 25 is configured to provide timing control to the display driver 20 based on an external synchronization input and an internal oscillation signal OSC. In the illustrated embodiment, the timing controller circuit 25 is configured to generate one or more result synchronization signals based on the external synchronization input and the internal oscillation signal OSC. The timing controller circuit 25 can be configured to generate one or more result synchronization signals synchronized with the external synchronization input when the external synchronization input is supplied to the display driver 20. The timing controller circuit 25 can also be configured to generate one or more result synchronization signals synchronized with the internal oscillation signal OSC when the external synchronization input is not supplied to the display driver 20. In embodiments where the external synchronization input includes Hsync groups and Vsync groups, the result synchronization signals can include a result horizontal synchronization signal Hsync and a result vertical synchronization signal Vsync. The result horizontal synchronization signal Hsync can be generated synchronously with the Hsync group, and the vertical horizontal synchronization signal Vsync can be generated synchronously with the Vsync group.

[0035] Panel interface circuit 26 is configured to generate and supply a gate start pulse signal GSTV, a gate clock GCK, a transmit start pulse signal ESTV, and a transmit clock ECK synchronized with one or more result synchronization signals received from timing controller circuit 25. The transmit start pulse signal ESTV can be generated synchronously with one or more result synchronization signals via pulse width modulation (PWM). In embodiments where one or more result synchronization signals include a result horizontal synchronization signal Hsync and a result vertical synchronization signal Vsync, panel interface circuit 26 can be configured to generate the gate start pulse signal GSTV, gate clock GCK, transmit start pulse signal ESTV, and transmit clock ECK synchronized with the result horizontal synchronization signal Hsync and the result vertical synchronization signal Vsync. The transmit start pulse signal ESTV synchronized with the result horizontal synchronization signal Hsync can be generated via PWM. The gate start pulse signal GSTV and the gate clock GCK are provided to gate scan driver circuit 12, and the transmit start pulse signal ESTV and the transmit clock ECK are provided to transmit scan driver circuit 13.

[0036] In the illustrated embodiment, the timing controller circuit 25 includes an external synchronization signal generator 31, an internal horizontal synchronization signal generator 32, and a selector 33. The external synchronization signal generator 31 is configured to generate an external horizontal synchronization signal Hsync_ext using an external synchronization input received from the control device 200 as a timing reference. In embodiments where the external synchronization input includes an Hsync group, the external synchronization signal generator 31 can be configured to generate an external horizontal synchronization signal Hsync_ext synchronized with the Hsync group. The external synchronization signal generator 31 can be configured not to generate the external horizontal synchronization signal Hsync_ext when no Hsync group (or external synchronization input) is supplied from the control device 200. The external synchronization signal generator 31 can also be configured to generate a resulting vertical synchronization signal Vsync synchronized with the external synchronization input. In embodiments where the external synchronization input includes a Vsync group, the external synchronization signal generator 31 can be configured to generate a resulting vertical synchronization signal Vsync synchronized with the Vsync group.

[0037] The internal horizontal synchronization signal generator 32 is configured to generate an internal horizontal synchronization signal Hsync_int using an internal oscillation signal OSC received from the internal oscillator circuit 24 as a timing reference. The internal horizontal synchronization signal generator 32 is configured to generate the internal horizontal synchronization signal Hsync_int independently of an external synchronization input (which may include an Hsync packet). In some embodiments, the internal horizontal synchronization signal generator 32 may be configured to adjust the phase of the internal horizontal synchronization signal Hsync_int to synchronize with the external horizontal synchronization signal Hsync_ext while generating the external horizontal synchronization signal Hsync_ext using the external synchronization input. This allows the internal horizontal synchronization signal generator 32 to synchronize the internal horizontal synchronization signal Hsync_int with the external horizontal synchronization signal Hsync_ext, while simultaneously generating the external horizontal synchronization signal Hsync_ext synchronously with the external synchronization input.

[0038] Selector 33 is configured to select a resulting horizontal synchronization signal Hsync between an external horizontal synchronization signal Hsync_ext and an internal horizontal synchronization signal Hsync_int. The resulting horizontal synchronization signal Hsync is provided to panel interface circuitry 26.

[0039] In one or more embodiments, Figure 1 The display system 1000 shown has two modes: normal mode (or first mode) and low frame rate mode (or second mode). Figure 2 The illustration shows an example operation of the display system 1000 in normal mode, and Figure 3The illustration shows an example operation of the display system 1000 in a low frame rate mode. The frame rate in low frame rate mode is lower than the frame rate in normal mode. The lower frame rate compared to normal mode results in each frame segment being longer than each frame segment in normal mode. In one implementation, the control device 200 can be configured to specify the frame rate of the display module 100 and select an operating mode between normal mode and low frame rate mode depending on the specified frame rate. The control device 200 can be configured to generate a frame rate instruction indicating the determined frame rate and / or the selected operating mode, and provide the frame rate instruction to the display driver 20.

[0040] In normal mode, such as Figure 2 As shown, the control device 200 continuously supplies external synchronization inputs (which may include Vsync packets and Hsync packets), and the timing controller circuit 25 continuously generates result synchronization signals (which may include a result vertical synchronization signal Vsync and a result horizontal synchronization signal Hsync) using the external synchronization inputs. Figure 2 (and Figure 3 In the diagram, “V” represents the Vsync group and “HS” represents the Hsync group supplied sequentially to the display driver 20. The panel interface circuit 26 uses the result synchronization signal received from the timing controller circuit 25 to generate the gate start pulse signal GSTV, the gate clock GCK, the transmit start pulse signal ESTV, and the transmit clock ECK. The transmit start pulse signal ESTV can be generated synchronously with the result synchronization signal generated using an external synchronization input via PWM. The gate scan driver circuit 12 continuously scans the gate scan lines SC [1] to SC [N] in response to the gate start pulse signal GSTV and the gate clock GCK, while the transmit scan driver circuit 13 continuously scans the transmit scan lines EM [1] to EM [N] in response to the transmit start pulse signal ESTV and the transmit clock ECK.

[0041] In low frame rate mode, such as Figure 3As shown, the control device 200 is configured not to supply an external sync input after completing the scanning of gate scan lines SC [1] to SC [N] in each frame period. By not supplying the external synchronization input, the power consumption of the control device 200 is effectively reduced. In the illustrated embodiment, the control device 200 is configured to supply an external synchronization input during a first period of each frame period and not supply an external synchronization input during a second period of each frame period, wherein the second period is after the first period. The gate scan driver circuit 12 completes the scanning of gate scan lines SC [1] to SC [N] in the first period and does not scan gate scan lines SC [1] to SC [N] during the second period. Meanwhile, the transmit scan driver circuit 13 continues to scan transmit scan lines EM [1] to EM [N] to keep the image displayed on the display panel 10 during the second period.

[0042] Since no external synchronization input is supplied to the display driver 20 during the second time period, the timing controller circuit 25 is configured to generate one or more result synchronization signals using the internal oscillation signal OSC during the second time period and supply them to the panel interface circuit 26. The panel interface circuit 26 is configured to generate a transmit start pulse signal ESTV and a transmit clock ECK using the result synchronization signals. In one or more embodiments, the timing controller circuit 25 generates an internal horizontal synchronization signal Hsync_int using the internal oscillation signal OSC, and the selector 33 selects the internal horizontal synchronization signal Hsync_int generated using the internal oscillation signal OSC as the result horizontal synchronization signal Hsync during the second time period. The panel interface circuit 26 uses the result horizontal synchronization signal Hsync to generate the transmit start pulse signal ESTV and the transmit clock ECK. The transmit start pulse signal ESTV can be generated synchronously with the result horizontal synchronization signal Hsync via PWM. Generating the result horizontal synchronization signal Hsync using the internal oscillation signal OSC during the second time period enables continuous display of images on the display panel 10 during the second time period, while reducing the power consumption of the display system 1000 by not supplying an external synchronization input to the display driver 20.

[0043] Figure 4 The illustration depicts an example operation of a display driver 20 in a low frame rate mode according to one or more embodiments. In the illustrated embodiment, each frame period includes a trailing edge period, a display update period, and a leading edge period. During the display update period, the pixel circuitry 14 is updated using the output voltage received from the data driver circuitry 23.

[0044] Control device 200 continuously supplies external synchronization input to display driver 20 during a first time period of each frame period. In the illustrated embodiment, the first time period includes a trailing edge period and a display update period. External synchronization signal generator 31 of timing controller circuit 25 generates an external horizontal synchronization signal Hsync_ext and a resulting vertical synchronization signal Vsync in response to the external synchronization input. In embodiments where the external synchronization input includes a Vsync packet, control device 200 transmits a Vsync packet to display driver 20 at the beginning of each frame period, and external synchronization signal generator 31 is configured to activate the resulting vertical synchronization signal Vsync at the beginning of each frame period in response to the Vsync packet. Each frame period can be defined as a time period between two points in time at which the resulting vertical synchronization signal Vsync is activated. In embodiments where the external synchronization input includes an Hsync packet, external synchronization signal generator 31 is configured to activate the external horizontal synchronization signal Hsync_ext in response to the Hsync packet.

[0045] During the first time period, selector 33 of timing controller circuit 25 selects external horizontal synchronization signal Hsync_ext as the resulting horizontal synchronization signal Hsync, and panel interface circuit 26 generates gate start pulse signal GSTV, gate clock GCK, emission start pulse signal ESTV, and emission clock ECK synchronized with the resulting horizontal synchronization signal Hsync. Gate scan driver circuit 12 scans gate scan lines SC [1] to SC [N] in response to gate start pulse signal GSTV and gate clock GCK during display update to update or program pixel circuit 14 of display panel 10. Emission scan driver circuit 13 scans emission scan lines EM [1] to EM [N] in response to emission start pulse signal ESTV and emission clock ECK to control light emission from pixel circuit 14 during trailing edge period and display update period. Scanning of gate scan lines SC [1] to SC [N] and updating of pixel circuit 14 are completed during the display update period of the first time period.

[0046] To reduce power consumption, the control device 200 does not supply external synchronization input during a second period after the first period in each frame time interval. In the illustrated embodiment, the second period includes a leading-edge period. The length of the leading-edge period can be adjusted to achieve the frame rate specified by the control device 200. In one implementation, the frame rate is reduced by increasing the length of the leading-edge period.

[0047] The external horizontal synchronization signal Hsync_ext may be invalid during the second time period because the timing controller circuit 25 does not receive the external synchronization input. To resolve this invalidity, the timing controller circuit 25 switches the synchronization of the resulting horizontal synchronization signal Hsync from the external synchronization input to the internal oscillator signal OSC at the beginning of the second time period. In one or more embodiments, this switching is achieved by having selector 33 select the internal horizontal synchronization signal Hsync_int generated using the internal oscillator signal OSC instead of the external horizontal synchronization signal Hsync_ext as the resulting horizontal synchronization signal Hsync. The switching from the external synchronization input to the internal oscillator signal OSC can be based on the valid count of the external horizontal synchronization signal Hsync_ext. In one implementation, selector 33 can switch the resulting horizontal synchronization signal Hsync from the external horizontal synchronization signal Hsync_ext to the internal horizontal synchronization signal Hsync_int in response to the valid count of the external horizontal synchronization signal Hsync_ext reaching a predetermined number. Panel interface circuit 26 continues to generate transmit start pulse signal ESTV and transmit clock ECK synchronized with result horizontal synchronization signal Hsync, and transmit scan driver circuit 13 uses transmit start pulse signal ESTV and transmit clock ECK to continue scanning transmit scan lines EM [1] to EM [N] to continuously display images on display panel 10.

[0048] The control device 200 resumes supplying external synchronization input to the display driver 20 at the start of the next frame period. The timing controller circuit 25 activates the resulting vertical synchronization signal Vsync at the start of the next frame period in response to the external synchronization input. In one implementation, the control device 200 transmits Vsync packets to the display driver 20 at the start of the next frame period, and the timing controller circuit 25 activates the resulting vertical synchronization signal Vsync at the start of the next frame period in response to the Vsync packets. The control device 200 can then continuously transmit Hsync packets to the display driver 20 during the first period of the next frame period (e.g., the trailing edge period and the display update period).

[0049] At the start of the next frame period, the timing controller circuit 25 switches the synchronization of the resulting horizontal synchronization signal Hsync from the internal oscillator signal OSC to the external synchronization input. In one or more embodiments, this switching is achieved by causing selector 33 to select the external horizontal synchronization signal Hsync_ext instead of the internal horizontal synchronization signal Hsync_int as the resulting horizontal synchronization signal Hsync. The switching from the internal oscillator signal OSC to the external synchronization input can be based on a valid count of the internal horizontal synchronization signal Hsync_int. In one implementation, selector 33 can switch the resulting horizontal synchronization signal Hsync from the internal horizontal synchronization signal Hsync_int to the external horizontal synchronization signal Hsync_ext in response to a predetermined number of valid counts of the internal horizontal synchronization signal Hsync_int.

[0050] Because the external horizontal sync signal Hsync_ext and the internal horizontal sync signal Hsync_int are generated using different timing references, timing mismatch may exist between them. When the resulting horizontal sync signal Hsync switches between the external and internal horizontal sync signals Hsync_ext, this timing mismatch can cause interference on the displayed image. To mitigate timing mismatch, in one or more embodiments, the internal horizontal sync signal Hsync_int may be synchronized with the external horizontal sync signal Hsync_ext, while the external synchronization input is supplied from the control device 200 to the display driver 20.

[0051] Figure 5The illustration shows an example operation of a display driver 20 according to such an embodiment in a low frame rate mode. In the illustrated embodiment, an internal horizontal sync signal generator 32 adjusts the phase of the internal horizontal sync signal Hsync_int during at least a portion of a first time period to synchronize the internal horizontal sync signal Hsync_int with the external horizontal sync signal Hsync_ext. Then, a selector 33 switches the resulting horizontal sync signal Hsync from the external horizontal sync signal Hsync_ext to the internal horizontal sync signal Hsync_int at the start of a second time period. The phase adjustment of the internal horizontal sync signal Hsync_int effectively reduces the timing mismatch between the external horizontal sync signal Hsync_ext and the internal horizontal sync signal Hsync_int at the timing of the switching, thereby mitigating the undesirable impact of the switching on the displayed image. The switching from the external horizontal sync signal Hsync_ext to the internal horizontal sync signal Hsync_int can be based on a valid count of the external horizontal sync signal Hsync_ext. In one implementation, the selector 33 can switch the resulting horizontal sync signal Hsync from the external horizontal sync signal Hsync_ext to the internal horizontal sync signal Hsync_int in response to a predetermined number of valid counts of the external horizontal sync signal Hsync_ext.

[0052] During the second time period, the timing controller circuit 25 selects the internal horizontal synchronization signal Hsync_int as the resulting horizontal synchronization signal Hsync, and the panel interface circuit 26 continues to generate the transmit start pulse signal ESTV and the transmit clock ECK synchronized with the resulting horizontal synchronization signal Hsync. This allows the transmit scan driver circuit 13 to continue scanning the transmit scan lines EM[1] to EM[N] using the transmit start pulse signal ESTV and the transmit clock ECK, thereby continuously displaying images on the display panel 10.

[0053] To reduce power consumption, control device 200 does not supply external synchronization input during the first part of the second time period. At the end of the first part of the second time period, interface circuit 21, under the control of timing controller circuit 25, activates the tear effect signal TE. In response to the activation of the tear effect signal TE, control device 200 resumes supplying external synchronization input. Control device 200 continuously supplies external synchronization input during the second part of the second time period, which follows the first part. External synchronization signal generator 31 generates an external horizontal synchronization signal Hsync_ext that is synchronized with the external synchronization input during the second part of the second time period. Simultaneously, internal horizontal synchronization signal generator 32 adjusts the phase of internal horizontal synchronization signal Hsync_int during the second part of the second time period to synchronize internal horizontal synchronization signal Hsync_int with external horizontal synchronization signal Hsync_ext.

[0054] At the start of the next frame period, the timing controller circuit 25 switches the synchronization of the resulting horizontal synchronization signal Hsync from the internal oscillation signal OSC to the external synchronization input. In one or more embodiments, this switching is achieved by causing selector 33 to select the external horizontal synchronization signal Hsync_ext instead of the internal horizontal synchronization signal Hsync_int as the resulting horizontal synchronization signal Hsync. Since the internal horizontal synchronization signal Hsync_int is synchronized with the external horizontal synchronization signal Hsync_ext just before the switching, therefore Figure 5 The operation shown effectively reduces the timing mismatch between the external horizontal sync signal Hsync_ext and the internal horizontal sync signal Hsync_int at the switching timing, thereby mitigating the undesirable impact of the switching on the displayed image. The switching from the internal horizontal sync signal Hsync_int to the external horizontal sync signal Hsync_ext can be based on the valid count of the internal horizontal sync signal Hsync_int during the latter part of the second time period. In one implementation, selector 33 can switch the resulting horizontal sync signal Hsync from the internal horizontal sync signal Hsync_int to the external horizontal sync signal Hsync_ext in response to the valid count of the internal horizontal sync signal Hsync_int reaching a predetermined number during the latter part of the second time period.

[0055] Figure 6 Method 600 illustrates a method for controlling a display panel (e.g., according to one or more embodiments) according to one or more embodiments. Figure 1 The steps of the display panel 10 shown are as follows. It should be noted that the order of the steps can be changed from the order shown.

[0056] At step 601, an internal oscillation signal is generated in the display driver (e.g., display driver 20). At step 602, an external synchronization input is supplied to the display driver from a control device (e.g., control device 200) during a first time period of the frame time. At step 603, a result synchronization signal is generated by the display driver using the external synchronization input during the first time period. At step 604, a result synchronization signal is generated by the display driver using the internal oscillation signal during a second time period of the frame time, after the first time period. At step 605, a transmission control signal is generated based on the result synchronization signal to control the transmission scan driver circuit (e.g., transmission scan driver circuit 13) configured to drive the transmission scan lines of the display panel.

[0057] While many embodiments have been described, those skilled in the art who benefit from this disclosure will understand that other embodiments can be devised without departing from the scope. Therefore, the scope of the invention should be limited only by the appended claims.

Claims

1. A display driver, comprising: An internal oscillator circuit is disposed inside the display driver and configured to generate an internal oscillation signal; The timing controller circuit is configured as follows: During the first period of the frame time, an external synchronization input received from an entity outside the display driver is used to generate a result synchronization signal; as well as The result synchronization signal is generated using the internal oscillation signal during a second time period of the frame time period, the second time period following the first time period, wherein the result synchronization signal includes a result horizontal synchronization signal, the result horizontal synchronization signal including one of an external horizontal synchronization signal generated based on the external synchronization input and an internal horizontal synchronization signal generated based on the internal oscillation signal, and wherein the internal horizontal synchronization signal is synchronized with the external horizontal synchronization signal for at least a portion of the first time period; and A panel interface circuit is configured to generate a transmission control signal based on the result synchronization signal, the transmission control signal controlling a transmission scan driver circuit configured to drive multiple transmission scan lines of the display panel.

2. The display driver of claim 1, wherein the external synchronization input is not received by the display driver during at least a portion of the second time period.

3. The display driver of claim 1, wherein the timing controller circuit is further configured to switch the synchronization of the result synchronization signal from the external synchronization input to the internal oscillation signal at the start of the second time period.

4. The display driver according to claim 1, wherein the result synchronization signal further includes a result vertical synchronization signal defining a frame period.

5. The display driver according to claim 4, wherein the timing controller circuit is further configured to: During the first time period, the external horizontal synchronization signal is selected as the resulting horizontal synchronization signal; and At the start of the second time period, the resulting horizontal synchronization signal is switched from the external horizontal synchronization signal to the internal horizontal synchronization signal.

6. The display driver of claim 5, wherein switching the resulting horizontal sync signal from the external horizontal sync signal to the internal horizontal sync signal is based on a valid count of the external horizontal sync signal.

7. The display driver of claim 5, wherein the timing controller circuit is further configured to switch the resulting horizontal synchronization signal from the internal horizontal synchronization signal to the external horizontal synchronization signal at the start of a third time period following the second time period.

8. The display driver of claim 7, wherein switching the resulting horizontal sync signal from the internal horizontal sync signal to the external horizontal sync signal is based on a valid count of the internal horizontal sync signal.

9. The display driver of claim 8, wherein the second time period comprises: In the first part, during the first part, the external synchronization input is not received by the display driver; as well as The latter part, during which the display driver receives the external synchronization input, occurs after the former part. The timing controller circuit is further configured to synchronize the internal horizontal synchronization signal with the external horizontal synchronization signal during the latter part of the second time period.

10. The display driver of claim 1, wherein the transmit control signal comprises a transmit start pulse signal generated by pulse width modulation (PWM) and synchronized with the result synchronization signal.

11. A display system, comprising: The display panel includes: Multiple emission scan lines; and A transmit scan driver circuit, the transmit scan driver circuit being configured to drive the plurality of transmit scan lines; A display driver, the display driver including an internal oscillator circuit disposed within the display driver and configured to generate an internal oscillation signal; and A control device configured to supply an external synchronization input during a first time period of a frame time period. The display driver is configured as follows: During the first time period, the external synchronization input received from the control device is used to generate a result synchronization signal; and The result synchronization signal is generated using the internal oscillation signal during a second time period of the frame time period, the second time period following the first time period, wherein the result synchronization signal includes a result horizontal synchronization signal, the result horizontal synchronization signal including one of an external horizontal synchronization signal generated based on the external synchronization input and an internal horizontal synchronization signal generated based on the internal oscillation signal, and wherein the internal horizontal synchronization signal is synchronized with the external horizontal synchronization signal for at least a portion of the first time period; and Based on the result, a transmission control signal is generated to control the transmit scan driver circuit.

12. The display system of claim 11, wherein the control device is configured to not supply the external synchronization input to the display driver during at least a portion of the second time period.

13. The display system of claim 11, wherein the display driver is further configured to switch the synchronization of the result synchronization signal from the external synchronization input to the internal oscillation signal at the start of the second time period.

14. The display system of claim 11, wherein the result synchronization signal further includes a result vertical synchronization signal defining a frame period.

15. The display system of claim 14, wherein the display driver is further configured to: During the first time period, the external horizontal synchronization signal is selected as the resulting horizontal synchronization signal; and At the start of the second time period, the resulting horizontal synchronization signal is switched from the external horizontal synchronization signal to the internal horizontal synchronization signal.

16. The display system of claim 15, wherein switching the resulting horizontal synchronization signal from the external horizontal synchronization signal to the internal horizontal synchronization signal is based on a valid count of the external horizontal synchronization signal.

17. A method for driving a display panel, comprising: Generate an internal oscillation signal in the display driver; During the first time period of a frame period, an external synchronization input is supplied from a control device to the display driver, the control device being external to the display driver; The display driver uses the external synchronization input to generate a result synchronization signal during the first time period; The display driver generates the result synchronization signal using the internal oscillation signal during a second time period of the frame time period, the second time period following the first time period, wherein the result synchronization signal includes a result horizontal synchronization signal, the result horizontal synchronization signal including one of an external horizontal synchronization signal generated based on the external synchronization input and an internal horizontal synchronization signal generated based on the internal oscillation signal, and wherein the internal horizontal synchronization signal is synchronized with the external horizontal synchronization signal for at least a portion of the first time period; and Based on the result synchronization signal, a transmission control signal is generated to control the transmission scan driver circuit, which is configured to drive multiple transmission scan lines of the display panel.

18. The method of claim 17, wherein the result synchronization signal further includes a result vertical synchronization signal defining a frame period.

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