Global-local read calibration

Abstract

The present application relates to global-local read calibration. A memory device is used to calibrate voltages used to read a group of memory cells. For example, the memory device measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages separated by a first voltage interval. An estimate of a read level for the group of memory cells is determined based on the first signal and noise characteristics. The memory device then measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages separated by a second voltage interval, the second voltage interval being smaller than the first voltage interval. An optimized read voltage for the read level is calculated based on the second signal and noise characteristics.

Description

Technical Field

[0001] At least some embodiments disclosed herein relate generally to memory systems, and more particularly, but not limited to, memory systems configured to determine a voltage for reading data from a memory cell. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, the present application provides a memory device comprising: an integrated circuit package encapsulating the memory device; and a plurality of memory cell groups formed on at least one integrated circuit die; wherein, in response to a command identifying a memory cell group within the plurality of groups, the memory device is configured to measure first signal and noise characteristics of the memory cell group at first test voltages separated from each other by a first voltage interval; determine an estimate of a read level for the memory cell group based on the first signal and noise characteristics; measure second signal and noise characteristics of the memory cell group at second test voltages separated from each other by a second voltage interval, the second voltage interval being less than the first voltage interval; and calculate an optimized read voltage for the read level based on the second signal and noise characteristics.

[0004] In another aspect, the present application provides a method comprising: measuring first signal and noise characteristics of a memory cell group by reading the memory cell group at first test voltages separated from each other by a first voltage interval; determining an estimate of a read level of the memory cell group based on the first signal and noise characteristics; measuring second signal and noise characteristics of the memory cell group by reading the memory cell group at second test voltages separated from each other by a second voltage interval, the second voltage interval being smaller than the first voltage interval; and calculating an optimized read voltage for the read level based on the second signal and noise characteristics.

[0005] In another aspect, the present application provides a memory subsystem comprising: a processing device; and at least one memory device having a group of memory cells formed on an integrated circuit die; wherein the processing device is configured to transmit a command having an address identifying the group of memory cells to the memory device; wherein in response to the command, the memory device is configured to: read the group of memory cells using first test voltages separated from each other by a first voltage interval; determine first signal and noise characteristics of the group of memory cells based on responses of the group of memory cells read using the first test voltage; determine an estimate of a read level of the group of memory cells based on the first signal and noise characteristics; read the group of memory cells using second test voltages separated from each other by a second voltage interval, the second voltage interval being less than the first voltage interval; determine second signal and noise characteristics of the group of memory cells based on responses of the group of memory cells read using the second test voltage; and calculate an optimized read voltage for the read level based on the second signal and noise characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

[0007] Figure 1 An example computing system with a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 An integrated circuit memory device having a calibration circuit configured to measure signal and noise characteristics is shown according to one embodiment.

[0009] Figure 3 An example of measuring signal and noise characteristics to improve memory operation according to one embodiment is presented.

[0010] Figure 4 A technique to measure global signal and noise characteristics and identify a global read level is shown according to one embodiment.

[0011] Figures 5 to 7 Methods for calibrating a read voltage according to some embodiments are shown.

[0012] Figure 8 is a block diagram of an example computer system on which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] At least some aspects of the present disclosure relate to a memory subsystem configured to calibrate voltages used to read groups of memory cells using a global-local calibration technique. Figure 1Examples of storage devices and memory modules are described. Generally speaking, a host system can utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system can provide data to be stored at the memory subsystem and can request retrieval of data from the memory subsystem.

[0014] Integrated circuit memory cells (e.g., flash memory cells) can be programmed to store data based on their states at a threshold voltage. For example, if a memory cell is configured / programmed to be in a state that allows a significant amount of current to pass through the memory cell at a threshold voltage, the memory cell is storing a one bit; otherwise, the memory cell is storing a zero bit. Furthermore, a memory cell can store multiple bits of data by being configured / programmed in different ways at multiple threshold voltages. For example, a memory cell can store multiple bits of data by having a combination of states at multiple threshold voltages; and different combinations of states of a memory cell at threshold voltages can be interpreted as representing different states of the data bits stored in the memory cell.

[0015] However, after configuring / programming the state of an integrated circuit memory cell using a write operation to store data in the memory cell, the optimal threshold voltage for reading the memory cell may shift due to several factors such as charge loss, read disturb, cross-temperature effects (e.g., writing and reading at different operating temperatures), etc., especially when the memory cell is programmed to store multiple bits of data.

[0016] Data may be encoded with redundant information to facilitate error detection and recovery. When data encoded with redundant information is stored in a memory subsystem, the memory subsystem may detect errors in data retrieved directly from memory cells in the memory subsystem and / or recover the original data used to generate the data stored in the memory cells. When the data retrieved directly from the memory cells in the memory subsystem contains fewer errors or the bit error rate in the retrieved data is low, the recovery operation may be successful (or have a high probability of success). For example, error detection and data recovery may be performed using techniques such as error correction codes (ECC) and low-density parity check (LDPC) codes.

[0017] When data retrieved from a memory cell of a memory subsystem has too many errors to be successfully decoded, the memory subsystem can retry executing the read command using the adjusted parameters used to read the memory cell. However, searching for a parameter set through multiple rounds of calibration, reading, decoding failure, and retrying until the encoded data retrieved from the memory cell can be decoded as error-free data is highly inefficient. For example, blindly searching for the optimal read voltage is inefficient. For example, one or more commands introduced between read retries can result in longer delays in recovering data from the error.

[0018] Conventional calibration circuitry has been used to calibrate memory regions themselves, applying read level signals to account for shifts in the threshold voltages of memory cells within the memory region. During calibration, the calibration circuitry is configured to apply different test signals to the memory region to count the number of memory cells that output a specified data state in response to the test signals. Based on the counts, the calibration circuitry determines a read level offset value in response to a calibration command.

[0019] At least some aspects of the present disclosure address the above and other deficiencies using a global-local read voltage calibration technique.

[0020] For example, a coarse voltage interval (e.g., 300 mV) can be used to sample the signal and noise characteristics of a group of memory cells over a wide global voltage range where one or more read levels can be found. A read level identifies the voltage used to read the memory cells to retrieve the data stored in the memory cells. Based on the coarse sampling of the signal and noise characteristics of the group of memory cells, a rough estimate of the read level / read voltage can be determined at a valley / local minimum point in the distribution of the signal and noise characteristics over the wide global voltage range. Subsequently, for each coarse estimate of the read level, a fine voltage interval (e.g., 40 mV or 50 mV) can be used to sample the signal and noise characteristics of the group of memory cells over a narrow local voltage range identified by the coarse sampling. A calibrated read level provides an optimized voltage for reading the memory cells and, therefore, retrieving data with a reduced / minimized bit error rate. This calibrated read level, or optimized read voltage, can be determined based on a local minimum in the distribution of the signal and noise characteristics over the narrow local voltage range.

[0021] For example, in response to a command from a controller of a memory subsystem, a memory device may use a global-local calibration technique to automatically calibrate read levels of a group of memory cells and read the group of memory cells using the calibrated read levels.

[0022] For example, in response to a failure to decode data retrieved from a group of memory cells based on a previously known set of read levels, the memory device can perform a global-local read calibration to establish a new set of read levels for the group of memory cells. The global-local read calibration can be performed in response to a read retry or an explicit command / request for the global-local read calibration.

[0023] For example, when it is predicted that charge loss, read disturb, cross-temperature effects, etc. may have caused significant shifts in read levels in a group of memory cells, global-local read calibration may be performed proactively to avoid failures when decoding data retrieved from the group of memory cells.

[0024] When applying a test voltage to read the memory cells, the signal and noise characteristics measured for the memory cells can be based on the bit counts of the memory cells in the group having a predetermined state. The memory cell group can have different bit counts at different test voltages separated from each other by a predetermined voltage interval or gap. The difference between the bit counts of two adjacent test voltages provides a count difference for the voltage interval or gap between the adjacent test voltages. The optimized read voltage can be obtained at a voltage where the distribution of count differences within the voltage reaches a minimum.

[0025] When a memory cell is configured to store multiple bits, the memory cell has multiple read levels over a wide voltage range (e.g., 6V). It is efficient to sample the wide voltage range of the distribution of count differences at coarse voltage intervals (e.g., 300mV) to find the approximate location of the read level, and then use fine voltage intervals (e.g., 40-50mV) to calibrate the read level near the found approximate location with high precision. For example, the entire local voltage range used for fine calibration of the read level can be smaller than the coarse voltage interval used to find / estimate the approximate location of the read level.

[0026] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0027] The memory subsystem 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0028] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0029] Computing system 100 may include a host system 120 coupled to one or more memory subsystems 110 . Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0030] The host system 120 may include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 116) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0031] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, a Serial Attached SCSI (SAS) interface, a Double Data Rate (DDR) memory bus interface, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), a Double Data Rate (DDR) interface, a Low Power Double Data Rate (LPDDR) interface, or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via the PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] The processing device 118 of the host system 120 can be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some cases, the controller 116 can be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 116 controls communications via a bus coupled between the host system 120 and the memory subsystem 110. Generally speaking, the controller 116 can send commands or requests to the memory subsystem 110 to access the memory devices 130, 140. The controller 116 can further include interface circuitry for communicating with the memory subsystem 110. The interface circuitry can convert responses received from the memory subsystem 110 into information for the host system 120.

[0033] The controller 116 of the host system 120 can communicate with the controller 115 of the memory subsystem 110 to perform operations, such as reading, writing, or erasing data at the memory devices 130 and 140, as well as other such operations. In some cases, the controller 116 is integrated into the same package as the processing device 118. In other cases, the controller 116 is separate from the package of the processing device 118. The controller 116 and / or the processing device 118 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 116 and / or the processing device 118 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0034] Memory devices 130, 140 may include any combination of different types of non-volatile memory components and / or volatile memory components. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0035] Some examples of non-volatile memory components include NAND (or NOT AND)-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Furthermore, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0036] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as a multi-level cell (MLC), a three-level cell (TLC), a four-level cell (QLC), and a five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0037] Although non-volatile memory devices such as 3D cross-point and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0038] The memory subsystem controller 115 (or, for simplicity, the controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations (e.g., in response to commands dispatched by the controller 116 on a command bus). The controller 115 can include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (e.g., hard-coded) logic to perform the operations described herein. The controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0039] The controller 115 may include a processing device 117 (e.g., a processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0040] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is shown as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0041] Generally speaking, the controller 115 may receive commands or operations from the host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0042] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the controller 115 and decode the addresses to access the memory device 130.

[0043] In some embodiments, memory device 130 includes a local media controller 150 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 150) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] Controller 115 and / or memory device 130 may include a read manager 113 configured to identify and / or calibrate read levels for groups of memory cells based on the signal and noise characteristics of the groups of memory cells. In some embodiments, controller 115 in memory subsystem 110 includes at least a portion of read manager 113. In other embodiments, or in combination, controller 116 and / or processing device 118 in host system 120 include at least a portion of read manager 113. For example, controller 115, controller 116, and / or processing device 118 may include logic circuitry that implements read manager 113. For example, controller 115 or processing device 118 (e.g., a processor) of host system 120 may be configured to execute instructions stored in memory for performing the operations of read manager 113 described herein. In some embodiments, read manager 113 is implemented in an integrated circuit chip disposed in memory subsystem 110. In other embodiments, read manager 113 may be part of firmware of memory subsystem 110, an operating system, a device driver, or an application of host system 120, or any combination thereof.

[0045] For example, the read manager 113 implemented in the controller 115 may transmit a command to the memory device 130. In response to the command, the read manager 113 implemented in the memory device 130 is configured to measure first signal and noise characteristics of a group of memory cells by reading the group of memory cells at a plurality of first test voltages configured within a global voltage range known to contain the read levels of the memory cells. Based on the measured first signal and noise characteristics, the read manager 113 may identify an estimate of the read level having a first precision level, the first precision level corresponding to a voltage interval among the first test voltages. For each of the read level estimates, the read manager 113 may further measure second signal and noise characteristics of the group of memory cells by reading the group of memory cells at a plurality of second test voltages configured to cover a local voltage range approximately corresponding to the corresponding estimate. The read level is calibrated using a second precision level corresponding to a voltage interval among the second test voltages based on the measured second signal and noise characteristics. Because the voltage interval among the second test voltages is smaller than the voltage interval among the first test voltages, the second precision level is higher than the first precision level. The voltage intervals among the first test voltages can be configured to obtain a first precision level such that an estimate of a read level obtained from the first signal and noise characteristics is sufficient to set a local voltage range of the second test voltage to cover the calibrated read level. The voltage intervals among the first test voltages can be configured to obtain a second precision level such that data retrieved from the memory cell using the calibrated read level has a reduced / minimized bit error rate for successful decoding.

[0046] Figure 2 An integrated circuit memory device 130 is shown with a calibration circuit 145 configured to measure signal and noise characteristics according to one embodiment. For example, Figure 1 The memory device 130 in the memory subsystem 110 can use Figure 2 The integrated circuit memory device 130 is implemented.

[0047] The integrated circuit memory device 130 may be enclosed in a single integrated circuit package. The integrated circuit memory device 130 includes a plurality of groups 131, ..., 133 of memory cells that may be formed in one or more integrated circuit dies. A typical memory cell in a group 131, ..., 133 may be programmed to store one or more bits of data.

[0048] Some memory cells in the integrated circuit memory device 130 can be configured to operate together for a specific type of operation. For example, the memory cells on the integrated circuit die can be organized into planes, blocks, and pages. A plane contains multiple blocks; a block contains multiple pages; and a page can have multiple strings of memory cells. For example, the integrated circuit die can be the smallest unit that can independently execute commands or report status; the same concurrent operation can be performed in parallel on multiple planes in the integrated circuit die; a block can be the smallest unit for performing an erase operation; and a page can be the smallest unit for performing a data programming operation (writing data into a memory cell). The memory cells of each string are connected to a common bit line; and the control gates of the memory cells at the same position in the string in the block or page are connected to a common word line. Control signals can be applied to the word lines and bit lines to address individual memory cells.

[0049] The integrated circuit memory device 130 has a communication interface 147 to receive a command having an address 135 from the controller 115 of the memory subsystem 110, retrieve memory data 173 from the memory cell identified by the memory address 135, and provide at least the memory data 173 as part of a response to the command. Optionally, the memory device 130 can decode the memory data 173 (e.g., using error correction code (ECC) techniques) and provide the decoded data as part of the response to the command. The address decoder 141 of the integrated circuit memory device 130 converts the address 135 into a control signal to select a group of memory cells in the integrated circuit memory device 130; and the read / write circuit 143 of the integrated circuit memory device 130 performs an operation to determine the memory data 173 stored in the memory cell at the address 135.

[0050] The integrated circuit memory device 130 has a calibration circuit 145 configured to determine measured values ​​of signal and noise characteristics 139 of memory cells in a group (e.g., 131, ..., or 133). For example, statistics of memory cells in a group or region having a particular state under one or more test voltages can be measured to determine the signal and noise characteristics 139. Optionally, the signal and noise characteristics 139 can be provided by the memory device 130 to the controller 115 of the memory subsystem 110 via the communication interface 147.

[0051] In at least some embodiments, calibration circuit 145 and / or read manager 113 determine an optimized read voltage for a group of memory cells based on signal and noise characteristics 139 .

[0052] For example, based on the estimate of the read level, the calibration circuit 145 and / or the read manager 113 can obtain different read responses of the memory cells in the group (e.g., 131, ..., 133) by varying the test voltages used to read the memory cells. The test voltages are configured within a local range centered around the estimate to obtain a calibrated read level having a precise level represented by the voltage interval of the test voltages.

[0053] Additionally, in the absence of an estimate of the read level to configure the finely calibrated test voltages so that a limited range of test voltages covers the optimal read level, calibration circuitry 145 and / or read manager 113 may perform a global calibration to find an estimate of the read level with sufficient accuracy to locate the finely calibrated test voltages. Global calibration is similarly performed by varying the test voltages to obtain different read responses from the memory cells, but with coarse voltage intervals to improve the efficiency of searching for an estimate of the read level. For example, the coarse voltage intervals may be equal to or greater than the voltage intervals of the test voltages used for the fine calibration.

[0054] For example, calibration circuit 145 may measure signal and noise characteristics 139 on the fly while executing a command to read memory data 173 from address 135. Because signal and noise characteristics 139 are measured as part of an operation to read memory data 173 from address 135, signal and noise characteristics 139 may be used in read manager 113 with a reduced penalty for latency in executing the command to read memory data 173 from address 135.

[0055] Figure 3 An example of measuring signal and noise characteristics 139 to improve memory operation is shown according to one embodiment.

[0056] exist Figure 3 In the calibration circuit 145, different read voltages V A 、V B 、V C 、V D and V E To read the states of the memory cells in the group (eg, 131, ... or 133). In general, more or fewer read voltages may be used to produce the signal and noise characteristics 139.

[0057] Due to the different voltages applied during the read operation, the same memory cell in a group (e.g., 131, ..., or 133) can show different states. A 、V B 、V C 、V D and V E The count C of memory cells with a predetermined stateA 、C B 、C C 、C D and C E The predetermined state may be a state with a large amount of current passing through the memory cell, or a state without a large amount of current passing through the memory cell. A 、C B 、C C 、C D and C E It can be called bit counting.

[0058] Calibration circuit 145 can be configured to read the memory cells by applying a read voltage V across a group of memory cells (eg, 131, . . . or 133) one at a time. A 、V B 、V C 、V D and V E to measure the bit count.

[0059] Alternatively, the memory cell group (eg, 131, . . . or 133) may be configured as a plurality of sub-groups; and the calibration circuit 145 may be configured by applying a read voltage V A 、V B 、V C 、V D and V E To measure the bit count of the subgroup in parallel. The bit count of the subgroup is considered to represent the bit count in the entire group (e.g., 131, ... or 133). Therefore, the count C is obtained A 、C B 、C C 、C D and C E The duration can be shortened.

[0060] For example, a voltage V C To obtain the bit count C C Then, the voltages applied to the four memory cell subgroups can be boosted and modulated to V A 、V B 、V D and V E , with V A 、V B 、V D and V E The bit counts of the four subgroups are obtained as follows. The bit counts of the subgroups can be increased proportionally according to their ratios of memory cells in the group to obtain bit counts C and C, respectively. A 、C B 、C D and C E Therefore, to measure the bit count CA to C E The time can be significantly shortened.

[0061] In some embodiments, the bit count C is measured during execution of a command to read data from address 135 that maps to one or more memory cells in a group (eg, 131, . . . or 133). A 、C B 、C C 、C D and C E Therefore, the controller 115 does not need to send a separate command to request the bit count C A 、C B 、C C 、C D and C E Signal and noise characteristics of 139.

[0062] The difference between the bit counts of adjacent voltages indicates an error in reading the states of the memory cells in the group (eg, 131, ..., or 133) caused by changing the voltage used to read the memory cells.

[0063] For example, according to C A -C B Calculate the count difference D A , the counting difference D A This is because the voltage read from V A Change to V B The wrong instructions are introduced.

[0064] Similarly, D B =C B -C C ;D C =C C -C D ; and D D =C D -C E .

[0065] Based on the count difference D A 、D B 、D C and D D The obtained count difference distribution 157 represents the prediction error as a function of the read voltage. Based on the count difference distribution 157 (and / or the count difference), the read voltage 151V is optimized. O can be calculated to provide the lowest D on the count difference distribution 157 MIN The local minimum point is 153.

[0066] According to the difference D A 、D B 、D Cand D D The count difference distribution 157 represents the calculation of the optimized read voltage V O Afterwards, the read / write circuit 143 may use the optimized read voltage V O To use the optimized read voltage V O The optimized read voltage V O The estimated read level is stored for the next operation and / or transmitted to the controller 115 of the memory subsystem 110. Optionally, the count difference D A 、D B 、D C and D D Transmitted to the controller 115 of the memory subsystem 110 .

[0067] Figure 3 The generation of a statistical data set (eg, bit count and / or count difference) for use in optimizing the read voltage V O 131 or 133. In general, a group of memory cells may be configured to store more than one bit in the memory cells, and the data stored in the memory cells may be read using multiple read voltages. A statistical data set may be measured in a similar manner for each of the read voltages to identify a corresponding optimized read voltage, wherein the test voltage in each statistical data set is configured near the expected position of the corresponding optimized read voltage. Thus, the signal and noise characteristics 139 measured for a group of memory cells (e.g., 131 or 133) may include multiple statistical data sets measured for multiple threshold voltages, respectively.

[0068] For example, the controller 115 may instruct the memory device 130 to perform a read operation by providing the address 135 and at least one read control parameter. For example, the read control parameter may be a suggested read voltage / voltage.

[0069] Memory device 130 may perform a read operation by determining a state of a memory cell at address 135 at a read voltage and providing data according to the determined state.

[0070] During a read operation, calibration circuitry 145 of memory device 130 generates signal and noise characteristics 139. Data and signal and noise characteristics 139 are provided from memory device 130 to controller 115 in response. Alternatively, processing of signal and noise characteristics 139 may be performed, at least in part, using logic circuitry configured in memory device 130. For example, processing of signal and noise characteristics 139 may be partially or fully implemented using processing logic configured in memory device 130. For example, processing logic may be implemented using complementary metal oxide semiconductor (CMOS) circuitry formed below the memory cell array on an integrated circuit die of memory device 130. For example, processing logic may be formed on a separate integrated circuit die within the integrated circuit package of memory device 130, the separate integrated circuit die being connected to the integrated circuit die having the memory cells using through silicon vias (TSVs) and / or other connection technologies.

[0071] The signal and noise characteristics 139 may be determined based at least in part on the read control parameters. For example, when the read control parameter is a suggested read voltage V for reading a memory cell at address 135, C When the calibration circuit 145 calculates the read voltage V around the recommended read voltage according to the voltage interval, A 、V B 、V C 、V D and V E .

[0072] The signal and noise characteristics 139 may include the bit count C A 、C B 、C C 、C D and C E Alternatively or in combination, the signal and noise characteristic 139 may include the count difference D A 、D B 、D C and D D .

[0073] The accuracy of the calibration / optimization read voltage 151 is subject to the test voltage V A 、V B 、V C 、V D and V E The voltage interval is limited. Reducing the voltage interval can improve the accuracy of calibrating / optimizing the read voltage 151. However, reducing the voltage interval reduces the voltage range V A to V E , and thus increase the voltage range V A to V EWhen the optimized reading voltage 151 is within the voltage range V A to V E When the count difference D A 、D B 、D C and D D It may not be sufficient to accurately determine the optimized read voltage 151 .

[0074] In some cases, there is a lack of sufficient voltage to locate the test voltage range V A to V E To cover the optimized read voltage V O The accuracy of the reading level estimate V C For example, charge loss, read disturbance, cross-temperature effects, etc. may cause large shifts in the read level. Such previously known read levels are not accurate enough to be used as estimates of the read level. A 、V B 、V C 、V D and V E Use the voltage interval to configure the fine-calibration test voltage. Using the fine-calibration voltage interval to search for the read level is inefficient.

[0075] In this case, a global search for an estimate of the read level can be performed using a larger voltage interval, e.g. Figure 4 As shown in .

[0076] Figure 4 A technique to measure global signal and noise characteristics and identify a global read level is shown according to one embodiment.

[0077] Figure 4 The count difference distribution 157 in FIG. 1 shows the optimized read voltage V for a memory cell group (eg, 131 or 133). O1 、V O2 、V O3 Generally speaking, the optimal read voltage V O1 、V O2 、V O3 The voltage range can be wide (e.g., 6V). A series of test voltages V1, V2, V3, ..., V n For example, the count difference 161 can be measured for the test voltage V1; the count difference 162 can be measured for the test voltage V2; the count difference 163 can be measured for the test voltage V3; and the count difference 164 can be measured for the test voltage V n The measured count difference is 169. Figure 3 The count difference D in Ato D D The count differences 161 to 169 are measured in a similar manner.

[0078] exist Figure 4 The test voltage V1 to V n The voltage interval is greater than Figure 3 The test voltage V A to V E For example, to improve the search optimization reading voltage V O1 、V O2 、V O3 Estimated efficiency, test voltage V1 to V n The voltage interval can be equal to or greater than Figure 3 The test voltage range V A to V E .

[0079] For example, the optimized read voltage V O1 、V O2 、V O3 Estimation of V C1 、V C2 、V C3 The test voltage is determined to have a count difference lower than that of its neighbors on both sides. For example, the count difference 163 at the test voltage V3 is lower than the count difference 162 at the test voltage V2 and the count difference 164 at the test voltage V4 to reach a local minimum on the set of count differences 161 to 169; and therefore, the test voltage V3 can be selected to correspond to the optimized read voltage V O1 An estimate of the read voltage level V C1 . Estimating V C1 Used as Figure 3 The center test voltage V C , can be based on Figure 3 V in A to V E The accuracy level of the voltage interval is used to calibrate / calculate the optimized reading voltage V O .

[0080] Optionally, a more precise / accurate estimate of V can be calculated based on a collection of count differences centered around the test voltage V3. C1 For example, an interpolation of the count difference distribution 157 within test voltages V2 to V4 centered around test voltage V3 may be used to determine a more precise / accurate estimate of V that reaches a local minimum in the interpolation. C1 For example, an interpolation of count difference distribution 157 within test voltages V1 to V5 (within another set of test voltages near test voltage V3 having the lowest count difference in the set) may be used to determine a more precise / accurate estimate V that reaches a local minimum in the interpolation.C1 .

[0081] Since the estimated V is determined based on the count difference 161 at V1, the count difference 162 at V2, the count difference 163 at V3, the count difference 164 at V4, and / or the count difference 165 at V5 C1 , so it is estimated that V C1 The error is less than the voltage interval among the test voltages V1 to V5. C1 The test voltage range is centered at V A to V E Expected coverage optimized read voltage / level V O1 .

[0082] In some embodiments, the calibration circuit 145 and / or the read / write circuit 143 may be modulated by a boost voltage. Figure 3 One of the test voltages is changed to the test voltage range V A to V E Another voltage within the range to shorten the time for reading the memory cell at different test voltages. O After that, the applied voltage can be further boosted and modulated to the optimized reading voltage V O to obtain memory data 173 at the corresponding read level.

[0083] The voltage range that can be achieved through boost modulation may be limited. For example, the calibration circuit 145 and / or the read / write circuit 143 may not be able to change the applied voltage from one test voltage (e.g., V1) to Figure 4 Another test voltage (e.g., V2) in.

[0084] Optionally, calibration circuit 145 and / or read / write circuit 143 may read subgroups of memory cells in a group (eg, 131 or 133) in parallel at different voltages to shorten the time required to measure the voltage. Figure 4 The time of the count difference 161 to 169 in . The statistics (eg, bit counts) measured for the subgroups can be scaled to obtain statistics for the group.

[0085] Figures 5 to 7 Methods for calibrating a read voltage according to some embodiments are shown. Figure 5 、 6 The methods of and / or 7 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software / firmware (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, Figure 5 、 6 or 7, at least in part by Figure 1Controller 115 or Figure 2 The processing logic in the memory device 130 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0086] For example, in Figure 1 The memory subsystem 110 shown in FIG. Figure 2 The calibration circuit 145 of the integrated circuit memory device 130 and the use of Figure 3 and 4 Global-local readout calibration technique is used to perform Figures 5 to 7 Method

[0087] exist Figure 5 In block 181 , the read manager 113 measures a coarse count difference distribution over a global voltage range having multiple read levels.

[0088] For example, the global voltage range can be the entire voltage range V1 to V n , where the optimized read voltage V O1 、V O2 、V O3 All read levels, such as Figure 5 As shown in .

[0089] Alternatively, the global voltage range can be the entire voltage range V1 to V n part, where the optimized read voltage V O1 、V O2 、V O3 One or more of the same read levels.

[0090] In block 183, the read manager 113 determines the read level V according to the local minimum point in the coarse count difference distribution. C1 、V C2 、V C3 wait.

[0091] For example, the read level V C1 、V C2 、V C3 The accuracy of the measurement can be controlled by the voltage interval used to measure the coarse count difference distribution within the global voltage range. For efficiency, the accuracy is calibrated to be low so that if the read level V is used C1 、V C2 、V C3If the memory cell group is read by the read level V, then it is very likely that the bit error rate in the retrieved memory data 173 is so high that decoding (e.g., using error correction code (ECC) techniques) will fail. However, the accuracy is calibrated to be sufficient to allow the memory cell group to be read by the read level V. C1 、V C2 、V C3 etc. The fine calibration is successful in each identified local area.

[0092] For example, the voltage interval for measuring the coarse count difference distribution within the global voltage range may be between 200 mV and 400 mV.

[0093] In block 185 , the read manager 113 measures a fine count difference distribution over the position voltage range for each of the read levels.

[0094] For example, the read level V C1 Used as a basis Figure 3 The center test voltage V in the fine calibration C .according to Figure 3 The test voltage range V in fine calibration A to V E It can be equal to or smaller than the voltage interval used to measure the coarse count difference distribution within the global voltage range. Figure 3 The voltage intervals used to measure the fine count difference distribution can be configured to allow voltage variations via boost modulation and / or fine calibration of read levels with precision so that memory data 173 retrieved using the calibrated read levels can be successfully decoded (e.g., using error correction code (ECC) techniques).

[0095] In block 187, the read manager 113 calculates the corresponding read level (eg, V C1 、V C2 or V C3 ) of the optimized read voltage V O .

[0096] Individual read level V C1 、V C2 、V C3 The measurement of the fine count difference distribution may be performed after the measurement of the entire coarse count difference distribution within the global voltage range.

[0097] Alternatively, individual read levels V C1 、V C2 、V C3 The measurement of the fine count difference distribution of V can be interleaved with the measurement of the entire coarse count difference distribution over the global voltage range. For example, in detecting / finding the read level V based on the count difference at a voltage close to V3,C1 Afterwards, the read manager 113 may continue to measure other count differences to detect / find the next read level V C2 Previously executed according to Figure 3 A fine calibration is performed to determine the read level V C1 The optimized read voltage V O1 .

[0098] exist Figure 6 In block 201, the read manager 113 generates a read signal in a plurality of optimized read voltages (e.g., V O1 、V O2 、V O3 The first signal and noise characteristics of the memory cell group are measured at a first voltage interval (eg, 300 mV) within a voltage range (eg, 6 V) of 10V to 10V.

[0099] For example, the first signal and noise characteristics may be as follows Figure 5 As discussed in and / or Figure 4 The rough count difference distribution is shown in .

[0100] Optionally, read manager 113 and / or calibration circuit 145 can measure first signal and noise characteristics of a group of memory cells by measuring subgroups of memory cells in parallel. For example, a group of memory cells can be divided into four subgroups. Each of the subgroups can be read using a different test voltage to obtain a bit count. It can be assumed that the bit count in a subgroup or the entire group is proportional to the number of memory cells in the subgroup or the entire group. Therefore, the bit count of the subgroup can be proportionally adjusted according to the ratio between the number of memory cells in the subgroup and the number of memory cells in the entire group to obtain the bit count of the group. Thus, the bit count of the group under four different test voltages can be obtained in parallel.

[0101] In block 203, the read manager 113 identifies a corresponding optimized read voltage (eg, V O1 、V O2 、V O3 etc.) (e.g., V C1 、V C2 、V C3 etc.), such as Figure 4 As shown in .

[0102] In block 205, the read manager 113 generates a read request in response to a plurality of estimates (e.g., V C1 、V C2 、V C3 etc.) (e.g., V C) is centered at a second voltage interval (e.g., 40 mV or 50 mV) that is smaller than the first voltage interval (e.g., 300 mV) and measures second signal and noise characteristics of the memory cell group.

[0103] In block 207, the read manager 113 calculates a signal corresponding to the estimate (eg, V C ) of the optimized read voltage (e.g., V O ),like Figure 3 As shown in .

[0104] In block 209, the read manager 113 uses the optimized read voltage (e.g., V O )Read the memory cell group.

[0105] In block 211, the read manager 113 generates a query for a plurality of estimates (e.g., V C1 、V C2 、V C3 Each of the blocks 200 and 201 makes a decision to repeat the operations of blocks 205 to 209.

[0106] In block 213, the read manager 113 generates a read request corresponding to the estimate (e.g., V C1 、V C2 、V C3 etc.) of the optimized read voltage (e.g., V O1 、V O2 、V O3 etc.) to decode the memory data 173 retrieved from the memory cell group.

[0107] Optionally, the read manager 113 identifies an estimate in block 203 and generates a query for a plurality of estimates (eg, V C1 、V C2 、V C3 Each of the blocks 200 and 201 makes a decision to repeat the operations of blocks 203 to 209.

[0108] exist Figure 7 In block 301, the read manager 113 measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages spaced apart from each other by first voltage intervals.

[0109] For example, the first voltage interval may be between 200 mV and 400 mV (eg, 300 mV).

[0110] For example, the first signal and noise characteristics respectively identify the first test voltage based on the bit count of the first test voltage (eg, Figure 4 V1, V2, V3, V4, V5, ..., Vn ) (e.g., Figure 4 The distribution shown in 157).

[0111] Generally speaking, the respective bit counts at the test voltage identify a number of memory cells in the group that provide predetermined bit values ​​when read at the test voltage; and the respective count differences between two adjacent test voltages respectively represent the differences between the bit counts at the adjacent test voltages.

[0112] The bit count of a memory cell group can be measured by reading the memory cells in the entire group or by reading a subgroup of memory cells as a sample. In addition, the subgroups can be read in parallel at different voltages to shorten the time period for measuring the signal and noise characteristics of the memory cell group.

[0113] In block 303, the read manager 113 determines an estimate of a read level for the group of memory cells based on the first signal and noise characteristics.

[0114] For example, the distribution of count differences identified by the first signal and noise characteristics (eg, Figure 4 The local minimum of the distribution 157 in the φ(R) determines the read level (e.g., Figure 4 V in C1 、V C2 or V C3 ) estimates, such as Figure 4 As shown in .

[0115] In block 305 , the read manager 113 measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages spaced apart from each other by a second voltage interval that is less than the first voltage interval.

[0116] For example, the second signal and noise characteristics respectively identify the second test voltage based on the bit count of the second test voltage (eg, Figure 3 V in A to V E ) (e.g., Figure 3 The distribution shown in 157).

[0117] For example, the second voltage interval may be between 40mV and 50mV. Therefore, the entire voltage range of the second test voltage (eg, Figure 3 V in A to V E ) may be no greater than the first voltage interval (eg, Figure 4 the gap between V1 and V2 in the image).

[0118] For example, the second voltage interval (eg, 40 mV to 50 mV) is smaller so that at the second test voltage (eg, V A to V E ) and applied to a group of memory cells during a read operation (e.g., to determine a bit count) A 、V C or V E ) can be adjusted to a voltage range (e.g., V A to V E ) within different read voltages (e.g., V B 、V C or V O ) (eg, to determine a bit count or read memory data 173 ). In contrast, a test voltage having a first voltage interval (eg, 300 mV) may be outside a range achievable via boost modulation.

[0119] For example, the second test voltage (eg, Figure 3 V in A to V C to V E ) can read the level (for example, Figure 4 V in C1 、V C2 or V C3 ) is centered on the estimate.

[0120] In block 307 , the read manager 113 calculates an optimized read voltage for the read level based on the second signal and noise characteristics.

[0121] For example, the distribution of count differences identified by the second signal and noise characteristics (eg, Figure 3 The optimized read voltage (e.g., Figure 3 V in O ),like Figure 3 As shown in .

[0122] For example, in determining the optimal read voltage (e.g., Figure 3 V in O ) after which the memory device 130 may be powered from a test voltage (eg, V A or V E ) to the optimal read voltage (e.g., V O ) to use an optimized read voltage (e.g., V O )Read the memory cell group.

[0123] Figure 8An example machine is shown of a computer system 400 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 400 may correspond to a host system (e.g., Figure 1 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 10) or may be used to perform operations of the read manager 113 (e.g., to execute instructions to perform operations corresponding to the reference Figures 1 to 7 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0124] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), A ), a cellular phone, a network appliance, a server, a network router, a switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets of instructions) to perform any one or more of the methodologies discussed herein.

[0125] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system 418 that communicate with each other via a bus 430 (which may include multiple buses).

[0126] Processing device 402 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements another instruction set or a combination of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may further include a network interface device 408 for communicating via a network 420.

[0127] The data storage system 418 may include a machine-readable medium 424 (also referred to as a computer-readable medium) on which is stored a set of one or more instructions 426 or software embodying any one or more of the methodologies or functions described herein. The instructions 426 may also reside, completely or at least partially, within the main memory 404 and / or within the processing device 402 during execution thereof by the computer system 400, with the main memory 404 and the processing device 402 also constituting machine-readable storage media. The machine-readable medium 424, the data storage system 418, and / or the main memory 404 may correspond to Figure 1 Memory subsystem 110.

[0128] In one embodiment, instructions 426 include instructions for implementing instructions corresponding to read manager 113 (e.g., referring to Figures 1 to 7 The term "machine-readable storage medium" includes instructions for the functionality of the read manager 113 described herein. Although the machine-readable medium 424 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0129] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0130] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0131] The present disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, CD-ROMs, C D - ROM and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each connected to the computer system bus.

[0132] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the following description. Furthermore, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0133] The present disclosure can be provided as a computer program product or software, which can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0134] In this specification, various functions and operations are described as being performed by computer instructions or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that the intention of such expressions is that the functions are derived from the execution of computer instructions by one or more controllers or processors such as microprocessors. Alternatively or in combination, functions and operations can be implemented using dedicated circuit systems with or without software instructions, such as using application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). Embodiments can be implemented using hard-wired circuit systems without software instructions or in combination with software instructions. Therefore, the technology is not limited to any specific combination of hardware circuit systems and software, nor to any specific source of instructions executed by the data processing system.

[0135] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A memory device comprising: an integrated circuit package encapsulating the memory device; as well as a plurality of memory cell groups formed on at least one integrated circuit die; wherein in response to a command identifying a group of memory cells within the plurality of groups, the memory device is configured to, measuring first signal and noise characteristics of the memory cell group at first test voltages spaced apart from each other by a first voltage interval; determining an estimate of a read level for the group of memory cells based on the first signal and noise characteristics; measuring second signal and noise characteristics of the memory cell group at second test voltages spaced apart from each other by a second voltage interval, the second voltage interval being less than the first voltage interval; as well as An optimized read voltage for the read level is calculated based on the second signal and noise characteristics. 2 . The memory device of claim 1 , wherein a voltage range of the second test voltage does not exceed the first voltage interval.

3. The memory device of claim 2, wherein the first voltage interval is between 200 mV and 400 mV; and the second voltage interval is between 40 mV and 50 mV.

4. The memory device of claim 2 , wherein the first signal and noise characteristics identify a distribution of count differences within the first test voltage based on bit counts for the first test voltage, respectively; wherein each respective bit count at a test voltage identifies a number of memory cells in the group that provide predetermined bit values ​​when read at the test voltage; and wherein each respective count difference between two adjacent test voltages represents a difference between the bit counts at the adjacent test voltages, respectively. 5 . The memory device of claim 4 , wherein the second signal and noise characteristics identify a distribution of count differences within the second test voltage based on bit counts for the second test voltage, respectively.

6. The memory device of claim 5, wherein the second test voltage is centered about the estimate of the read level. 7 . The memory device of claim 6 , wherein the optimized read voltage is calculated according to a local minimum of the distribution of count differences identified by the second signal and noise characteristic.

8. The memory device of claim 6, wherein the estimate of a read level is determined from a local minimum of the distribution of count differences identified by the first signal and noise characteristic.

9. The memory device of claim 6, wherein a test voltage within the voltage range of the second test voltage and applied to the memory cell group during a read operation is adjustable to a different read voltage within the voltage range via boost modulation.

10. A method for memory operation, comprising: measuring first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages spaced apart from each other by first voltage intervals; determining an estimate of a read level for the group of memory cells based on the first signal and noise characteristics; measuring second signal and noise characteristics of the memory cell group by reading the memory cell group at second test voltages spaced apart from each other by a second voltage interval, the second voltage interval being less than the first voltage interval; as well as An optimized read voltage for the read level is calculated based on the second signal and noise characteristics. The method of claim 10 , wherein the range of the second test voltage is smaller than the first voltage interval.

12. The method of claim 10, wherein the first voltage interval is between 200 mV and 400 mV; And the second voltage interval is between 40mV and 50mV.

13. The method according to claim 10, further comprising: The group of memory cells is read using the optimized read voltage.

14. The method of claim 13, wherein the first signal and noise characteristics identify a distribution of count differences within the first test voltage based on bit counts of the first test voltage, respectively; wherein the second signal and noise characteristics respectively identify a distribution of count differences within the second test voltage based on bit counts of the second test voltage; wherein each respective bit count at a test voltage identifies a number of memory cells in the group that provide predetermined bit values ​​when read at the test voltage; and Each corresponding count difference between two adjacent test voltages represents a difference between bit counts at the adjacent test voltages.

15. A method according to claim 14, wherein the second test voltage is centered about the estimate of the read level; the optimized read voltage is calculated based on a local minimum of the distribution of count differences identified by the second signal and noise characteristics; and the estimate of the read level is determined based on a local minimum of the distribution of count differences identified by the first signal and noise characteristics.

16. A memory subsystem comprising: processing device; as well as at least one memory device having a group of memory cells formed on an integrated circuit die; wherein the processing device is configured to transmit a command having an address identifying the group of memory cells to the memory device; wherein in response to the command, the memory device is configured to: reading the memory cell groups using first test voltages spaced apart from each other by a first voltage interval; determining first signal and noise characteristics of the group of memory cells based on responses of the group of memory cells read using the first test voltage; determining an estimate of a read level for the group of memory cells based on the first signal and noise characteristics; reading the memory cell group using second test voltages spaced apart from each other by a second voltage interval, the second voltage interval being smaller than the first voltage interval; determining second signal and noise characteristics of the group of memory cells based on responses of the group of memory cells read using the second test voltage; as well as An optimized read voltage for the read level is calculated based on the second signal and noise characteristics.

17. The memory subsystem of claim 16, wherein the range of the second test voltage is smaller than the first voltage interval.

18. The memory subsystem of claim 16, wherein the first voltage interval is between 200 mV and 400 mV; and the second voltage interval is between 40 mV and 50 mV.

19. The memory subsystem of claim 16 , wherein in response to the command, the memory device is further configured to: The group of memory cells is read using the optimized read voltage.

20. The memory subsystem of claim 19, wherein the first signal and noise characteristics identify a distribution of count differences within the first test voltage based on bit counts for the first test voltage, respectively; wherein the second signal and noise characteristics respectively identify a distribution of count differences within the second test voltage based on bit counts of the second test voltage; and wherein each respective bit count at a test voltage identifies a number of memory cells in the group that provide predetermined bit values ​​when read at the test voltage; and wherein each respective count difference between two adjacent test voltages respectively represents a difference between the bit counts at the adjacent test voltages; and wherein the second test voltage is centered about the estimate of the read level; and the optimized read voltage is calculated based on a local minimum of the distribution of count differences identified by the second signal and noise characteristics; and determining the estimate of a read level from a local minimum of the distribution of count differences identified by the first signal and noise characteristic.

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