A 4T3R circuit structure for realizing high-speed logic operations based on resistive random access memory

Abstract

The present invention discloses a 4T3R circuit structure for implementing high-speed logical operations based on a resistive random access memory (RRAM), including that the bottom electrode of RRAM1 is electrically connected to the drain of NMOS transistor M1 and the drain of NMOS transistor M2; the gate of M1 is electrically connected to WLA; the gate of M2 is electrically connected to WLC; the sources of NMOS transistor M2 and NMOS transistor M3 are both electrically connected to the top electrode of RRAM2; the gate of NMOS transistor M3 is electrically connected to WLB; the bottom electrode of RRAM3 is electrically connected to the drain of NMOS transistor M4; the gate of M4 is electrically connected to WLS; the source of NMOS transistor M1, the bottom electrode of RRAM2, and the source of NMOS transistor M4 are all electrically connected to SL and resistor R1, and the other end of resistor R1 is grounded. The present invention uses RRAM to implement basic logical operations in in-memory computing, improving the logical operation efficiency of the circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of resistive random access memory (RRAM), and particularly to a 4T3R circuit structure for realizing high-speed logic operations based on a resistive random access memory. Background Art

[0002] In recent years, artificial intelligence algorithms have developed rapidly and demonstrated significant performance advantages in fields such as image processing and speech recognition. In traditional von Neumann architecture computers, the separation of the computing unit and the storage unit is an important factor hindering the development of these applications. When the degree of parallelism of computing increases continuously, the bandwidth required for data transmission limits the computing speed, which is usually referred to as the von Neumann bottleneck. To overcome the drawbacks brought by these traditional von Neumann architectures, computing in memory (CIM) has emerged. As a non-von Neumann architecture, CIM is considered to be one of the future mainstream trends for hardware acceleration of artificial intelligence algorithms. The collaborative work of the storage unit and the logic unit is the key to the hardware acceleration of artificial intelligence algorithms. Abandoning the separation of the storage unit and the logic unit in the traditional structure effectively avoids the bandwidth limitation of data transmission, thereby improving the computing speed of the circuit. In theory, CIM has multiple working modes. Different from traditional logic operations, CIM uses the current storage state of the storage unit during the operation process. The actual working modes can be divided into three types: Mode 1, the calculation result is related to both the input and the storage state, and the result is directly output; Mode 2, the calculation result is related to both the input and the storage state, and the result is saved in the storage unit; Mode 3, the calculation result is related to both the input and the storage state, and the result is output and the storage state is updated simultaneously. The CIM technology breaks through the limitations of the traditional von Neumann architecture, optimizes the structures of the storage unit and the logic unit, alleviates the data transfer problem, and thus significantly reduces the energy consumption.

[0003] Non-volatile storage devices are the key to the implementation of CIM. For non-volatile storage devices, such as NOR Flash, RRAM, etc., analog storage, non-volatility, and low power consumption are their significant advantages, which also reflect the core competitiveness of CIM solutions. In the scope of non-volatile memories, NOR Flash is a relatively mature memory technology, and there are mature tools for process parameters, device models, and module designs. Therefore, its CIM solution will be realized first. In the future, the core design of the system architecture of NOR Flash can be migrated to new non-volatile devices such as RRAM, so as to achieve technological iteration and innovation and product continuation. However, in the prior art, the logic operation efficiency of the in-memory computing circuit implemented by RRAM is relatively low and needs to be improved.

[0004] In view of this, the present invention is specifically proposed. Summary of the Invention

[0005] The objective of the present invention is to provide a 4T3R circuit structure for realizing high-speed logical operations based on a resistive random access memory (RRAM) to solve the above-mentioned technical problems existing in the prior art. The present invention uses RRAM to realize basic logical operations in in-memory computing, improving the logical operation efficiency of the circuit.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] A 4T3R circuit structure for realizing high-speed logical operations based on a resistive random access memory (RRAM) includes 4 NMOS transistors, 3 resistive random access memories, and 1 resistor R1. The 4 NMOS transistors are respectively defined as M1, M2, M3, and M4. The 3 resistive random access memories are respectively defined as RRAM1, RRAM2, and RRAM3. The resistive random access memories RRAM1, RRAM2, and RRAM3 have the same orientation, with the top electrode facing upward and the bottom electrode facing downward. The bottom electrode of the resistive random access memory RRAM1 is electrically connected to the drain of the NMOS transistor M1 and the drain of the NMOS transistor M2. The gate of the NMOS transistor M1 is electrically connected to the signal line WLA. The gate of the NMOS transistor M2 is electrically connected to the signal line WLC. The source of the NMOS transistor M2 and the source of the NMOS transistor M3 are both electrically connected to the top electrode of the resistive random access memory RRAM2. The gate of the NMOS transistor M3 is electrically connected to the signal line WLB. The bottom electrode of the resistive random access memory RRAM3 is electrically connected to the drain of the NMOS transistor M4. The gate of the NMOS transistor M4 is electrically connected to the signal line WLS. The source of the NMOS transistor M1, the bottom electrode of the resistive random access memory RRAM2, and the source of the NMOS transistor M4 are all electrically connected to the signal line SL and are also all electrically connected to one end of the resistor R1, while the other end of the resistor R1 is grounded.

[0008] Preferably, by controlling the conduction and cutoff of the NMOS transistors M1, M2, M3, and M4 through the signal lines WLA, WLC, WLB, and WLS respectively, at least one of the following logical operations of the circuit structure can be realized:

[0009] (1) By turning on WLA and WLB and turning off WLC, the parallel connection of the resistive random access memories RRAM1 and RRAM2 is realized, thereby realizing the OR operation of the circuit structure.

[0010] (2) By turning off WLA and WLB and turning on WLC, the series connection of the resistive random access memories RRAM1 and RRAM2 is realized, thereby realizing the AND operation of the circuit structure.

[0011] (3) By turning on WLA, WLB, and WLS and turning off WLC, the parallel connection of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is achieved, thereby implementing the writing of the logical NOR operation result of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 into the resistive random access memory RRAM3;

[0012] (4) By turning off WLA and WLB and turning on WLC and WLS, the series connection of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is achieved, thereby implementing the writing of the logical NAND operation result of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 into the resistive random access memory RRAM3;

[0013] (5) First, by turning off WLA and WLB and turning on WLC and WLS, the series connection of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is achieved, thereby writing the logical NAND operation result of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 into the resistive random access memory RRAM3. Then, by turning on WLA, WLB, and WLS and turning off WLC, the structure in which the resistive random access memory RRAM1 is in parallel with the resistive random access memory RRAM2 is connected in series with the resistive random access memory RRAM3, thereby implementing the exclusive OR operation of the circuit structure.

[0014] Preferably, the top electrode of the resistive random access memory RRAM1 is electrically connected to the signal line BLA; the drain of the NMOS transistor M3 is electrically connected to the signal line BLB; the top electrode of the resistive random access memory RRAM3 is electrically connected to the signal line BL0.

[0015] Compared with the prior art, the present invention constructs a 4T3R circuit structure using 4 NMOS transistors, 3 resistive random access memories, and 1 resistor R1. By storing data in the resistive random access memories and then controlling the on and off of the NMOS transistors M1, M2, M3, and M4 through the signal lines WLA, WLC, WLB, and WLS respectively, the series and parallel connections of the resistive random access memories RRAM1, RRAM2, and RRAM3 are further controlled. Thus, according to the characteristics of the high resistance state and low resistance state of the RRAM, the 4T3R circuit structure can implement basic logical operations such as OR operation, AND operation, NOR operation, NAND operation, and exclusive OR operation in in-memory computing. Finally, the stored data is read out, which improves the logical operation efficiency of the data. Description of the Drawings

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic diagram of the overall structure of the 4T3R circuit structure for implementing high-speed logic operations based on a resistive random access memory provided by the embodiments of the present invention;

[0018] Figure 2 It is a circuit diagram of the NAND circuit for writing to RRAM3 used in the embodiments of the present invention;

[0019] Figure 3 It is a circuit diagram when the NAND write operation is open in the embodiments of the present invention;

[0020] Figure 4 It is a circuit diagram of the NOR circuit for writing to RRAM3 used in the embodiments of the present invention;

[0021] Figure 5 It is an operation timing diagram provided by the embodiments of the present invention;

[0022] Figure 6 It is a simulation result diagram of the NAND RRAM resistance state provided by the embodiments of the present invention;

[0023] Figure 7 It is a simulation result diagram of the RRAM resistance state and the XOR output provided by the embodiments of the present invention. Detailed implementation manners

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention; obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments, which does not constitute a limitation to the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0025] First, the following explanations will be made for the terms that may be used in this article:

[0026] Descriptions using terms such as "comprising", "including", "containing", "having" or other similar semantics should be construed as non-exclusive inclusion. For example, including a technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, dimension, part, component, mechanism, device, step, process, method, reaction condition, processing condition, parameter, algorithm, signal, data, product or article, etc.) should be construed as not only including the explicitly listed technical feature element, but also including other technical feature elements known in the art that are not explicitly listed.

[0027] The following provides a detailed description of the 4T3R circuit structure for realizing high-speed logic operations based on a resistive random access memory (RRAM) according to the present invention. Contents not described in detail in the present invention belong to the prior art well-known to those skilled in the art. In the embodiments of the present invention, those not specified in specific conditions are carried out according to the conventional conditions in the art or the conditions recommended by the manufacturer. Reagents or instruments not specified in the embodiments of the present invention in terms of the manufacturer are all conventional products that can be obtained through commercial purchase.

[0028] Embodiment 1

[0029] As Figures 1 to 7 shown, Embodiment 1 of the present invention provides a 4T3R circuit structure for realizing high-speed logic operations based on a resistive random access memory (RRAM). It is a circuit structure for realizing high-speed logic operations with RRAM in in-memory computing, including 4 NMOS transistors, 3 resistive random access memories, and 1 resistor R1; these 4 NMOS transistors are respectively defined as M1, M2, M3, and M4; these 3 resistive random access memories are respectively defined as RRAM1, RRAM2, and RRAM3.

[0030] The resistive random access memories RRAM1, RRAM2, and RRAM3 have the same orientation, with the top electrode facing up and the bottom electrode facing down.

[0031] The bottom electrode of the resistive random access memory RRAM1 is electrically connected to the drain of the NMOS transistor M1 and the drain of the NMOS transistor M2; the gate of the NMOS transistor M1 is electrically connected to the signal line WLA; the gate of the NMOS transistor M2 is electrically connected to the signal line WLC.

[0032] The source of the NMOS transistor M2 and the source of the NMOS transistor M3 are both electrically connected to the top electrode of the resistive random access memory RRAM2; the gate of the NMOS transistor M3 is electrically connected to the signal line WLB.

[0033] The bottom electrode of the resistive random access memory RRAM3 is electrically connected to the drain of the NMOS transistor M4; the gate of the NMOS transistor M4 is electrically connected to the signal line WLS.

[0034] The source of NMOS transistor M1, the bottom electrode of resistive random access memory RRAM2, and the source of NMOS transistor M4 are all electrically connected to signal line SL, and are also all electrically connected to one end of resistor R1, while the other end of resistor R1 is grounded.

[0035] The top electrode of resistive random access memory RRAM1 is electrically connected to signal line BLA; the drain of NMOS transistor M3 is electrically connected to signal line BLB; the top electrode of resistive random access memory RRAM3 is electrically connected to signal line BL0.

[0036] Specifically, in this 4T3R circuit structure, by controlling the conduction and cutoff of NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, and NMOS transistor M4 through signal line WLA, signal line WLC, signal line WLB, and signal line WLS respectively, at least one of the following logic operations of this circuit structure can be achieved:

[0037] (1) By turning on WLA and WLB and turning off WLC, the parallel connection of resistive random access memory RRAM1 and resistive random access memory RRAM2 is achieved, thereby realizing the OR operation of this circuit structure.

[0038] (2) By turning off WLA and WLB and turning on WLC, the series connection of resistive random access memory RRAM1 and resistive random access memory RRAM2 is achieved, thereby realizing the AND operation of this circuit structure.

[0039] (3) By turning on WLA, WLB, and WLS and turning off WLC, the parallel connection of resistive random access memory RRAM1 and resistive random access memory RRAM2 is achieved, thereby realizing writing the result of the logical NOR operation of resistive random access memory RRAM1 and resistive random access memory RRAM2 into resistive random access memory RRAM3.

[0040] (4) By turning off WLA and WLB and turning on WLC and WLS, the series connection of resistive random access memory RRAM1 and resistive random access memory RRAM2 is achieved, thereby realizing writing the result of the logical NAND operation of resistive random access memory RRAM1 and resistive random access memory RRAM2 into resistive random access memory RRAM3.

[0041] (5) First, by turning off WLA and WLB and turning on WLC and WLS, the series connection of resistive random access memory RRAM1 and resistive random access memory RRAM2 is achieved, thereby writing the result of the logical NAND operation of resistive random access memory RRAM1 and resistive random access memory RRAM2 into resistive random access memory RRAM3. Then, by turning on WLA, WLB, and WLS and turning off WLC, the structure of resistive random access memory RRAM1 in parallel with resistive random access memory RRAM2 is connected in series with resistive random access memory RRAM3, thereby realizing the XOR operation of this circuit structure.

[0042] Further, the following examples are used to completely describe the whole process of performing two basic logic operations on the 4T3R circuit structure for realizing high-speed logic operations based on a resistive random access memory (RRAM) provided in Embodiment 1 of the present invention, and the feasibility of the present invention is verified through simulation diagrams:

[0043] The 4T3R circuit structure for realizing high-speed logic operations based on a resistive random access memory (RRAM) provided in Embodiment 1 of the present invention can be realized according to the working principle of the RRAM: when the RRAMs are in parallel, the circuit is not turned on if and only if both RRAMs are in the high resistance state (HRS); when the RRAMs are in series, the circuit is turned on if and only if both RRAMs are in the low resistance state (LRS).

[0044] (I) The whole process and simulation of the exclusive OR logic operation:

[0045] As Figure 1 shown, it is the basic circuit structure diagram of Embodiment 1 of the present invention. Define the high resistance state (HRS) of the RRAM as 0 and the low resistance state (LRS) as 1. In cycle A, the gate voltage of the NMOS transistor M1 is set to Vh by controlling through the signal line WLA, the gate voltage of the NMOS transistor M3 is set to Vh by controlling through the signal line WLB, and the gate voltage of the NMOS transistor M4 is set to Vh by controlling through the signal line WLS; in cycle B, the gate voltage of the NMOS transistor M4 is set to VL by controlling through the signal line WLS, so that after the circuit is turned on, (VL - VR) = VGS < Vth, which is sufficient to turn off WLS.

[0046] In cycle A, logical values are written into the resistive random access memory RRAM1 and the resistive random access memory RRAM2, and the resistive random access memory RRAM3 is initialized to the high resistance state (HRS).

[0047] Open WLA and WLB, turn off WLC and WLS, apply a Vset voltage at the BLA and BLB terminals, set the SL voltage to 0, and set the resistive random access memory RRAM1 and the resistive random access memory RRAM2 to the low resistance state (LRS), that is, the resistive random access memory RRAM1 and the resistive random access memory RRAM2 form the logical value 11.

[0048] Turn off WLA, WLB, and WLC, open WLS, apply a Vreset voltage at the SL terminal, set BL0 to 0, and reset the resistive random access memory RRAM3 to the high resistance state (HRS).

[0049] In cycle B, as Figure 2For the shown conduction circuit structure, to turn off WLA and WLB and turn on WLC and WLS, a lower VL gate voltage needs to be applied to WLS in this cycle; apply a VR voltage to the WLA end and apply a short Vset voltage at the end of this cycle; this can achieve the series connection of the resistive random access memory RRAM1 and the resistive random access memory RRAM2.

[0050] When both the resistive random access memory RRAM1 and the resistive random access memory RRAM2 are in the low resistance state (i.e., RRAM1 and RRAM2 form the logic value 11), the circuit conducts, thereby increasing the source voltage of WLS and then turning off WLS, keeping the resistive random access memory RRAM3 in the high resistance state (HRS), that is, forming a circuit path structure as Figure 3 shown.

[0051] When at least one of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is in the high resistance state (i.e., RRAM1 and RRAM2 form the logic values 00, 01, or 10), the circuit does not conduct, and the resistive random access memory RRAM3 will be set to the low resistance state (LRS).

[0052] From the above operations, it can be realized to perform a NAND operation on the logic values written into the resistive random access memory RRAM1 and the resistive random access memory RRAM2 and write the result of the NAND operation into the resistive random access memory RRAM3. The simulation result is as Figure 6 the resistance state of the resistive random access memory RRAM3 shown.

[0053] In cycle C, by turning on WLA, WLB, and WLS and turning off WLC, the resistive random access memory RRAM1 and the resistive random access memory RRAM2 are connected in parallel and then in series with the resistive random access memory RRAM3, thereby realizing the exclusive OR operation of this circuit structure. As Figure 7 shown is to complete the exclusive OR logic operation and detect the current I2t output result at the BL0 end.

[0054] Turn on WLA, WLB, and WLS, turn off WLC, and apply a read voltage Vr to BLA and BLB. Divide the cycle of each logical operation into three cycles, namely cycle A, cycle B, and cycle C. Cycle A completes the writing of the states of the resistive random access memory RRAM1 and the resistive random access memory RRAM2, cycle B completes the writing of the state of the resistive random access memory RRAM3, and cycle C completes the output of the exclusive OR result.

[0055] When writing logic 1 into the resistive random access memory RRAM1 and the resistive random access memory RRAM2 in cycle A; keep the resistive random access memory RRAM3 in the high resistance state (HRS) in cycle B; apply a read voltage to BLA in cycle C, the circuit does not conduct, and the output current detected at the BL0 end is logic 0.

[0056] When writing a logic 1 to the resistive random access memory RRAM1 and writing a logic 0 to the resistive random access memory RRAM2 in cycle A; in cycle B, writing the resistive random access memory RRAM3 to the low resistance state (LRS); in cycle C, applying a read voltage at BLA, the circuit is turned on, and the output current detected at the BL0 terminal is logic 1.

[0057] When writing a logic 0 to the resistive random access memory RRAM1 and the resistive random access memory RRAM2 in cycle A; in cycle B, writing the resistive random access memory RRAM3 to the low resistance state (LRS); in cycle C, applying a read voltage at BLA, the circuit is not turned on, and the output current detected at the BL0 terminal is logic 0.

[0058] When writing a logic 0 to the resistive random access memory RRAM1 and writing a logic 1 to the resistive random access memory RRAM2 in cycle A; in cycle B, writing the resistive random access memory RRAM3 to the low resistance state (LRS); in cycle C, applying a read voltage at BLA, the circuit is turned on, and the output current detected at the BL0 terminal is logic 1.

[0059] The above operations can implement the exclusive OR logic operation of the circuit, and the output result can be detected at the BL0 terminal. The simulation results and input timing are as Figure 5 shown.

[0060] (2) The whole process and simulation of the NOR logic operation:

[0061] In cycle A, write logical values into the resistive random access memory RRAM1 and the resistive random access memory RRAM2, and initialize the resistive random access memory RRAM3 to the high resistance state (HRS).

[0062] Turn on WLA and WLB, turn off WLC and WLS, apply a Vset voltage at the BLA and BLB terminals, set the SL voltage to 0, and set the resistive random access memory RRAM1 and the resistive random access memory RRAM2 to the low resistance state (LRS), that is, the resistive random access memory RRAM1 and the resistive random access memory RRAM2 form the logical value 11.

[0063] Turn off WLA, WLB, and WLC, turn on WLS, apply a Vreset voltage at the SL terminal, set BL0 to 0, and reset the resistive random access memory RRAM3 to the high resistance state (HRS).

[0064] In cycle B, as Figure 4 shown in the on - circuit structure, turn on WLA, WLB, and WLS, turn off WLC, realize the parallel connection of the resistive random access memory RRAM1 and the resistive random access memory RRAM2, so as to write the result of the logical NOR operation of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 into the resistive random access memory RRAM3.

[0065] Turn on WLA, WLB, and WLS, and turn off WLC. A lower VL voltage needs to be applied to WLS in this cycle. Apply a VR voltage to the WLA terminal and apply a short Vset voltage at the end of this cycle.

[0066] When both the resistive random access memory RRAM1 and the resistive random access memory RRAM2 are in the high resistance state (i.e., RRAM1 and RRAM2 form a logic value of 00), the circuit is not conducting, which causes the source voltage of WLS to increase and then turn off WLS, setting the resistive random access memory RRAM3 to the low resistance state (LRS).

[0067] When at least one of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is in the low resistance state (i.e., RRAM1 and RRAM2 form a logic value of 01, 10, or 11), the circuit conducts, and the resistive random access memory RRAM1 will be kept in the high resistance state (HRS).

[0068] The above operations can implement the NOR logic operation of the circuit and save the operation result in RRAM3.

[0069] In summary, the embodiment of the present invention uses RRAM to implement basic logic operations in in-memory computing, improving the logic operation efficiency of the circuit.

[0070] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background art part of this article is only intended to deepen the understanding of the overall background art of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art.

Claims

1. A 4T3R circuit structure for realizing high-speed logical operations based on a resistive random access memory, characterized in that It includes 4 NMOS transistors, 3 resistive random access memories, and 1 resistor R1; these 4 NMOS transistors are respectively defined as M1, M2, M3, and M4; these 3 resistive random access memories are respectively defined as RRAM1, RRAM2, and RRAM3; The bottom electrode of the resistive random access memory RRAM1 is electrically connected to the drain of the NMOS transistor M1 and the drain of the NMOS transistor M2; the gate of the NMOS transistor M1 is electrically connected to the signal line WLA; the gate of the NMOS transistor M2 is electrically connected to the signal line WLC; The source of the NMOS transistor M2 and the source of the NMOS transistor M3 are both electrically connected to the top electrode of the resistive random access memory RRAM2; the gate of the NMOS transistor M3 is electrically connected to the signal line WLB; The bottom electrode of the resistive random access memory RRAM3 is electrically connected to the drain of the NMOS transistor M4; the gate of the NMOS transistor M4 is electrically connected to the signal line WLS; The source of the NMOS transistor M1, the bottom electrode of the resistive random access memory RRAM2, and the source of the NMOS transistor M4 are all electrically connected to the signal line SL, and are also all electrically connected to one end of the resistor R1, and the other end of the resistor R1 is grounded; The top electrode of the resistive random access memory RRAM1 is electrically connected to the signal line BLA; the drain of the NMOS transistor M3 is electrically connected to the signal line BLB; the top electrode of the resistive random access memory RRAM3 is electrically connected to the signal line BL0.

2. The 4T3R circuit structure for realizing high-speed logic operations based on a resistive random access memory according to claim 1, characterized in that By controlling the conduction and cutoff of the NMOS transistors M1, M2, M3, and M4 through the signal lines WLA, WLC, WLB, and WLS respectively, at least one of the following logical operations of this circuit structure can be achieved: (1) By turning on WLA and WLB and turning off WLC, the parallel connection of the resistive random access memories RRAM1 and RRAM2 is achieved, thereby achieving the OR operation of this circuit structure; (2) By turning off WLA and WLB and turning on WLC, the series connection of the resistive random access memories RRAM1 and RRAM2 is achieved, thereby achieving the AND operation of this circuit structure; (3) By turning on WLA, WLB, and WLS and turning off WLC, the parallel connection of the resistive random access memories RRAM1 and RRAM2 is achieved, thereby achieving writing the result of the logical NOR operation of the resistive random access memories RRAM1 and RRAM2 into the resistive random access memory RRAM3; (4) By turning off WLA and WLB and turning on WLC and WLS, the series connection of the resistive random access memories RRAM1 and RRAM2 is achieved, thereby achieving writing the result of the logical NAND operation of the resistive random access memories RRAM1 and RRAM2 into the resistive random access memory RRAM3; (5) First, by turning off WLA and WLB and turning on WLC and WLS, the series connection of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is realized, so that the result of the logical NAND operation of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is written into the resistive random access memory RRAM3. Then, by turning on WLA, WLB, and WLS and turning off WLC, the structure of the resistive random access memory RRAM1 in parallel with the resistive random access memory RRAM2 is connected in series with the resistive random access memory RRAM3, thereby realizing the exclusive OR operation of the circuit structure.

3. The 4T3R circuit structure for implementing high-speed logic operations based on a resistive random access memory according to claim 1 or 2, characterized in that The placement directions of the resistive random access memory RRAM1, the resistive random access memory RRAM2, and the resistive random access memory RRAM3 are the same, with the top electrode facing up and the bottom electrode facing down.

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