memory devices

Abstract

This invention relates to a memory device. The memory device according to the invention may include: a plurality of planes; independent operation controllers configured to control read operations on the plurality of planes respectively; a common operation controller configured to control programming or erasing operations on any one of the plurality of planes; a command decoder configured to provide a read command from a plurality of commands to an independent operation controller controlling the plane indicated by an address corresponding to the read command, and configured to provide a programming or erasing command from the plurality of commands to the common operation controller; and peripheral circuitry configured to generate operating voltages for the read operations, the programming operations, and the erasing operations.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more specifically, to a memory device and a memory system including the memory device. Background Technology

[0002] A memory system is a device that stores data based on a host device such as a computer or smartphone. A memory system may include a memory device that stores data and a memory controller that controls the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are devices that store data only when powered on and lose the stored data when the power is turned off. Volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0004] Non-volatile memory devices are devices that retain data even when power is cut off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory, etc. Summary of the Invention

[0005] A memory device according to embodiments of the present disclosure may include: a plurality of planes, each of the plurality of planes having a plurality of memory cells; an independent operation controller configured to control read operations on the plurality of planes respectively; a common operation controller configured to control programming operations or erase operations on any one of the plurality of planes; a command decoder configured to receive a plurality of commands and addresses corresponding to the plurality of commands from a memory controller, configured to provide a read command among the plurality of commands to an independent operation controller that controls the plane indicated by the address corresponding to the read command, and configured to provide a programming command or erase command among the plurality of commands to the common operation controller; and peripheral circuitry configured to generate operating voltages for the read operations, the programming operations, and the erase operations based on the independent operation controllers and the common operation controller.

[0006] A memory device according to embodiments of the present disclosure may include: a memory cell array having a plurality of planes; peripheral circuitry configured to perform read operations, program operations, or erase operations on memory cells included in the plurality of planes, respectively; and control logic configured to control the memory cell array and the peripheral circuitry to execute operations corresponding to at least two commands in parallel when receiving at least two commands from a memory controller: a programming command initiating a programming operation on the plurality of planes, an erase command initiating an erase operation on the plurality of planes, and a read command initiating a read operation on the plurality of planes. When a subsequent command initiating another programming operation is input while the programming operation is being performed, the control logic may maintain the start of the other programming operation corresponding to the subsequent command; and when a subsequent command initiating another erase operation is input while the erase operation is being performed, the control logic may maintain the start of the other erase operation corresponding to the subsequent command.

[0007] The memory device according to embodiments of the present disclosure may include: a plurality of planes, each having a plurality of memory cells; an independent operation controller configured to control read operations on the plurality of planes respectively; and a common operation controller configured to control programming or erasing operations on any one of the plurality of planes, wherein different operations can be performed simultaneously on different planes among the plurality of planes. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0009] Figure 2 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0010] Figure 3 This is a block diagram illustrating the specific operation of the control logic according to embodiments of the present disclosure.

[0011] Figure 4 This is a block diagram illustrating the specific operation of a voltage generating circuit according to an embodiment of the present disclosure.

[0012] Figure 5 This is a diagram illustrating the internal operation of a memory device according to an embodiment of the present disclosure.

[0013] Figure 6 This is a diagram illustrating the internal operation of a memory device according to another embodiment of the present disclosure.

[0014] Figure 7 This is a diagram illustrating the internal operation of a memory device according to another embodiment of the present disclosure.

[0015] Figure 8 This is a diagram illustrating a memory cell array according to an embodiment of the present disclosure.

[0016] Figure 9 This is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0017] Figure 10 This is a diagram illustrating a memory block according to another embodiment of the present disclosure.

[0018] Figure 11 This is a diagram illustrating a memory block according to another embodiment of the present disclosure.

[0019] Figure 12 This is a block diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0020] Figure 13 This is a diagram illustrating a memory card system according to an embodiment of the present disclosure.

[0021] Figure 14 This is a diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present disclosure.

[0022] Figure 15 This is a diagram illustrating a user system according to an embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions illustrating embodiments of the concepts disclosed in this specification or application are for the purpose of describing embodiments of the concepts disclosed herein. Embodiments of the concepts disclosed herein may be implemented in various forms, and the description is not limited to the embodiments described in this specification or application.

[0024] In this specification, the expression "simultaneously" is used to describe the execution of a specific operation, which can indicate some overlap in the timing of the operations. This expression can mean that the specific operations are executed "simultaneously" even if they occur at different points in time.

[0025] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement the technical spirit of the present disclosure.

[0026] Embodiments of this disclosure provide a memory device in which multiple planes can independently perform internal operations, and a memory system having the memory device.

[0027] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0028] Reference Figure 1The memory system 1000 may include a memory device 100 and a memory controller 200.

[0029] The storage system 1000 can be a device for storing data based on a host 2000 such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, display device, tablet PC, or in-vehicle infotainment system.

[0030] The memory system 1000 can be implemented as any of various types of memory systems, depending on the host interface that serves as the communication method with the host 2000. For example, the memory system 1000 can be implemented as any of various types of memory systems, such as SSDs, MMCs, eMMCs, RS-MMCs, and micro MMCs; secure digital cards in the form of SDs, mini SDs, and micro SDs; Universal Serial Bus (USB) storage devices; Universal Flash Memory (UFS) storage devices; PCMCIA (Personal Computer Memory International Association) card-type storage devices; Peripheral Component Interconnect (PCI) card-type storage devices; PCI Express (PCI-E) card-type storage devices; Compact Flash (CF) cards; smart media cards; and Memory Sticks.

[0031] The memory system 1000 can be implemented in any of a variety of package types. For example, the memory system 1000 can be implemented in any of a variety of package types such as point-of-purchase (POP), system-in-package (SIP), system-on-a-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0032] The memory device 100 can store data or use the stored data. Specifically, the memory device 100 can operate based on the memory controller 200. In addition, the memory device 100 may include a plurality of memory dies, and each of the plurality of memory dies may include a memory cell array having a plurality of memory cells for storing data.

[0033] Each memory cell can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0034] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells, and a memory block may include multiple pages. Here, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100. According to an embodiment, the memory cell array may include multiple planes.

[0035] The memory device 100 may be implemented as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Transfer Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, it is assumed that the memory device 100 is a NAND flash memory.

[0036] Memory device 100 may receive commands and addresses from memory controller 200. Memory device 100 may be configured to access a region in the memory cell array selected by the received address. Accessing the selected region may represent performing an operation corresponding to the received command on the selected region. For example, memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. Here, a programming operation may be an operation in which memory device 100 writes data to the region selected by the address. A read operation may represent an operation in which memory device 100 reads data from the region selected by the address. An erase operation may represent an operation in which memory device 100 erases data stored in the region selected by the address.

[0037] According to embodiments of this disclosure, the memory device 100 may include a read operation controller, a programming operation controller, and an erase operation controller. The read operation controller, programming operation controller, and erase operation controller may be configured to perform internal operations based on commands received from the memory controller 200. Specifically, when a read command is received from the memory controller 200, the read operation controller may control the memory device 100 to perform an operation to read data from an address-selected region. When a programming command is received from the memory controller 200, the programming operation controller may control the memory device 100 to perform an operation to write data to an address-selected region. When an erase command is received from the memory controller 200, the erase operation controller may control the memory device 100 to perform an operation to erase data stored in an address-selected region.

[0038] When power is applied to the memory system 1000, the memory controller 200 can execute firmware (FW). The firmware (FW) may include a host interface layer (HIL) that receives requests from or outputs responses to the host 2000, a flash translation layer (FTL) that manages the operation between the interface of the host 2000 and the interface of the memory device 100, and a flash interface layer (FIL) that provides commands to or receives responses from the memory device 100.

[0039] The memory controller 200 can receive data and logical addresses (LA) from the host 2000 and convert the LA into physical addresses (PA) that indicate the addresses of memory cells included in the memory device 100 where data will be stored. The LA can be a logical block address (LBA), and the PA can be a physical block address (PBA).

[0040] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, or erase operations according to requests from the host 2000. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, PBA, and data. During a read operation, the memory controller 200 can provide the memory device 100 with read commands and PBA. During an erase operation, the memory controller 200 can provide the memory device 100 with erase commands and PBA.

[0041] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations on its own, regardless of requests from the host 2000. For example, the memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations for background operations such as wear leveling, garbage collection, and read recycling.

[0042] According to embodiments of this disclosure, when the memory device 100 performs any one of its internal operations—programming, reading, or erasing—the memory controller 200 can control the memory device 100 to perform another internal operation. The memory controller 200 can also control the memory device 100 to perform an interleaving operation. That is, the memory controller 200 can control the memory device 100 to simultaneously access multiple planes and perform different internal operations.

[0043] The host 2000 can communicate with the memory system 1000 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Unloaded DIMM (LRDIMM).

[0044] Figure 2 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0045] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 160.

[0046] The memory cell array 110 may include multiple planes. These planes may include a first plane 110a, a second plane 110b, a third plane 110c, and a fourth plane 110d. Each of the first planes 110a to 110d may include multiple memory blocks BLK1 to BLKi. The multiple memory blocks BLK1 to BLKi included in each plane can be connected via row lines RL to the row decoders 130 corresponding to each memory block BLK1 to BLKi. For example, the multiple memory blocks BLK1 to BLKi included in the first plane 110a can be connected via row lines RL to the first decoder 131.

[0047] Multiple memory blocks BLK1 to BLKi can be connected to page buffer group 150 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKi may include multiple memory cells. Furthermore, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block may include multiple pages. Row line RL may include at least one source select line, multiple word lines, and at least one drain select line.

[0048] Each memory cell included in the memory cell array 110 can be configured as an SLC storing one data bit, an MLC storing two data bits, a TLC storing three data bits, or a QLC storing four data bits.

[0049] Peripheral circuitry 120 can be configured to perform programming, reading, or erasing operations on selected regions of memory cell array 110 based on control logic 160. That is, peripheral circuitry 120 can drive memory cell array 110 based on control logic 160. For example, peripheral circuitry 120 can apply various operating voltages to row lines RL and bit lines BL1 to BLn, or release the applied voltages, based on control logic 160. According to embodiments of this disclosure, peripheral circuitry 120 can independently perform reading, programming, or erasing operations on memory cells included in each of a plurality of planes.

[0050] The peripheral circuitry 120 may include a row decoder 130, a voltage generation circuit 140, a current sensing circuit 121, a column decoder 123, and an input / output circuit 125 to independently perform read, program, or erase operations on memory cells included in each of the multiple planes.

[0051] The row decoder 130 may include multiple decoders corresponding to the plurality of planes. Specifically, the row decoder 130 may include a first decoder 131, a second decoder 132, a third decoder 133, and a fourth decoder 134, and each decoder may correspond to one of the first plane 110a to the fourth plane 110d. The row decoder 130 may be connected to the memory cell array 110 via row lines RL. According to embodiments of the present disclosure, the multiple decoders included in the row decoder 130 may be connected to the plurality of planes respectively. Specifically, the first decoder 131 may be connected via row lines RL to a plurality of memory blocks BLK1 to BLKi included in the first plane 110a. Additionally, the second decoder 132 may be connected via row lines RL to a plurality of memory blocks BLK1 to BLKi included in the second plane 110b. The third decoder 133 may be connected via row lines RL to a plurality of memory blocks BLK1 to BLKi included in the third plane 110c. The fourth decoder 134 may be connected via row lines RL to a plurality of memory blocks BLK1 to BLKi included in the fourth plane 110d. Additionally, the row line RL may include at least one source select line, multiple word lines, and at least one drain select line. In one embodiment, the word lines may include normal word lines and dummy word lines. Furthermore, the row line RL may also include a pipe select line.

[0052] The row decoder 130 can be configured to operate based on control logic 160. The row decoder 130 can receive a row address RADD from the control logic 160. Specifically, the row decoder 130 can be configured to decode the row address RADD. The row decoder 130 can select at least one memory block from BLK1 to BLKz included in the plurality of planes based on the decoded address.

[0053] Additionally, the row decoder 130 can select at least one word line of a selected memory block based on the decoded address to apply a voltage generated by the voltage generation circuit 140 to the at least one word line. According to embodiments of this disclosure, the row decoder 130 can select any one of a plurality of planes based on the decoded address and apply a voltage generated by the voltage generation circuit 140 to at least one word line using a decoder corresponding to the selected plane. According to embodiments of this disclosure, the row decoder 130 can select a first decoder 131 based on the decoded address and apply a voltage generated by the voltage generation circuit 140 to a plurality of memory blocks BLK1 to BLKi included in the first plane 110a using the first decoder 131.

[0054] In this embodiment, during a programming operation, the line decoder 130 may apply a programming voltage to the selected word line and apply a programming pass voltage (at a level lower than the programming voltage) to the unselected word line. During a programming verification operation, the line decoder 130 may apply a verification voltage to the selected word line and apply a verification pass voltage (at a level higher than the verification voltage) to the unselected word line. During a reading operation, the line decoder 130 may apply a read voltage to the selected word line and apply a read pass voltage (at a level higher than the read voltage) to the unselected word line.

[0055] In this embodiment, the erase operation of the memory cell array 110 can be performed on a block-by-block basis. During the erase operation, the row decoder 130 can select a memory block based on the decoded address, and the row decoder 130 can apply a ground voltage to the word line connected to the selected memory block.

[0056] The voltage generating circuit 140 can operate based on control logic 160. Specifically, the voltage generating circuit 140 can be configured to generate multiple voltages based on the control logic 160 using an external power supply voltage provided to the memory device 100. For example, the voltage generating circuit 140 can generate programming voltage, verification voltage, pass voltage, read voltage, and erase voltage, etc., based on the control logic 160. That is, the voltage generating circuit 140 can generate various operating voltages Vop for programming operations, read operations, and erase operations in response to the operation signal OPSIG.

[0057] Additionally, the voltage generating circuit 140 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generating circuit 140 can be used as the operating voltage of the memory cell array 110. The voltage generating circuit 140 can generate multiple voltages by using either an external power supply voltage or an internal power supply voltage. For example, the voltage generating circuit 140 may include multiple pumps that receive the internal power supply voltage, and the multiple pumps can be selectively activated based on control logic 160 to generate multiple voltages. Furthermore, the generated voltages can be provided to the memory cell array 110 via the row decoder 130.

[0058] According to embodiments of this disclosure, the voltage generating circuit 140 may include a read voltage generator 141, a programming voltage generator 143, and an erase voltage generator 145. The read voltage generator 141 generates a voltage for a read operation. The programming voltage generator 143 generates a voltage for a programming operation. The erase voltage generator 145 generates a voltage for an erase operation.

[0059] The current sensing circuit 121 can generate a reference current in response to the enable bit signal VRYBIT during a read or verification operation, can compare the sensed voltage VPB received from the page buffer group 150 with the reference voltage generated by the reference current, and can output a pass signal PASS or a failure signal FAIL.

[0060] Page buffer group 150 may include first page buffer PB1 to m-th page buffer PBm. First page buffer PB1 to m-th page buffer PBm may be connected to memory cell array 110 via first bit line BL1 to m-th bit line BLm, respectively. In addition, first page buffer PB1 to m-th page buffer PBm may be operated based on control logic 160.

[0061] Specifically, the first page buffer PB1 to the m-th page buffer PBm can operate in response to the page buffer control signal PBSIGNALS. For example, the first page buffer PB1 to the m-th page buffer PBm can temporarily store data received through the first bit line BL1 to the m-th bit line BLm, or the voltage or current of the bit lines BL1 to BLm can be sensed during read or verification operations.

[0062] Specifically, during programming operations, when a programming pulse is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first bit line BL1 to the m-th bit line BLm. The memory cell of the selected page can be programmed according to the transmitted data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can remain unchanged.

[0063] During the programming verification operation, page data can be read from the selected memory cell through the first bit line BL1 to the m-th bit line BLm.

[0064] During a read operation, the first page buffer PB1 to the m-th page buffer PBm can read data DATA from the memory cell of the selected page through the first bit line BL1 to the m-th bit line BLm, and output the read data DATA to the input / output circuit 125 based on the column decoder 123.

[0065] During the erase operation, the first page buffer PB1 to the m-th page buffer PBm can float the first bit line BL1 to the m-th bit line BLm.

[0066] The column decoder 123 can transfer data between the input / output circuit 125 and the page buffer group 150 in response to the column address CADD. For example, the column decoder 123 can exchange data with the first page buffer PB1 to the m-th page buffer PBm via the data line DL, or it can exchange data with the input / output circuit 125 via the column line CL.

[0067] The input / output circuit 125 can transmit the command CMD and address ADDR received from the memory controller 200 to the control logic 160, or it can exchange data DATA with the column decoder 123.

[0068] Control logic 160 can respond to command CMD and address ADDR output operation signals OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit signal VRYBIT to control peripheral circuitry 120. Additionally, control logic 160 can respond to the PASS signal or the FAIL signal to determine whether the internal operation's verification operation passed or failed.

[0069] According to embodiments of this disclosure, control logic 160 may include an independent operation controller 170 and a common operation controller 180. Furthermore, the independent operation controller 170 can control the peripheral circuitry 120 to independently perform read operations on the first plane 110a to the fourth plane 110d. Furthermore, the common operation controller 180 can control the peripheral circuitry 120 to independently perform programming and erasing operations on the first plane 110a to the fourth plane 110d. (See also...) Figure 3 The specific characteristics of the independent operation controller 170 and the common operation controller 180 are described in detail.

[0070] Figure 3 This is a block diagram illustrating the specific operation of the control logic according to embodiments of the present disclosure.

[0071] Reference Figure 3 The image shows a memory device 100 having a memory cell array 110, a page buffer group 150, and control logic 160.

[0072] The memory cell array 110 and page buffer group 150 can be divided into multiple planes and multiple page buffer circuits connected by bit lines BL, respectively. That is, the memory cell array 110 and page buffer group 150 can be paired and operate on a plane-by-plane basis. For example, the first plane 110a and the first page buffer circuit 151 can form a pair and operate on a plane-by-plane basis, the second plane 110b and the second page buffer circuit 152 can form a pair and operate on a plane-by-plane basis, the third plane 110c and the third page buffer circuit 153 can form a pair and operate on a plane-by-plane basis, and the fourth plane 110d and the fourth page buffer circuit 154 can form a pair and operate on a plane-by-plane basis. The memory cell array 110 and the multiple page buffer circuits included in the memory device 100 can be divided into multiple corresponding pairs, and each pair can operate independently as a unit.

[0073] Control logic 160 may include an independent operation controller 170 and a common operation controller 180. Furthermore, control logic 160 can use the independent operation controller 170 and the common operation controller 180 to control peripheral circuitry 120 to independently perform read, program, or erase operations on memory cells included in each of the plurality of planes. For example, control logic 160 can use the independent operation controller 170 to control peripheral circuitry 120 to perform read operations on the first plane 110a and the second plane 110b.

[0074] The independent operation controller 170 may include a first read operation controller 171 to a fourth read operation controller 174. The independent operation controller 170 can control the peripheral circuitry 120 to independently perform read operations for each plane by using the first read operation controller 171 to the fourth read operation controller 174. Specifically, the read operation controllers included in the independent operation controller 170 may correspond to multiple planes respectively, and each read operation controller can control the read operations performed on the corresponding plane.

[0075] For example, a first read operation controller 171 may correspond to a first plane 110a and control the read operations performed on the first plane 110a. A second read operation controller 172 may correspond to a second plane 110b and control the read operations performed on the second plane 110b. A third read operation controller 173 may correspond to a third plane 110c and control the read operations performed on the third plane 110c. A fourth read operation controller 174 may correspond to a fourth plane 110d and control the read operations performed on the fourth plane 110d.

[0076] Since the independent operation controller 170 controls the read operation performed on each of the multiple planes, the read operation can be performed independently for each plane.

[0077] The common operation controller 180 may include a programming operation controller 181, an erasure operation controller 183, and a backup operation storage unit 185.

[0078] The programming operation controller 181 can control the peripheral circuitry 120 to independently perform programming operations on the plurality of planes. Specifically, the programming operation controller 181 can use the peripheral circuitry 120 to control the programming operations performed on the first plane 110a to the fourth plane 110d. Furthermore, the programming operation controller 181 can control the peripheral circuitry 120 such that programming operations are performed independently, regardless of whether another internal operation (e.g., an erase operation or a read operation) is performed.

[0079] The programming operation controller 181 can control the memory cell array 110 and peripheral circuitry 120 to simultaneously initiate programming operations on two or more planes. For example, the programming operation controller 181 can control the first page buffer circuit 151 and the second page buffer circuit 152 to simultaneously initiate programming operations on the first plane 110a and the second plane 110b.

[0080] The erase operation controller 183 can control the peripheral circuitry 120 to independently perform erase operations on multiple planes. Specifically, the erase operation controller 183 can use the peripheral circuitry 120 to control the erase operations performed on the first plane 110a to the fourth plane 110d. Furthermore, the erase operation controller 183 can control the peripheral circuitry 120 such that the erase operations are performed independently, regardless of whether another internal operation (e.g., a programming operation or a reading operation) is performed.

[0081] The erase operation controller 183 can control the memory cell array 110 and peripheral circuitry 120 to simultaneously initiate erase operations on two or more planes. For example, the erase operation controller 183 can control the first page buffer circuit 151 and the second page buffer circuit 152 to simultaneously initiate erase operations on the first plane 110a and the second plane 110b.

[0082] When the programming operation controller 181 is operating, the backup operation storage unit 185 can store the input programming commands. Alternatively, when the erase operation controller 183 is operating, the backup operation storage unit 185 can store the input erase commands. Specifically, when a programming operation is in progress, the programming operation controller 181 can start another programming operation after the current programming operation has ended. Similarly, when an erase operation is in progress, the erase operation controller 183 can start another erase operation after the current erase operation has ended. The backup operation storage unit 185 can store programming commands input during the execution of a programming operation, and it can also store erase commands input during the execution of an erase operation. Furthermore, when a subsequent programming command is input while a programming operation is being executed, the backup operation storage unit 185 can maintain the start of the programming operation corresponding to the subsequent command. Likewise, when a subsequent erase command is input while an erase operation is being executed, the backup operation storage unit 185 can maintain the start of the erase operation corresponding to the subsequent command.

[0083] Simultaneously, when a subsequent command for an erase or read operation is input while a programming operation is being performed, the control logic 160 can control the peripheral circuit 120 to execute the erase or read operation corresponding to the subsequent command. Furthermore, when a subsequent command for a programming or read operation is input while a erase operation is being performed, the control logic 160 controls the peripheral circuit 120 to execute the programming, erase, or read operation corresponding to the subsequent command. Additionally, when a subsequent command for a programming, erase, or read operation is input while a read operation is being performed, the control logic 160 can control the peripheral circuit 120 to execute the programming, erase, or read operation corresponding to the subsequent command.

[0084] Figure 4 This is a block diagram illustrating the specific operation of a voltage generating circuit according to an embodiment of the present disclosure.

[0085] Reference Figure 4 The diagram shows a voltage generation circuit 140 having a read voltage generator 141, a programmable voltage generator 143, and an erase voltage generator 145.

[0086] The voltage generating circuit 140 can operate based on control logic 160 having an independent operation controller 170, a programming operation controller 181, and an erasing operation controller 183. Specifically, the read voltage generator 141 can generate a voltage for read operations in response to a read operation signal RD_OPSIG included in the independent operation controller 170 (first to fourth read operation controllers). See reference... Figure 3As described, the first to fourth read operation controllers included in the independent operation controller 170 can be configured to control read operations performed in each plane, and the read voltage generator 141 can generate a voltage for the read operation performed on the first plane 110a in response to the read operation signal RD_OPSIG of the first read operation controller 171. Additionally, the read voltage generator 141 can generate a voltage for the read operation performed on the second plane 110b to the fourth plane 110d in response to the read operation signals RD_OPSIG of the second to fourth read operation controllers 172 to 174.

[0087] The programming voltage generator 143 can generate a voltage for programming operations based on the programming operation controller 181. Specifically, the programming operation controller 181 can be configured to independently control programming operations, and the programming voltage generator 143 can independently generate a voltage for programming operations in response to the programming operation signal PGM_OPSIG from the programming operation controller 181. That is, the programming voltage generator 143 can independently generate a voltage for programming operations, regardless of whether another internal operation (e.g., an erase operation or a read operation) is performed.

[0088] The erase voltage generator 145 can generate a voltage for the erase operation based on the erase operation controller 183. Specifically, the erase operation controller 183 can be configured to independently control the erase operation, and the erase voltage generator 145 can independently generate a voltage for the erase operation in response to the erase operation signal ER_OPSIG of the erase operation controller 183. That is, the erase voltage generator 145 can independently generate a voltage for the erase operation, regardless of whether another internal operation (e.g., a programming operation or a read operation) is performed.

[0089] Figure 5 This is a diagram illustrating the internal operation of a memory device according to an embodiment of the present disclosure.

[0090] Reference Figure 5 This illustrates the internal operations performed in the memory device 100 over time as erase commands, programming commands, and read commands are sequentially input from the memory controller 200.

[0091] When a subsequent command to initiate an internal operation (e.g., a programming operation or a read operation) is input from the memory controller 200 to the memory device 100 while the memory device 100 is performing an erase operation, the memory device 100 may simultaneously perform the erase operation and the internal operation corresponding to the subsequent command.

[0092] Specifically, the memory device 100 can receive an erase command ER CMD P1 from the memory controller 200. Additionally, the memory device 100 can perform an erase operation 51 on the first plane in response to the input command. Furthermore, when subsequent commands PGM CMD P2 & P3 are input from the memory controller 200 while the memory device 100 is performing the erase operation 51, the memory device 100 can simultaneously perform the erase operation 51 and the programming operation 52.

[0093] Simultaneously, memory device 100 can initiate programming or erasing operations on two or more planes. After data to be written to two or more planes is received sequentially into the respective page buffer circuits, memory device 100 can simultaneously begin programming operations. For example, memory device 100 can receive programming commands PGM CMD P2&P3 for the second and third planes from memory controller 200. Additionally, in response to the input commands, memory device 100 can store data for the second plane in the second page buffer circuit and data for the third plane in the third page buffer circuit. After all data for each plane has been input, memory device 100 can simultaneously begin programming operations on the second and third planes. Here, tXfer can refer to the time when data is input / output to / from memory device 100 via input / output circuit 125. Multiple planes can share input / output circuit 125 to sequentially input / output data for each plane.

[0094] exist Figure 5 For ease of description, programming operations performed on two or more planes are shown, but erasure operations performed on two or more planes can be performed in the same manner.

[0095] While the memory device 100 performs the erase operation 51 and the programming operation 52, when the subsequent command RD CMD P4 is input, the memory device 100 can simultaneously perform the erase operation 51, the programming operation 52 and the read operation 53 on the fourth plane.

[0096] Figure 6 This is a diagram illustrating the internal operation of a memory device according to another embodiment of the present disclosure.

[0097] Reference Figure 6 This illustrates the internal operations performed in the memory device 100 over time as erase commands, multiple read commands, and programming commands are sequentially input from the memory controller 200.

[0098] The memory device 100 can receive an erase command ER CMD P1 from the memory controller 200. Additionally, the memory device 100 can perform an erase operation 61 on the first plane in response to the input command. Furthermore, when a subsequent command RD CMD P3 is input from the memory controller 200 while the memory device 100 is performing the erase operation 61, the memory device 100 can simultaneously perform the erase operation 61 and the read operation 62.

[0099] Simultaneously, the memory device 100 can perform read operations on two or more planes at the same time. The memory device 100 may include multiple read operation controllers for each plane, and the read operation on each plane can be controlled individually using these multiple read operation controllers. For example, the memory device 100 can perform read operation 62 in response to a read command RD CMD P3 input from the memory controller 200 for a third plane. Additionally, when read command RD CMD P2 is input while the memory device 100 is performing read operation 62, the memory device 100 can simultaneously perform read operation 62 on the third plane and read operation 63 on the second plane. The memory device 100 can output the data (62-1) read from the third plane using input / output circuitry 125, and can sequentially output the data (63-1) read from the second plane.

[0100] While the memory device 100 is performing the erase operation 61, when the subsequent command PGM CMD P3 is input, the memory device 100 can simultaneously perform the erase operation 61 and the programming operation 64 on the third plane.

[0101] Figure 7 This is a diagram illustrating the internal operation of a memory device according to another embodiment of the present disclosure.

[0102] Reference Figure 7 This illustrates the internal operations performed in the memory device 100 over time as multiple programming commands, erase commands, and read commands are sequentially input from the memory controller 200.

[0103] When a subsequent command to initiate a programming operation is input from the memory controller 200 to the memory device 100 while the memory device 100 is performing a programming operation, the memory device 100 can maintain the start of the programming operation corresponding to the subsequent command.

[0104] Specifically, the memory device 100 can receive the programming command PGM CMD P1 from the memory controller 200. Furthermore, after receiving data 71-1, the memory device 100 can perform a programming operation 71 on the first plane. When a subsequent command PGM CMD P2 is input from the memory controller 200 while the memory device 100 is performing programming operation 71, the memory device 100 can maintain the start of the programming operation 73 based on the subsequent command. Additionally, since the memory device 100 performs programming operations according to the input order, when the ongoing programming operation 71 has ended, the memory device 100 can execute the programming operation 73 based on the subsequent command PGM CMD P2. Simultaneously, the memory device 100 can store the subsequent command PGM CMD P2 input during the programming operation in the backup operation storage unit 185. Furthermore, when the ongoing programming operation 71 has ended, the subsequent command PGM CMD P2 stored in the backup operation storage unit 185 can be returned to the programming operation controller 181, and programming operation 73 can be executed.

[0105] Since programming and erasing operations, or programming and reading operations, can be performed simultaneously, when the memory device 100 receives the erase command ER CMD P3 and the read command RD CMD P4 while performing programming operation 71, the memory device 100 can simultaneously perform programming operation 71, erase operation 72, and read operation 74.

[0106] exist Figure 7 For ease of description, the example shown illustrates the case where subsequent programming commands are entered during the programming operation; however, the same method can be applied to the case where subsequent erase commands are entered during the erase operation.

[0107] Figure 8 This is a diagram illustrating a memory cell array according to an embodiment of the present disclosure.

[0108] Reference Figure 8 The memory cell array 110i may include multiple memory blocks BLK1 to BLKz. Figure 8 The memory cell array 110i shown can represent the corresponding memory cell array 110i. Figure 2 The memory cell array shown is any one of the first plane 110a to the fourth plane 110d.

[0109] Each memory block can be formed as a three-dimensional structure, and each memory block can include multiple memory cells stacked on a substrate. The multiple memory cells can be arranged along the +X, +Y, and +Z directions. (Refer to...) Figures 9 to 11 The structure of each memory block is described in more detail.

[0110] Figure 9 This illustrates the structure of a memory block according to an embodiment of the present disclosure.

[0111] Reference Figure 9 In a memory block BLKi, multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be a source select line SSL, and the second select line can be a drain select line DSL. More specifically, the memory block BLKi can include multiple string STs connected between bit lines BL1 to BLm and the source line SL. Bit lines BL1 to BLm can be connected to each string ST individually, and the source line SL can be connected together to each string ST. Since the string STs can be configured to be identical to each other, the string ST connected to the first bit line BL1 is specifically described as an example.

[0112] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may include more than the number of memory cells MC1 to MC16 shown in the figure.

[0113] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL, the gate of the drain select transistor DST can be connected to the drain select line DSL, and the gate of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different string STs can be referred to as a physical page PPG. Therefore, a memory block BLKi can include a number of physical pages PPGs from word lines WL1 to WL16.

[0114] Each memory cell can be configured as an SLC that stores one data bit, an MLC that stores two data bits, a TLC that stores three data bits, or a QLC that can store four data bits.

[0115] An SLC can store one bit of data. One physical page (PPG) of an SLC can store one logical page (LPG) of data. A logical page (LPG) of data can include data bits corresponding to the number of cells included in a physical page (PPG).

[0116] MLC, TLC, and QLC can store two or more bits of data. In this case, a physical page (PPG) can store two or more logical pages (LPGs) of data.

[0117] Figure 10 This is a diagram illustrating a memory block according to another embodiment of the present disclosure.

[0118] Reference Figure 10 , showed Figure 8 The memory block BLKa can be any one of the memory blocks BLK1 to BLKz. Memory block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. As an example, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In memory block BLKa, m cell strings can be arranged along the row direction (i.e., the +X direction).

[0119] At the same time, Figure 10 In this context, two unit strings can be arranged in the column direction (i.e., the +Y direction), but this is for ease of description, and obviously three or more unit strings can be arranged in the column direction.

[0120] Each of the multiple cell strings CS11 to CS1m and CS21 to Cs2m may include at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0121] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. As one embodiment, pillars for providing the channel layer may be provided in each cell string. As one embodiment, pillars for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0122] The source selection transistor SST of each cell string can be connected between the common source line CSL and memory cells MC1 to MCp.

[0123] As one embodiment, source-select transistors in cell strings arranged in the same row can be connected to source-select lines extending along the row direction, while source-select transistors in cell strings arranged in different rows can be connected to different source-select lines. (Refer to...) Figure 10The source select transistors in the first row of cell strings CS11 to CS1m can be connected to the first source select line SSL1. The source select transistors in the second row of cell strings CS21 to CS2m can be connected to the second source select line SSL2.

[0124] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0125] The first memory cell MC1 to the nth memory cell MCn of each cell string can be connected between the source selection transistor SST and the drain selection transistor DST.

[0126] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cell MCp and (p+1)th memory cells MCp+1 to the nth memory cell MCn. The first memory cells MC1 to the pth memory cell MCp can be arranged sequentially in the direction opposite to the +Z direction and can be connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th memory cells MCP+1 to the nth memory cell MCn can be arranged sequentially in the +Z direction and can be connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cell MCp and the (p+1)th memory cells MCp+1 to the nth memory cell MCn can be connected via the channel transistor PT. The gates of the first memory cells MC1 to the nth memory cell MCn in each cell string can be connected to the first word line WL1 to the nth word line WLn, respectively.

[0127] The gate of the pipe transistor PT in each unit string can be connected to the pipe PL.

[0128] The drain select transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged along the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row can be connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row can be connected to the second drain select line DSL2.

[0129] A string of cells arranged along the column direction can be connected to a bit line extending along the column direction. (See reference...) Figure 10 The cell strings CS11 and CS21 in the first column can be connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column can be connected to the m-th bit line BLm.

[0130] Memory cells connected to the same word line within a cell string arranged along a row can be configured as a page. For example, memory cells in cell strings CS11 to CS1m in the first row that are connected to the first word line WL1 can be configured as a page. Memory cells in cell strings CS21 to CS2m in the second row that are connected to the first word line WL1 can be configured as another page. A cell string arranged in a row can be selected by selecting one of the drain selection lines DSL1 and DSL2. Alternatively, a page in a selected cell string can be selected by selecting any of the word lines WL1 to WLn.

[0131] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be set instead of the first bit line BL1 to the m-th bit line BLm. Additionally, even-numbered cell strings from the row-oriented cell strings CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and odd-numbered cell strings from the row-oriented cell strings CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0132] As an example, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. Providing more dummy memory cells can improve the operational reliability of the memory block BLKa, but the size of the memory block BLKa may increase. Providing fewer dummy memory cells can reduce the size of the memory block BLKa, but the operational reliability of the memory block BLKa may decrease.

[0133] To effectively control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or part of the dummy memory cells before or after an erase operation on the memory block BLKa. When an erase operation is performed after a programming operation, the dummy memory cells can have a desired threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0134] Figure 11 This is a diagram illustrating a memory block according to another embodiment of the present disclosure.

[0135] Reference Figure 11 , showed Figure 8Another embodiment of memory block BLKb in memory blocks BLK1 to BLKz. Memory block BLKb may include multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' may extend along the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) beneath memory block BLK1b.

[0136] The source select transistor SST of each cell string can be connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row can be connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row can be connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row can be connected to the second source select line SSL2. As another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' can be connected to a single source select line.

[0137] The first memory cell MC1 to the nth memory cell MCn in each cell string can be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn can be connected to the first word line WL1 to the nth word line WLn, respectively.

[0138] The drain select transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged along the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row can be connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row can be connected to the second drain select line DSL2.

[0139] As a result, in addition to excluding the pipe transistor PT from each cell string, Figure 11 The memory block BLKb can have similar characteristics to Figure 9 The equivalent circuit of the memory block BLKa.

[0140] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be set instead of the first bit line BL1 to the m-th bit line BLm. Additionally, even-numbered cell strings from the row-oriented cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the even-numbered bit lines, and odd-numbered cell strings from the row-oriented cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the odd-numbered bit lines.

[0141] As one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. Providing more dummy memory cells can improve the operational reliability of the memory block BLKb, but the size of the memory block BLKb may increase. Providing fewer dummy memory cells can reduce the size of the memory block BLKb, but the operational reliability of the memory block BLKb may decrease.

[0142] To effectively control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cells can have a desired threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0143] Figure 12 This is a block diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0144] Reference Figure 12 The memory controller 200 may include a host interface 210, an ECC component 220, a CPU 230, internal memory 240, a buffer memory 250, an interleaving component 260, and a memory interface 270.

[0145] The host interface 210 may include protocols for exchanging data between the host 2000 and the memory controller 200. Specifically, the host interface 210 may be configured to communicate with the host 2000 via at least one of various interface protocols such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0146] ECC component 220 can detect and correct errors during programming or reading operations. Specifically, ECC component 220 can perform error correction operations based on error correction codes (ECC). Additionally, ECC component 220 can perform error correction encoding (ECC encoding) based on the data to be written to memory device 100. The error-corrected data can be transmitted to memory device 100 via memory interface 270. Furthermore, ECC component 220 can perform error correction decoding on data received from memory device 100 via memory interface 270.

[0147] CPU 230 can communicate with host 2000 via host interface 210 and perform logical operations to control the operation of memory controller 200. For example, CPU 230 can load programming commands, data files, and data structures based on requests received from host 2000 or external devices, perform various operations, or generate commands and addresses. For example, CPU 230 can generate programming commands, read commands, and erase commands for performing programming, read, and erase operations. Additionally, CPU 230 can generate addresses for performing programming, read, and erase operations.

[0148] Additionally, CPU 230 can perform Flash Translation Layer (FTL) functions. CPU 230 can use the FTL to translate Logical Block Addresses (LBAs) provided by the host into Physical Block Addresses (PBAs). The FTL can receive LBAs and translate them into PBAs using a mapping table. The address mapping methods of the FTL can vary depending on the mapping unit. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0149] Additionally, CPU 230 can generate commands without a request from host 2000. For example, CPU 230 can generate commands for background operations such as wear leveling for memory device 100 and garbage collection for memory device 100.

[0150] The internal memory 240 can be used as a storage unit for various information required for the operation of the controller 200. Specifically, the internal memory 240 may include a mapping table, and physical-logical address information and logical-physical address information may be stored in the mapping table. In addition, the internal memory 240 may be controlled by the CPU 230.

[0151] The buffer memory 250 can be used as the operating memory or cache memory of the CPU 230. Additionally, the buffer memory 250 can store code and commands executed by the CPU 230. The buffer memory 250 can also store data processed by the CPU 230. Furthermore, when implementing the buffer memory 250, it can be implemented using static RAM (SRAM) or dynamic RAM (DRAM).

[0152] The interleaving component 260 can identify operations performed by each memory cell included in the memory device 100. Here, the operation can be any one of a programming operation, a read operation, and an erase operation. Specifically, the interleaving component 260 can receive information from the memory device 100 via the memory interface 270 regarding the progress or completion of an operation performed by the memory device 100, and identify the operation performed by the memory device 100 based on the received information. According to embodiments of this disclosure, the interleaving component 260 can identify operations performed by the memory device 100 from either a separate operation controller 170 or a common operation controller 180 included in the control logic 160. Specifically, the interleaving component 260 can receive information from the separate operation controller 170 regarding a read operation being performed and the plane on which the read operation is being performed. Additionally, the interleaving component 260 can receive information from the common operation controller 180 regarding a programming operation being performed or an erase operation being performed. Furthermore, the interleaving component 260 can identify a retained programming or erase operation based on commands stored in the backup operation storage unit 185.

[0153] The memory interface 270 can communicate with the memory device 100 via a communication protocol based on the CPU 230. Specifically, the memory interface 270 can transmit commands, addresses, and data to the memory device 100 through a channel.

[0154] Figure 13 This is a diagram illustrating a memory card system according to an embodiment of the present disclosure.

[0155] Reference Figure 13 The memory card system 3000 may include a memory controller 3100, a memory device 3200, and a connector 3300.

[0156] The memory controller 3100 can be electrically connected to the memory device 3200, and the memory controller 3100 can be configured to access the memory device 3200. For example, the memory controller 3100 can be configured to control read operations, write operations, erase operations, and background operations of the memory device 3200. The memory controller 3100 can be configured to provide an interface between the memory device 3200 and a host. Additionally, the memory controller 3100 can drive firmware for controlling the memory device 3200.

[0157] For example, the memory controller 3100 may include components such as random access memory (RAM), a processor, a host interface, a memory interface, and error correction circuitry.

[0158] The memory controller 3100 can communicate with an external device via connector 3300. The memory controller 3100 can communicate with the external device (e.g., a host) according to a specific communication standard. For example, the memory controller 3100 can be configured to communicate with the external device via at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 3300 can be defined by at least one of the aforementioned communication standards.

[0159] For example, the memory device 3200 can be implemented as a variety of non-volatile memory elements such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin torque magnetic RAM (STT-MRAM).

[0160] The memory controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC), and universal flash storage (UFS).

[0161] Figure 14 This is a diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present disclosure.

[0162] Reference Figure 14 The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals SIG with the host 4100 through a signal connector 4001 and receive power PWR through a power connector 4002. The SSD 4200 may include an SSD controller 3210, multiple flash memory units 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0163] In one embodiment, the SSD controller 4210 may perform a reference... Figure 1 The memory controller 200 is described in terms of its functionality. The SSD controller 4210 can control a plurality of said flash memory memories 4221 to 422n in response to a signal SIG received from the host 4100. For example, the signal SIG can be a signal based on the interface between the host 4100 and the SSD 4200. For example, the signal SIG can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0164] Auxiliary power supply unit 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply unit 4230 can receive and charge power from host 4100. When the power supply from host 4100 is unstable, auxiliary power supply unit 4230 can provide power to SSD 4200. For example, auxiliary power supply unit 4230 can be located inside SSD 4200 or external to SSD 4200. For example, auxiliary power supply unit 4230 can be located on the motherboard and can provide auxiliary power to SSD 4200.

[0165] Buffer memory 4240 serves as a buffer for SSD 4200. For example, buffer memory 4240 may temporarily store data received from host 4100 or data received from the plurality of flash memories 4221 to 422n, or it may temporarily store metadata (e.g., mapping tables) of flash memories 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0166] Figure 15 This is a diagram illustrating a user system according to an embodiment of the present disclosure.

[0167] Reference Figure 15 The user system 5000 may include an application processor 5100, a memory module 5200, a network module 5300, a storage module 5400, and a user interface 5500.

[0168] Application processor 5100 can drive components, operating systems (OS), or user programs included in user system 5000. For example, application processor 5100 may include controllers, interfaces, and graphics engines that control components included in user system 5000. Application processor 5100 can be configured as a system-on-a-chip (SoC).

[0169] Memory module 5200 can operate as main memory, operational memory, buffer memory, or cache memory of user system 5000. Memory module 5200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, application processor 5100 and memory module 5200 may be packaged based on a stacked package (POP) and configured as a single semiconductor package.

[0170] Network module 5300 can communicate with external devices. For example, network module 5300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMAX, WLAN, UWB, Bluetooth, Wi-Fi, and 5G (Sub-6GHz, mmWave). For example, network module 5300 can be included in application processor 5100.

[0171] Storage module 5400 can store data. For example, storage module 5400 can store data received from application processor 5100. Alternatively, storage module 5400 can send data stored in storage module 5400 to application processor 5100. For example, storage module 5400 can be implemented as a non-volatile semiconductor memory element such as phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and three-dimensional NAND flash memory. For example, storage module 5400 can be configured as a removable storage device (removable drive) such as a memory card and an external drive of user system 5000.

[0172] For example, storage module 5400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be used in conjunction with a reference. Figures 1 to 12 The memory device described operates in the same manner. The memory module 5400 can be compared with the referenced... Figure 1 The memory system 1000 described operates in the same manner.

[0173] User interface 5500 may include interfaces for inputting data or instructions to application processor 5100 or for outputting data to external devices. For example, user interface 5500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 5500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0174] Cross-references to related applications

[0175] This application claims priority to Korean Patent Application No. 10-2020-0139606, filed with the Korean Intellectual Property Office on October 26, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple planes, each of which has multiple memory units; An independent operation controller, wherein each independent operation controller controls the reading operations on the plurality of planes; A common operation controller that controls programming or erasing operations on any one of the plurality of planes; The command decoder receives multiple commands and multiple addresses corresponding to the multiple commands from the memory controller, provides the read command among the multiple commands to the independent operation controller that controls the plane indicated by the address corresponding to the read command, and provides the programming command or erase command among the multiple commands to the common operation controller. as well as The peripheral circuitry generates operating voltages for the read, program, and erase operations based on the independent operation controller and the common operation controller. Specifically, when at least two of the programming command, the erasing command, and the reading command are received for the plurality of planes, the command decoder provides the at least two commands to execute the operations corresponding to the at least two commands in parallel, and When the memory device operates in response to one of the at least two commands, the other of the at least two commands is received.

2. The memory device according to claim 1, wherein, The command decoder provides the address among the plurality of addresses corresponding to the programming command or the erasure command to the common operation controller.

3. The memory device according to claim 1, wherein, The peripheral circuit includes a voltage generating circuit, which includes: A read voltage generator generates a voltage for the read operation; A programming voltage generator that generates a voltage for the programming operation; and An erase voltage generator generates a voltage for the erase operation.

4. The memory device according to claim 1, wherein, The independent operation controllers correspond to the first plane to the fourth plane respectively, and include the first independent operation controller to the fourth independent operation controller. The first independent operation controller to the fourth independent operation controller control the peripheral circuit to independently perform the read operation on the first plane to the fourth plane.

5. The memory device according to claim 1, wherein, The common operation controller includes: A programming operation controller that controls the peripheral circuitry to independently perform the programming operations on the plurality of planes; An erase operation controller that controls the peripheral circuitry to independently perform the erase operation on the plurality of planes; and A backup operation storage unit stores programming commands entered while the programming operation is being performed, and also stores erasure commands entered while the erasure operation is being performed.

6. The memory device according to claim 1, wherein, When a subsequent command to initiate another programming operation is input while the current programming operation is being performed, the common operation controller maintains the start of the other programming operation corresponding to the subsequent command.

7. The memory device according to claim 1, wherein, When a subsequent command to initiate another erase operation is entered while the erase operation is being performed, the common operation controller maintains the start of the other erase operation corresponding to the subsequent command.

8. The memory device of claim 3, further comprising: A line decoder is connected between the voltage generation circuit and the plurality of planes. The row decoder includes multiple decoders that correspond to the plurality of planes respectively.

9. The memory device according to claim 1, wherein, While the erase operation or the programming operation is being performed on at least one of the plurality of planes, when a read command is input for the remaining planes other than the at least one plane, the independent operation controller controls the peripheral circuitry to perform a read operation on the remaining planes.

10. The memory device according to claim 1, wherein, While the programming operation is being performed on at least one of the plurality of planes, when an erase command is input for the remaining planes other than the at least one plane, the common operation controller controls the peripheral circuitry to perform an erase operation on the remaining planes.

11. The memory device according to claim 1, wherein, While the erasure operation is being performed on at least one of the plurality of planes, the common operation controller controls the peripheral circuitry to perform programming operations on the remaining planes when programming commands for the remaining planes other than the at least one plane are input.

12. A memory device comprising: A memory cell array having multiple planes; Peripheral circuits, which respectively perform read operations, program operations, or erase operations on memory cells included in the plurality of planes; as well as The control logic controls the memory cell array and the peripheral circuitry to execute, in parallel, operations corresponding to at least two of the following commands received from the memory controller: a programming command initiating a programming operation on the plurality of planes, an erase command initiating an erase operation on the plurality of planes, and a read command initiating a read operation on the plurality of planes. Specifically, when a subsequent command to initiate another programming operation is input while the current programming operation is being performed, the control logic maintains the start of the other programming operation corresponding to the subsequent command, and Specifically, when a subsequent command to initiate another erase operation is input while the erase operation is being performed, the control logic maintains the start of the other erase operation corresponding to the subsequent command.

13. The memory device according to claim 12, wherein, The control logic includes: An independent operation controller controls the reading operations on the plurality of planes; A common operation controller that controls the programming or erasing operations on the plurality of planes; A backup operation storage unit stores the programming commands input during the execution of the programming operation and the erasure commands input during the execution of the erasure operation.

14. The memory device according to claim 13, wherein, The plurality of planes includes the first plane to the fourth plane, and The independent operation controller includes a first read operation controller to a fourth read operation controller, which controls the peripheral circuit to independently perform the read operation on the first plane to the fourth plane.

15. The memory device according to claim 12, wherein, The peripheral circuit includes: A read voltage generator generates a voltage for the read operation; A programming voltage generator, which is separately disposed from the read voltage generator, generates a voltage for the programming operation; and An erase voltage generator is provided separately from the read voltage generator or the programmable voltage generator, and generates a voltage for the erase operation.

16. The memory device according to claim 12, wherein, The peripheral circuitry includes multiple decoders connected to the memory cell array, each of which corresponds to one of the multiple planes.

17. The memory device of claim 12, further comprising: Page buffer group, which is connected to the memory cell array and buffers data, wherein the page buffer group includes multiple page buffers corresponding to the plurality of planes respectively.

18. A memory device comprising: Multiple planes, each of which has multiple memory units; An independent operation controller, wherein each independent operation controller controls the reading operations on the plurality of planes; A common operation controller controls programming or erasing operations on any one of the plurality of planes. This means that different operations can be performed simultaneously on different planes among the multiple planes. Specifically, when at least two of the programming, erasing, and reading commands are received for the plurality of planes, the at least two commands are provided to execute the operations corresponding to the at least two commands in parallel, and When the memory device operates in response to one of the at least two commands, the other of the at least two commands is received.

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