Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, on which a pattern transfer material layer is formed; forming a mask layer on the pattern transfer material layer, wherein an opening is formed in the mask layer and extends through the mask layer; forming a sidewall layer on the sidewall of the opening; using the sidewall layer as a mask, performing a first ion implantation on the pattern transfer material layer at the bottom of the opening, implanting target ions into the pattern transfer material layer to form a pattern layer extending through the pattern transfer material layer, wherein the target ions are used to improve the etching selectivity between the material transfer layer and the pattern layer; after forming the pattern layer, removing the mask layer and the sidewall layer. By forming the sidewall layer in the opening, the present invention facilitates ensuring that the target ion concentration at each position of the pattern layer along the thickness of the pattern layer meets process requirements, while also improving the problem of severe lateral diffusion of the target ions near the bottom of the opening, thereby facilitating improved sidewall verticality and line width accuracy of the pattern layer, thereby improving the accuracy of pattern transfer.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to advance towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In the development of integrated circuits, the functional density (i.e., the number of internal interconnect structures on each chip) generally increases while the geometric size (i.e., the minimum component size that can be produced using the process steps) decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] At present, as technology nodes continue to shrink, how to improve the accuracy of graphics transmission has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve pattern transfer accuracy.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a pattern transfer material layer is formed; forming a mask layer on the pattern transfer material layer, wherein an opening penetrating the mask layer is formed in the mask layer; forming a sidewall layer on the sidewall of the opening; using the sidewall layer as a mask, performing a first ion implantation on the pattern transfer material layer at the bottom of the opening, and injecting target ions into the pattern transfer material layer to form a pattern layer penetrating the pattern transfer material layer, wherein the target ions are used to improve the etching selectivity between the material transfer layer and the pattern layer; after forming the pattern layer, removing the mask layer and the sidewall layer.

[0007] Optionally, in the step of performing target ion implantation on the pattern transfer material layer at the bottom of the opening, the target ions are used to improve the etching resistance of the pattern layer; after forming the pattern layer, the forming method further includes: removing the remaining pattern transfer material layer.

[0008] Optionally, the step of forming the sidewall layer includes: forming a sidewall material layer at the bottom and sidewall of the opening, wherein the sidewall material layer also covers the top of the mask layer; removing the sidewall material layer located at the bottom of the opening and the top of the mask layer, and retaining the sidewall material layer at the sidewall of the opening as the sidewall layer.

[0009] Optionally, the step of forming the sidewall layer includes: forming a sidewall material layer at the bottom and sidewall of the opening, the sidewall material layer also covering the top of the mask layer, wherein the sidewall material layer located on the sidewall of the opening serves as the sidewall layer.

[0010] Optionally, after the first ion implantation and before removing the mask layer and the side wall layer, the formation method further includes: removing the side wall material layer located at the bottom of the opening and the top of the mask layer, retaining the side wall layer; after removing the side wall material layer located at the bottom of the opening and the top of the mask layer, using the side wall layer as a mask, performing a second ion implantation on the graphic layer exposed by the opening, and injecting the target ions into the graphic layer.

[0011] Optionally, the implantation energy of the second ion implantation is less than the implantation energy of the first ion implantation, and the implantation dose of the second ion implantation is greater than the implantation dose of the first ion implantation.

[0012] Optionally, after forming the graphic layer and before removing the mask layer and the sidewall layer, the formation method further includes: forming a protective layer in the opening to protect the graphic layer during the removal of the mask layer; the formation method further includes: removing the protective layer.

[0013] Optionally, the step of forming the protective layer in the opening includes: filling the opening with a protective material layer; and performing a planarization process on the protective material layer to retain the protective material layer in the opening as the protective layer.

[0014] Optionally, after the protective layer is formed in the opening, the mask layer is removed by a chemical mechanical polishing process, and the protective layer and the sidewall layer are removed during the chemical mechanical polishing process.

[0015] Optionally, after forming the protective layer, the mask layer is etched away using the protective layer and the side wall layer as masks; the step of removing the remaining graphic transfer material layer includes: using the protective layer and the side wall layer as masks, etching away the remaining graphic transfer material layer; after removing the remaining graphic transfer material layer, removing the protective layer and the side wall layer.

[0016] Optionally, the material of the protection layer is the same as that of the sidewall layer.

[0017] Optionally, the sidewall material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

[0018] Optionally, the material of the spacer layer includes one or more of SiCN, SiN and SiC.

[0019] Optionally, along a direction perpendicular to the sidewall of the opening, the thickness of the sidewall spacer layer is 5 nm to 20 nm.

[0020] Optionally, the material of the protective layer includes one or more of SiCN, SiN and SiC.

[0021] Optionally, the material of the pattern transfer material layer includes one or both of amorphous silicon and polycrystalline silicon.

[0022] Optionally, a wet etching process is used to remove the remaining pattern transfer material layer.

[0023] Optionally, the target ions include one or more of B, BF, C and In.

[0024] Optionally, the parameters of the first ion implantation include: implantation energy of 5 KeV to 20 KeV, implantation dose of 2E14 atoms per square centimeter to 2E15 atoms per square centimeter, and implantation angle of 0° to 5°.

[0025] Optionally, the parameters of the second ion implantation include: implantation energy of 2 KeV to 12 KeV, implantation dose of 5E14 atoms per square centimeter to 5E15 atoms per square centimeter, and implantation angle of 0° to 5°.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] In the formation method provided by an embodiment of the present invention, after the opening is formed in the mask layer, a sidewall layer is formed on the sidewall of the opening. After the sidewall layer is formed, a first ion implantation is performed on the pattern transfer material layer at the bottom of the opening to form a pattern layer penetrating the pattern transfer material layer, wherein the target ions are used to improve the etching selectivity between the pattern transfer material layer and the pattern layer. After the target ions are implanted into the pattern transfer material layer, lateral diffusion of the ions usually occurs. Since the sidewall layer occupies part of the space of the opening, the target ions are implanted into the pattern transfer material layer through the surface of the pattern transfer material layer exposed by the sidewall layer. The sidewall layer can provide a margin for the lateral diffusion of the target ions. Therefore, after the pattern layer is formed, it is easy to ensure that the target ion concentration at each position of the pattern layer meets the process requirements along the thickness direction of the pattern layer. At the same time, it can improve the problem of severe lateral diffusion of the target ions near the bottom of the opening, thereby facilitating the improvement of the sidewall verticality and line width accuracy of the pattern layer, thereby improving the accuracy of the pattern transfer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0029] Figures 5 to 12 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0030] Figures 13 to 19 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0031] The electrical performance and reliability of current devices still need to be improved. This paper analyzes the reasons why the electrical performance and reliability still need to be improved by combining a method for forming a semiconductor structure.

[0032] refer to Figures 1 to 4 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0033] refer to Figure 1 , providing a substrate 10, on which a pattern transfer material layer 20 is formed; forming an etch stop layer 30 on the pattern transfer material layer 20; forming a mask layer 31 on the etch stop layer 30; and forming an anti-reflective coating 32 on the mask layer 31.

[0034] refer to Figure 2 A patterning process is used to form an opening 33 in the mask layer 31 , and the opening 33 passes through the etch stop layer 30 , the mask layer 31 and the anti-reflective coating 32 .

[0035] refer to Figure 3 , forming the opening 33 (such as Figure 2 As shown), ions are implanted into the pattern transfer material layer 20 at the bottom of the opening 33 to form a pattern layer 21 penetrating the pattern transfer material layer 20.

[0036] The target ion implantation is used to improve the etching selectivity of the pattern layer 21 and the pattern transfer material layer 20. For example, the target ion implantation is used to improve the etching resistance of the pattern layer 21.

[0037] refer to Figure 4 After forming the pattern layer 21, the etch stop layer 30, the mask layer 31 and the anti-reflective coating 32 are removed.

[0038] exist Figure 4 After the above steps, the subsequent step further includes: removing the remaining pattern transfer material layer 20 exposed by the pattern layer 21 , thereby transferring the pattern to the substrate 10 using the pattern layer 21 .

[0039] However, when ions are injected into the pattern transfer material layer 20, the ion concentration generally decreases with increasing injection depth. Furthermore, after the ions are injected into the pattern transfer material layer 20, lateral diffusion of the ions generally occurs, and the degree of lateral diffusion slows down with increasing injection depth. Therefore, the ion concentration is higher near the top surface of the pattern layer 21. Simultaneously, due to the influence of lateral ion diffusion, the top line width of the pattern layer 21 is larger. Accordingly, the ion concentration is too low near the bottom of the pattern layer 21, and the bottom line width of the pattern layer 21 is smaller, ultimately resulting in the formation of the pattern layer 21 in an inverted trapezoidal shape. Furthermore, the etching rate of the material near the bottom of the pattern layer 21 is likely to be close to that of the pattern transfer material layer 20, so that after the remaining pattern transfer material layer 20 is removed, bottom footing defects are likely to occur, which can easily cause the pattern layer 21 to collapse, thereby reducing the pattern transfer accuracy.

[0040] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a pattern transfer material layer is formed; forming a mask layer on the pattern transfer material layer, wherein an opening penetrating the mask layer is formed in the mask layer; forming a sidewall layer on the sidewall of the opening; using the sidewall layer as a mask, performing a first ion implantation on the pattern transfer material layer at the bottom of the opening, and injecting target ions into the pattern transfer material layer to form a pattern layer penetrating the pattern transfer material layer, wherein the target ions are used to improve the etching selectivity between the material transfer layer and the pattern layer; after forming the pattern layer, removing the mask layer and the sidewall layer.

[0041] In the formation method provided by an embodiment of the present invention, after the opening is formed in the mask layer, a sidewall layer is formed on the sidewall of the opening. After the sidewall layer is formed, a first ion implantation is performed on the pattern transfer material layer at the bottom of the opening to form a pattern layer penetrating the pattern transfer material layer, wherein the target ions are used to improve the etching selectivity between the pattern transfer material layer and the pattern layer. After the target ions are implanted into the pattern transfer material layer, lateral diffusion of the ions usually occurs. Since the sidewall layer occupies part of the space of the opening, the target ions are implanted into the pattern transfer material layer through the surface of the pattern transfer material layer exposed by the sidewall layer. The sidewall layer can provide a margin for the lateral diffusion of the target ions. Therefore, after the pattern layer is formed, it is easy to ensure that the target ion concentration at each position of the pattern layer meets the process requirements along the thickness direction of the pattern layer. At the same time, it can improve the problem of severe lateral diffusion of the target ions near the bottom of the opening, thereby facilitating the improvement of the sidewall verticality and line width accuracy of the pattern layer, thereby improving the accuracy of the pattern transfer.

[0042] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 5 to 12 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0044] refer to Figure 5 , providing a substrate 100, on which a pattern transfer material layer 200 is formed.

[0045] The substrate 100 provides a foundation for subsequent processes.

[0046] According to actual process conditions, the base 100 includes a substrate and a functional structure formed on the substrate. For example, the functional structure may include semiconductor devices such as MOS field effect transistors, resistor structures, etc.

[0047] In this embodiment, the substrate is made of silicon. In other embodiments, the substrate may be made of one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other substrate types. In other embodiments, when the semiconductor structure formed is a fin field-effect transistor, the substrate may also be a substrate having fins.

[0048] In this embodiment, the formation method is applied to a back-end of line (BEOL) process in a semiconductor manufacturing process as an example. The base 100 further includes an intermetallic dielectric layer formed on the substrate. Subsequently, metal interconnects are formed in the intermetallic dielectric layer.

[0049] As an example, the top surface of the substrate 100 is the top surface of the intermetallic dielectric layer.

[0050] The pattern transfer material layer 200 is then patterned, so that the patterned pattern transfer material layer 200 is used to transfer the pattern to the substrate 100 .

[0051] In this embodiment, the pattern transfer material layer 200 is made of amorphous silicon (a-Si). Amorphous silicon has high process compatibility. By selecting amorphous silicon, it is easy to change the etching resistance of certain areas of the pattern transfer material layer 200 through ion doping, thereby facilitating patterning of the pattern transfer material layer 200. In other embodiments, the pattern transfer material layer can also be made of polycrystalline silicon.

[0052] In this embodiment, an etch stop layer 300 is further formed on the pattern transfer material layer 200 .

[0053] Subsequently, a mask layer having an opening is formed on the etch stop layer 300, and the opening is formed by etching the mask layer. The top surface of the etch stop layer 300 serves as an etching stop for etching the mask layer to form the opening, thereby reducing the probability of over etching (OE) of the pattern transfer material layer 200.

[0054] In this embodiment, the material of the etch stop layer 300 is a plasma enhanced oxide (PEOX) layer. The PEOX layer is deposited using a plasma enhanced chemical vapor deposition (PECVD) process, and the PEOX layer has a high density.

[0055] In other embodiments, the material of the etch stop layer may also be SiCN, SiOC, SiN, SiON, AlN or Al2O3.

[0056] Combined with reference Figure 5 and Figure 6 A mask layer 310 is formed on the pattern transfer material layer 200 , and an opening 330 penetrating the mask layer 310 is formed in the mask layer 310 .

[0057] The mask layer 310 is used as a mask for subsequent patterning of the pattern transfer material layer 200 .

[0058] Specifically, a first ion implantation is subsequently performed on the pattern transfer material layer 200 at the bottom of the opening 330 , and the mask layer 310 is used as a mask for the first ion implantation.

[0059] In this embodiment, the mask layer 310 is made of spin-on carbon (SOC). SOC is formed by a spin coating process, which has a low process cost. Moreover, the use of SOC helps to improve the flatness of the top surface of the mask layer 310, thereby providing a good interface for the formation of the opening 330.

[0060] In this embodiment, a patterning process is used to form the opening 330 in the mask layer 310 .

[0061] Specifically, the patterning process includes a dry etching process, and the mask layer 310 is etched to form the opening 330 in the mask layer 310 .

[0062] like Figure 5As shown, before forming the opening 330 , the process further includes: forming an anti-reflection layer 320 on the mask layer 310 .

[0063] In order to form the opening 330 in the mask layer 310, the formation method further includes: forming a patterned photoresist layer (not shown) on the anti-reflection layer 320; accordingly, using the photoresist layer as a mask, etching the anti-reflection layer 320 and the mask layer 310 in sequence along the patterned pattern opening to form the opening 330 located in the mask layer 310.

[0064] The process of forming a patterned photoresist layer includes steps such as coating, exposure, and development of the photoresist layer. The anti-reflective coating 320 is used to reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern.

[0065] As an example, the anti-reflective coating 320 is a bottom anti-reflective coating (BARC) layer. Specifically, the material of the anti-reflective coating 320 is Si-ARC (silicon-containing anti-reflective coating) material.

[0066] Therefore, in the process of forming the opening 330 in the mask layer 310 , the anti-reflection coating 320 is first etched to expose the mask layer 310 , and then the mask layer 310 exposed by the anti-reflection coating 320 is etched.

[0067] In this embodiment, after etching the mask layer 310 , the etch stop layer 300 is etched to expose the pattern transfer material layer 200 .

[0068] By exposing the pattern transfer material layer 200 , preparation is made for subsequent ion implantation of the pattern transfer material layer 200 .

[0069] Therefore, in this embodiment, the opening 330 penetrates the etch stop layer 300 , the mask layer 310 and the anti-reflective coating 320 .

[0070] Combined with reference Figure 7 and Figure 8 , a spacer layer 410 is formed on the sidewall of the opening 330 .

[0071] Subsequently, the sidewall layer 410 is used as a mask to perform a first ion implantation on the graphic transfer material layer 200 at the bottom of the opening 330, and target ions are implanted into the graphic transfer material layer 200 to form a graphic layer that penetrates the graphic transfer material layer 200. During the ion implantation, the sidewall layer 410 is used to provide a margin for the lateral diffusion of the target ions in the graphic transfer material layer 200.

[0072] Specifically, the step of forming the spacer layer 410 includes: forming a spacer material layer 400 at the bottom and sidewalls of the opening 330, wherein the spacer material layer 400 also covers the top of the anti-reflective coating 320; removing the spacer material layer 400 located at the bottom of the opening 330 and the top of the anti-reflective coating 320, and retaining the spacer material layer 400 located at the sidewalls of the opening 330 as the spacer layer 410.

[0073] In this embodiment, the spacer material layer 400 is formed by adopting an atomic layer deposition process.

[0074] In this embodiment, the spacer material layer 400 formed by the atomic layer deposition process has good thickness uniformity and good step coverage capability, so that the spacer material layer 400 can conformally cover the bottom and sidewalls of the opening 330 and the top of the anti-reflective coating 320.

[0075] In other embodiments, a chemical vapor deposition process may also be used to form the spacer material layer.

[0076] refer to Figure 8 , using a dry etching process (for example, an anisotropic dry etching process) to remove the sidewall material layer 400 located at the bottom of the opening 330 and the top of the anti-reflective coating 320 , and retaining the sidewall material layer 400 located at the sidewall of the opening 330 as the sidewall layer 410 .

[0077] The anisotropic dry etching process has anisotropic etching characteristics, with its vertical etching rate being much greater than its horizontal etching rate. This allows the spacer material layer 400 at the bottom of the opening 330 and the top of the anti-reflective coating 320 to be removed while retaining the spacer material layer 400 on the sidewalls of the opening 330. This helps improve the morphology quality of the formed spacer layer 410 and meets process requirements. Furthermore, by selecting a dry etching process, the etching stop position can be easily controlled, thereby reducing damage to the film layer located below the spacer material layer 400.

[0078] In this embodiment, the material of the spacer layer 410 includes one or more of SiCN, SiN and SiC.

[0079] The SiCN, SiN and SiC generally have the characteristics of high hardness and wear resistance, so that the formed sidewall layer 410 can maintain a good morphology and maintain accuracy when transferring patterns to the pattern transfer material layer 200.

[0080] It should be noted that the thickness of the sidewall layer 410 in the direction perpendicular to the sidewall of the opening 330 should not be too small or too large. If the thickness of the sidewall layer 410 is too small, it will be difficult to provide sufficient margin for the lateral diffusion of the target ions in the pattern transfer material layer 200 during the subsequent ion implantation process. The lateral diffusion of the target ions in the sidewall material layer 200 will be difficult to control, and near the bottom of the opening 330, it is easy to cause severe lateral diffusion of the target ions, resulting in an excessively large top line width (CD) of the pattern layer. If the thickness of the sidewall layer 410 is too large, it is easy to provide too much margin for the lateral diffusion of the target ions, which can easily cause the line width of the pattern layer to fail to meet process requirements. To this end, in this embodiment, the thickness of the sidewall layer 410 is 5nm to 20nm. For example, the thickness of the sidewall layer 410 is 7nm, 10nm, 15nm, or 17nm.

[0081] refer to Figure 9 , using the sidewall layer 410 as a mask, a first ion implantation is performed on the pattern transfer material layer 200 at the bottom of the opening 330 , where target ions are implanted into the pattern transfer material layer 200 to form the pattern layer 210 .

[0082] The target ions are used to improve the etching selectivity between the pattern transfer material layer 200 and the pattern layer 210 .

[0083] After the target ions are injected into the graphic transfer material layer 200, lateral diffusion of the ions usually occurs. Since the sidewall layer 410 occupies part of the space of the opening 330, the target ions are injected into the graphic transfer material layer 200 through the surface of the graphic transfer material layer 200 exposed by the sidewall layer 410. The sidewall layer 410 can provide a margin for the lateral diffusion of the target ions. Therefore, after the graphic layer 210 is formed, it is easy to make the target ion concentration at each position of the graphic layer 210 meet the process requirements along the thickness direction of the graphic layer 210. At the same time, it can improve the problem of severe lateral diffusion of the target ions near the bottom of the opening 330, which is beneficial to improve the sidewall verticality and line width accuracy of the graphic layer 210, thereby improving the accuracy of the graphic transfer.

[0084] Specifically, in order to ensure that the target ion concentration at each position of the graphic layer 210 meets the process requirements, the injection energy of the first ion injection can be increased. Since the sidewall layer 410 can provide a margin for the lateral diffusion of the target ions, the probability of the line width of the graphic layer 210 being too large is reduced, making it easier for the line width and sidewall morphology of the graphic layer 210 to meet the process requirements.

[0085] According to process requirements, after the pattern layer 210 is formed, the remaining pattern transfer material layer 200 may be a film layer to be removed, or the pattern layer 210 may be a film layer to be removed.

[0086] In this embodiment, the pattern layer 210 formed by implanting target ions has a greater etch resistance than the pattern transfer material layer 200. This allows the pattern layer 210 to be retained when the remaining pattern transfer material layer 200 is subsequently removed. In other embodiments, depending on different processes and requirements, the pattern transfer material layer may also have a greater etch resistance than the pattern layer.

[0087] The target ions may be one or more of B, BF, C and In.

[0088] By implanting one or more of the target ions B, BF, C, and In, the etching resistance of the pattern layer 210 can be significantly improved, thereby increasing the etching selectivity between the pattern transfer material layer 200 and the pattern layer 210. Furthermore, the target ions are highly stable, which helps improve the thermal and chemical stability of the pattern layer 210. Furthermore, the target ions are commonly used doping ions in the semiconductor field and have high process compatibility.

[0089] The parameters of the first ion implantation include: implantation energy of 5KeV to 20KeV, implantation dose of 2E14 atoms per square centimeter to 2E15 atoms per square centimeter, and implantation angle of 0° to 5°, wherein the implantation angle is the angle between the ion implantation direction and the surface normal direction of the graphic transfer material layer.

[0090] The injection energy of the first ion implantation should be neither too low nor too high. If the injection energy is too low, it will be difficult to ensure that the target ions are doped throughout the entire thickness of the pattern transfer material layer 200, which can easily cause the pattern layer 210 to assume an inverted trapezoidal shape. When the remaining pattern transfer material layer 200 is subsequently removed, void defects can easily appear at the bottom of the pattern layer 210, leading to the collapse of the pattern layer 210. If the injection energy is too high, the target ions can easily be implanted into other film layers below the pattern transfer material layer 200, thereby affecting the normal progress of subsequent processes and easily causing severe lateral diffusion of the target ions, which can easily lead to excessive line width dimensions in the pattern layer 210. To this end, in this embodiment, the injection energy of the first ion implantation is between 5 KeV and 20 KeV. For example, the injection energy of the first ion implantation is 5 KeV, 10 KeV, 15 KeV, or 20 KeV.

[0091] The implantation dose of the first ion implantation should be neither too low nor too high. The lower the implantation dose, the lower the doping concentration of the pattern layer 210, making it difficult for the etching selectivity between the pattern transfer material layer 200 and the pattern layer 210 to meet process requirements. If the implantation dose is too high, the doping concentration of the pattern layer 210 is too high, and the target ions in the pattern layer 210 are likely to diffuse into the remaining pattern transfer material layer 200, thereby adversely affecting the subsequent etching and removal of the remaining pattern transfer material layer 200. Therefore, in this embodiment, the implantation dose of the first ion implantation is 2E14 atoms per square centimeter to 2E15 atoms per square centimeter.

[0092] The angle between the injection direction of the first ion implantation and the surface normal of the pattern transfer material layer 200 should not be too large. If the angle is too large, the target ions may be easily mis-doped into other areas of the pattern transfer material layer 200. Furthermore, the target ions may be affected by shielding effects, thereby hindering the subsequent formation of the pattern layer 210. Therefore, in this embodiment, the angle between the injection direction of the first ion implantation and the surface normal of the pattern transfer material layer 200 is between 0° and 5°. Specifically, the angle can be 0 degrees, meaning that the injection direction is perpendicular to the surface of the pattern transfer material layer 200.

[0093] refer to Figure 10 After forming the pattern layer 210, the method further includes: Figure 9 A protective layer 420 is formed in the embodiment shown in FIG.

[0094] The protection layer 420 is used to protect the pattern layer 210 during the subsequent removal of the mask layer 310 .

[0095] The subsequent process also includes removing the mask layer 310 and the remaining graphic transfer material layer 200 to obtain the graphic layer 210. Therefore, this protective layer 420 is formed to protect the graphic layer 210 during the process of removing the mask layer 310, thereby reducing the probability of damage to the graphic layer 210, which is beneficial to ensuring the morphology quality and line width accuracy of the graphic layer 210, and correspondingly improving the accuracy of graphic transfer.

[0096] Specifically, the step of forming the protective layer 420 includes: filling the opening 330 with a protective material layer (not shown); and performing a planarization process on the protective material layer, leaving the protective material layer in the opening 330 as the protective layer 420 .

[0097] In this embodiment, a chemical mechanical polishing process is used to planarize the protective material layer.

[0098] In this embodiment, the top surface of the anti-reflection coating 320 is used as a stop position to perform a planarization process on the protective material layer.

[0099] The material of the protection layer 420 can be one or more of SiCN, SiN and SiC.

[0100] The SiCN, SiN and SiC generally have the characteristics of high hardness and wear resistance. When the mask layer 310 is removed, the protection layer 420 can play a good protective role on the pattern layer 210.

[0101] In this embodiment, the material of the protection layer 420 is the same as that of the sidewall layer 410 .

[0102] The protective layer 420 and the sidewall layer 410 are made of the same material, which reduces the probability of a gap or mutual interference between the protective layer 420 and the sidewall layer 410. The adhesion between the protective layer 420 and the sidewall layer 410 is high, and the protective layer 420 and the sidewall layer 410 can be removed in the same step later, simplifying the process steps.

[0103] refer to Figure 11 After forming the pattern layer 210, the mask layer 310 (eg Figure 8 As shown) and the sidewall layer 410 (as shown Figure 8 shown).

[0104] The mask layer 310 and the spacer layer 410 are removed to expose the pattern layer 210 and the pattern transfer material layer 200 , thereby preparing for the subsequent removal of the pattern transfer material layer 200 .

[0105] In this embodiment, the forming method further includes: removing the protective layer 420 .

[0106] After the pattern transfer material layer 200 exposed by the pattern layer 210 is subsequently removed, the substrate 100 is etched using the pattern layer 210 as a mask. By removing the protective layer 420, the pattern layer 210 is exposed, thereby preparing for the subsequent etching of the substrate 100.

[0107] In this embodiment, the mask layer 310, the etch stop layer 300 and the anti-reflective coating 320 are removed by chemical mechanical polishing, and the protective layer 420 (such as Figure 10 As shown) and the sidewall layer 410 (as shown Figure 8 shown).

[0108] The chemical mechanical polishing process combines the advantages of chemical polishing and mechanical polishing, and can ensure that the mask layer 310, the etch stop layer 300, the anti-reflective coating 320, the protective layer 420 (such as Figure 10 As shown) and the sidewall layer 410 (as shown Figure 8 shown) and obtain a better surface.

[0109] Moreover, in the same step, the mask layer 310 , the etch stop layer 300 , the anti-reflection layer 320 , the protection layer 420 and the spacer layer 410 are removed, thereby simplifying the process steps.

[0110] refer to Figure 12 After forming the pattern layer 210 , the forming method further includes: removing the remaining pattern transfer material layer 200 .

[0111] After removing the remaining pattern transfer material layer 200 , the substrate 100 is exposed, thereby preparing for subsequent etching of the substrate 100 using the pattern layer 210 as a mask.

[0112] In this embodiment, a wet etching process is used to remove the remaining pattern transfer material layer 200 (eg Figure 11 As shown), the graphic layer 210 is formed.

[0113] The wet etching process has the characteristic of isotropic etching, which is beneficial for clearing the remaining pattern transfer material layer 200 and improving the formation quality of the pattern layer 210 .

[0114] In other embodiments, the protective layer may be used as a mask, and the mask layer and the pattern transfer material layer may be removed first, and then the protective layer may be removed to obtain the pattern layer.

[0115] Figures 13 to 19 1 is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.

[0116] The similarities between the embodiment of the present invention and the aforementioned embodiment are not repeated here. The difference between the embodiment of the present invention and the aforementioned embodiment is that a first ion implantation is performed before etching the spacer material layer 810 .

[0117] refer to Figure 13 A spacer material layer 800 is formed at the bottom and sidewalls of the opening 730 , and the spacer material layer 800 also covers the top of the mask layer 710 , wherein the portion of the spacer material layer 800 located at the sidewall of the opening 730 is the spacer layer.

[0118] The first ion implantation is performed by using the sidewall material layer 800 located on the sidewall of the opening 730 as a sidewall layer, and the sidewall material layer 800 at the bottom 730 of the opening is not removed, so that the etching surface of the pattern layer formed in the subsequent process is more uniform.

[0119] For the description of the spacer material layer 800 and the spacer layer, reference may be made to the corresponding description in the aforementioned embodiment, which will not be repeated here.

[0120] Continue to refer Figure 13 , using the sidewall layer as a mask, performing a first ion implantation on the pattern transfer material layer 600 at the bottom of the opening 730 , implanting target ions into the pattern transfer material layer 600 to form a pattern layer 610 penetrating the pattern transfer material layer 600 .

[0121] The target ions are used to improve the etching selectivity between the pattern transfer material layer 600 and the pattern layer 610 .

[0122] For the description of the first ion implantation, reference may be made to the corresponding description in the aforementioned embodiment, which will not be repeated here.

[0123] refer to Figure 14 After the first ion implantation, the formation method further includes: removing the spacer material layer 800 located at the bottom of the opening 730 and the top of the mask layer 710, and retaining the spacer layer 810.

[0124] The spacer material layer 800 at the bottom of the opening 730 and the top of the mask layer 710 is removed to expose the pattern layer 610 at the bottom of the opening 730 , thereby preparing for the subsequent second ion implantation of the pattern layer 610 exposed by the opening 730 .

[0125] In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to remove the spacer material layer 800 located at the bottom of the opening 730 and the top of the mask layer 710. For a detailed description of this step, please refer to the corresponding description in the previous embodiment and will not be repeated here.

[0126] refer to Figure 15 After removing the sidewall material layer 800 located at the bottom of the opening 730 and the top of the mask layer 710, the sidewall layer 810 is used as a mask to perform a second ion implantation on the graphic layer 610 exposed by the opening 730, and the target ions are implanted into the graphic layer 610.

[0127] Since during the first ion implantation, the sidewall material layer 800 conformally covers the bottom and sidewalls of the opening 730, the thickness at the bottom corner of the opening 730 is usually larger, which easily reduces the implantation effect of the first ion implantation at the bottom corner of the opening 730. Therefore, the second ion implantation is performed so that the concentration of the target ions in the graphic layer 610 can meet the process requirements, thereby correspondingly improving the graphic accuracy of the graphic layer 610 and further ensuring that the graphic layer 610 and the graphic transfer material layer 600 maintain a high etching ratio.

[0128] The target ions may include one or more of B, BF, C, and In. For a detailed description of the target ions, reference may be made to the corresponding description in the aforementioned embodiments, which will not be repeated here.

[0129] The parameters of the second ion implantation include: implantation energy of 2KeV to 12KeV, implantation dose of 5E14 atoms per square centimeter to 5E15 atoms per square centimeter, and implantation angle of 0° to 5°, wherein the implantation angle is the angle between the ion implantation direction and the surface normal direction of the graphic transfer material layer.

[0130] In this embodiment, the second ion implantation is used to compensate for the ion concentration of the graphic layer 610 at the bottom corner of the opening 730. The implantation depth of the second ion is smaller. Therefore, the implantation energy of the second ion implantation is smaller than the implantation energy of the first ion implantation. Accordingly, at a smaller implantation energy, in order to ultimately ensure that the concentration of the target ions in the graphic layer 610 can meet the process requirements and improve the verticality of the side wall of the graphic layer 610, the implantation dose of the second ion implantation is smaller than the implantation dose of the first ion implantation.

[0131] The injection energy of the second ion implantation should be neither too low nor too high. If the injection energy is too low, the process effect of the second ion implantation will be reduced; if the injection energy is too high, the target ions will be easily implanted into other film layers below the pattern transfer material layer 600, thereby affecting the normal progress of subsequent processes. To this end, in this embodiment, the injection energy of the second ion implantation is 2KeV to 12KeV. For example, the injection energy of the second ion implantation is 2KeV, 5KeV, 7KeV, 9KeV, or 11KeV.

[0132] The second ion implantation dose should be neither too low nor too high. If the dose is too low, the process effect of the second ion implantation will be reduced. If the dose is too high, the doping concentration of the pattern layer 610 will be too high, and the target ions in the pattern layer 610 will easily diffuse into the remaining pattern transfer material layer 600, thereby affecting the subsequent etching and removal of the remaining pattern transfer material layer 600. Therefore, in this embodiment, the second ion implantation dose is 5E14 atoms per square centimeter to 5E15 atoms per square centimeter.

[0133] The angle between the injection direction of the second ion implantation and the surface normal of the pattern transfer material layer 600 should not be too large. If the angle is too large, the target ions may be easily mis-doped into other areas of the pattern transfer material layer 600. Furthermore, the target ions may be affected by the shadowing effect, thereby reducing the process effectiveness of the second ion implantation. To this end, in this embodiment, the angle between the injection direction of the second ion implantation and the surface normal of the pattern transfer material layer 600 is between 0° and 5°. Specifically, the angle can be 0 degrees, meaning that the injection direction is perpendicular to the surface of the pattern transfer material layer 600.

[0134] In this embodiment, the target ions of the second ion implantation are the same as the target ions of the first ion implantation.

[0135] The same target ions are used to reduce process difficulty and better improve the etching ratio of the pattern layer 610 and the pattern transfer material layer 600.

[0136] refer to Figure 16 , after the second ion implantation, further comprising: in the opening 730 (such as Figure 15 The protective layer 820 is formed in the process of removing the mask layer 710 to protect the graphic layer 610.

[0137] The subsequent process also includes removing the mask layer 710 and the remaining graphic transfer material layer 600 to obtain the graphic layer 610. Therefore, this protective layer 820 is formed to protect the graphic layer 610 during the process of removing the mask layer 710, thereby reducing the probability of damage to the graphic layer 610, which is beneficial to ensuring the morphology quality and line width accuracy of the graphic layer 610, and correspondingly improving the accuracy of graphic transfer.

[0138] It should be noted that, in this embodiment, the protection layer 820 is also used to protect the graphic layer 610 during the subsequent removal of the graphic transfer material layer 600 , thereby further reducing the probability of damage to the graphic layer 610 .

[0139] For a detailed description of the protective layer 820 and its formation process, reference may be made to the corresponding description in the aforementioned embodiments, which will not be repeated here.

[0140] refer to Figure 17 , using the protective layer 820 and the sidewall layer 810 as masks, the mask layer 710 is etched away (eg Figure 16 As shown), the anti-reflective coating 720 (as Figure 16 As shown) and the etch stop layer 700 (as shown Figure 16 shown).

[0141] The mask layer 710 is removed using the protection layer 820 as a mask, thereby protecting the morphology of the pattern layer 610 at the same time.

[0142] In this embodiment, a dry etching process is used to remove the mask layer 710 , the anti-reflective coating 720 , and the etch-stop layer 700 .

[0143] The dry etching process has anisotropic etching characteristics and good etching directionality, which is conducive to accurately removing the mask layer 710, the anti-reflective coating 720 and the etch stop layer 700, meeting process requirements.

[0144] refer to Figure 18 , using the protective layer 820 and the sidewall layer 810 as masks, remove the remaining pattern transfer material layer 600 (such as Figure 17 shown).

[0145] The remaining pattern transfer material layer 600 is removed using the protective layer 820 as a mask, while still protecting the morphology of the pattern layer 610 .

[0146] In this embodiment, a wet etching process is used to remove the remaining pattern transfer material layer 600 to expose the pattern layer 610 .

[0147] The wet etching process has the characteristic of isotropic etching, which is beneficial for clearing the remaining pattern transfer material layer 600 and improving the formation quality of the pattern layer 610 .

[0148] refer to Figure 19 , remove the protective layer 820 (such as Figure 18 As shown) and the sidewall layer 810 (as shown Figure 18 As shown), the graphic layer 610 is obtained.

[0149] In this embodiment, a chemical mechanical polishing process is used to remove the protection layer 820 and the sidewall layer 810 .

[0150] The chemical mechanical polishing process combines the advantages of chemical polishing and mechanical polishing, ensuring efficient removal of the protective layer 820 and the sidewall layer 810 while simultaneously achieving a better surface, which is conducive to obtaining a precise topography of the patterned layer 610. The detailed description of the formation method described in this embodiment can be combined with the corresponding description of the previous embodiment and will not be repeated here.

[0151] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, on which a pattern transfer material layer is formed; forming a mask layer on the pattern transfer material layer, wherein an opening penetrating the mask layer is formed in the mask layer; forming a sidewall layer on the sidewall of the opening; Using the sidewall layer as a mask, a first ion implantation is performed on the pattern transfer material layer at the bottom of the opening, wherein target ions are implanted into the pattern transfer material layer to form a pattern layer penetrating the pattern transfer material layer, wherein the target ions are used to improve the etching selectivity between the pattern transfer material layer and the pattern layer, and the sidewall layer is used to provide a margin for the lateral diffusion of the target ions; After forming the pattern layer, the mask layer and the sidewall layer are removed.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of implanting target ions into the pattern transfer material layer at the bottom of the opening, the target ions are used to improve the etching resistance of the pattern layer; After forming the pattern layer, the forming method further includes: removing the remaining pattern transfer material layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the spacer layer includes: forming a spacer material layer on the bottom and sidewalls of the opening, wherein the spacer material layer also covers the top of the mask layer; The spacer material layer located at the bottom of the opening and the top of the mask layer is removed, and the spacer material layer at the sidewall of the opening is retained as a spacer layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the spacer layer includes: forming a spacer material layer at the bottom and sidewall of the opening, the spacer material layer also covering the top of the mask layer, wherein the spacer material layer located on the sidewall of the opening serves as the spacer layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: After the first ion implantation and before removing the mask layer and the spacer layer, the forming method further comprises: removing the spacer material layer located at the bottom of the opening and the top of the mask layer, and retaining the spacer layer; After removing the sidewall material layer located at the bottom of the opening and the top of the mask layer, the sidewall layer is used as a mask to perform a second ion implantation on the pattern layer exposed by the opening to implant the target ions into the pattern layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: The implantation energy of the second ion implantation is less than the implantation energy of the first ion implantation, and the implantation dose of the second ion implantation is greater than the implantation dose of the first ion implantation.

7. The method for forming a semiconductor structure according to claim 2, wherein: After forming the pattern layer and before removing the mask layer and the sidewall layer, the forming method further comprises: forming a protection layer in the opening to protect the pattern layer during the process of removing the mask layer; The forming method further includes: removing the protective layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the protective layer in the opening includes: filling the opening with a protective material layer; The protective material layer is planarized, and the protective material layer in the opening is retained as a protective layer.

9. The method for forming a semiconductor structure according to claim 7, wherein: After the protection layer is formed in the opening, the mask layer is removed by a chemical mechanical polishing process, and the protection layer and the sidewall layer are removed during the chemical mechanical polishing process.

10. The method for forming a semiconductor structure according to claim 7, wherein: After forming the protective layer, using the protective layer and the sidewall layer as masks, etching to remove the mask layer; The step of removing the remaining pattern transfer material layer comprises: using the protective layer and the sidewall layer as masks to etch and remove the remaining pattern transfer material layer; After removing the remaining pattern transfer material layer, the protection layer and the sidewall layer are removed.

11. The method for forming a semiconductor structure according to claim 7, wherein: The material of the protection layer is the same as that of the sidewall layer.

12. The method for forming a semiconductor structure according to claim 3 or 4, wherein: The sidewall material layer is formed by adopting an atomic layer deposition process or a chemical vapor deposition process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the spacer layer includes one or more of SiCN, SiN and SiC.

14. The method for forming a semiconductor structure according to claim 1, wherein: Along a direction perpendicular to the sidewall of the opening, the thickness of the sidewall spacer layer is 5 nm to 20 nm.

15. The method for forming a semiconductor structure according to claim 7, wherein: The material of the protection layer includes one or more of SiCN, SiN and SiC.

16. The method for forming a semiconductor structure according to claim 1, wherein: The material of the pattern transfer material layer includes one or both of amorphous silicon and polycrystalline silicon.

17. The method for forming a semiconductor structure according to claim 2, wherein: A wet etching process is adopted to remove the remaining pattern transfer material layer.

18. The method for forming a semiconductor structure according to claim 1, wherein: The target ions include one or more of B, BF, C and In.

19. The method for forming a semiconductor structure according to claim 1, wherein: The parameters of the first ion implantation include: implantation energy of 5 KeV to 20 KeV, implantation dose of 2E14 atoms per square centimeter to 2E15 atoms per square centimeter, and implantation angle of 0° to 5°.

20. The method for forming a semiconductor structure according to claim 5, wherein: The parameters of the second ion implantation include: an implantation energy of 2 KeV to 12 KeV, an implantation dose of 5E14 atoms per square centimeter to 5E15 atoms per square centimeter, and an implantation angle of 0° to 5°.

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