A nano-grid structure and a preparation method and application thereof

Abstract

The application provides a nanometer gate structure, which comprises a wafer (1), a first composite dielectric isolation layer formed by horizontally and alternately arranging a first dielectric isolation layer (3C), a second dielectric isolation layer (4C) and a third dielectric isolation layer (5C) and a fourth dielectric isolation layer (6) on the wafer, a nanometer gate (10), a second composite dielectric isolation layer formed by the first dielectric isolation layer (3C) and the second dielectric isolation layer (4B), the nanometer gate (10), a fifth dielectric isolation layer (7B), the nanometer gate (10), a fifth dielectric isolation layer (7A), a sixth dielectric isolation layer (8C) and a seventh dielectric isolation layer (9), and a preparation method and application thereof. The method can simplify the preparation of the nanometer gate, accurately control the gate length size, realize the preparation of the nanometer gate device, and further improve the performance of the electronic device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication, not only to discrete devices, but also to the field of integrated circuit fabrication, specifically to a method for fabricating nanogates using thin film deposition technology. Background Technology

[0002] In the field of integrated circuits, there has been a continuous trend towards higher integration levels, with new processes and technologies constantly being developed to achieve chips with smaller linewidths, and these processes are gradually approaching their physical limits.

[0003] The gate is the control terminal of a transistor, and its size has a significant impact on the performance of electronic devices. Currently, fabricating gates at the nanoscale is becoming increasingly difficult. When fabricating electronic devices using existing photolithography techniques, the gate length depends not only on the resolution of the photolithography equipment but also on various influencing factors in the photolithography process, such as the type of photoresist, baking temperature, exposure dosage, development temperature, and time. This makes it difficult to precisely control the gate length, especially for nanoscale gate fabrication. Currently, the main method for fabricating nanopatterns is through extreme ultraviolet (EUV) lithography combined with FIN-FET technology, which is costly, requires large equipment, and is not easily mass-produced.

[0004] Besides using extreme ultraviolet (EUV) lithography to fabricate micro-patterns of 100 nm and below, electron beam lithography (EBL) can also be used. Since electrons have a very short de Broglie wavelength, fine structures below 10 nm can be fabricated. However, EBL has low efficiency and a strong proximity effect, requiring high equipment stability. Furthermore, significant challenges exist in the development and etching processes associated with electron beam lithography.

[0005] In order to maintain the continuous development of the integrated circuit industry, it is necessary to develop new fabrication methods to simplify the fabrication of nanoscale gates, precisely control the gate length, and realize the fabrication of nanoscale patterned devices, thereby improving the performance of electronic devices. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of current methods and to propose a method for fabricating nanogates by combining thin film deposition technology, thereby improving the device fabrication process and reducing the device fabrication cost.

[0007] Before describing the content of this invention, the following terms are defined as follows:

[0008] The term "ALD" refers to Atomic layer deposition.

[0009] The term "CMP" refers to Chemical Mechanical Polishing.

[0010] The term "RIE" refers to Reaction Ionetching.

[0011] The term "PECVD" refers to Plasma Enhanced Chemical Vapor Deposition.

[0012] The term "ICP-CVD" refers to Inductive Coupled Plasma Chemical Vapor Deposition.

[0013] The term "DUV lithography" refers to deep ultraviolet lithography.

[0014] The term "EUV lithography" refers to extreme ultraviolet lithography.

[0015] The term "HEMT" refers to High Electron Mobility Transistor.

[0016] The term "NAND" stands for: Not AND, computer flash memory device.

[0017] The term "PSG" refers to: phosphor silicon glass.

[0018] The term "ICP" refers to Inductively Coupled Plasma.

[0019] The term "MESFET" refers to Metal-Semiconductor Field Effect Transistor.

[0020] The term "MOSFET" refers to Metal-Oxide-Semiconductor Field-Effect Transistor.

[0021] To achieve the above objectives, a first aspect of the present invention provides a nanogate structure comprising a wafer (1) and a first composite dielectric isolation layer formed by a first dielectric isolation layer (3C), a second dielectric isolation layer (4C), a third dielectric isolation layer (5C), and a fourth dielectric isolation layer (6) arranged horizontally on the wafer, a nanogate (10), a second composite dielectric isolation layer formed by the first dielectric isolation layer (3C) and the second dielectric isolation layer (4B), a nanogate (10), a fifth dielectric isolation layer (7B), a nanogate (10), and a third composite isolation layer formed by the fifth dielectric isolation layer (7A), a sixth dielectric isolation layer (8C), and a seventh dielectric isolation layer (9);

[0022] The linewidth of the nanogate is consistent with the thickness of the first, third, and sixth dielectric isolation layers.

[0023] According to the nanogate structure of the first aspect of the present invention, the wafer material is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium, and a wafer having a functional layer;

[0024] The nanogrid is made of one or more of the following materials: gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, polycrystalline silicon, silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride; and / or

[0025] The material of the isolation layer is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide;

[0026] Preferably, the linewidth of the nanogrid structure is less than 100 nm, more preferably less than 28 nm, more preferably less than 14 nm, more preferably less than 7 nm, more preferably less than 5 nm, and most preferably less than 3 nm.

[0027] According to the nanogrid structure of the first aspect of the present invention, wherein the first, third, and sixth dielectric isolation layers are made of the same material; and / or

[0028] The second, fourth, fifth, and seventh dielectric isolation layers are made of the same material;

[0029] Preferably, the etching selectivity ratio of the materials of the first dielectric isolation layer and the second dielectric isolation layer is greater than 1:2.

[0030] A second aspect of the present invention provides a method for preparing the nanogrid described in the first aspect, the method comprising the following steps:

[0031] (a) Provide the wafers required for the fabrication process;

[0032] (b) Fabricating an isolation layer material on a wafer; preferably, the thickness of the isolation layer is 5 nm or more;

[0033] (c) The isolation layer is fabricated into a first patterned structure;

[0034] (d) Deposit a first dielectric isolation layer material to cover the first patterned structure;

[0035] (e) Deposit a second dielectric isolation layer material to cover the patterned structure;

[0036] (f) Depositing a third dielectric isolation layer material to cover the patterned structure; preferably, the third dielectric isolation layer material is the same as the first dielectric isolation layer material;

[0037] (g) Deposit a fourth dielectric isolation layer material to fill the trench and cover the surface; preferably, the fourth dielectric isolation layer material is the same as the second dielectric isolation layer material;

[0038] (h) The surface of the material obtained in step (g) is planarized to obtain an alternating structure of an isolation layer material, a first dielectric isolation layer, a second dielectric isolation layer superimposed with the first dielectric isolation layer to form a second composite dielectric isolation layer, a third, a second, and a fourth composite isolation layer superimposed with the first dielectric isolation layer, and a first composite isolation layer superimposed with the fourth, third, and second dielectric isolation layers, such that the height of the remaining dielectric isolation layer is the height of the initially deposited isolation layer material in step (b);

[0039] (i) Remove the isolation layer material obtained in step (b) to obtain a second pattern structure that is complementary to the first pattern structure;

[0040] (j) Deposit a fifth dielectric isolation layer material to cover the second patterned structure; preferably, the fifth dielectric isolation layer material is the same as the second dielectric isolation layer material;

[0041] (k) Deposit a sixth dielectric isolation layer material to cover the patterned structure; preferably, the sixth dielectric isolation layer material is the same as the first dielectric isolation layer material;

[0042] (l) Deposit a seventh dielectric isolation layer material to fill the trench and cover the surface; preferably, the seventh dielectric isolation layer material is the same as the second dielectric isolation layer material;

[0043] (m) The surface of the material obtained in step (l) is planarized to obtain a structure in which the first dielectric isolation layer, the second dielectric isolation layer superimposed on the first dielectric isolation layer form a second composite dielectric isolation layer, the third, the second and the first dielectric isolation layer superimposed on the fourth dielectric isolation layer form a first composite dielectric isolation layer, the fifth dielectric isolation layer, the sixth and the fifth dielectric isolation layer superimposed on the fifth dielectric isolation layer form a fifth composite dielectric isolation layer, and the seventh and the sixth the third composite dielectric isolation layer superimposed on the fifth dielectric isolation layer are arranged alternately;

[0044] (n) Etching removes the material at the locations of the exposed first dielectric isolation layer, fourth composite dielectric isolation layer and fifth dielectric isolation layer down to the wafer surface;

[0045] (o) Deposit nanogrid materials to fill trenches and cover the surface;

[0046] (p) Remove the nanogrid material from the surface of the material obtained in step (o) to obtain the nanogrid structure.

[0047] According to the preparation method of the second aspect of the present invention, in steps (d)-(g), (j)-(l), and (o), the deposition method is a thin film deposition technique, preferably selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, and electron beam evaporation;

[0048] According to the preparation method of the second aspect of the present invention, the pattern preparation technology in step (c) is selected from one or more of the following: photolithography, electron beam lithography, laser direct writing, etc.;

[0049] Preferably, the photolithography technology is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, and immersion lithography.

[0050] According to the preparation method of the second aspect of the present invention, the planarization method in steps (h) and (m) is selected from one or more of the following: CMP technology, PSG technology (depositing PSG material combined with heating to planarize the surface), ion selective bombardment (using ion selective bombardment of the surface to planarize it), large-area etching (including argon ion etching, RIE technology, ICP technology); preferably CMP technology.

[0051] According to the preparation method of the second aspect of the present invention, the method further includes the following steps:

[0052] (q) The non-nanogate retention area is processed using conventional processes to obtain the desired mesa structure;

[0053] Preferably, the conventional process is selected from one or more of the following: photolithography, wet etching, dry etching, etc.

[0054] A third aspect of the present invention provides a semiconductor device comprising a nanogate as described in the first aspect and / or a nanogate fabricated according to the fabrication method of the second or third aspect;

[0055] Preferably, the semiconductor device is selected from one or more of the following: integrated circuit, HEMT, MESFET, MOSFET, NAND Flash, NOR Flash, DRAM.

[0056] This invention relates to the field of semiconductor device fabrication, not only to discrete devices, but also to the field of integrated circuit fabrication.

[0057] This invention provides a method for fabricating nanogates using thin film deposition technology. The structure of the nanogates, from bottom to top, is as follows:

[0058] Wafers required for the process;

[0059] The first, second, and third dielectric isolation layers form a first composite dielectric isolation layer, a nanogate, the first and second dielectric isolation layers form a second composite dielectric isolation layer, a nanogate, a fifth dielectric isolation layer, a nanogate, and the fifth, sixth, and seventh dielectric isolation layers form a third composite isolation layer; the material surface after planarization.

[0060] Preferably, the wafer includes, but is not limited to, a silicon substrate, a sapphire substrate, etc.

[0061] Preferably, the wafer refers to a wafer having a functional layer;

[0062] Preferably, the material of the dielectric isolation layer includes, but is not limited to, silicon nitride, silicon oxide, and other materials;

[0063] Preferably, the first dielectric isolation layer is made of the same material as the third and sixth dielectric isolation layers;

[0064] Preferably, the second dielectric isolation layer is made of the same material as the fourth, fifth, and seventh dielectric isolation layers;

[0065] Preferably, the etching selectivity ratio between the first dielectric isolation layer and the second dielectric isolation layer is greater than 1:2;

[0066] Preferably, the preparation method of the dielectric isolation layer includes, but is not limited to, ALD, PECVD, ICP-CVD, etc.

[0067] Preferably, the material of the nanogate includes, but is not limited to, gold, nickel, aluminum, polycrystalline silicon, titanium nitride, etc.

[0068] Preferably, the nanograting is prepared by methods including, but not limited to, electron beam evaporation, sputtering, etc.

[0069] This invention provides a method for fabricating nanogratings using thin film deposition technology, comprising the following steps:

[0070] Provide wafers with planarized surfaces required for the process;

[0071] Fabricating isolation layer materials on the wafer surface;

[0072] The first patterned structure is obtained by using photolithography or other patterning techniques to fabricate the isolation layer;

[0073] A first dielectric isolation layer material is grown using thin film deposition technology to coat the patterned structure;

[0074] A second dielectric isolation layer material is grown using thin film deposition technology to coat the patterned structure;

[0075] A third dielectric isolation layer material is grown using thin film deposition technology to coat the patterned structure;

[0076] A fourth dielectric isolation layer material is grown using thin film deposition technology to fill trenches and cover the surface;

[0077] Using CMP technology, a planarized surface is obtained, and a structure is obtained in which the following materials are arranged alternately: an isolation layer material, a first dielectric isolation layer, a second dielectric isolation layer superimposed on the first dielectric isolation layer to form a second composite dielectric isolation layer, a third, a second, and a fourth composite isolation layer superimposed on the first dielectric isolation layer, and a first composite isolation layer superimposed on the fourth, third, and second dielectric isolation layers.

[0078] Remove the isolation layer material to obtain a second graphic structure that is complementary to the first graphic structure;

[0079] A fifth dielectric isolation layer material was grown using thin film deposition technology to coat the patterned structure.

[0080] A sixth dielectric isolation layer material was grown using thin film deposition technology to coat the patterned structure.

[0081] A seventh dielectric isolation layer material was grown using thin film deposition technology to fill the trenches and cover the surface;

[0082] Using CMP technology, a planarized surface is obtained, and a structure is obtained in which the following layers are arranged alternately: a first dielectric isolation layer, a second composite dielectric isolation layer formed by superimposing the second dielectric isolation layer with the first dielectric isolation layer, a fourth composite dielectric isolation layer formed by superimposing the third, second, and first dielectric isolation layers, a first composite dielectric isolation layer formed by superimposing the fourth, third, and second dielectric isolation layers with the first dielectric isolation layer, a fifth dielectric isolation layer, a fifth composite dielectric isolation layer formed by superimposing the sixth dielectric isolation layer with the fifth dielectric isolation layer, and a third composite dielectric isolation layer formed by superimposing the seventh and sixth fifth dielectric isolation layers.

[0083] Using etching technology, the material at the locations of the exposed first dielectric isolation layer, fourth composite dielectric isolation layer, and fifth dielectric isolation layer is removed down to the wafer surface;

[0084] Using materials deposition technology, nanogrid materials are deposited to fill trenches and cover the surface;

[0085] Using CMP technology, the surface nanogrid material is removed, exposing the first, second and third dielectric isolation layers to form a structure in which the first composite dielectric isolation layer, nanogrid, second composite dielectric isolation layer formed by the first and second dielectric isolation layers, nanogrid, fifth dielectric isolation layer, nanogrid, and third composite isolation layer formed by the fifth, sixth and seventh dielectric isolation layers are arranged alternately.

[0086] Perform subsequent processes to prepare the desired structure.

[0087] The wafers mentioned include not only common substrate materials, such as silicon, gallium arsenide, and silicon carbide substrates, but also wafers with functional layers;

[0088] The process involves depositing a dielectric isolation layer material on a wafer using thin film deposition technology, which includes, but is not limited to, ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, and other techniques.

[0089] The techniques for preparing the isolation layer include, but are not limited to, ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, and other techniques.

[0090] The dielectric isolation layer material includes, but is not limited to, silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, etc.

[0091] The isolation layer material includes, but is not limited to, silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, polyimide, etc.

[0092] The isolation layer is prepared using photolithography or other patterning techniques to obtain the relevant pattern structure. The photolithography techniques include controllable photolithography techniques such as ordinary ultraviolet lithography, DUV lithography, EUV lithography, and immersion lithography.

[0093] The isolation layer is prepared by photolithography or other patterning techniques to obtain the relevant pattern structure. Other patterning techniques include, but are not limited to, controllable patterning techniques such as electron beam lithography and laser direct writing.

[0094] The third and sixth dielectric isolation layer materials are grown using thin film deposition technology, and their materials are the same as those of the first dielectric isolation layer.

[0095] The fourth, fifth, and seventh dielectric isolation layer materials are grown using thin film deposition technology, and their materials are the same as those of the second dielectric isolation layer.

[0096] The first dielectric isolation layer material and the second dielectric isolation layer material are grown using thin film deposition technology. The two materials should have a large etching selectivity ratio, which is greater than 1:2.

[0097] The material deposition technology is used to deposit materials, fill the grid trenches, and cover the surface. The deposition technology includes, but is not limited to, electron beam evaporation, sputtering, chemical deposition, and other techniques.

[0098] The material deposition technology is used to deposit materials, fill the grid trenches, and cover the surface. The materials include, but are not limited to, gold, aluminum, nickel, titanium, polycrystalline silicon, tungsten, titanium nitride, etc.

[0099] In the process described above, the non-nanogate retention area can be treated using conventional processes to obtain the desired mesa structure;

[0100] The final linewidth is determined by the thickness of the first, third, and sixth dielectric isolation layers. The thickness is not specifically specified and can cover the current 100nm, 28nm, 14nm, and 7nm processes, and can even be extended to 5nm, 3nm, and other processes.

[0101] The process result is a nanogate structure, and the subsequent process applications of this nanogate include, but are not limited to, microelectronic devices such as HEMT and memory devices such as NAND.

[0102] The method of the present invention may have, but is not limited to, the following beneficial effects:

[0103] The method of this invention can simplify the fabrication of nanoscale gates, precisely control the gate length, and realize the fabrication of nanoscale gate devices, thereby improving the performance of electronic devices. Attached Figure Description

[0104] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings, wherein:

[0105] Figure 1 The flowcharts of embodiments 1-2 of the present invention are shown.

[0106] Figure 2 A schematic diagram of the preparation of the isolation layer in Embodiments 1-2 of the present invention is shown.

[0107] Figure 3 The diagram shows a schematic of the fabrication of a patterned structure on an isolation layer in Embodiments 1-2 of the present invention.

[0108] Figure 4 The diagram shows a schematic of the patterned structure covered by the first dielectric isolation layer in Embodiments 1-2 of the present invention.

[0109] Figure 5 The diagram shows a schematic of the patterned structure covered by a second dielectric isolation layer in Embodiments 1-2 of the present invention.

[0110] Figure 6 The diagram shows a schematic of the patterned structure covered by a third medium isolation layer in Embodiments 1-2 of the present invention.

[0111] Figure 7 The diagram shows a schematic of filling the trench using a fourth medium isolation layer in Embodiments 1-2 of the present invention.

[0112] Figure 8 The diagram shows a surface planarization process using CMP in Embodiments 1-2 of the present invention.

[0113] Figure 9 The diagram shows the result after removing the isolation layer in Embodiments 1-2 of the present invention.

[0114] Figure 10 The diagram shows a schematic of the patterned structure covered by the fifth medium isolation layer in Embodiments 1-2 of the present invention.

[0115] Figure 11 The diagram shows a schematic of the patterned structure covered by the sixth medium isolation layer in Embodiments 1-2 of the present invention.

[0116] Figure 12 The diagram shows a schematic of filling the trench using a seventh medium isolation layer in embodiments 1-2 of the present invention.

[0117] Figure 13 The diagram shows a surface planarization process using CMP in Embodiments 1-2 of the present invention.

[0118] Figure 14This diagram illustrates how, in Embodiments 1-2 of the present invention, material at the locations of the exposed first dielectric isolation layer, fourth composite dielectric isolation layer, and fifth dielectric isolation layer is removed to the wafer surface using etching technology.

[0119] Figure 15 The diagram illustrates the fabrication of gates using material deposition technology in Embodiments 1-2 of the present invention.

[0120] Figure 16 The diagram illustrates the removal of surface gate material using CMP technology in Embodiments 1-2 of the present invention.

[0121] Explanation of reference numerals in the attached figures:

[0122] 1. Wafer; 2. Isolation layer material; 3A, 3B, 3C, First dielectric isolation layer material; 4A, 4B, 4C, Second dielectric isolation layer material; 5A, 5B, 5C, Third dielectric isolation layer material; 6. Fourth dielectric isolation layer material; 7A, 7B, 7C, Fifth dielectric isolation layer material; 8A, 8B, 8C, Sixth dielectric isolation layer material; 9. Seventh dielectric isolation layer material; 10. Gate material. Detailed Implementation

[0123] The present invention will be further illustrated below with specific embodiments. However, it should be understood that these embodiments are merely for more detailed and specific illustration and should not be construed as limiting the present invention in any way.

[0124] This section provides a general description of the materials and testing methods used in the experiments of this invention. While many of the materials and methods of operation used to achieve the objectives of this invention are well known in the art, the invention is still described in as much detail as possible herein. It will be apparent to those skilled in the art that, unless otherwise stated in the context, the materials and methods of operation used in this invention are well known in the art.

[0125] Example 1

[0126] This embodiment illustrates the method for preparing nanogratings using thin film deposition technology according to the present invention.

[0127] The specific process is as follows: Figure 1 As shown, it includes the following steps:

[0128] S100: Provides wafers 1 required for process fabrication;

[0129] S200: Preparation of isolation layer material 2;

[0130] S300: The isolation layer 2 is fabricated into a strip-shaped pattern structure;

[0131] S400: Material 3 for the first media isolation layer, classified as 3A, 3B, and 3C according to different deposition locations;

[0132] S500: Deposited second medium isolation layer material 4, which is divided into 4A, 4B and 4C according to different deposition locations;

[0133] S600: Material 5 for depositing the third medium isolation layer, classified as 5A, 5B, and 5C according to different deposition locations;

[0134] S700: Deposit fourth medium isolation layer material 6 to fill the trench;

[0135] S800: The material surface is planarized to obtain an alternating structure of an isolation layer material, a first dielectric isolation layer, a second dielectric isolation layer superimposed on the first dielectric isolation layer to form a second composite dielectric isolation layer, a third, a second, and a fourth composite isolation layer superimposed on the first dielectric isolation layer, and a first composite isolation layer superimposed on the fourth, third, and second dielectric isolation layers.

[0136] S900: Remove the isolation layer material;

[0137] S1000: Depositional fifth media isolation layer material 7, classified into 7A, 7B, and 7C according to different deposition locations;

[0138] S1100: Material 8 for the sixth media isolation layer, classified as 8A, 8B, and 8C according to different deposition locations;

[0139] S1200: Deposit the seventh medium isolation layer material 9 to fill the trench;

[0140] S1300: The material surface is planarized to obtain a structure in which the following layers are arranged alternately: a first dielectric isolation layer, a second composite dielectric isolation layer formed by superimposing the second dielectric isolation layer with the first dielectric isolation layer, a third, a second, and a fourth composite dielectric isolation layer formed by superimposing the first dielectric isolation layer, a fourth, a third, and a second composite dielectric isolation layer formed by superimposing the first dielectric isolation layer, a fifth dielectric isolation layer, a sixth and a fifth composite dielectric isolation layer formed by superimposing the fifth dielectric isolation layer, and a seventh and a sixth composite dielectric isolation layer formed by superimposing the fifth dielectric isolation layer.

[0141] S1400: Etching removes the material at the locations of the exposed first dielectric isolation layer, third dielectric isolation layer, and sixth dielectric isolation layer down to the wafer surface;

[0142] S1500: Deposited gate material 10;

[0143] S1600: Planarize the material surface and remove the gate material 10 from the surface.

[0144] In this embodiment, the material of wafer 1 in S100 can be selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium, and wafers with functional layers.

[0145] In a preferred embodiment, the material of wafer 1 is selected as a silicon substrate with a (001) crystal orientation.

[0146] The isolation layer preparation technology described in S200 is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, etc.

[0147] In this embodiment, the material of the dielectric isolation layer is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, polyimide, etc.

[0148] In a preferred embodiment, a 1µm layer of isolation material 2 and photoresist material are spin-coated using spin-coating technology, such as... Figure 2 As shown.

[0149] The pattern preparation technology described in S300 is selected from one or more of the following: photolithography, electron beam lithography, and laser direct writing; the photolithography technology is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, and immersion lithography.

[0150] In a preferred embodiment, photolithography is used, employing a photoresist substrate with a linewidth of 190 nm, a spacing of 230 nm, and a period of 420 nm. The linewidth and spacing are selected based on design requirements and subsequent process design. Exposure and development processes are then performed using photolithography to obtain the corresponding photoresist pattern structure. For example... Figure 3 As shown.

[0151] The deposition method described in S400 is a thin film deposition technique, which is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.

[0152] In a preferred embodiment, using ALD technology, a 20nm first dielectric isolation layer material 3A, 3B, and 3C silica is grown at a deposition temperature of 200°C. The precursor materials used are aminosilane and water vapor, and the deposition time is 1 hour. The resulting surface pattern structure is as follows: Figure 4 As shown.

[0153] The deposition method described in S500 is a thin film deposition technique, which is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.

[0154] In a preferred embodiment, using ALD technology, a 50 nm thick second dielectric isolation layer material 4A, 4B, and 4C alumina is deposited at a deposition temperature of 300°C. The precursor materials used are trimethylaluminum and water vapor, and the deposition time is 2 hours. Figure 5 As shown.

[0155] The deposition method described in S600 is a thin film deposition technique, which is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.

[0156] In a preferred embodiment, 20nm third dielectric isolation layer materials 5A, 5B, and 5C silica are grown using ALD technology at a deposition temperature of 200°C. The precursor materials used are aminosilane and water vapor, and the deposition time is 1 hour. The resulting surface pattern structure is as follows: Figure 6 As shown.

[0157] The deposition method described in S700 is a thin film deposition technique, which is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.

[0158] In a preferred embodiment, CVD technology is used to deposit a 1µm thick fourth dielectric isolation layer material, 6A, 6B, and 6C alumina, at a deposition temperature of 380°C. The precursor materials used are trimethylaluminum and water vapor, and the deposition time is 30 minutes. Figure 7 As shown.

[0159] The planarization method described in S800 is selected from one or more of the following: CMP technology, PSG technology, ion selective bombardment, and large-area etching.

[0160] In a preferred embodiment, surface planarization is performed using CMP technology: a polishing machine combined with an alumina polishing slurry is used for polishing at a polishing rate of 10 nm / min, resulting in a residual dielectric isolation layer with a height equal to the initial deposited isolation layer material 2 photoresist height, i.e., 1 μm. This exposes a pattern of alternating alumina, silicon oxide, and alumina phases on the surface, such as... Figure 8 As shown.

[0161] The methods for removing the isolation layer material described in S900 include wet etching and dry etching.

[0162] In a preferred embodiment, the isolation layer 2 is removed by soaking in acetone for 3 minutes and then wiping it off; such as Figure 9 As shown.

[0163] The deposition method described in S1000 is a thin film deposition technique, which is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.

[0164] In a preferred embodiment, using ALD technology, a 50 nm thick fifth dielectric isolation layer material 7A, 7B, and 7C alumina is deposited at a deposition temperature of 300°C. The precursor materials used are trimethylaluminum and water vapor, and the deposition time is 2 hours. Figure 10 As shown.

[0165] The deposition method described in S1100 is a thin film deposition technique, which is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.

[0166] In a preferred embodiment, 20nm sixth dielectric isolation layer materials 8A, 8B, and 8C silica are grown using ALD technology at a deposition temperature of 200°C. The precursor materials used are aminosilane and water vapor, and the deposition time is 1 hour. The resulting surface pattern structure is as follows: Figure 11 As shown.

[0167] The deposition method described in S1200 is a thin film deposition technique, which is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.

[0168] In a preferred embodiment, a 1µm thick seventh dielectric isolation layer material, alumina, is deposited using CVD technology to fill the grooves in the pattern, such as... Figure 12 As shown.

[0169] The planarization method described in S1300 is selected from one or more of the following: CMP technology, PSG technology, ion selective bombardment, and large-area etching.

[0170] In a preferred embodiment, surface planarization is performed using CMP technology: a polishing machine combined with an alumina polishing slurry is used for polishing at a rate of 10 nm / min, resulting in a residual dielectric isolation layer with a height equal to the initial deposited isolation layer material 2, i.e., 1 μm. Figure 13 As shown.

[0171] The etching method described in S1400 is selected from one or more of the following: RIE, ICP.

[0172] In a preferred embodiment, RIE etching technology is used to etch away the exposed material at the locations of the first dielectric isolation layer 3B, the third dielectric isolation layer 5B, and the sixth dielectric isolation layer 8B down to the wafer surface; CHF3 and O2 are used as etching gases, with a power set to 150W and flow rates of CHF3:25sccm / O2:25sccm, respectively, and an etching time of 25min, resulting in a groove structure with a width of 20nm. Figure 14 As shown.

[0173] The deposition method described in S1500 is selected from one or more of the following: electron beam evaporation, sputtering, ALD, etc.

[0174] The gate material described in S1500 is selected from one or more of the following: gold, aluminum, nickel, titanium, germanium, platinum, chromium, polysilicon, titanium nitride, etc.

[0175] In a preferred embodiment, metallic aluminum is deposited using electron beam evaporation technology: metallic aluminum is evaporated using an electron beam evaporation device at a rate of 1 A / s, filling the trenches created by etching and achieving full surface coverage, such as... Figure 15 As shown.

[0176] The planarization method described in S1600 is selected from one or more of the following: CMP technology, PSG technology, and ion selective bombardment.

[0177] In a preferred embodiment, CMP (Chemical Mechanical Polishing) technology is used to planarize the surface: a polishing machine combined with aluminum polishing slurry is used for polishing at a rate of 10 nm / min to remove the gate metal 10 of aluminum from the surface. Finally, a device structure with aluminum as the gate is obtained, such as... Figure 16 As shown.

[0178] Figure 2 This is a schematic diagram corresponding to the spin coating of photoresist on the silicon surface in this embodiment; Figure 3 This diagram corresponds to the schematic diagram of fabricating a patterned structure on photoresist in this embodiment; Figure 4 A schematic diagram corresponding to the silicon dioxide covering pattern structure in this invention; Figure 5 A schematic diagram corresponding to the silicon oxide structure covered by the deposited alumina material of the present invention; Figure 6 A schematic diagram corresponding to the silica material deposited to cover the alumina structure of the present invention; Figure 7 A schematic diagram corresponding to the deposition of alumina to fully cover the trenches in this invention; Figure 8 This is a schematic diagram corresponding to the surface planarization performed by CMP according to the present invention; Figure 9 This diagram corresponds to the image after the photoresist has been removed. Figure 10 A schematic diagram corresponding to the silicon oxide structure covered by the deposited alumina material of the present invention; Figure 11 A schematic diagram corresponding to the silica material deposited to cover the alumina structure of the present invention; Figure 12 A schematic diagram corresponding to the deposition of alumina to fully cover the trenches in this invention; Figure 13 This is a schematic diagram corresponding to the surface planarization performed by CMP according to the present invention; Figure 14 This diagram corresponds to the state after the exposed silicon dioxide has been etched away. Figure 15 A schematic diagram corresponding to the deposition of metallic aluminum using an electron beam; Figure 16This diagram corresponds to the present invention's use of CMP for surface planarization to remove surface aluminum.

[0179] Example 2

[0180] The present invention relates to a method for fabricating nanogratings using thin film deposition technology, the specific process of which is as follows: Figure 1 As shown, it includes the following steps:

[0181] S100: Provides wafers 1 required for process fabrication;

[0182] S200: Preparation of isolation layer material 2;

[0183] S300: The isolation layer 2 is fabricated into a strip-shaped pattern structure;

[0184] S400: Material 3 for the first media isolation layer, classified as 3A, 3B, and 3C according to different deposition locations;

[0185] S500: Deposited second medium isolation layer material 4, which is divided into 4A, 4B and 4C according to different deposition locations;

[0186] S600: Material 5 for depositing the third medium isolation layer, classified as 5A, 5B, and 5C according to different deposition locations;

[0187] S700: Deposit fourth medium isolation layer material 6 to fill the trench;

[0188] S800: The material surface is planarized to obtain an alternating structure of an isolation layer material, a first dielectric isolation layer, a second dielectric isolation layer superimposed on the first dielectric isolation layer to form a second composite dielectric isolation layer, a third, a second, and a fourth composite isolation layer superimposed on the first dielectric isolation layer, and a first composite isolation layer superimposed on the fourth, third, and second dielectric isolation layers.

[0189] S900: Remove the isolation layer material;

[0190] S1000: Depositional fifth media isolation layer material 7, classified into 7A, 7B, and 7C according to different deposition locations;

[0191] S1100: Material 8 for the sixth media isolation layer, classified as 8A, 8B, and 8C according to different deposition locations;

[0192] S1200: Deposit the seventh medium isolation layer material 9 to fill the trench;

[0193] S1300: The material surface is planarized to obtain a structure in which the following layers are arranged alternately: a first dielectric isolation layer, a second composite dielectric isolation layer formed by superimposing the second dielectric isolation layer with the first dielectric isolation layer, a third, a second, and a fourth composite dielectric isolation layer formed by superimposing the first dielectric isolation layer, a fourth, a third, and a second composite dielectric isolation layer formed by superimposing the first dielectric isolation layer, a fifth dielectric isolation layer, a sixth and a fifth composite dielectric isolation layer formed by superimposing the fifth dielectric isolation layer, and a seventh and a sixth composite dielectric isolation layer formed by superimposing the fifth dielectric isolation layer.

[0194] S1400: Etching removes the material at the locations of the exposed first dielectric isolation layer, third dielectric isolation layer, and sixth dielectric isolation layer down to the wafer surface;

[0195] S1500: Deposited gate material 10;

[0196] S1600: Planarize the material surface and remove the gate material 10 from the surface.

[0197] In this embodiment, a 100nm thick isolation layer material 2 photoresist is first spin-coated onto a silicon substrate with a (001) crystal orientation on wafer 1 using spin-coating technology. For example... Figure 2 As shown.

[0198] Then, using photolithography, combined with a photoresist plate with a linewidth of 40nm, a spacing of 50nm, and a period of 90nm, exposure and development processes are performed. The exposure time is 4s, and the development time is 30s, to obtain the corresponding photoresist pattern structure; such as Figure 3 As shown. The linewidth and spacing are selected based on design requirements and subsequent process design. Then, using ALD technology, 5nm of the first dielectric isolation layer material 3A, 3B, and 3C silicon oxide is deposited; the deposition temperature is 200℃, the precursor materials used are aminosilane and water vapor, and the deposition time is 0.5h. Figure 4 As shown;

[0199] Then, using ALD technology, 10 nm thick second dielectric isolation layer materials 4A, 4B, and 4C silicon nitride were grown at a deposition temperature of 200°C. The precursor materials used were aminosilane and nitrogen, and the deposition time was 1 hour. The resulting surface pattern structure was as follows: Figure 5 As shown;

[0200] Then, using ALD technology, 5nm of the third dielectric isolation layer material 5A, 5B, and 5C silicon oxide was deposited; the deposition temperature was 200℃, the precursor materials used were aminosilane and water vapor, and the deposition time was 0.5h. Figure 6 As shown;

[0201] Next, using CVD technology, a 100nm thick fourth dielectric isolation layer material, silicon nitride, was deposited at a deposition temperature of 380℃. The precursor materials used were aminosilane and water vapor, and the deposition time was 3 minutes. The trenches of the pattern were then filled, as shown below. Figure 7 As shown;

[0202] Then, surface planarization is performed using CMP technology: a polishing machine combined with polishing fluid is used for polishing at a rate of 2 nm / min, so that the height of the residual dielectric isolation layer is equal to the height of the initial spin-coated isolation layer material 2 photoresist, i.e., 100 nm, exposing a pattern of alternating silicon oxide, silicon nitride, and silicon oxide phases on the surface, such as... Figure 8 As shown;

[0203] Then, the photoresist is removed using acetone to obtain a new patterned structure, such as... Figure 9 As shown;

[0204] Then, using ALD technology, 10nm of the fifth dielectric isolation layer materials 7A, 7B, and 7C silicon nitride were grown at a deposition temperature of 200℃. The precursor materials used were aminosilane and nitrogen gas, and the deposition time was 1 hour. The resulting surface pattern structure was as follows: Figure 10 As shown;

[0205] Then, using ALD technology, 5nm of the sixth dielectric isolation layer material 8A, 8B, and 8C silicon oxide was deposited; the deposition temperature was 200℃, the precursor materials used were aminosilane and water vapor, and the deposition time was 0.5h. Figure 11 As shown;

[0206] Next, using CVD technology, a 100nm thick seventh dielectric isolation layer material, silicon nitride, was deposited at a deposition temperature of 380℃. The precursor materials used were aminosilane and water vapor, and the deposition time was 3 minutes. The trenches of the pattern were then filled, as shown below. Figure 12 As shown;

[0207] Then, surface planarization is performed using CMP technology: a polishing machine combined with polishing slurry is used for polishing at a rate of 2 nm / min, so that the height of the residual dielectric isolation layer is equal to the initial spin-coated photoresist height, i.e., 100 nm, exposing a pattern of alternating silicon oxide, silicon nitride, and silicon oxide phases on the surface, such as... Figure 13 As shown;

[0208] Next, using RIE etching technology and CHF2 as the etching gas, the exposed silicon nitride and silicon oxide at the locations of the first dielectric isolation layer material 3B, the third dielectric isolation layer 5B, and the sixth dielectric isolation layer 8B were etched away. CHF2 was used as the etching gas, with a power of 150W, a flow rate of CHF2:25 sccm, and an etching time of 3 minutes, resulting in a groove structure with a width of 5 nm. Figure 14 As shown;

[0209] Then, using electron beam evaporation technology, metallic aluminum is deposited at a rate of 1 A / s to fill the etched trenches and achieve full surface coverage, such as... Figure 15 As shown;

[0210] Finally, CMP (Chemical Mechanical Polishing) technology was used to planarize the surface: a polishing machine combined with aluminum polishing fluid was used for polishing at a rate of 2 nm / min to remove the aluminum from the surface. This resulted in a device structure with aluminum as the gate metal, as shown below. Figure 16 As shown.

[0211] Figure 2 This is a schematic diagram corresponding to the spin coating of photoresist on the silicon surface in this embodiment; Figure 3 This diagram corresponds to the schematic diagram of fabricating a patterned structure on photoresist in this embodiment; Figure 4 A schematic diagram corresponding to the silicon dioxide covering pattern structure in this invention; Figure 5 A schematic diagram corresponding to the silicon nitride material deposited in this invention covering the silicon oxide structure; Figure 6 A schematic diagram corresponding to the silicon dioxide material deposited and covered silicon nitride structure of the present invention; Figure 7 A schematic diagram corresponding to the deposition of silicon nitride covering the entire trench in this invention; Figure 8 This is a schematic diagram corresponding to the surface planarization performed by CMP according to the present invention; Figure 9 This diagram corresponds to the image after the photoresist has been removed. Figure 10 A schematic diagram corresponding to the silicon nitride material deposited in this invention covering the silicon oxide structure; Figure 11 A schematic diagram corresponding to the silicon dioxide material deposited and covered silicon nitride structure of the present invention; Figure 12 A schematic diagram corresponding to the deposition of silicon nitride covering the entire trench in this invention; Figure 13 This is a schematic diagram corresponding to the surface planarization performed by CMP according to the present invention; Figure 14 This diagram corresponds to the state after the exposed silicon dioxide has been etched away. Figure 15 A schematic diagram corresponding to the deposition of metallic aluminum using an electron beam; Figure 16 This diagram corresponds to the present invention's use of CMP for surface planarization to remove surface aluminum.

[0212] The etching selectivity ratio of the materials of the first dielectric isolation layer and the second dielectric isolation layer is greater than 1:2.

[0213] Although the invention has been described to a certain extent, it is apparent that appropriate variations can be made to the various conditions without departing from the spirit and scope of the invention. It is understood that the invention is not limited to the described embodiments, but falls within the scope of the claims, which include equivalent substitutions for each of the elements.

Claims

1. A nanogrid structure, characterized in that, The nanogate structure package Including wafers And a first composite dielectric isolation layer and a nanogate formed by depositing a first dielectric isolation layer, a second dielectric isolation layer, a third dielectric isolation layer and a fourth dielectric isolation layer in sequence, arranged horizontally on the wafer; a second composite dielectric isolation layer and a nanogate formed by stacking the first dielectric isolation layer and the second dielectric isolation layer in sequence; a fifth dielectric isolation layer and a nanogate formed by stacking the seventh dielectric isolation layer and the sixth dielectric isolation layer in sequence; and a third composite dielectric isolation layer formed by stacking the seventh dielectric isolation layer and the sixth dielectric isolation layer and the fifth dielectric isolation layer in sequence. The linewidth of the nanogate is consistent with the thickness of the first, third, and sixth dielectric isolation layers.

2. The nanogrid structure according to claim 1, characterized in that, The material of the wafer is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, and germanium; The nanogrid is made of one or more of the following materials: gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, polycrystalline silicon, silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride; and / or The material of the isolation layer is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide.

3. The nanogrid structure according to claim 1 or 2, characterized in that, The linewidth of the nanogate structure is less than 100 nm.

4. The nanogrid structure according to claim 3, characterized in that, The linewidth of the nanogate structure is less than 28 nm.

5. The nanogrid structure according to claim 4, characterized in that, The linewidth of the nanogate structure is less than 14 nm.

6. The nanogrid structure according to claim 5, characterized in that, The linewidth of the nanogate structure is less than 7 nm.

7. The nanogrid structure according to claim 6, characterized in that, The linewidth of the nanogate structure is less than 5 nm.

8. The nanogrid structure according to claim 7, characterized in that, The linewidth of the nanogate structure is less than 3 nm.

9. The nanogrid structure according to claim 1 or 2, characterized in that, The wafer is a wafer with a functional layer; and / or The first, third, and sixth dielectric isolation layers are made of the same material; and / or The second, fourth, fifth, and seventh dielectric isolation layers are made of the same material.

10. The nanogrid structure according to claim 1 or 2, characterized in that, The etching selectivity ratio of the materials of the first dielectric isolation layer and the second dielectric isolation layer is greater than 1:

2.

11. The method for preparing the nanogate structure according to any one of claims 1 to 10, characterized in that, The method includes the following steps: (a) Provide the wafers required for the process fabrication; (b) Fabricating an isolation layer material on a wafer; (c) The isolation layer is fabricated into a first patterned structure; (d) Deposit a first dielectric isolation layer material to cover the first patterned structure; (e) Deposit a second dielectric isolation layer material to cover the patterned structure; (f) Deposit a third dielectric isolation layer material to cover the patterned structure; (g) Deposit a fourth dielectric isolation layer material to fill the trench and cover the surface; (h) The surface of the material obtained in step (g) is planarized to obtain an alternating structure of an isolation layer material, a first dielectric isolation layer, a second dielectric isolation layer superimposed with the first dielectric isolation layer to form a second composite dielectric isolation layer, a third, a second, and a fourth composite isolation layer superimposed with the first dielectric isolation layer, and a first composite isolation layer superimposed with the fourth, third, and second dielectric isolation layers, such that the height of the remaining dielectric isolation layer is the height of the initially deposited isolation layer material in step (b); (i) Remove the isolation layer material obtained in step (b) to obtain a second pattern structure that is complementary to the first pattern structure; (j) Deposit a fifth dielectric isolation layer material to cover the second patterned structure; (k) Deposit a sixth dielectric isolation layer material to cover the patterned structure; (l) Deposit the seventh medium isolation layer material, fill the trench and cover the surface; (m) The surface of the material obtained in step (l) is planarized to obtain a structure in which the first dielectric isolation layer, the second dielectric isolation layer superimposed on the first dielectric isolation layer form a second composite dielectric isolation layer, the third, the second, and the first dielectric isolation layer superimposed on the first dielectric isolation layer form a fourth composite dielectric isolation layer, the fourth, the third, and the second superimposed on the first dielectric isolation layer form a first composite dielectric isolation layer, the fifth dielectric isolation layer, the sixth superimposed on the fifth dielectric isolation layer form a fifth composite dielectric isolation layer, and the seventh and sixth superimposed on the fifth dielectric isolation layer form a third composite dielectric isolation layer are arranged alternately. (n) Etching removes the material at the locations of the exposed first dielectric isolation layer, fourth composite dielectric isolation layer, and fifth dielectric isolation layer down to the wafer surface; (o) Deposit nanogrid material to fill trenches and cover the surface; (p) Remove the nanogrid material from the surface of the material obtained in step (o) to obtain the nanogrid structure.

12. The method according to claim 11, characterized in that: In step (b), the thickness of the isolation layer is 5 nm or more; In step (f), the material of the third dielectric isolation layer is the same as the material of the first dielectric isolation layer; In step (g), the material of the fourth dielectric isolation layer is the same as the material of the second dielectric isolation layer; In step (j), the material of the fifth dielectric isolation layer is the same as the material of the second dielectric isolation layer; In step (k), the material of the sixth dielectric isolation layer is the same as the material of the first dielectric isolation layer; and / or In step (l), the material of the seventh dielectric isolation layer is the same as that of the second dielectric isolation layer.

13. The method according to claim 11, characterized in that, The material deposition method is thin film deposition technology.

14. The method according to claim 13, characterized in that, The thin film deposition technology is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, and electron beam evaporation.

15. The method according to any one of claims 11 to 14, characterized in that, The graphic structure described in step (c) has a spacing between its graphics that is not less than twice the thickness of the first dielectric isolation layer.

16. The method according to any one of claims 11 to 14, characterized in that, The fabrication technique for the patterned structure described in step (c) is selected from one or more of the following: photolithography, electron beam lithography, and laser direct writing.

17. The method according to claim 16, characterized in that... The photolithography technology is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, and immersion lithography.

18. The method according to any one of claims 11 to 14, characterized in that, The planarization method in steps (h) and (m) is selected from one or more of the following: CMP technology, PSG technology, ion selective bombardment, argon ion etching, RIE technology, ICP technology; and / or The process for removing the surface nanogrid material in step (p) is selected from one or more of the following: CMP technology, PSG technology, ion selective bombardment, argon ion etching, RIE technology, and ICP technology.

19. The method according to claim 18, characterized in that... The flattening methods in steps (h) and (m) are both CMP techniques.

20. The method according to any one of claims 11 to 14, characterized in that, The method further includes the following steps: (q) The non-nanogate retention area is processed using conventional processes to obtain the desired mesa structure.

21. The method according to claim 20, characterized in that... The conventional process described in step (q) is selected from one or more of the following: photolithography, wet etching, dry etching, etc.

22. A semiconductor device, characterized in that, The semiconductor device includes a nanogate as described in any one of claims 1 to 10 and / or a nanogate prepared according to the preparation method described in any one of claims 11 to 21.

23. The semiconductor device according to claim 22, characterized in that... The semiconductor device is selected from one or more of the following: integrated circuit, HEMT, MESFET, MOSFET, NAND Flash, NOR Flash, DRAM.

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