Three-dimensional memory and methods of making the same

Abstract

The application discloses a three-dimensional memory and a preparation method thereof. The preparation method comprises the following steps: forming a stack structure comprising a plurality of stepped terraces on a substrate; forming a hydrogen-containing medium covering layer on at least the plurality of stepped terraces, wherein the hydrogen-containing medium covering layer comprises hydrogen in any one or combination of a bonding form, a free single atom form and a free molecule form; and performing annealing treatment on the hydrogen-containing medium covering layer to form a modified medium covering layer. The preparation method of the three-dimensional memory provided by the application can effectively reduce lattice dislocation and wafer warping by performing low-temperature annealing treatment on the hydrogen-containing medium covering layer after the hydrogen-containing medium covering layer is formed to form the modified medium covering layer, which is beneficial to subsequent planarization treatment in a central region of the stack structure and can improve the overall performance of the three-dimensional memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more specifically, to a three-dimensional memory and a method for fabricating the same. Background Technology

[0002] Three-dimensional memory includes a stacked structure formed by alternating stacking of gates and inter-gate insulating layers. The central region of the stacked structure can be further divided into a memory array region with a memory array and a step region with multiple steps.

[0003] Typically, an insulating filler layer with a planarized top surface is required above the multiple steps in the stepped area. This insulating filler layer may include a high-density plasma (HDP) layer and a tetraethyl orthosilicate (TEOS) layer. The insulating filler layer's formation process can cause wafer warping, which is detrimental to subsequent processing of the stacked structure and affects the overall performance of the 3D memory.

[0004] Therefore, how to eliminate the adverse effects of the insulating filler layer on the performance of the three-dimensional memory structure is an urgent problem to be solved. Summary of the Invention

[0005] To address or partially address the aforementioned problems in related technologies, one aspect of this application provides a method for fabricating a three-dimensional memory. The method includes: forming a stacked structure comprising multiple stepped steps on a substrate; forming a hydrogen-containing dielectric capping layer on at least the multiple stepped steps, wherein the hydrogen-containing dielectric capping layer contains hydrogen in any one or a combination of bonded, free single atoms, and free molecules; and annealing the hydrogen-containing dielectric capping layer to form a modified dielectric capping layer.

[0006] In one embodiment of this application, annealing the hydrogen-containing dielectric coating layer after its formation includes: directly annealing the hydrogen-containing dielectric coating layer after its formation.

[0007] In one embodiment of this application, the annealing conditions are: annealing temperature of 500°C to 600°C and annealing time of 1 hour to 10 hours.

[0008] In one embodiment of this application, the annealing process further includes performing the annealing process under a low-pressure environment, wherein the pressure is less than or equal to 5 Torr.

[0009] In one embodiment of this application, forming a hydrogen-containing dielectric capping layer on at least the plurality of stepped surfaces includes: forming the hydrogen-containing dielectric capping layer on at least the plurality of stepped surfaces using a high-density plasma chemical vapor deposition process.

[0010] In one embodiment of this application, the hydrogen-containing dielectric capping layer includes a silicon hydroxide-containing layer.

[0011] In one embodiment of this application, the method further includes: forming a dielectric filling layer on the modified dielectric capping layer; planarizing the modified dielectric capping layer and the dielectric filling layer; and annealing the dielectric filling layer.

[0012] In one embodiment of this application, the dielectric filling layer comprises a tetraethyl orthosilicate material layer.

[0013] In one embodiment of this application, the planarization process includes any one or a combination of etching and chemical mechanical polishing processes.

[0014] In one embodiment of this application, the conditions for annealing the medium filling layer are: annealing temperature of 700°C to 800°C and annealing time of 5 minutes to 30 minutes.

[0015] In one embodiment of this application, the method further includes: after annealing the hydrogen-containing dielectric capping layer, forming a substrate conditioning layer on the surface of the substrate opposite to the stacked structure; and after planarizing the modified dielectric capping layer and the dielectric filling layer, removing the substrate conditioning layer.

[0016] In one embodiment of this application, the stacked structure includes alternating insulating layers and gate sacrificial layers, or the stacked structure includes alternating insulating layers and gate layers.

[0017] Another aspect of this application provides a three-dimensional memory comprising: a substrate; a stacked structure formed on the substrate and including a plurality of stepped steps; and a modified dielectric capping layer formed by annealing a hydrogen-containing dielectric capping layer containing hydrogen in any one or a combination of bonded, free single atoms, and free molecules, wherein the modified dielectric capping layer at least covers the plurality of stepped steps.

[0018] In one embodiment of this application, the modified dielectric capping layer includes a modified silicon oxide layer.

[0019] In one embodiment of this application, the memory further includes a dielectric filling layer formed on the modified dielectric overlay.

[0020] In one embodiment of this application, the dielectric filling layer comprises a tetraethyl orthosilicate material layer.

[0021] According to at least one embodiment of the present application, a three-dimensional memory and its fabrication method are provided. By performing low-temperature annealing on a hydrogen-containing dielectric capping layer, a modified dielectric capping layer is formed, which can effectively reduce lattice dislocations and wafer warpage. This is beneficial for subsequent processing such as planarization in the central region of the stacked structure (e.g., the memory array region and the step region), and can improve the overall performance of the three-dimensional memory.

[0022] Furthermore, after forming the hydrogen-containing dielectric coating layer, it can be directly subjected to low-temperature annealing to enhance the aforementioned beneficial effects.

[0023] Furthermore, the three-dimensional memory and its fabrication method provided according to at least one embodiment of this application can effectively reduce the fabrication cost of the three-dimensional memory, while expanding the process window of the modified dielectric capping layer by making the modified dielectric capping layer have greater stress and a thicker film thickness, thereby reducing lattice dislocations. Attached Figure Description

[0024] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Embodiments of this application are illustrated in the accompanying drawings by way of example rather than limitation, in which the same reference numerals indicate similar elements. Wherein:

[0025] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to one embodiment of this application;

[0026] Figure 2 This is a cross-sectional schematic diagram of the structure formed after forming a multilayer structure on a substrate according to a preparation method according to one embodiment of this application;

[0027] Figure 3 This is a schematic cross-sectional view of a structure formed after multiple stepped steps are formed in a laminated structure according to one embodiment of the preparation method of this application.

[0028] Figure 4 This is a flowchart of a preparation method for forming an insulating dielectric layer according to one embodiment of this application.

[0029] Figure 5 This is a flowchart of the method for fabricating a three-dimensional memory according to another embodiment of this application, specifically the process of forming an insulating dielectric layer;

[0030] Figure 6This is a cross-sectional schematic diagram of the structure formed after planarization treatment of the modified medium capping layer and the medium filling layer according to one embodiment of the preparation method of this application;

[0031] Figure 7 This is a cross-sectional electron microscope (TEM) top view of a structure formed after a substrate adjustment layer is formed on a surface of the substrate opposite to the stacked structure and planarization is performed according to an embodiment of this application; and

[0032] Figure 8 This is a cross-sectional electron microscope top view of the structure formed after planarization treatment of the modified dielectric capping layer formed by low-temperature annealing of the dielectric filling layer and the hydrogen-containing dielectric capping layer according to another embodiment of the present application. Detailed Implementation

[0033] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] In the accompanying drawings, the size, dimensions, and shapes of the elements have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not strictly to scale. Furthermore, the order in which the processing steps are described in this application does not necessarily indicate the order in which these processes occur in actual operation, unless otherwise expressly defined or inferred from the context.

[0035] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0036] Additionally, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. In an exemplary embodiment, when the device in one of the figures is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Therefore, depending on the specific orientation of the figure, the exemplary term “down” can encompass both “down” and “up” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Therefore, the exemplary term “below” or “under” can encompass both “up” and “down” orientations.

[0037] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0038] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added to the top surface of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0039] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Further, a layer may be a region of a homogeneous or non-homogeneous continuous structure, wherein the non-homogeneous continuous structure has a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may comprise multiple layers.

[0040] As used herein, the term "three-dimensional memory" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings") on a laterally oriented substrate, such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0041] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0043] Figure 1 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to one embodiment of this application. For example... Figure 1 As shown, this application provides a method 1000 for fabricating a three-dimensional memory, comprising:

[0044] S1, a stacked structure including multiple stepped steps is formed on the substrate.

[0045] S2, forming a hydrogen-containing medium covering layer on at least the plurality of step-like surfaces, wherein the hydrogen-containing medium covering layer contains hydrogen in any one or combination of bonding, free single atoms, and free molecules.

[0046] S3, anneal the hydrogen-containing dielectric coating layer to form a modified dielectric coating layer.

[0047] The specific processes of each step of the above preparation method 1000 will be described in detail below with reference to the accompanying drawings.

[0048] Step S1

[0049] Figure 2 This is a cross-sectional schematic diagram of the structure formed after forming a stacked structure 200 on a substrate 100 according to a preparation method according to one embodiment of this application. Figure 3 This is a schematic cross-sectional view of a structure formed after forming multiple stepped steps 500 in a laminated structure 200 according to a preparation method of one embodiment of this application.

[0050] like Figure 2 and Figure 3As shown, step S1, which forms a multi-step stacked structure on a substrate, may include, for example,: preparing a substrate 100; forming a multi-step stacked structure 200 on the substrate 100; and forming a multi-step stacked structure 500 in the multi-step stacked structure 200.

[0051] Specifically, such as Figure 2 As shown, in one embodiment of this application, the substrate 100 can be made of any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), or gallium arsenide and other group III-V compounds.

[0052] In one embodiment of this application, the substrate 100 for supporting the device structure thereon can be formed by sequentially depositing multiple layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0053] In one embodiment of this application, the substrate 100 may be a composite substrate, such as including a substrate, a substrate semiconductor layer and a substrate barrier layer formed sequentially.

[0054] The substrate semiconductor layer can be, for example, a polycrystalline silicon layer. Further, well regions formed in the substrate semiconductor layer by doping with N-type or P-type dopants via ion implantation or diffusion processes can be formed. In some embodiments of this application, the well regions can be prepared using the same dopant or different dopants; furthermore, the doping concentration of the well regions can be the same or different, and this application does not limit this.

[0055] Furthermore, the substrate barrier layer may be disposed on the outermost side of the substrate 100, and may include a single layer, multiple layers, or a suitable composite layer. Alternatively, when the substrate barrier layer is a composite layer, it may include any one or more of dielectric materials, semiconductor materials, and conductive materials.

[0056] After the substrate 100 is formed, a stacked structure 200 can be formed on the substrate 100.

[0057] Specifically, in one embodiment of this application, multiple thin film deposition processes may be used to form a stacked structure 200 on the surface of the substrate 100. The thin film deposition processes may include, but are not limited to, CVD, PVD, ALD or any combination thereof, and this application does not limit them.

[0058] Alternatively, a gate-last process can be used to fabricate the gate layer, and the stack structure 200 may include multiple pairs of insulating layers 210 and gate sacrificial layers 220 stacked alternately. In some embodiments, the insulating layer 210 and the gate sacrificial layer 220 may each include a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials used to form the insulating layer 210 and the gate sacrificial layer 220 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer, while the silicon nitride layer may be used as a sacrificial stack layer. The sacrificial stack layer may then be etched away and replaced with a conductive layer comprising a conductive material to form the gate layer of the three-dimensional memory. The alternatingly stacked insulating layers 210 and gate sacrificial layers 220 may constitute multiple stack layers, wherein each stack layer may include a gate sacrificial layer 210 and an adjacent insulating layer 220.

[0059] Alternatively, a gate-first process can be used to fabricate the gate layer, and the stacked structure may include multiple pairs of insulating layers and gates stacked alternately. The insulating layer may include at least one dielectric material; exemplary materials for forming the insulating layer may include silicon oxide. The silicon oxide layer (insulating layer) may be used as an isolation stack layer. The gate layer may be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides. The alternately stacked insulating and gate layers may constitute multiple stacked layers, wherein each stacked layer may include a gate layer and an adjacent insulating layer. In other words, the stacked structure for forming multiple steps may include alternately stacked insulating and gate sacrificial layers, or may include alternately stacked insulating and gate layers, which is not limited in this application.

[0060] Furthermore, with the increasing demand for 3D memory storage, the size of memory stacks is gradually increasing. To overcome the limitations of traditional processes, dual-stack or multi-stack techniques can be used to form a stacked structure by sequentially stacking multiple sub-stacked structures in the thickness direction of the stacked structure. Each sub-stacked structure may include multiple alternately stacked insulating layers and gate sacrificial layers (or gate layers). The number of layers in each sub-stacked structure may be the same or different. Since the fabrication process of the single-stacked structure described above is fully or partially applicable to the stacked structure consisting of multiple sub-stacked structures described herein, related or similar content will not be repeated. However, those skilled in the art will understand that subsequent fabrication processes can be performed based on multi-stacked or dual-stacked structures.

[0061] like Figure 3As shown, the stacked structure 200 may have a memory array region (not shown) and a step region 01. The memory array region can be used to form a memory array, and the step region 01 can be used to form multiple stepped steps 500. Subsequently, the gate layers in the memory array can be connected and turned on one by one through word line contacts formed on each stepped step. According to some embodiments, the memory array region may be located in the center of the stacked structure, and the step region may be located on one or more edges of the stacked structure. According to some embodiments, the step region may be located in the center of the stacked structure, and the memory array region may be located at the edge of the stacked structure. This application does not limit the relative position and specific structure of the memory array region and the step region.

[0062] Furthermore, the method 1000 for fabricating a three-dimensional memory provided in this application may also include, for example, forming a channel structure (not shown); and forming a virtual channel structure (not shown).

[0063] Specifically, the channel structure can be formed in the memory array region, the channel structure can penetrate the stacked structure 200 and extend into the substrate 100 in the direction perpendicular to the thickness of the stacked structure 200, and forming the channel structure may include, for example, forming a channel hole (not shown) penetrating the stacked structure 200; and sequentially forming a functional layer (not shown) and a channel layer (not shown) on the inner wall of the channel hole.

[0064] The via can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. Other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. The via can have a cylindrical or columnar shape that extends through the stacked structure 200 and extends over the substrate 100.

[0065] Furthermore, after forming a stacked structure using dual-stack or multi-stack technology, the stacked structure may include N sub-stacked structures, and correspondingly, the channel holes may also include N×M sub-channel holes, wherein each sub-stacked structure may include M sub-channel holes, where M≥1 and N≥2. Forming vias in a stacked structure using dual-stack or multi-stack techniques may include: forming a first sub-stacked structure on one side of a substrate and forming M vias penetrating the first sub-stacked structure and extending into the substrate; continuing to form subsequent sub-stacked structures and vias until an Nth sub-stacked structure and M vias located in the Nth sub-stacked structure are formed; then filling the corresponding vias in the N-1 sub-stacked structures other than the Nth sub-stacked structure with a via-filling sacrificial layer; and removing the via-filling sacrificial layer in the N-1 sub-stacked structures based on the M vias of the Nth sub-stacked structure, such that adjacent sub-channels in the N sub-stacked structures are at least partially aligned with each other to obtain M vias.

[0066] After the trench is formed, a functional layer, a trench layer, and a trench plug (not shown) and a filling medium layer (not shown) can be formed sequentially in the trench. The functional layer includes a barrier layer (not shown), a charge trapping layer (not shown), and a tunneling layer (not shown) sequentially disposed in the trench.

[0067] In one embodiment of this application, a functional layer and a channel layer can be formed in the channel hole by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0068] In some embodiments, the functional layer may include an oxide-nitride-oxide (ONO) structure. However, in other embodiments, the functional layer may have a structure different from that of an ONO configuration. For example, the functional layer may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0069] The channel layer can be used to transport the required charge (electrons or holes). According to an exemplary embodiment of this application, the channel layer can be formed on the surface of the tunneling layer by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0070] In some embodiments, the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer includes, but is not limited to, p-type doped polycrystalline silicon. Similar to the vias, the channel layer also extends through the stacked structure 200 and into the substrate 100.

[0071] Furthermore, in one embodiment of this application, a virtual channel structure may be formed in the stacked structure 200. The virtual channel structure penetrates the stacked structure 200 and extends to the substrate 100 in the direction perpendicular to the thickness of the stacked structure 200. The virtual channel structure may include a virtual channel via (not shown) and a filling dielectric layer (not shown) disposed in the virtual channel via. In the back gate process, the virtual channel structure can provide structural support for the operation of removing the gate sacrificial layer during the formation of the gate layer. The formation process of the virtual channel structure is similar to that of the channel structure and will not be described in detail here.

[0072] In the three-dimensional memory structure provided in this application, the step structure of the three-dimensional memory may include multiple step structures, each of which may include multiple stepped steps 500. Furthermore, each step structure may be a single stepped step structure or a partitioned stepped step structure, the partitioned stepped step structure having different partitions. Multiple step structures may be formed simultaneously or in stages, and this application does not limit this. Alternatively, multiple trimming-etching cycles can be performed on the edge portions of the stacked structure 200 to give the stacked structure 200 one or more sloping edges and a top (away from substrate 100) stacked layer pair shorter than the bottom (closer to substrate 100) stacked layer pair. Any suitable etching process (including any one or a combination of dry etching and wet etching processes) may be used in the step structure formation process, and this application does not limit this.

[0073] In some embodiments of this application, the channel structure may be formed after the plurality of stepped steps 500 are formed. In some other embodiments, the channel structure may be formed before the plurality of stepped steps 500 are formed. This application does not limit this to any particular embodiment.

[0074] Step S2

[0075] Refer again Figure 3 Step S2 involves forming a hydrogen-containing dielectric capping layer on at least a plurality of stepped steps, wherein the hydrogen-containing dielectric capping layer contains hydrogen in any form or combination of bonding, free single atoms, and free molecules. For example, this may include forming a hydrogen-containing dielectric capping layer 510 on the top surface of the stacked structure 200 away from the substrate 100 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, wherein the top surface of the stacked structure 200 includes at least the surface of a plurality of stepped steps 500.

[0076] In one embodiment of this application, the top surface of the stacked structure 200 may include a portion located in the step region 01, a portion located in the memory array region, and a portion located in the peripheral circuit region, wherein the peripheral circuit region may be located on the side of the step region away from the memory array region. Therefore, the hydrogen-containing dielectric capping layer 510 formed on the top surface of the stacked structure 200 may cover the step region 01, the memory array region, and the peripheral circuit region of the stacked structure 200. In other words, the hydrogen-containing dielectric capping layer 510 may at least cover the surfaces of a plurality of stepped surfaces 500, wherein the hydrogen-containing dielectric capping layer 510 contains hydrogen in any one or a combination of bonded, free single-atom, and free molecule forms.

[0077] Alternatively, a high-density plasma (HDP) layer can be formed as a hydrogen-containing dielectric capping layer 510 using a high-density plasma chemical vapor deposition process that has good thin film deposition gap-filling capabilities.

[0078] In one embodiment of this application, the hydrogen-containing dielectric capping layer 510 may be a silicon hydroxide-containing layer, such as a silicon oxide layer formed by a high-density plasma chemical vapor deposition process.

[0079] Step S3

[0080] Figure 4 This is a flowchart of a method for fabricating a three-dimensional memory according to one embodiment of this application, specifically the process of forming an insulating dielectric layer. Figure 5 This is a flowchart of the method for preparing a three-dimensional memory according to another embodiment of this application, specifically the process of forming an insulating dielectric layer. Figure 6 This is a method for preparing a modified medium covering layer (not shown) and a medium filling layer 520 (e.g., according to one embodiment of this application). Figure 3 (See diagram) A cross-sectional view of the structure formed after planarization.

[0081] like Figures 4 to 6 As shown, step S3, which involves annealing the hydrogen-containing dielectric capping layer to form a modified dielectric capping layer, may include, for example, annealing the intermediate structure of the hydrogen-containing dielectric capping layer 510 to form a modified dielectric capping layer (not shown); forming a dielectric filling layer 520 on the modified dielectric capping layer; and planarizing the modified dielectric capping layer and the dielectric filling layer 520.

[0082] In the structure of a 3D memory, the height of the stepped sections increases continuously, making them significantly higher than the peripheral circuit areas. To ensure the smooth progress of subsequent planarization processes in the central region of the stacked structure, an insulating dielectric layer is required. Typically, at least one of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, aluminum oxide, or any combination thereof, or a combination thereof, can be used to cover the surface of the stacked structure away from the substrate (including the surfaces of multiple stepped sections in the stepped region) to form the insulating dielectric layer. Then, planarization processes such as etching and chemical mechanical polishing are used to remove part of the insulating dielectric layer, thereby maintaining the surface of the entire wafer as flat.

[0083] The insulating dielectric layer is typically a composite structure, where a hydrogen-containing dielectric capping layer can be one layer within the composite structure. For example, the insulating dielectric layer in a composite structure may typically include a hydrogen-containing dielectric capping layer (HDP layer) deposited directly on the surface of the stacked structure and formed by, for example, a high-density plasma chemical vapor deposition process; and a dielectric filling layer deposited on the surface of the HDP layer, which may be a tetraethyl orthosilicate (TEOS) material layer formed using, for example, a TEOS source, wherein the hydrogen-containing dielectric capping layer can be used to isolate the step steps and the dielectric filling layer.

[0084] Because the insulating dielectric layer is very thick, its film stress can easily cause wafer warpage and film cracking. Therefore, in the fabrication process of 3D memory, the relatively thick dielectric filling layer in the insulating dielectric layer is usually treated, for example, by annealing the dielectric filling layer, in order to release its film stress and thus reduce wafer warpage. However, as the number of stacked layers in 3D memory increases, the dielectric filling layer becomes increasingly thick, and the effect of reducing wafer warpage gradually diminishes.

[0085] The inventors of this application have discovered that although the HDP layer is typically thinner than other layers in the insulating dielectric layer (e.g., dielectric filling layers), it contributes significantly to wafer warpage. Specifically, the HDP layer is rich in hydrogen in any combination of bonded, free single-atom, and free molecular forms, resulting in a large number of vacancies, voids, and impurities. This leads to significant thermal mismatches and lattice dislocations between the HDP layer and other layers. These thermal mismatches and lattice dislocations cause wafer warpage, hindering subsequent processing such as planarization in the central region of the stacked structure, and ultimately reducing the overall performance of the 3D memory.

[0086] Therefore, this application proposes to perform low-temperature annealing on the hydrogen-containing dielectric capping layer to effectively reduce lattice dislocations in the hydrogen-containing dielectric capping layer, thereby reducing wafer warpage and improving the overall performance of the three-dimensional memory.

[0087] Specifically, as an alternative, the annealing conditions described above can be: an annealing temperature of 500°C to 600°C and an annealing time of 1 hour to 10 hours. In one embodiment of this application, the intermediate structure including the hydrogen-containing dielectric capping layer 510 is annealed at a temperature of approximately 550°C and for approximately 4 hours.

[0088] Furthermore, the annealing temperature can also be approximately 520℃, 530℃, 555℃, 560℃, etc., and the annealing time can also be approximately 3 hours, 4.5 hours, 5 hours, 6 hours, etc. Those skilled in the art should understand that the above annealing temperatures and times are merely examples, and the various results and advantages described herein can be obtained by performing annealing with any other suitable process parameters without departing from the teachings of this application.

[0089] like Figure 4 As shown, in one embodiment of this application, the following steps for forming an insulating dielectric layer are typically included. For example, step S2: forming a hydrogen-containing dielectric capping layer (e.g., an HDP layer) on at least a plurality of stepped surfaces; step S20: after forming the hydrogen-containing dielectric capping layer, forming a substrate conditioning layer on the back side of the substrate (the surface opposite to the stacked structure); step S30: forming a dielectric filling layer (e.g., a TEOS layer) on the hydrogen-containing dielectric capping layer; step S40: planarizing the hydrogen-containing dielectric capping layer and the dielectric filling layer; step S50: removing the substrate conditioning layer; and step S60: performing a high-temperature annealing treatment on the dielectric filling layer.

[0090] The planarization process in step S40 removes part of the insulating dielectric layer through planarization processes such as etching and chemical mechanical polishing, thereby keeping the surface of the entire wafer flat. Due to the fixing effect of the substrate adjustment layer on the back side of the substrate, deformation during the planarization process can be reduced, thus lowering wafer warpage. However, the substrate adjustment layer's contribution to reducing wafer warpage is limited, and its formation is costly. Furthermore, the substrate adjustment layer formed on the back side of the substrate does not address the lattice dislocation problem, and therefore cannot improve the overall characteristics of the 3D memory.

[0091] Therefore, this application proposes to perform low-temperature annealing on the hydrogen-containing dielectric capping layer based on the above embodiments, so as to further solve the problem of lattice dislocation and reduce wafer warpage.

[0092] Alternatively, the hydrogen-containing dielectric capping layer can be annealed directly after its formation. Alternatively, the hydrogen-containing dielectric capping layer can be annealed in subsequent steps.

[0093] The following description uses the example of directly annealing the hydrogen-containing dielectric coating layer after its formation to illustrate the specific process and beneficial effects of annealing. Those skilled in the art should understand that annealing in subsequent steps after the formation of the hydrogen-containing dielectric coating layer can also follow the specific process described below and achieve the corresponding beneficial effects.

[0094] like Figure 3 , Figure 5 and Figure 6As shown, in another embodiment of this application, the following steps may be included to form an insulating dielectric layer. For example, step S2: forming a hydrogen-containing dielectric capping layer 510 (e.g., an HDP layer) on at least a plurality of stepped steps 500; step S3: after forming the hydrogen-containing dielectric capping layer 510, directly annealing it to reduce the hydrogen content in the hydrogen-containing dielectric capping layer 510 and forming a modified dielectric capping layer (not shown); step S4: forming a dielectric filling layer 520 (e.g., a TEOS layer) on the modified dielectric capping layer; step S5: performing a planarization treatment on the modified dielectric capping layer and the dielectric filling layer 520; and step S6: performing a high-temperature annealing treatment on the planarized dielectric filling layer 521.

[0095] Due to the low-temperature annealing process in step S3, the bound hydrogen (e.g., hydrogen in silicon-hydrogen bonds) and active groups (e.g., hydrogen in the form of free single atoms or free molecules) within the hydrogen-containing dielectric capping layer are released in the form of hydrogen gas. This causes the atoms in the hydrogen-containing dielectric capping layer to rearrange, eliminating or partially eliminating structural defects and forming a modified dielectric capping layer. Furthermore, the modified dielectric capping layer, after the above process, reduces the thermal stress of the film layer. Therefore, during the planarization process in step S5, it is possible to reduce wafer warpage and eliminate lattice dislocations.

[0096] Alternatively, the low-temperature annealing process in step S3 can be performed under ambient pressure, for example, 720–760 Torr. Performing the low-temperature annealing process under ambient pressure can reduce wafer warpage, eliminate lattice dislocations, and reduce thermal stress in the film layer by reducing process costs.

[0097] Alternatively, the low-temperature annealing process in step S3 can be performed under low pressure to enhance the above effects, such as reducing wafer warpage, eliminating lattice dislocations, and reducing thermal stress in the film. For example, the hydrogen-containing dielectric capping layer 510 can be low-temperature annealed under a pressure of 5 Torr or less.

[0098] In one embodiment of this application, the low-temperature annealing of the hydrogen-containing medium capping layer 510 can be performed under a pressure of, for example, 1.2 Torr.

[0099] Refer again Figure 3 In one embodiment of this application, the dielectric filling layer 520 formed in step S4 may be a tetraethyl orthosilicate (TEOS) material layer prepared by chemical vapor deposition using tetraethyl orthosilicate (TEOS) as a raw material.

[0100] Furthermore, in one embodiment of this application, to enhance the above-mentioned effects, for example, to further reduce wafer warpage, it is also possible to... Figure 5As shown in the dashed box, after the hydrogen-containing dielectric capping layer is directly annealed, a substrate conditioning layer is formed on the surface of the substrate away from the stacked structure. After the modified dielectric capping layer and dielectric filling layer are planarized, the substrate conditioning layer is removed to further reduce deformation during the planarization process and reduce wafer warpage.

[0101] Alternatively, the substrate conditioning layer may typically comprise an oxide layer formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and the thickness of the substrate conditioning layer may typically be approximately 1.2 micrometers.

[0102] Step S5, planarizing the modified dielectric capping layer and dielectric filling layer 520, may include, for example, removing excess portions of the insulating dielectric layer (e.g., including the modified dielectric and dielectric filling layer 520) using any one or a combination of etching and chemical mechanical polishing processes, to give the stacked structure 200 a planarized top surface. The structure obtained after the planarization process is as follows: Figure 6 As shown. The planarization process can be carried out using existing conventional techniques, depending on the actual needs, and will not be elaborated here.

[0103] Furthermore, the high-temperature annealing of the dielectric filling layer in step S6 has a completely different effect than the low-temperature annealing of the hydrogen-containing dielectric coating layer in step S3. In step S6, by performing high-temperature annealing on the dielectric filling layer, the film layer of the dielectric filling layer can be shrunk, facilitating the completion of subsequent processes. Alternatively, the annealing conditions for the dielectric filling layer can be: an annealing temperature of 700°C to 800°C and an annealing time of 5 to 30 minutes.

[0104] In one embodiment of this application, the dielectric filling layer is annealed at a temperature of approximately 750°C for approximately 10 minutes.

[0105] The method for fabricating a three-dimensional memory provided in at least one embodiment of this application can form a modified dielectric capping layer by performing low-temperature annealing on a hydrogen-containing dielectric capping layer, thereby effectively reducing lattice dislocations and wafer warpage, which is beneficial for subsequent planarization processing in the central region of the stacked structure, and ultimately improving the overall performance of the three-dimensional memory.

[0106] Furthermore, after forming the hydrogen-containing dielectric coating layer, it can be directly subjected to low-temperature annealing to enhance the aforementioned beneficial effects.

[0107] Furthermore, according to at least one embodiment of the present application, the method for fabricating a three-dimensional memory can effectively reduce the fabrication cost of the three-dimensional memory, and by making the modified dielectric capping layer have greater stress and a thicker film thickness, the process window of the modified dielectric capping layer can be expanded, thereby reducing lattice dislocations.

[0108] In addition, in at least one embodiment of this application, after annealing the hydrogen-containing dielectric capping layer, a substrate conditioning layer is formed on the surface of the substrate away from the stacked structure, which can further reduce deformation during processes such as planarization and reduce wafer warpage.

[0109] Figure 7 This is a cross-sectional electron microscope top view of a structure formed by forming a substrate adjustment layer on a surface of a substrate away from the stacked structure and performing planarization treatment according to an embodiment of this application. Figure 8 This is a cross-sectional electron microscope (TEM) top view of the structure formed after planarization treatment of a modified dielectric capping layer formed by low-temperature annealing of a dielectric filling layer and a hydrogen-containing dielectric capping layer according to another embodiment of this application. Table 1 is a comparison table of various indicators between the three-dimensional memory fabrication method provided in one embodiment of this application and the three-dimensional memory fabrication method provided in another embodiment of this application.

[0110] like Figure 7 As shown in Table 1, in one embodiment of this application, the typically selected process steps are: forming a hydrogen-containing dielectric capping layer (e.g., an HDP layer) on the surface of the stacked structure; and after forming the hydrogen-containing dielectric capping layer, forming a substrate conditioning layer on the back side of the substrate (away from the surface of the stacked structure); subsequently forming a dielectric filling layer (e.g., a TEOS layer) on the hydrogen-containing dielectric capping layer; and planarizing the hydrogen-containing dielectric capping layer and the dielectric filling layer. Due to the fixing effect of the substrate conditioning layer on the back side of the substrate, deformation during the planarization process can be reduced, thus reducing wafer warpage. The process and parameters for forming the substrate conditioning layer are typically: forming an oxide layer, for example, using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof; the thickness of the substrate conditioning layer is typically approximately 1.2 micrometers. The process and parameters for removing the substrate conditioning layer are typically: removing the substrate conditioning layer using any one or a combination of chemical mechanical polishing, etching, and photolithography. Therefore, in the above process, the cost of forming the substrate conditioning layer is usually $13.79 / pcs, the cost of removing the substrate conditioning layer is usually $1.03 / pcs, and the total cost is $14.82 / pcs.

[0111] By forming a substrate conditioning layer followed by planarization of the hydrogen-containing dielectric capping layer and dielectric filling layer, the thickness of the hydrogen-containing dielectric capping layer does not shrink after the above process. The non-shrinkage hydrogen-containing dielectric capping layer facilitates subsequent steps and ensures that the process thickness of this layer is formed according to the required thickness, thus reducing process complexity. However, the substrate conditioning layer contributes limitedly to reducing wafer warpage; typically, a substrate conditioning layer formed on the surface of the substrate away from the stacked structure can reduce wafer warpage by approximately 293 micrometers. Furthermore, this method does not solve the problem of lattice dislocations, such as… Figure 7 The irregular lines enclosed in the black circle represent lattice dislocations, which can be observed in... Figure 7 The local structure exhibits multiple lattice dislocations.

[0112] like Figure 8 As shown in Table 1, in another embodiment of the three-dimensional memory fabrication method provided in this application, a modified dielectric coating layer can be formed by performing a low-temperature annealing treatment after forming a hydrogen-containing dielectric coating layer. The process steps may include, for example, an annealing temperature of approximately 550°C and an annealing time of approximately 4 hours.

[0113] This application provides a method for fabricating a three-dimensional memory according to at least one embodiment. After planarization of the modified dielectric capping layer and the dielectric filling layer, the thickness of the modified dielectric capping layer does not shrink. The non-shrinkage modified dielectric capping layer facilitates subsequent steps and ensures that the process thickness of the layer is formed according to the required thickness, thus reducing the process difficulty. Furthermore, low-temperature annealing of the hydrogen-containing dielectric capping layer effectively reduces wafer warpage by approximately 350 micrometers. Additionally, the process cost of low-temperature annealing of the hydrogen-containing dielectric capping layer is $6 / pcs, which is only 40% of the overall cost of removing the substrate conditioning layer.

[0114] In addition, such as Figure 8 As shown, the cross-section of the intermediate formed after planarization is smooth and flat, without any lattice dislocations. Therefore, the method for low-temperature annealing of the hydrogen-containing dielectric capping layer provided in at least one embodiment of this application is beneficial for subsequent planarization in the central region of the stacked structure and can effectively reduce lattice dislocations and improve the overall performance of the three-dimensional memory.

[0115] Furthermore, in one embodiment of this application, after annealing the hydrogen-containing dielectric capping layer, a substrate conditioning layer can be formed on the substrate surface opposite to the stacked structure, thereby further reducing deformation during processes such as planarization and reducing wafer warpage. In this embodiment, although the manufacturing cost increases, the effect of reducing wafer warpage is significant.

[0116]

[0117]

[0118] Table 1

[0119] Refer again Figure 6 Another aspect of this application provides a three-dimensional memory. This three-dimensional memory can be fabricated using any of the above-described methods. The three-dimensional memory may include a substrate 100 and a stacked structure 200, wherein the stacked structure 200 is formed on the substrate 100 and includes a plurality of stepped steps 500. A modified dielectric capping layer 511 covers the plurality of stepped steps 500, wherein the modified dielectric capping layer 511 is formed by annealing to remove hydrogen present therein in any form or combination of bonding, free single atoms, or free molecules.

[0120] In one embodiment of this application, the modified dielectric capping layer 511 may be a modified silicon oxide layer.

[0121] In addition, such as Figure 6 As shown, the three-dimensional memory also includes a dielectric filling layer 521 formed on the modified dielectric capping layer 511. The modified dielectric capping layer 511 and the dielectric filling layer 521 have flush top surfaces (which can be understood as surfaces away from the substrate). Alternatively, the dielectric filling layer 521 may be a tetraethyl orthosilicate material layer.

[0122] According to at least one embodiment of the present application, a modified dielectric capping layer can be formed by performing low-temperature annealing on the hydrogen-containing dielectric capping layer, thereby effectively reducing lattice dislocations and wafer warpage, which is beneficial for subsequent planarization processing in the central region of the stacked structure and can improve the overall performance of the three-dimensional memory.

[0123] Furthermore, after forming the hydrogen-containing dielectric coating layer, it can be directly subjected to low-temperature annealing to enhance the aforementioned beneficial effects.

[0124] Furthermore, the three-dimensional memory provided according to at least one embodiment of this application can effectively reduce the fabrication cost of the three-dimensional memory, while expanding the process window of the modified dielectric capping layer by making the modified dielectric capping layer have greater stress and a thicker film thickness, thereby reducing lattice dislocations.

[0125] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0126] Although exemplary methods and structures for fabricating three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the materials of the layers described are merely exemplary.

[0127] Although this application uses a hydrogen-containing dielectric capping layer filled in the insulating dielectric layer of the step region as an example to illustrate how low-temperature annealing can reduce the amount of hydrogen present within it in any form or combination of bonded, free single atoms, or free molecules, thereby effectively reducing lattice dislocations and wafer warpage, and improving the overall performance of the 3D memory, those skilled in the art will understand that, without departing from the teachings of this application, the hydrogen-containing dielectric capping layer can also be disposed in other locations within the 3D memory, and similarly, low-temperature annealing can be used to reduce the amount of hydrogen present within it in any form or combination of bonded, free single atoms, or free molecules to obtain the various results and advantages described in this specification.

[0128] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, The method includes: A multilayer structure comprising multiple stepped steps is formed on the substrate; A hydrogen-containing dielectric capping layer is formed on at least the plurality of stepped surfaces, wherein the hydrogen-containing dielectric capping layer contains hydrogen in any one or a combination of bonded, free single-atom, and free molecule forms, and the hydrogen-containing dielectric capping layer is subjected to low-temperature annealing to form a modified dielectric capping layer; and A dielectric filling layer is formed on the modified dielectric capping layer. The modified dielectric capping layer and the dielectric filling layer are planarized, and the dielectric filling layer is subjected to high-temperature annealing. The thickness of the modified medium covering layer is less than the thickness of the medium filling layer.

2. The method according to claim 1, characterized in that, After forming the hydrogen-containing dielectric capping layer, the annealing process includes: After the hydrogen-containing dielectric coating layer is formed, the hydrogen-containing dielectric coating layer is directly annealed.

3. The method according to claim 1, characterized in that, The annealing conditions are as follows: annealing temperature is 500℃ to 600℃, and annealing time is 1 hour to 10 hours.

4. The method according to claim 3, characterized in that, Annealing also includes: Annealing is performed in a low-pressure environment, wherein the pressure of the low-pressure environment is less than or equal to 5 Torr.

5. The method according to claim 1, characterized in that, Forming a hydrogen-containing dielectric capping layer on at least the plurality of stepped surfaces includes: The hydrogen-containing dielectric coating layer is formed on at least the plurality of stepped surfaces using a high-density plasma chemical vapor deposition process.

6. The method according to claim 1, characterized in that, The hydrogen-containing dielectric coating layer includes a silicon hydroxide layer.

7. The method according to claim 1, characterized in that, The dielectric filling layer includes a tetraethyl orthosilicate material layer.

8. The method according to claim 1, characterized in that, The flattening process includes: Etching and chemical mechanical polishing processes, or any combination thereof.

9. The method according to claim 1, characterized in that, The conditions for annealing the medium filling layer are: annealing temperature of 700°C to 800°C and annealing time of 5 minutes to 30 minutes.

10. The method according to claim 1, characterized in that, The method further includes: After annealing the hydrogen-containing dielectric capping layer, a substrate conditioning layer is formed on the surface of the substrate facing away from the stacked structure; and After planarizing the modified dielectric capping layer and the dielectric filling layer, the substrate conditioning layer is removed.

11. The method according to any one of claims 1 to 10, characterized in that, The stacked structure includes alternating insulating layers and gate sacrificial layers, or the stacked structure includes alternating insulating layers and gate layers.

12. A three-dimensional memory, characterized in that, include: Substrate; A stacked structure is formed on the substrate and includes multiple stepped steps; The modified medium capping layer is formed by low-temperature annealing of a hydrogen-containing medium capping layer containing hydrogen in any one or a combination of bonded, free single atoms, and free molecules, wherein the modified medium capping layer covers at least the plurality of step steps. as well as A dielectric filling layer is formed on the modified dielectric covering layer and is formed by high-temperature annealing. The thickness of the modified medium covering layer is less than the thickness of the medium filling layer.

13. The memory according to claim 12, characterized in that, The modified dielectric capping layer includes a modified silicon oxide layer.

14. The memory according to claim 12, characterized in that, The dielectric filling layer includes a tetraethyl orthosilicate material layer.

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