Stacked electrical connection structure for superconducting integrated circuit and preparation method thereof

Abstract

The present invention provides a stacked electrical connection structure for superconducting integrated circuits and a preparation method thereof. A photolithography window is formed by patterning a photoresist layer, and a superconducting connection layer is formed based on the photolithography window. Then, an upper superconducting metal layer is formed on the superconducting connection layer, so that the upper and lower superconducting metal layers are electrically connected through the superconducting connection layer. Since the photoresist layer forms a photolithography window by exposure and development, and the shape of the photolithography window is very regular, the shape of the formed superconducting connection layer is very regular. At the same time, the upper superconducting metal layer is formed on the regular superconducting connection layer, so that the interconnection of the preset number of superconducting metal layers is achieved. The obtained electrical connection structure has the characteristics of a block inductor, and the inductance value is small and easy to control; in addition, the electrical connection path pattern is regular and intact, which greatly improves the conduction carrying current of the hole, and the current path has no bends and the current distribution is uniform; finally, the photolithography window process density is large, which can effectively reduce the volume of the electrical connection structure.

Description

Technical Field

[0001] The present invention relates to the technical field of superconducting quantum devices, and in particular to a stacked electrical connection structure applied to superconducting integrated circuits and a preparation method thereof. Background Art

[0002] Superconducting circuits are electronic devices made of superconducting materials, mainly including superconducting quantum interference devices (SQUIDs), single flux quantum devices (SFQs) and other circuit devices that use superconducting Josephson junctions. Superconducting quantum interference devices (SQUIDs) are superconducting quantum devices based on the Josephson effect and the principle of magnetic flux quantization. Its basic structure is to insert two Josephson junctions in a superconducting ring. SQUID is the most sensitive magnetic flux detection sensor known so far. The magnetic flux noise of a typical SQUID device is μΦ0 / Hz. 1 / 2 Magnitude (1Φ0=2.07×10 -15 Wb), whose magnetic field noise is in fT / Hz 1 / 2 Magnitude (1fT = 1×10 -15 T), due to its extremely high sensitivity, it can be widely used in various fields such as medical cardio-encephalometric, material detection, earth magnetic field, military, earthquake and archaeology. The flux microscope prepared by it can be used for basic research. Single Flux Quantum (SFQ) is a superconducting circuit technology that uses a single flux quantum in a Josephson junction to represent logical "1" and "0". The clock frequency of the superconducting digital circuit based on this can reach 770GHz, which can be used for ultra-wideband analog-to-digital / digital-to-analog converters in radar and communication systems, broadband network switches, digital autocorrelators for radio astronomy, and superconducting computers.

[0003] At present, the development of superconducting circuits is moving towards large-scale, highly integrated superconducting integrated circuits. For example, the SIMIT-Nb03 process developed by the Superconducting Excellence Center of the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, has only one wiring layer, and the scale of the circuit it can carry is limited to 10 5 Josephson knot magnitude (10 5JJ), so we thought of increasing the number of Nb metal layers to increase the wiring layer to achieve a process structure with higher circuit integration. However, the SIMIT-Nb03 process does not perform chemical mechanical polishing (CMP) on the insulating layer to flatten it. Therefore, after the insulating layer is opened, the thickness of the next layer of Nb metal is usually designed to be 50nm to 100nm thicker than the thickness of the insulating layer to ensure complete step coverage and connectivity of the through hole. In this case, if the number of Nb metal layers is increased, both the Nb film and the insulating layer film can only become thicker and thicker as the number of layers increases. The thicker the insulating layer film, the larger the opening needs to be to ensure the connectivity of the through hole; in addition, the undulating metal layer not only increases the risk of defects in the through hole, but also causes the current to flow through the metal layer to generate bending of the current path, causing unnecessary uneven current distribution, thereby forming a large parasitic inductance. The undulating insulating layer will also cause uneven inductance and capacitance between metal layers. Therefore, based on the SIMIT-Nb03 process, improvements were made to create the SIMIT-Nb04 process. The SIMIT-Nb04 process has four more wiring layers. Assuming that the top wiring layer is used to connect the Josephson junction, the number of openings is five.

[0004] In the double-layer Josephson junction process currently developed by SIMIT, the Josephson junction is in a stacked form in the process structure. This process structure increases the circuit density by at least two times. The connection between the lower Josephson junction and the upper Josephson junction is the connection between the bottom electrode of the lower junction and the top electrode of the upper junction. The number of insulating layers to be crossed by the connection is four, and four holes need to be opened. The first three insulating layers are all planarized.

[0005] It can be seen that the VLSI (Very Large Scale Integration) of superconducting integrated circuits inevitably requires the addition of more metal layers, and the addition of more metal layers inevitably requires the problem of continuous drilling. In superconducting integrated circuits, there are two main ways to continuously drill holes: Figure 1 The staggered continuous openings shown and Figure 2 The stacked continuous openings shown. The connectivity of the staggered openings is good, and the size of the openings is independent of the size of the through-holes in the adjacent layers, and is only related to the thickness of the insulating layer. However, the through-holes are irregular, and the through-hole inductance is large and difficult to suppress. In particular, in the SFQ circuit, the inductance parameter is a key parameter, especially the inductance connecting the Josephson junctions, which needs to be controlled within ±5%. The continuous opening method of staggered openings is difficult to control the through-hole inductance to a small inductance. The process density of the stacked openings is relatively large, so the size of the electrical connection structure is smaller than that of the staggered opening method, but the electrical connectivity is not good, and the holes can only be opened larger and larger, and the inductance is also difficult to control. In addition, both of these opening methods inevitably have the problem of the etched through-hole having a slope. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a stacked electrical connection structure for superconducting integrated circuits and a preparation method thereof, so as to solve the problems in the prior art that, in the continuous hole opening process of the stacked electrical connection structure of the superconducting integrated circuit, staggered holes are used, the through holes are irregular, and the through hole inductance is large and difficult to suppress; when stacked holes are used, the electrical connectivity is poor, and the holes can only be opened larger and larger, and the inductance is also difficult to control; in addition, both of these two hole opening methods inevitably have the problem that the etched through holes have a slope.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a stacked electrical connection structure for superconducting integrated circuits, the method comprising:

[0008] Providing a substrate, on which a first superconducting metal layer is formed, and forming a first insulating layer on the substrate;

[0009] Etching the first insulating layer until a surface of the first superconducting metal layer is exposed;

[0010] A photoresist layer is coated on the structure, and patterned to form a photolithography window, wherein the photolithography window exposes a portion of the surface of the first superconducting metal layer that needs to be connected later;

[0011] forming a superconducting material layer on the structure;

[0012] removing the photoresist layer and the superconducting material layer on the photoresist layer, and forming the remaining superconducting material layer into a superconducting connection layer;

[0013] forming a second insulating layer on the structure;

[0014] Etching the second insulating layer until the surface of the superconducting connection layer is exposed;

[0015] A second superconducting metal layer is formed on the above structure.

[0016] Optionally, the above steps are repeated N times in sequence, where N≥1, until a preset number of superconducting metal layers is reached.

[0017] Furthermore, N=3.

[0018] Optionally, the first superconducting metal layer includes at least one of a niobium nitride layer and a niobium layer; the superconducting connecting layer includes at least one of a niobium nitride layer and a niobium layer; and the second superconducting metal layer includes at least one of a niobium nitride layer and a niobium layer.

[0019] Optionally, a material of the first insulating layer includes SiO 2 or SiNx; a material of the second insulating layer includes SiO 2 or SiNx.

[0020] Optionally, the first insulating layer is polished by a CMP process until a surface of the first superconducting metal layer is exposed; and the second insulating layer is polished by a CMP process until a surface of the superconducting connecting layer is exposed.

[0021] Optionally, the superconducting material layer is formed by a magnetron sputtering process; and the second superconducting metal layer is formed by a magnetron sputtering process.

[0022] Optionally, the method of forming the second superconducting metal layer includes:

[0023] forming a layer of superconducting metal material on the surface of the obtained structure;

[0024] The superconducting metal material layer is photoetched to obtain the second superconducting metal layer.

[0025] Optionally, a size of the second superconducting metal layer is not greater than a size of the first superconducting metal layer.

[0026] The present invention also provides a stacked electrical connection structure applied to a superconducting integrated circuit. The electrical connection structure is prepared by any of the above-mentioned methods for preparing a stacked electrical connection structure applied to a superconducting integrated circuit.

[0027] As described above, the stacked electrical connection structure and preparation method thereof for superconducting integrated circuits of the present invention form a photolithography window by patterning the photoresist layer, form a superconducting connection layer based on the photolithography window, and then form an upper superconducting metal layer on the superconducting connection layer to achieve electrical connection between the upper and lower superconducting metal layers through the superconducting connection layer. Since the photoresist layer forms a photolithography window by exposure and development, the shape of the photolithography window is very regular, so the shape of the formed superconducting connection layer is very regular, and at the same time, the upper superconducting metal layer is formed on the regular superconducting connection layer, so as to achieve the interconnection of the preset number of superconducting metal layers, and the obtained electrical connection structure has the characteristics of a block inductor, with a small inductance value and easy to control; in addition, the formed electrical connection path pattern is regular and intact, which greatly improves the conduction carrying current of the hole, and the current path has no bends and the current distribution is uniform; finally, the process density of the photolithography window is large, which can effectively reduce the volume of the electrical connection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It shows a schematic diagram of the cross-sectional structure of each step in the main process flow of staggered continuous opening in the prior art.

[0029] Figure 2It shows a schematic diagram of the cross-sectional structure presented at each step in the main process flow of stacked continuous opening in the prior art.

[0030] Figure 3 It is a flow chart of a method for preparing a stacked electrical connection structure applied to a superconducting integrated circuit according to the present invention.

[0031] Figures 4 to 16 It is a schematic diagram of the cross-sectional structure presented in each step of the preparation process of the stacked electrical connection structure applied to superconducting integrated circuits of the present invention.

[0032] Component number description

[0033] 300 Substrate

[0034] 301 First superconducting metal layer

[0035] 302 First insulation layer

[0036] 303 Photoresist layer

[0037] 304 Lithography Window

[0038] 305 Superconducting Material Layer

[0039] 306 Superconducting connection layer

[0040] 307 Second insulation layer

[0041] 308 Superconducting metal material layer

[0042] 309 Second superconducting metal layer

[0043] 310 Insulation dielectric layer

[0044] 311 The third superconducting metal layer

[0045] 312 Fourth superconducting metal layer

[0046] 313 Fifth superconducting metal layer

[0047] Steps S1 to S8 DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] See also Figures 1 to 16It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed according to actual needs, and the component layout type may also be more complicated.

[0050] As described in the background art, there are two main ways of continuously opening holes in the electrical connection structure of a superconducting integrated circuit, one is staggered continuous opening holes, and the other is stacked continuous opening holes.

[0051] like Figure 1 The figure shows the schematic diagram of the cross-sectional structure of each step of preparing the electrical connection structure of 5 superconducting metal layers by using the staggered continuous hole opening process. The process mainly includes: 1. Figure 1 As shown in 1a, the I1 insulating layer covering the M1 superconducting metal layer is etched by I1 through-hole etching to expose the M1 superconducting metal layer through the I1 through-hole; 2. Figure 1 As shown in 1b, a layer of M2 superconducting metal layer is sputtered, and the thickness is greater than the I1 insulating layer to ensure step coverage and through-hole connection; 3. Figure 1 As shown in 1c, a thick insulating layer is deposited; 4. Figure 1 As shown in 1d, CMP is performed on the basis of this thick insulating layer to form an I2 insulating layer; 5. Figure 1 As shown in 1e, an I2 hole is opened at a position not directly above the I1 through hole. The size of the I2 through hole depends on the thickness of the silicon dioxide at the opening position and has no direct relationship with the size of the I1 through hole. A layer of M3 superconducting metal layer is subsequently sputtered; 6. Figure 1 As shown in 1f, repeat the above steps 3, 4, and 5 to obtain an I3 insulating layer and an M4 superconducting metal layer; 7. Figure 1 As shown in 1g, a high-quality insulating layer I4 is deposited, and this layer is not subjected to CMP; 8. Figure 1 As shown in 1h, an I4 hole is opened at a position not directly above the I4 through hole, and then a layer of M5 superconducting metal layer is sputtered. From the above preparation process, it can be seen that the electrical connectivity of the staggered continuous holes is better. The size of the holes is independent of the size of the through holes in the adjacent layers, and is only related to the thickness of the insulating layer. However, the etched through holes have a slope, which leads to irregular through holes and large through hole inductance that is difficult to suppress. In the SFQ circuit, the inductance parameter is a key parameter, especially the inductance connecting the Josephson junctions, which needs to be controlled within ±5%. The staggered continuous hole method is difficult to control the through hole inductance to a small inductance; in addition, the formed electrical connection structure will cause the current to flow through the superconducting metal layer to generate a bend in the current path, causing uneven distribution of the current; finally, the staggered holes will cause the formed electrical connection structure to be larger in volume, reducing the integration of superconducting integrated circuits.

[0052] like Figure 2 The figure shows the schematic diagram of the cross-sectional structure of each step of preparing the electrical connection structure of 5 layers of superconducting metal layers by using the stacked continuous hole opening process. The process mainly includes: 1. Figure 2 As shown in 2a, the I1 insulating layer covering the M1 superconducting metal layer is etched by I1 through-hole etching to expose the M1 superconducting metal layer through the I1 through-hole; 2. Figure 2 As shown in 2b, a layer of M2 superconducting metal layer is sputtered, and the thickness is greater than the I1 insulating layer to ensure step coverage and through-hole connection; 3. Figure 2 As shown in 2c, a thick insulating layer is deposited; 4. Figure 2 As shown in 2d in FIG. 5 , CMP is performed on the basis of this thick insulating layer to form an I2 insulating layer; 5. Figure 2 As shown in 2e, an I2 hole is opened just above the I1 through hole. The size of the I2 through hole must be larger than that of the I1 through hole. A layer of M3 superconducting metal layer is subsequently sputtered; 6. Figure 2 As shown in 2f in FIG. 7 , repeat the above steps 3, 4, and 5 to obtain an I3 insulating layer and an M4 superconducting metal layer. In order to maintain electrical connectivity, the through holes of each layer must be larger than the through holes of the lower layer; 7. Figure 2 As shown in 2g, a high-quality insulating layer I4 is deposited, and this layer is not subjected to CMP; 8. Figure 2 As shown in 2h, an I4 hole is opened just above the I4 through hole and then a layer of M5 superconducting metal layer is sputtered. From the above preparation process, it can be seen that the process density of stacked continuous hole opening is relatively large, which can reduce the volume of the electrical connection structure, but the etched through hole also has a slope and the hole can only be opened larger and larger, resulting in irregular through holes and poor control of through hole inductance. In addition, the formed electrical connection structure will also cause the current to flow through the superconducting metal layer to generate a bend in the current path, causing uneven distribution of current; finally, the electrical connection structure formed in this way has poor electrical connectivity.

[0053] Based on the above problems in the prior art, the present invention provides a method for preparing a stacked electrical connection structure for superconducting integrated circuits, the preparation method comprising the following steps:

[0054] S1. providing a substrate, on which a first superconducting metal layer is formed, and forming a first insulating layer on the substrate;

[0055] S2, etching the first insulating layer until the surface of the first superconducting metal layer is exposed;

[0056] S3, coating a photoresist layer on the above structure, and patterning it to form a photolithography window, wherein the photolithography window exposes a portion of the surface of the first superconducting metal layer that needs to be connected later;

[0057] S4, forming a superconducting material layer on the above structure;

[0058] S5, removing the photoresist layer and the superconducting material layer on the photoresist layer, and forming the remaining superconducting material layer into a superconducting connection layer;

[0059] S6, forming a second insulating layer on the above structure;

[0060] S7, etching the second insulating layer until the surface of the superconducting connection layer is exposed;

[0061] S8. Form a second superconducting metal layer on the above structure.

[0062] The preparation method of the electrical connection structure of the present invention forms a photolithography window by patterning a photoresist layer, forms a superconducting connection layer based on the photolithography window, and then forms an upper superconducting metal layer on the superconducting connection layer to achieve electrical connection between the upper and lower superconducting metal layers through the superconducting connection layer. Since the photoresist layer forms a photolithography window by exposure and development, the shape of the photolithography window is very regular, so the shape of the formed superconducting connection layer is very regular, and at the same time, the upper superconducting metal layer is formed on the regular superconducting connection layer, so that the interconnection of the preset number of superconducting metal layers is achieved, and the obtained electrical connection structure has the characteristics of a block inductor, and the inductance value is small and easy to control; in addition, the formed electrical connection path pattern is regular and intact, which greatly improves the conduction carrying current of the hole, and the current path has no bends and the current distribution is uniform; finally, the process density of the photolithography window is large, which can effectively reduce the volume of the electrical connection structure.

[0063] The method for preparing the stacked electrical connection structure for superconducting integrated circuits of the present invention will be described in detail below with reference to the accompanying drawings.

[0064] like Figures 3 to 5 As shown, firstly, step S1 is performed to provide a substrate 300, on which a first superconducting metal layer 301 (such as Figure 4 As shown), a first insulating layer 302 is formed on the substrate 300 (as shown Figure 5 shown).

[0065] The substrate 300 may include at least one of a silicon substrate, a silicon carbide substrate, a silicon oxide substrate, a magnesium oxide substrate and a sapphire substrate, but is not limited thereto. Any substrate suitable for preparing a superconducting integrated circuit may be used.

[0066] As an example, an insulating dielectric layer 310 may be formed on the substrate 300 to electrically isolate the first superconducting metal layer 301 from the substrate 300. The insulating dielectric layer 310 may be made of any suitable insulating material, such as SiO2 or SiNx.

[0067] The first superconducting metal layer 301 includes at least one of a niobium nitride layer and a niobium layer, that is, it can be one of them or a stacked structure of both, but it is not limited thereto and can also be a superconducting metal layer of other materials. In this embodiment, the first superconducting metal layer 301 is selected as a niobium layer.

[0068] As an example, the method for forming the first superconducting metal layer 301 includes: depositing a superconducting layer on the substrate 300; and then performing photolithography and etching on the superconducting layer to obtain the first superconducting metal layer 301 of a preset shape.

[0069] It should be noted that the thickness of the first insulating layer 302 is generally thick, so as to obtain a relatively flat surface after subsequent polishing of the first insulating layer 302. The material of the first insulating material layer 302 includes SiO2 or SiNx, but is not limited thereto, and other materials with better insulating properties may also be used.

[0070] like Figure 3 and Figure 6 As shown, step S2 is then performed to etch the first insulating layer 302 until the surface of the first superconducting metal layer 301 is exposed.

[0071] As an example, the first insulating layer 302 is polished by a CMP polishing process until the surface of the first superconducting metal layer 301 is exposed.

[0072] like Figure 3 and Figure 7 As shown, step S3 is then performed to coat a photoresist layer 303 on the above structure and pattern it to form a photolithography window 304, wherein the photolithography window 304 exposes the surface of the first superconducting metal layer 301 that needs to be connected later. The shape of the photolithography window obtained by exposure and development is very regular, which lays the foundation for the subsequent formation of a regular superconducting connection layer.

[0073] like Figure 3 and Figure 8 As shown, the next step is to perform step S4 to form a superconducting material layer 305 on the structure. The superconducting material layer 305 fills the photolithography window 304 completely.

[0074] As an example, the superconducting material layer 305 includes at least one of a niobium nitride layer and a niobium layer, that is, it can be one of them or a laminated structure composed of the two, but it is not limited thereto and can also be a superconducting metal layer of other materials. In this embodiment, the superconducting material layer 305 is selected as a niobium layer.

[0075] As an example, the superconducting material layer 305 may be formed by a PVD process. In this embodiment, the superconducting material layer 305 is formed by a magnetron sputtering process.

[0076] like Figure 3 and Fig. 9 As shown, step S5 is then performed to remove the photoresist layer 303 and the superconducting material layer 305 on the photoresist layer 303, and the remaining superconducting material layer 305 is formed into a superconducting connection layer 306. The superconducting connection layer 306 is formed based on the etching window 304, so the formed superconducting connection layer 306 has a regular shape and is easy to control.

[0077] like Figure 3 and Fig.10 As shown, step S6 is then performed to form a second insulating layer 307 on the above structure.

[0078] It should be noted that the thickness of the second insulating layer 307 is generally thick, so as to obtain a relatively flat surface after subsequent polishing of the second insulating layer 307. The material of the second insulating material layer 307 includes SiO2 or SiNx, but is not limited thereto, and other materials with better insulating properties may also be used.

[0079] like Figure 3 and Fig.11 As shown, step S7 is then performed to etch the second insulating layer 307 until the surface of the superconducting connection layer 306 is exposed.

[0080] As an example, the second insulating layer 307 is polished by a CMP polishing process until the surface of the superconducting connection layer 306 is exposed.

[0081] like Figure 3 and Fig.13 As shown, step S8 is finally performed to form a second superconducting metal layer 309 on the above structure.

[0082] As an example, the second superconducting metal layer 309 may be formed by a PVD process. In this embodiment, the second superconducting metal layer 309 is formed by a magnetron sputtering process.

[0083] As an example, the second superconducting metal layer 309 includes at least one of a niobium nitride layer and a niobium layer, that is, it can be one of them or a stacked structure composed of both, but it is not limited thereto and can also be a superconducting metal layer of other materials. In this embodiment, the second superconducting metal layer 309 is selected as a niobium layer.

[0084] like Fig.12 and Fig.13 As shown, as an example, the method of forming the second superconducting metal layer 309 includes: Fig.12 As shown, a superconducting metal material layer 308 is formed on the surface of the obtained structure; Fig.13As shown, the superconducting metal material layer 308 is photoetched to obtain the second superconducting metal layer 309 .

[0085] As an example, the size of the second superconducting metal layer 309 is not greater than the size of the first superconducting metal layer 301. The size here mainly refers to the surface area of ​​the superconducting metal layer.

[0086] The second superconducting metal layer 309 is formed on the superconducting connection layer 306, and the first superconducting metal layer 301 is electrically connected to the second superconducting metal layer 309 through the superconducting connection layer 306. Since the shape of the superconducting connection layer 306 is regular, and the shapes of the upper and lower superconducting metal layers are controllable, the shape of the entire connection path is regular, and has the characteristics of a block inductor; and since the connection path pattern is regular and intact, the conduction carrying current of the hole can be greatly improved, and the current path has no bends, the current distribution is uniform, and the electrical connectivity performance is good.

[0087] The implementation of the above steps completes the electrical connection of two adjacent superconducting metal layers through the superconducting connection layer. Based on this, the above steps can be repeated in sequence to achieve the electrical connection of a preset number of N superconducting metal layers through the superconducting connection layer, where N ≥ 3. Fig.14 As shown, an electrical connection structure is realized in which the first superconducting metal layer 301, the second superconducting metal layer 309 and the third superconducting metal layer 311 are interconnected in sequence through the superconducting connection layer; Fig.15 As shown, an electrical connection structure is realized in which the first superconducting metal layer 301, the second superconducting metal layer 309, the third superconducting metal layer 311 and the fourth superconducting metal layer 312 are interconnected in sequence through the superconducting connection layer; Fig.16 As shown, an electrical connection structure is realized in which five superconducting metal layers, namely, the first superconducting metal layer 301, the second superconducting metal layer 309, the third superconducting metal layer 311, the fourth superconducting metal layer 312 and the fifth superconducting connection layer 313, are sequentially interconnected through the superconducting connection layer. The more layers are interconnected in this way, the greater the process density of the lithography window is, which can effectively reduce the volume of the electrical connection structure and facilitate the integration of superconducting integrated circuits.

[0088] As an example, the materials and structures of all superconducting metal layers in the stacked electrical connection structure are the same, namely, the first superconducting metal layer to the Nth superconducting metal layer and the superconducting connection layer, so as to facilitate theoretical calculation and simulation effect simulation.

[0089] As an example, the materials and structures of all the insulating layers in the stacked electrical connection structure are kept consistent, that is, the first insulating layer to the N-1th insulating layer, so as to achieve homogeneous growth of insulating material layers. The homogeneous growth has no obvious interface and has no impact on subsequent processes.

[0090] This embodiment also provides a stacked electrical connection structure applied to a superconducting integrated circuit, which is prepared by using the method for preparing the stacked electrical connection structure applied to a superconducting integrated circuit as described above.

[0091] In summary, the present invention provides a stacked electrical connection structure and a preparation method thereof for superconducting integrated circuits, wherein a photolithography window is formed by patterning a photoresist layer, and a superconducting connection layer is formed based on the photolithography window, and then an upper superconducting metal layer is formed on the superconducting connection layer, so that the upper and lower superconducting metal layers are electrically connected through the superconducting connection layer. Since the photoresist layer forms a photolithography window by exposure and development, and the shape of the photolithography window is very regular, the shape of the formed superconducting connection layer is very regular, and at the same time, the upper superconducting metal layer is formed on the regular superconducting connection layer, so that the interconnection of the preset number of superconducting metal layers is achieved, and the obtained electrical connection structure has the characteristics of a block inductor, and the inductance value is small and easy to control; in addition, the formed electrical connection path pattern is regular and intact, which greatly improves the conduction carrying current of the hole, and the current path has no bends and the current distribution is uniform; finally, the process density of the photolithography window is large, which can effectively reduce the volume of the electrical connection structure. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0092] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a stacked electrical connection structure for superconducting integrated circuits, characterized in that: The preparation method comprises: S1, providing a substrate, on which a first superconducting metal layer is formed, and a first insulating layer is formed on the substrate; S2, etching the first insulating layer until the surface of the first superconducting metal layer is exposed; S3, coating a photoresist layer on the above structure and patterning it to form a photolithography window, wherein the photolithography window exposes a portion of the surface of the first superconducting metal layer that needs to be connected later; S4, forming a superconducting material layer on the above structure; S5, removing the photoresist layer and the superconducting material layer on the photoresist layer, and forming the remaining superconducting material layer into a superconducting connection layer; S6, forming a second insulating layer on the above structure; S7, etching the second insulating layer until the surface of the superconducting connection layer is exposed; S8, forming a second superconducting metal layer on the above structure.

2. The method for preparing a stacked electrical connection structure for superconducting integrated circuits according to claim 1, characterized in that: Steps S1 to S8 are cycled N times in sequence, where N≥1, until a preset number of superconducting metal layers is reached.

3. The method for preparing a stacked electrical connection structure for superconducting integrated circuits according to claim 2, characterized in that: N＝3。 4. The method for preparing a stacked electrical connection structure for superconducting integrated circuits according to claim 1, characterized in that: The first superconducting metal layer includes at least one of a niobium nitride layer and a niobium layer; the superconducting connection layer includes at least one of a niobium nitride layer and a niobium layer; and the second superconducting metal layer includes at least one of a niobium nitride layer and a niobium layer.

5. The method for preparing a stacked electrical connection structure for superconducting integrated circuits according to claim 1, characterized in that: The material of the first insulating layer includes SiO2 or SiNx; the material of the second insulating layer includes SiO2 or SiNx.

6. The method for preparing a stacked electrical connection structure for superconducting integrated circuits according to claim 1, characterized in that: The first insulating layer is polished by a CMP process until the surface of the first superconducting metal layer is exposed; and the second insulating layer is polished by a CMP process until the surface of the superconducting connecting layer is exposed.

7. The method for preparing a stacked electrical connection structure for superconducting integrated circuits according to claim 1, characterized in that: The superconducting material layer is formed by a magnetron sputtering process; and the second superconducting metal layer is formed by a magnetron sputtering process.

8. The method for preparing a stacked electrical connection structure for superconducting integrated circuits according to claim 1, characterized in that: The method of forming the second superconducting metal layer comprises: forming a layer of superconducting metal material on the surface of the obtained structure; The superconducting metal material layer is photoetched to obtain the second superconducting metal layer.

9. The method for preparing a stacked electrical connection structure for superconducting integrated circuits according to claim 1, characterized in that: The size of the second superconducting metal layer is not greater than that of the first superconducting metal layer.

10. A stacked electrical connection structure applied to a superconducting integrated circuit, characterized in that: The electrical connection structure is prepared by the method for preparing a stacked electrical connection structure applied to a superconducting integrated circuit as claimed in any one of claims 1 to 9.

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