Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. A semiconductor device includes a first insulating layer, wiring contacts spaced apart from each other by the first insulating layer, and a bonding wire connected to the wiring contacts. Each of the wiring contacts includes a base portion in the first insulating layer and a protruding portion protruding from an inner portion of the first insulating layer to an outer portion. The protruding portion of the wiring contact is in contact with the bonding wire.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a semiconductor device and a manufacturing method of a semiconductor device, and more particularly, to a three-dimensional semiconductor device and a manufacturing method of a three-dimensional semiconductor device. BACKGROUND

[0002] A semiconductor device includes memory cells capable of storing data. A three-dimensional semiconductor device includes memory cells arranged in three dimensions, so that an area occupied by the memory cells on a substrate can be reduced.

[0003] To improve the integration of a three-dimensional semiconductor device, the number of stacked levels of memory cells of the three-dimensional semiconductor device can be increased. However, as the number of stacked levels increases, the operational reliability of the three-dimensional semiconductor device can deteriorate. SUMMARY

[0004] In an embodiment of the present disclosure, a semiconductor device includes a first insulating layer, wiring contacts spaced apart from each other by the first insulating layer, and a bonding wire connected to the wiring contacts. Each of the wiring contacts includes a base in the first insulating layer and a protrusion protruding from an inner portion of the first insulating layer to an outer portion. The protrusions of the wiring contacts are in contact with the bonding wire.

[0005] In an embodiment of the present disclosure, a semiconductor device includes a first insulating layer including a recessed portion, wiring contacts exposed through the recessed portion of the first insulating layer, a bonding wire connected to the wiring contacts, and a second insulating layer filling the recessed portion. The bonding wire includes at least one interposition part interposed between the wiring contacts. A lower surface of the at least one interposition part is in contact with at least one of the first insulating layer and the second insulating layer.

[0006] In an embodiment of the present disclosure, a semiconductor device includes a semiconductor structure including a stacked structure and an insulating layer surrounding the stacked structure, a peripheral circuit structure including a peripheral transistor, a connection structure disposed between the semiconductor structure and the peripheral circuit structure, the connection structure including a wiring connection conductor, a wiring contact penetrating the insulating layer, the wiring contact being electrically connected to the wiring connection conductor, and a bonding wire connected to the wiring contact.

[0007] In an embodiment of the present disclosure, a method of manufacturing a semiconductor device includes forming a stacked structure including alternately stacked conductive patterns and insulating patterns, forming an insulating layer surrounding the stacked structure, forming wiring contacts penetrating the insulating layer, etching the insulating layer to expose the wiring contacts, and forming a bonding wire connected to the wiring contacts. BRIEF DESCRIPTION OF DRAWINGS

[0008] In the following, example embodiments are described with reference to the accompanying drawings; however, they can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein.

[0009] In the drawings, the size of some of the components can be exaggerated, for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between these two elements or one or more additional elements can also be present. Like reference numerals refer to like elements throughout.

[0010] FIG. 1A is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0011] FIG. 1B is FIG. 1A is an enlarged view of the region A shown.

[0012] FIG. 1C is a plan view illustrating a wiring contact and a bonding wire according to an embodiment of the present disclosure.

[0013] FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 and FIG. 9 are diagrams illustrating a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.

[0014] FIG. 10 is a cross-sectional view illustrating a wiring contact and a bonding wire according to an embodiment of the present disclosure.

[0015] FIG. 11 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0016] FIG. 12 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The specific configurations or functional descriptions disclosed herein are merely illustrative of embodiments in accordance with the concept of the present disclosure. Embodiments in accordance with the concept of the present disclosure can be implemented in various forms, and should not be interpreted as being limited to the specific embodiments set forth herein.

[0018] Hereinafter, the terms "first" and "second" are used to distinguish one component from another component, not to describe the number or order of the components. These terms can be used to describe various components, but the components are not limited by these terms.

[0019] Some embodiments relate to a semiconductor device in which integration density is enhanced and operation reliability is improved.

[0020] FIG. 1A is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 1B is FIG. 1A is an enlarged view of the region A shown. FIG. 1C is a plan view illustrating a wiring contact and a bonding wire according to an embodiment of the present disclosure.

[0021] Referring to FIG. 1A , the semiconductor device can include a cell region CER, a first connection region COR1, and a second connection region COR2. The cell region CER, the first connection region COR1, and the second connection region COR2 can be separated from each other in a plane extending in a first direction D1 and a second direction D2. The active region and the isolation region can be separated from each other in the plane extending in the first direction D1 and the second direction D2. The cell region CER can be surrounded by the first connection region COR1. Because the directions D1 and D2 are not parallel, the first direction D1 and the second direction D2 can cross each other. In an embodiment, the first direction D1 and the second direction D2 can be orthogonal to each other.

[0022] The semiconductor device can include a peripheral circuit structure PER. The peripheral circuit structure PER can include a first substrate 100, a first peripheral transistor TR1, a second peripheral transistor TR2, an isolation layer IS, a first insulating layer 110, a first contact CT1, a first line ML1, a first bonding pad BP1, a second contact CT2, a second line ML2, a second bonding pad BP2, a third line ML3, and a third bonding pad BP3.

[0023] The first substrate 100 can have a plate-like shape extending in the first direction D1 and the second direction D2. In an embodiment, the first substrate 100 can be a semiconductor substrate.

[0024] The first insulating layer 110 can cover the first substrate 100. The first insulating layer 110 can include an insulating material. In an embodiment, the first insulating layer 110 can include an oxide or a nitride.

[0025] The first peripheral transistor TR1 and the second peripheral transistor TR2 can be located between the first insulating layer 110 and the first substrate 100. The first peripheral transistor TR1 can be located in the cell region CER. The second peripheral transistor TR2 can be located in the first connection region COR1. The first peripheral transistor TR1 and the second peripheral transistor TR2 can constitute a peripheral circuit of the semiconductor device, or can be transistors connected to a peripheral circuit of the semiconductor device. In an embodiment, the first peripheral transistor TR1 can constitute a page buffer of the semiconductor device, or can be a transistor connected to a page buffer of the semiconductor device. In an embodiment, the second peripheral transistor TR2 can constitute an X-decoder of the semiconductor device, or can be a transistor connected to an X-decoder of the semiconductor device.

[0026] Each of the first peripheral transistor TR1 and the second peripheral transistor TR2 can include an impurity region IR, a gate insulating layer GI, and a gate electrode GM. The impurity region IR can be formed by doping an impurity into the first substrate 100. The gate electrode GM can be spaced apart from the first substrate 100 by the gate insulating layer GI. The gate insulating layer GI can include an insulating material. In an embodiment, the gate insulating layer GI can include an oxide. The gate electrode GM can include a conductive material. In an embodiment, the gate electrode GM can include tungsten.

[0027] The gate electrode GM and the gate insulating layer GI of the first peripheral transistor TR1 can extend in the second direction D2. The gate electrode (not shown) and the gate insulating layer (not shown) of the second peripheral transistor TR2 can extend in the first direction D1. The second peripheral transistor TR2 can share the gate electrode and the gate insulating layer.

[0028] An isolation layer IS can be located in the first substrate 100. The isolation layer IS can electrically isolate the impurity regions IR of the first peripheral transistor TR1 and the second peripheral transistor TR2 from each other. The isolation layer IS can include an insulating material. In an embodiment, the isolation layer IS can include an oxide.

[0029] A first contact CT1 and a first line ML1 can be connected to the first peripheral transistor TR1. The first contact CT1 and the first line ML1 can be connected to each other. The first contact CT1 and the first line ML1 can be located in the first insulating layer 110. The first contact CT1 and the first line ML1 can be located in the cell region CER. The first contact CT1 and the first line ML1 can include a conductive material. In an embodiment, the first contact CT1 and the first line ML1 can include tungsten.

[0030] The first bonding pad BP1 can be connected to the first line ML1. The first bonding pad BP1 can be located in the first insulating layer 110. The first bonding pad BP1 can be located in the cell region CER. The width of the first bonding pad BP1 can be smaller as it gets closer to the first substrate 100. In an embodiment, the width of the first bonding pad BP1 in the first direction D1 can be smaller as it gets closer to the first substrate 100. The first bonding pad BP1 can include a conductive material. In an embodiment, the first bonding pad BP1 can include copper.

[0031] The second contact CT2 and the second line ML2 can be connected to the second peripheral transistor TR2. The second contact CT2 and the second line ML2 can be connected to each other. The second contact CT2 and the second line ML2 can be located in the first insulating layer 110. The second contact CT2 and the second line ML2 can be located in the first connection region COR1. The second contact CT2 and the second line ML2 can include a conductive material. In an embodiment, the second contact CT2 and the second line ML2 can include tungsten.

[0032] The second bonding pad BP2 can be disposed at the same height as the first bonding pad BP1. The second bonding pad BP2 can be connected to the second line ML2. The second bonding pad BP2 can be located in the first insulating layer 110. The second bonding pad BP2 can be located in the first connection region COR1. The width of the second bonding pad BP2 can be smaller as it gets closer to the first substrate 100. In an embodiment, the width of the second bonding pad BP2 in the first direction D1 can be smaller as it gets closer to the first substrate 100. The second bonding pad BP2 can include a conductive material. In an embodiment, the second bonding pad BP2 can include copper.

[0033] The third line ML3 can be located in the first insulating layer 110. The third line ML3 can be disposed at the same height as some lines disposed at the highest height among the first line ML1 and the second line ML2. The third line ML3 can be located in the second connection region COR2. The third line ML3 can include a conductive material. In an embodiment, the third line ML3 can include tungsten.

[0034] The third bonding pad BP3 can be disposed at the same height as the first bonding pad BP1 and the second bonding pad BP2. A plurality of third bonding pads BP3 can be connected to the third line ML3. The third bonding pad BP3 can be located in the first insulating layer 110. The third bonding pad BP3 can be located in the second connection region COR2. The width of the third bonding pad BP3 can be smaller as it gets closer to the first substrate 100. In an embodiment, the width of the third bonding pad BP3 in the first direction D1 can be smaller as it gets closer to the first substrate 100. The third bonding pad BP3 can include a conductive material. In an embodiment, the third bonding pad BP3 can include copper.

[0035] The connection structure CNS can be located on the peripheral circuit structure PER. The connection structure CNS can comprise the second insulating layer 120, the fourth bonding pad BP4, the fifth bonding pad BP5, the sixth bonding pad BP6, the first connection conductor CO1, the second connection conductor CO2, the wiring connection conductor WCO, the third contact CT3, the fourth contact CT4, the fifth contact CT5, the bit line BL, the fourth line ML4, the fifth line ML5, the sixth contact CT6, and the seventh contact CT7.

[0036] The second insulating layer 120 can cover the first insulating layer 110. The second insulating layer 120 can comprise an insulating material. In embodiments, the second insulating layer 120 can comprise an oxide or a nitride.

[0037] The fourth bonding pad BP4 can be connected to the first bonding pad BP1. The fourth bonding pad BP4 can be in contact with the first bonding pad BP1. The fourth bonding pad BP4 can be located in the second insulating layer 120. The fourth bonding pad BP4 can be located in the cell region CER. The width of the fourth bonding pad BP4 can become larger the closer it is to the first bonding pad BP1. In embodiments, the width of the fourth bonding pad BP4 in the first direction D1 can become larger the closer it is to the first bonding pad BP1. The width of the first bonding pad BP1 can become larger the closer it is to the fourth bonding pad BP4. The fourth bonding pad BP4 can comprise an electrically conductive material. In embodiments, the fourth bonding pad BP4 can comprise copper.

[0038] The fifth bonding pad BP5 can be disposed at the same height as the fourth bonding pad BP4. The fifth bonding pad BP5 can be connected to the second bonding pad BP2. The fifth bonding pad BP5 can be in contact with the second bonding pad BP2. The fifth bonding pad BP5 can be located in the second insulating layer 120. The fifth bonding pad BP5 can be located in the first connection region COR1. The width of the fifth bonding pad BP5 can become larger the closer it is to the second bonding pad BP2. In embodiments, the width of the fifth bonding pad BP5 in the first direction D1 can become larger the closer it is to the second bonding pad BP2. The width of the second bonding pad BP2 can become larger the closer it is to the fifth bonding pad BP5. The fifth bonding pad BP5 can comprise an electrically conductive material. In embodiments, the fifth bonding pad BP5 can comprise copper.

[0039] The sixth bonding pad BP6 can be disposed at the same height as the fourth bonding pad BP4 and the fifth bonding pad BP5. The sixth bonding pad BP6 can be connected to the third bonding pad BP3. The sixth bonding pad BP6 can be in contact with the third bonding pad BP3. The sixth bonding pad BP6 can be located in the second insulating layer 120. The sixth bonding pad BP6 can be located in the second connection region COR2. The width of the sixth bonding pad BP6 can become larger as it gets closer to the third bonding pad BP3. In an embodiment, the width of the sixth bonding pad BP6 in the first direction D1 can become larger as it gets closer to the third bonding pad BP3. The width of the third bonding pad BP3 can become larger as it gets closer to the sixth bonding pad BP6. The sixth bonding pad BP6 can include a conductive material. In an embodiment, the sixth bonding pad BP6 can include copper.

[0040] The first connection conductor CO1 can be connected to the fourth bonding pad BP4. The first connection conductor CO1 can be located in the second insulating layer 120. The first connection conductor CO1 can be located in the cell region CER.

[0041] The second connection conductor CO2 can be connected to the fifth bonding pad BP5. The second connection conductor CO2 can be disposed at the same height as the first connection conductor CO1. The second connection conductor CO2 can be located in the second insulating layer 120. The second connection conductor CO2 can be located in the first connection region COR1.

[0042] The wiring connection conductor WCO can be connected to the sixth bonding pad BP6. The wiring connection conductor WCO can be disposed at the same height as the first connection conductor CO1 and the second connection conductor CO2. The wiring connection conductor WCO can be located in the second insulating layer 120. The wiring connection conductor WCO can be located in the second connection region COR2.

[0043] The third contact CT3 can be connected to the first connection conductor CO1. The third contact CT3 can be located in the second insulating layer 120. The third contact CT3 can be located in the cell region CER. The third contact CT3 can include a conductive material. In an embodiment, the third contact CT3 can include tungsten.

[0044] The fourth contact CT4 can be connected to the second connection conductor CO2. The fourth contact CT4 can be located in the second insulating layer 120. The fourth contact CT4 can be located in the first connection region COR1. The fourth contact CT4 can be disposed at the same height as the third contact CT3. The fourth contact CT4 can include a conductive material. In an embodiment, the fourth contact CT4 can include tungsten.

[0045] A plurality of fifth contacts CT5 can be connected to the wiring connection conductor WCO. The fifth contacts CT5 can be located in the second connection region COR2. The fifth contacts CT5 can be disposed at the same height as the third contacts CT3 and the fourth contacts CT4. The fifth contacts CT5 can comprise an electrically conductive material. In embodiments, the fifth contacts CT5 can comprise tungsten.

[0046] A bit line BL can be connected to the third contacts CT3. The bit line BL can be located in the second insulating layer 120. The bit line BL can be located in the cell region CER. The bit line BL can extend in the second direction D2. The bit line BL can comprise an electrically conductive material. The bit line BL can comprise tungsten.

[0047] A fourth line ML4 can be connected to the fourth contacts CT4. The fourth line ML4 can be located in the second insulating layer 120. The fourth line ML4 can be located in the first connection region COR1. The fourth line ML4 can be disposed at the same height as the bit line BL. The fourth line ML4 can comprise an electrically conductive material. The fourth line ML4 can comprise tungsten.

[0048] A fifth line ML5 can be connected to the plurality of fifth contacts CT5. The fifth line ML5 can be located in the second insulating layer 120. The fifth line ML5 can be located in the second connection region COR2. The fifth line ML5 can be disposed at the same height as the bit line BL and the fourth line ML4. The fifth line ML5 can comprise an electrically conductive material. The fifth line ML5 can comprise tungsten.

[0049] A semiconductor structure SEM can be located on the connection structure CNS. The semiconductor structure SEM can comprise the third insulating layer 130, the stacked structure STA, the word line contacts WCT, the cell plugs CPL, and the dummy plugs DPL. The connection structure CNS can be disposed between the semiconductor structure SEM and the peripheral circuit structure PER.

[0050] The third insulating layer 130 can cover the second insulating layer 120. The third insulating layer 130 can comprise an insulating material. In embodiments, the third insulating layer 130 can comprise an oxide or a nitride.

[0051] The stacked structure STA can be located on the third insulating layer 130. The stacked structure STA can comprise electrically conductive patterns CP and insulating patterns IP alternately stacked in a third direction D3. Because the directions D1, D2, and D3 are not parallel, the third direction D3 can cross the first direction D1 and the second direction D2. In embodiments, the third direction D3 can be orthogonal to the first direction D1 and the second direction D2.

[0052] The electrically conductive patterns CP can function as word lines or select lines of the semiconductor device. The electrically conductive patterns CP can comprise an electrically conductive material. The insulating patterns IP can comprise an insulating material. In embodiments, the insulating patterns IP can comprise an oxide.

[0053] The stacked structure STA can include a stepped structure. The conductive pattern CP and the insulating pattern IP can be stacked to form the stacked structure STA in the first connection region COR1. The third insulating layer 130 can include a stepped surface corresponding to the stepped structure of the stacked structure STA.

[0054] The cell plug CPL can extend in the third direction D3 to penetrate the stacked structure STA. The cell plug CPL can be located in the cell region CER. The cell plug CPL can include a cell fill layer CFI, a cell channel layer CCL surrounding the cell fill layer CFI, and a cell memory layer CML surrounding the cell channel layer CCL.

[0055] The cell fill layer CFI can include an insulating material. In an embodiment, the cell fill layer CFI can include an oxide. The cell channel layer CCL can include a semiconductor material. In an embodiment, the cell channel layer CCL can include polysilicon. The cell memory layer CML can include a tunnel insulating layer surrounding the cell channel layer CCL, a data storage layer surrounding the tunnel insulating layer, and a blocking layer surrounding the data storage layer. The tunnel insulating layer can include a material through which a charge can tunnel. In an embodiment, the tunnel insulating layer can include an oxide. In some embodiments, the data storage layer can include a material that can trap a charge. In an embodiment, the data storage layer can include nitride. In other embodiments, the data storage layer can include various materials according to a data storage method. In an embodiment, the data storage layer can include silicon, a phase change material, or a nanodot. The blocking layer can include a material capable of blocking the movement of a charge. In an embodiment, the blocking layer can include an oxide.

[0056] The dummy plug DPL can extend in the third direction D3 to penetrate the stacked structure STA. The dummy plug DPL can penetrate the stepped structure of the stacked structure STA. The dummy plug DPL can be located in the first connection region COR1. The dummy plug DPL can include a dummy fill layer DFI, a dummy channel layer DCL surrounding the dummy fill layer DFI, and a dummy memory layer DML surrounding the dummy channel layer DCL.

[0057] The dummy fill layer DFI can include an insulating material. The dummy fill layer DFI can include the same material as the cell fill layer CFI. In an embodiment, the dummy fill layer DFI can include an oxide. The dummy channel layer DCL can include a semiconductor material. The dummy channel layer DCL can include the same material as the cell channel layer CCL. In an embodiment, the dummy channel layer DCL can include polysilicon. The dummy memory layer DML can include a tunnel insulating layer surrounding the dummy channel layer DCL, a data storage layer surrounding the tunnel insulating layer, and a blocking layer surrounding the data storage layer. The tunnel insulating layer, the data storage layer, and the blocking layer of the dummy memory layer DML can be similar to the tunnel insulating layer, the data storage layer, and the blocking layer of the cell memory layer CML.

[0058] Each word line contact WCT can connect the sixth contact CT6 and the conductive pattern CP. The word line contact WCT can penetrate the third insulating layer 130. The word line contact WCT can be located in the first connection region COR1. The word line contact WCT can include a conductive material. In an embodiment, the word line contact WCT can include tungsten.

[0059] The conductive pattern CP can be electrically connected to the second peripheral transistor TR2 through the word line contact WCT, the sixth contact CT6, the fourth line ML4, the fourth contact CT4, the second connection conductor CO2, the fifth bonding pad BP5, the second bonding pad BP2, the second contact CT2, and the second line ML2. The word line contact WCT, the sixth contact CT6, the fourth line ML4, the fourth contact CT4, the second connection conductor CO2, the fifth bonding pad BP5, the second bonding pad BP2, the second contact CT2, and the second line ML2 through which the conductive pattern CP is electrically connected to the second peripheral transistor TR2 can be defined as a first conductor. The conductive pattern CP can be electrically connected to the second peripheral transistor TR2 through the first conductor.

[0060] The semiconductor device can include a bit line contact BCT. The bit line contact BCT can connect the bit line BL to the cell channel layer CCL of the cell plug CPL. The bit line contact BCT can penetrate the third insulating layer 130. The bit line contact BCT can be located in the cell region CER. The bit line contact BCT can include a conductive material. In an embodiment, the bit line contact BCT can include tungsten.

[0061] The cell channel layer CCL of the cell plug CPL can be electrically connected to the first peripheral transistor TR1 through the bit line contact BCT, the bit line BL, the third contact CT3, the first connection conductor CO1, the fourth bonding pad BP4, the first bonding pad BP1, the first contact CT1, and the first line ML1. The cell channel layer CCL of the cell plug CPL electrically connected to the first peripheral transistor TR1 through the bit line contact BCT, the bit line BL, the third contact CT3, the first connection conductor CO1, the fourth bonding pad BP4, the first bonding pad BP1, the first contact CT1, and the first line ML1 can be defined as a second conductor. The cell channel layer CCL of the cell plug CPL can be electrically connected to the first peripheral transistor TR1 through the second conductor.

[0062] The fourth insulating layer 140 can be located on the semiconductor structure SEM. The fourth insulating layer 140 can cover the third insulating layer 130 and the stack structure STA. The fourth insulating layer 140 can include an insulating material. In an embodiment, the fourth insulating layer 140 can include an oxide or a nitride.

[0063] The cell source structure CSS can be located in the fourth insulating layer 140. The cell source structure CSS can be located on the stack structure STA. The cell source structure CSS can be located in the cell region CER. The cell source structure CSS can be connected to the cell channel layer CCL of the cell plug CPL. The cell source structure CSS can include a conductive material. In an embodiment, the cell source structure CSS can include polysilicon.

[0064] The dummy source structure DSS can be located in the fourth insulating layer 140. The dummy source structure DSS can be located on the stack structure STA. The dummy source structure DSS can be located in the first connection region COR1. The dummy source structure DSS can be connected to the dummy channel layer DCL of the dummy plug DPL. The dummy source structure DSS can be disposed at the same height as the cell source structure CSS. The dummy source structure DSS can include a conductive material. The dummy source structure DSS can include the same material as the cell source structure CSS. In an embodiment, the dummy source structure DSS can include polysilicon.

[0065] The cell source structure CSS and the dummy source structure DSS can be spaced apart from each other. A portion of the fourth insulating layer 140 can be interposed between the cell source structure CSS and the dummy source structure DSS. The cell source structure CSS and the dummy source structure DSS can be electrically isolated from each other.

[0066] The recess RC can be defined by the third insulating layer 130 and the fourth insulating layer 140. The recess RC can be defined by surfaces of the third insulating layer 130 and the fourth insulating layer 140. The recess RC can penetrate the fourth insulating layer 140. A top surface 132 of the third insulating layer 130 can be depressed to define the recess RC. A lowermost portion of the recess RC can be disposed in the third insulating layer 130. The recess RC can include sidewalls defined by sidewalls of the third insulating layer 130 and the fourth insulating layer 140.

[0067] The semiconductor device can include wiring contacts WRC. The wiring contacts WRC can penetrate the third insulating layer 130. The wiring contacts WRC can be connected to the seventh contacts CT7. The wiring contacts WRC can be located in the second connection region COR2. The wiring contacts WRC can be exposed by the recess RC. The wiring contacts WRC can be disposed at the same height as the stacked structure STA. The wiring contacts WRC can include a conductive material. In an embodiment, the wiring contacts WRC can include tungsten. The wiring contacts WRC can be spaced apart from each other by the third insulating layer 130. A portion of the third insulating layer 130 can be located between the wiring contacts WRC.

[0068] The bonding wire BW can be connected to the plurality of wiring contacts WRC. The bonding wire BW can be in contact with the plurality of wiring contacts WRC. A portion of the bonding wire BW can be located in the recess RC. The bonding wire BW can be electrically connected to the third line ML3 by the wiring contacts WRC, the seventh contacts CT7, the fifth line ML5, the fifth contacts CT5, the wiring connection conductor WCO, the sixth bonding pad BP6, and the third bonding pad BP3. The bonding wire BW can electrically connect the semiconductor device to an external circuit. The bonding wire BW can include a conductive material. In an embodiment, the bonding wire BW can include at least one of gold, silver, copper, and aluminum.

[0069] The first connection conductor CO1, the second connection conductor CO2, and the wiring connection conductor WCO can include a material different from a material of the first to seventh contacts CT1, CT2, CT3, CT4, CT5, CT6, and CT7, the first to fifth lines ML1, ML2, ML3, ML4, and ML5, the bit line BL, the bit line contact BCT, the word line contact WCT, and the wiring contact WRC. In an embodiment, the first to seventh contacts CT1, CT2, CT3, CT4, CT5, CT6, and CT7, the first to fifth lines ML1, ML2, ML3, ML4, and ML5, the bit line BL, the bit line contact BCT, the word line contact WCT, and the wiring contact WRC can include tungsten, and the first connection conductor CO1, the second connection conductor CO2, and the wiring connection conductor WCO can include copper or aluminum. The first connection conductor CO1, the second connection conductor CO2, and the wiring connection conductor WCO can include the same material.

[0070] The fourth insulating layer 140, the wiring contact WRC, and the bonding wire BW can be covered with a fifth insulating layer 150. A portion of the fifth insulating layer 150 can fill the recessed portion RC. The fifth insulating layer 150 can include an insulating material. In an embodiment, the fifth insulating layer 150 can include an oxide or a nitride.

[0071] Referring to FIG. 1B and FIG. 1C Each of the wiring contacts WRC can include a base portion BA and a protruding portion PT. The base portion BA can be a portion surrounded by the third insulating layer 130. The base portion BA can be disposed in the third insulating layer 130. The protruding portion PT can be a portion protruding outside of the third insulating layer 130. The protruding portion PT can be exposed by the recessed portion RC. A top surface PT_U of the protruding portion PT can be curved. In an embodiment, the top surface PT_U of the protruding portion PT can be curved, as viewed from the perspective of the cross-section shown in FIG. 10. FIG. 1B

[0072] The third insulating layer 130 can include a first surface 131 defining a bottom surface of the recessed portion RC. The wiring contact WRC can penetrate the first surface 131. A height of a boundary between the base portion BA and the protruding portion PT of the wiring contact WRC can be the same as a height of the first surface 131.

[0073] The bonding wire BW can include one or more intervening portions IN intervening between the protruding portions PT of the wiring contacts WRC. The intervening portions IN can be connected to each other. The protruding portions PT can be intervened by the intervening portions IN. The intervening portions IN can be in contact with the top surface PT_U and the sidewall PT_S of the protruding portion PT. A lower surface IN_L of the intervening portion IN can be curved. In an embodiment, the lower surface IN_L of the intervening portion IN can be curved, as viewed from the perspective of the cross-section shown in FIG. 11. FIG. 1B

[0074] A portion of the fifth insulating layer 150 can intervene between the protruding portions of the wiring contact WRC. The portion of the fifth insulating layer 150 intervening between the protruding portions PT can be defined as a first portion 151 of the fifth insulating layer 150. The first portion 151 of the fifth insulating layer 150 can be in contact with the lower surface IN_L of the intervening portion IN, the sidewall PT_S of the protruding portion PT, and the first surface 131 of the third insulating layer 130.

[0075] ​​In the semiconductor device according to the embodiment of the present disclosure, the bonding wire BW can be positioned in the recessed portion RC defined by the third insulating layer 130 and the fourth insulating layer 140, and can directly contact the wire contact WRC without an intermediate medium such as a top metal pattern. Therefore, it is possible to reduce the distance of transmitting a signal between the bonding wire BW and the peripheral transistor.

[0076] In the semiconductor device according to the embodiment of the present disclosure, the bonding wire BW, the wire contact WRC, and the wire connection conductor WCO can be disposed adjacent to the stacked structure STA and the cell plug CPL, so that it is possible to reduce the size of the semiconductor device.

[0077] In the semiconductor device according to the embodiment of the present disclosure, only the wire contact WRC exposed by the recessed portion RC is connected to the bonding wire BW, so that it is possible to prevent a phenomenon in which the bonding wire BW contacts another conductor. More specifically, the conductors other than the wire contact WRC, such as the first connection conductor CO1, the second connection conductor CO2, the wire connection conductor WCO, the conductive pattern CP, the word line contact WCT, the cell source structure CSS, and the like, can be covered with the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140. Therefore, it is possible to prevent the bonding wire BW from contacting the conductors other than the wire contact WRC.

[0078] In the semiconductor device according to the embodiment of the present disclosure, a part of each wire contact WRC can be exposed by the recessed portion RC defined by the third insulating layer 130 and the fourth insulating layer 140, and the other part of each wire contact WRC can be protected by the third insulating layer 130. Therefore, it is possible to reduce damage to the wire contact WRC.

[0079] FIG. 2 、 FIG. 3 、 FIG. 4 、 FIG. 5 、 FIG. 6 、 FIG. 7 、 FIG. 8 and FIG. 9 are diagrams illustrating a method of manufacturing a semiconductor device according to the embodiment of the present disclosure. For ease of description, repetitive description of components already described with reference to FIGS. 1A-1C will be omitted. FIGS. 1A-1C The method of manufacturing a semiconductor device illustrated in

[0080] With reference to FIG. 2 , a second substrate 200 can be formed. The second substrate 200 can have a plate-like shape extending in a first direction D1 and a second direction D2. In the embodiment, the second substrate 200 can be a semiconductor substrate.

[0081] A semiconductor structure SEM can be formed on the second substrate 200. A stacked structure STA, a cell plug CPL, a dummy plug DPL, and a third insulating layer 130 can be formed on the second substrate 200. The stacked structure STA can include conductive patterns CP and insulating patterns IP alternately stacked on the second substrate 200. The third insulating layer 130 can surround the stacked structure STA.

[0082] Referring to FIG. 3 , a word line contact WCT and a wiring contact WRC can be formed to penetrate the third insulating layer 130. The wiring contact WRC can be surrounded by the third insulating layer 130. The wiring contact WRC can include a preliminary etching part PE inserted into the second substrate 200. The preliminary etching part PE can be located in the second substrate 200.

[0083] Referring to FIG. 4 , a connection structure CNS can be formed on the semiconductor structure SEM. The second insulating layer 120, a bit line contact BCT, a sixth contact CT6, a seventh contact CT7, a bit line BL, a fourth line ML4, a fifth line ML5, a third contact CT3, a fourth contact CT4, a fifth contact CT5, a first connection conductor CO1, a second connection conductor CO2, a wiring connection conductor WCO, a fourth bonding pad BP4, a fifth bonding pad BP5, and a sixth bonding pad BP6 can be formed on the third insulating layer 130.

[0084] Referring to FIG. 5 , a peripheral circuit structure PER can be formed to include the first substrate 100 and first and second peripheral transistors TR1 and TR2. Impurity regions IR of the first and second peripheral transistors TR1 and TR2 can be insulated from each other by an isolation layer IS disposed in the first substrate 100. A gate insulating layer GI and a gate electrode GM of each of the first and second peripheral transistors TR1 and TR2 can be stacked on the first substrate 100. The peripheral circuit structure PER can include a first insulating layer 110, a first contact CT1, a first line ML1, a second contact CT2, a second line ML2, a first bonding pad BP1, a second bonding pad BP2, a third line ML3, and a third bonding pad BP3 disposed on the first substrate 100.

[0085] Referring to FIG. 6The second substrate 200, the semiconductor structure SEM, and the connection structure CNS can be reversed. Subsequently, the connection structure CNS and the peripheral circuit structure PER can be bonded to each other. The fourth bonding pad BP4 can be bonded to the first bonding pad BP1. Thus, the cell plug CPL can be electrically connected to the first peripheral transistor TR1. The fifth bonding pad BP5 can be bonded to the second bonding pad BP2. Thus, the conductive pattern CP can be electrically connected to the second peripheral transistor TR2. The sixth bonding pad BP6 can be bonded to the third bonding pad BP3.

[0086] Referring to FIG. 7 The second substrate 200 can be removed. Thus, the preliminary etching portion PE of the wiring contact WRC can be exposed. The preliminary etching portion PE of the wiring contact WRC can protrude further in the upward direction D3 than the third insulating layer 130 of the semiconductor structure SEM. The upper portion of the cell memory layer CML of the cell plug CPL and the upper portion of the dummy memory layer DML of the dummy plug DPL can be removed. In some embodiments, the upper portion of the cell memory layer CML of the cell plug CPL and the upper portion of the dummy memory layer DML of the dummy plug DPL can be removed together with the second substrate 200 in a process of removing the second substrate 200. In some embodiments, the upper portion of the cell memory layer CML of the cell plug CPL and the upper portion of the dummy memory layer DML of the dummy plug DPL can be removed by a process separate from the process of removing the second substrate 200.

[0087] When the upper portion of the cell memory layer CML of the cell plug CPL and the upper portion of the dummy memory layer DML of the dummy plug DPL are removed, the cell channel layer CCL of the cell plug CPL can be exposed, and the dummy channel layer DCL of the dummy plug DPL can be exposed.

[0088] Referring to FIG. 8 The cell source structure CSS and the dummy source structure DSS can be formed. Forming the cell source structure CSS and the dummy source structure DSS can include forming a preliminary source structure (not shown) connected to the cell plug CPL and the dummy plug DPL, and isolating the preliminary source structure into the cell source structure CSS and the dummy source structure DSS.

[0089] The fourth insulating layer 140 can be formed to cover the cell source structure CSS and the dummy source structure DSS. The preliminary etching portion PE of the wiring contact WRC can be covered by the fourth insulating layer 140.

[0090] Referring to FIG. 9The recess RC can be formed by etching the fourth insulating layer 140 and the third insulating layer 130. In the process of forming the recess RC, the wiring contact WRC can be etched together with the third insulating layer 130 and the fourth insulating layer 140. The third insulating layer 130, the fourth insulating layer 140, and the wiring contact WRC can be etched using a first etching material capable of etching the third insulating layer 130, the fourth insulating layer 140, and the wiring contact WRC. The wiring contact WRC can have etch selectivity relative to the third insulating layer 130 and the fourth insulating layer 140. The etching rate of the third insulating layer 130 and the fourth insulating layer 140 by the first etching material can be higher than the etching rate of the wiring contact WRC by the first etching material.

[0091] The initial etched portion PE of the wiring contact WRC can be removed during etching. The length of the wiring contact WRC can be reduced by etching it. In this embodiment, the maximum length of the wiring contact WRC in the third direction D3 can be reduced by etching it. The top surface PT_U of the protrusion PT of the wiring contact WRC can be formed into a curved shape by etching the wiring contact WRC.

[0092] The protrusion PT of the wiring contact WRC can be exposed through the recess RC by etching the third insulating layer 130.

[0093] Subsequently, a bonding wiring BW can be formed to connect to the exposed wiring contact WRC, such as FIG. 1A As shown. Furthermore, a fifth insulating layer 150 can be formed to fill the recessed portion RC, as... FIG. 1A As shown.

[0094] FIG. 10 This is a cross-sectional view illustrating wiring contacts and joint wiring according to an embodiment of the present disclosure.

[0095] Apart from the portions described below, the semiconductor device according to these embodiments can be similar to that according to FIGS. 1A-1C The semiconductor device of the embodiment shown.

[0096] Reference FIG. 10 The recessed portion RCa can be defined by a third insulating layer 130a and a fourth insulating layer 140a. A fifth insulating layer 150a can fill the recessed portion RCa. The protruding portion PTa of the wiring contact WRCa can be exposed through the recessed portion RCa. The base BAa of the wiring contact WRCa can be located in the third insulating layer 130a. The insertion portion INa of the bonding wiring BWa can be inserted between the protruding portions PTa of the wiring contact WRCa.

[0097] The first surface 131a of the third insulating layer 130a can be a surface defining a bottom surface of the recessed portion RCa. The interposition portion INa of the bonding wire BWa can be spaced apart from the third insulating layer 130a. The lower surface IN_La and the lowermost portion IN_Ba of the interposition portion INa of the bonding wire BWa can be spaced apart from the first surface 131a of the third insulating layer 130a. The first portion 151a of the fifth insulating layer 150a can be interposed between the interposition portion INa of the bonding wire BWa and the first surface 131a of the third insulating layer 130a. The interposition portion INa of the bonding wire BWa and the first surface 131a of the third insulating layer 130a can be spaced apart from each other by the first portion 151a of the fifth insulating layer 150a. The lower surface IN_La and the lowermost portion IN_Ba of the interposition portion INa of the bonding wire BWa can be in contact with the first portion 151a of the fifth insulating layer 150a.

[0098] FIG. 11 is a block diagram illustrating a configuration of a memory system 1100 according to an embodiment of the disclosure.

[0099] Referring to FIG. 11 , the memory system 1100 can include a memory device 1120 and a memory controller 1110.

[0100] The memory device 1120 can include the semiconductor device described above. The memory device 1120 can be a multi-chip package configured with a plurality of flash memory chips.

[0101] The memory controller 1110 is configured to control the memory device 1120, and can include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a memory interface 1115. The SRAM 1111 is used as an operation memory of the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected with the memory system 1100. The ECC circuit 1114 detects and corrects an error included in data read from the memory device 1120, and the memory interface 1115 is interfaced with the memory device 1120. Furthermore, the memory controller 1110 can further include a ROM for storing code data, etc. for connection with the host interface.

[0102] The memory system 1100 configured as described above can be a solid state drive (SSD) or a memory card in which the memory device 1120 is combined with the memory controller 1110 together. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external (e.g., a host) through one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a PCI-express (PCI-E) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0103] FIG. 12 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the disclosure.

[0104] Referring to FIG. 12 , the computing system 1200 can include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, a battery for providing an operating voltage to the computing system 1200 can be further included, and an application chipset, a camera image processor, a mobile DRAM, etc. can be further included.

[0105] The memory system 1210 can be configured with a memory device 1212 and a memory controller 1211 similar to the memory device and the memory controller described with reference to FIG. 11

[0106] In the semiconductor device according to the disclosure, the bonding wire, the wire contact, and the wire connection conductor can be disposed adjacent to the stacked structure and the cell plug. Accordingly, the size of the semiconductor device can be reduced, and the integration of the semiconductor device can be improved.

[0107] In the semiconductor device according to the disclosure, the wire contact exposed through the recess can be connected to the bonding wire, and a conductor other than the wire contact can be prevented from contacting the bonding wire. Accordingly, the operation reliability of the semiconductor device can be improved.

[0108] Cross Reference to Related Applications

[0109] This application claims priority to Korean Patent Application No. 10-2020-0138389, filed on October 23, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.​

Claims

1. A semiconductor device comprising: a laminated structure including conductive patterns and insulating patterns alternately laminated; a first insulating layer surrounding the laminated structure; wiring contacts spaced apart from each other by the first insulating layer; and a bonding wire connected to the wiring contacts, wherein each of the wiring contacts includes a base in the first insulating layer and a protruding portion protruding from an inner portion of the first insulating layer to an outer portion, and wherein the protruding portions of the wiring contacts are in contact with the bonding wire, wherein a top surface of the first insulating layer is recessed to define a recessed portion, and wherein the protruding portions of the wiring contacts are exposed through the recessed portion. a second insulating layer filling the recessed portion.

2. The semiconductor device according to claim 1, further comprising: The bonding wire is disposed in the recessed portion.

3. The semiconductor device according to claim 1, wherein The bonding wire includes at least one intervening portion interposed between the protruding portions of the wiring contacts.

4. The semiconductor device according to claim 1, wherein The at least one intervening portion is in contact with the first insulating layer.

5. The semiconductor device according to claim 4, wherein The at least one intervening portion is in contact with sidewalls of the protruding portions of the wiring contacts.

6. The semiconductor device according to claim 4, wherein 7. A semiconductor device comprising: a first insulating layer including a recessed portion; wiring contacts exposed through the recessed portion of the first insulating layer; a bonding wire connected to the wiring contacts; a second insulating layer filling the recessed portion; and a laminated structure including conductive patterns and insulating patterns alternately laminated, wherein the bonding wire includes at least one intervening portion interposed between the wiring contacts, and wherein a lower surface of the at least one intervening portion is in contact with at least one of the first insulating layer and the second insulating layer, wherein the first insulating layer surrounds the laminated structure. A lowermost portion of the at least one intervening portion is in contact with the first insulating layer. Each of the wiring contacts includes a base in the first insulating layer and a protruding portion exposed through the recessed portion.

8. The semiconductor device according to claim 7, wherein The at least one intervening portion is interposed between the protruding portions of the wiring contacts.

9. The semiconductor device according to claim 7, wherein The wiring contacts are disposed at the same height as the laminated structure.

10. The semiconductor device according to claim 9, wherein 12. A semiconductor device comprising:

11. The semiconductor device according to claim 7, wherein a semiconductor structure including a laminated structure and an insulating layer surrounding the laminated structure; a peripheral circuit structure including peripheral transistors; a connection structure disposed between the semiconductor structure and the peripheral circuit structure, the connection structure including a wiring connection conductor; a wiring contact penetrating the insulating layer, the wiring contact electrically connected to the wiring connection conductor; and a bonding wire connected to the wiring contact, wherein the insulating layer includes a recessed portion through which the wiring contact is exposed, and wherein the bonding wire is in contact with the wiring contact in the recessed portion. The wiring connection conductor and the wiring contact include different materials. ​ ​ 13. The semiconductor device according to claim 12, wherein ​ 14. The semiconductor device according to claim 13, wherein The wiring connection conductor includes at least one of copper and aluminum.

15. The semiconductor device according to claim 12, wherein The semiconductor structure further includes a cell plug that penetrates the laminated structure, wherein the connection structure includes a first connection conductor that electrically connects the peripheral transistor and the cell plug, and wherein the first connection conductor is disposed at the same height as the wiring connection conductor.

16. The semiconductor device according to claim 15, wherein The first connection conductor and the wiring connection conductor include the same material.

17. The semiconductor device according to claim 12, wherein The laminated structure includes a conductive pattern that is electrically connected to the peripheral transistor, wherein the connection structure includes a second connection conductor that electrically connects the peripheral transistor and the conductive pattern, and wherein the second connection conductor is disposed at the same height as the wiring connection conductor.

18. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a laminated structure including alternately laminated conductive patterns and insulating patterns; forming an insulating layer that surrounds the laminated structure; forming wiring contacts that penetrate the insulating layer; etching the insulating layer to expose the wiring contacts; and forming bonding wires that are connected to the wiring contacts, wherein the step of etching the insulating layer includes the step of etching the wiring contacts together with the insulating layer.

19. The method of claim 18, wherein, The step of etching the wiring contacts includes the step of reducing a length of each of the wiring contacts.

20. The method of claim 18, wherein, The step of forming the wiring contacts that penetrate the insulating layer includes the step of forming the wiring contacts to be spaced apart from each other by the insulating layer.

21. The method according to claim 18, further comprising the steps of: forming a cell plug that penetrates the laminated structure, wherein the cell plug is formed to include a cell channel layer and a cell memory layer that surrounds the cell channel layer; and removing an upper portion of the cell memory layer of the cell plug to expose the cell channel layer.

22. The method according to claim 18, further comprising the steps of: forming first bonding pads that are electrically connected to each of the conductive patterns; forming a peripheral transistor; forming second bonding pads that are electrically connected to the peripheral transistor; and bonding the first bonding pads and the second bonding pads to each other.

23. The method of claim 18, wherein, The step of etching the insulating layer to expose the wiring contacts includes the step of etching a top surface of each of the wiring contacts to have a curved shape.

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