Display device

Abstract

A display device includes: a first gate electrode disposed in a peripheral region and included in a gate driver; a second gate electrode disposed in a display region and integrated with a gate line driven by the gate driver; a first oxide semiconductor disposed above the first gate electrode; a second oxide semiconductor disposed above the second gate electrode; a first source electrode in contact with the first oxide semiconductor at a first opening of a second insulating film; a first drain electrode in contact with the first oxide semiconductor at a second opening of the second insulating film; a second source electrode in contact with the second oxide semiconductor at a third opening of the second insulating film; and a second drain electrode in contact with the second oxide semiconductor at a fourth opening of the second insulating film, wherein a length of a laminate of the second insulating film and the first source electrode between the first opening and the second opening is greater than a length of a laminate of the second insulating film and the second source electrode between the third opening and the fourth opening.

Description

[0001] Related Application

[0002] This application is based on and claims the priority of Japanese Patent Application No. 2020-179098 filed on October 26, 2020, the entire content of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a display device. Background Art

[0004] In a liquid crystal display device, the following technology has been proposed: a transistor including an oxide semiconductor is provided in a pixel circuit in a display region, and a transistor including a silicon semiconductor is provided in a driving circuit in a peripheral region. Summary of the Invention

[0005] An object of the present embodiment is to provide a display device that can be miniaturized.

[0006] A display device according to an embodiment includes:

[0007] an insulating substrate; a first gate electrode disposed above the insulating substrate in a peripheral region and included in a gate driver; a second gate electrode disposed above the insulating substrate in a display region and integrated with a gate line driven by the gate driver; a first insulating film covering the first gate electrode and the second gate electrode; a first oxide semiconductor disposed above the first gate electrode and in contact with the first insulating film; a second oxide semiconductor disposed above the second gate electrode and in contact with the first insulating film; a second insulating film covering the first oxide semiconductor and the second oxide semiconductor; a first source electrode in contact with the second insulating film and in contact with the first oxide semiconductor at a first opening of the second insulating film; a first drain electrode in contact with the second insulating film and in contact with the first oxide semiconductor at a second opening of the second insulating film; a second source electrode in contact with the second insulating film and in contact with the second oxide semiconductor at a third opening of the second insulating film; and a second drain electrode in contact with the second insulating film and in contact with the second oxide semiconductor at a fourth opening of the second insulating film, wherein a length of a laminate of the second insulating film and the first source electrode between the first opening and the second opening is greater than a length of a laminate of the second insulating film and the second source electrode between the third opening and the fourth opening.

[0008] In addition, the display device according to other embodiments includes: an insulating substrate; a first gate electrode disposed in a peripheral region above the insulating substrate and included in a gate driver; a second gate electrode disposed in a display region above the insulating substrate and integrated with a gate line driven by the gate driver; a first insulating film covering the first gate electrode and the second gate electrode; a first oxide semiconductor disposed above the first gate electrode and in contact with the first insulating film; and a second oxide semiconductor disposed above the second gate electrode and in contact with the first insulating film, the first oxide semiconductor having a first channel region; and a first low-resistance region adjacent to the first channel region and having a lower resistance than the first channel region, the second oxide semiconductor having a second channel region; and a second low-resistance region adjacent to the second channel region and having a lower resistance than the second channel region, the length of the first low-resistance region being greater than the length of the second low-resistance region.

[0009] According to the present embodiment, a display device capable of miniaturization can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a top view showing the structure of the DSP of the display device according to the present embodiment.

[0011] Figure 2 It includes Figure 1 A cross-sectional view of the DSP of the display device including the pixel PX shown.

[0012] Figure 3 It is a cross-sectional view showing an example of the first transistor TR1.

[0013] Figure 4 It is a cross-sectional view showing an example of the second transistor TR2.

[0014] Figure 5 It is a graph showing the result of the reliability test of the first transistor TR1 according to the comparative example.

[0015] Figure 6 It is a graph showing the result of the reliability test of the first transistor TR1 according to the present embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] Hereinafter, this embodiment will be described with reference to the accompanying drawings. It should be noted that the disclosure is merely an example, and for those skilled in the art, the content that can be easily conceived by making appropriate changes while maintaining the gist of the invention is of course included in the scope of the present invention. In addition, in order to make the description clearer, the drawings sometimes schematically show the widths, thicknesses, shapes, etc. of the respective parts, as compared with the actual mode, but after all, it is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each drawing, components that perform the same or similar functions as the components described above in the previously shown drawings may be labeled with the same reference numerals, and repeated detailed descriptions may be appropriately omitted.

[0017] It should be noted that in the drawings, for ease of understanding, the X-axis, Y-axis, and Z-axis orthogonal to each other are shown as needed. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. The plane defined by the X-axis and the Y-axis is referred to as the X-Y plane, and observing the X-Y plane is referred to as a top view.

[0018] In this embodiment, as an example of a display device, an electrophoretic display device will be described. It should be noted that the main structures disclosed in this embodiment can also be used in display devices having self-luminous light-emitting elements such as organic electroluminescence (EL) elements, micro LEDs, and mini LEDs, in addition to liquid crystal display devices.

[0019] Figure 1 It is a top view showing the structure of the display device DSP according to this embodiment. The display device DSP includes a display area DA for displaying an image and a peripheral area (non-display area) SA around the display area DA. Figure 1 In the example shown, the peripheral area SA is formed in a frame shape surrounding the display area DA.

[0020] The display device DSP includes a gate driver GD1, a gate driver GD2, and a source driver SD in the peripheral area SA. The gate driver GD1 and the gate driver GD2 each include a plurality of shift registers SR. The shift register SR includes a first transistor TR1. In this way, the gate driver GD1 and the gate driver GD2 are formed on the same substrate together with the respective elements of the display area DA.

[0021] The display device DSP includes a plurality of pixels PX, a plurality of gate lines GL, a plurality of source lines SL, a plurality of capacitor wirings CW, and a common electrode CE in the display area DA. The plurality of pixels PX are arranged in a matrix in the first direction X and the second direction Y.

[0022] A plurality of gate lines GL extend respectively along a first direction X, and are arranged at intervals in a second direction Y. It should be noted that sometimes the gate line GL is referred to as a scan line. The gate line GL is electrically connected to a gate driver GD1 and a gate driver GD2. For example, the odd-numbered gate lines GL are connected to the shift register SR of the gate driver GD1, and the even-numbered gate lines GL are connected to the shift register SR of the gate driver GD2. The gate lines GL are respectively driven by the gate driver GD1 and the gate driver GD2.

[0023] A plurality of source lines SL extend respectively along the second direction Y, and are arranged at intervals in the first direction X. It should be noted that sometimes the source line SL is referred to as a signal line. In a display area DA, a plurality of source lines SL intersect a plurality of gate lines GL. The source line SL is electrically connected to a source driver SD. The source lines SL are respectively driven by the source driver SD.

[0024] A plurality of capacitor wirings CW extend along the first direction X or the second direction Y. The plurality of capacitor wirings CW are bundled, for example, in a peripheral area SA, and are connected to a voltage supply unit Vpc that supplies a predetermined voltage.

[0025] A common electrode CE is disposed over a plurality of pixels PX. The common electrode CE is connected to a voltage supply unit Vcom that supplies a predetermined voltage.

[0026] As Figure 1 As enlarged and shown in the figure, each pixel PX includes a second transistor TR2 and a pixel electrode PE. Although it will be described later, the first transistor TR1 and the second transistor TR2 are formed of, for example, thin film transistors (TFTs). The second transistor TR2 is electrically connected to the gate line GL and the source line SL. The gate line GL is electrically connected to the second transistor TR2 of each pixel PX arranged along the first direction X. The source line SL is electrically connected to the second transistor TR2 of each pixel PX arranged along the second direction Y.

[0027] The pixel electrode PE is electrically connected to the second transistor TR2. The pixel electrodes PE face the common electrode CE respectively. A capacitor CS1 is formed between the pixel electrode PE and the capacitor wiring CW. A capacitor CS2 is formed between the common electrode CE and the pixel electrode PE.

[0028] Figure 2 It is a cross-sectional view of a display device DSP including Figure 1 the pixel PX shown.

[0029] The first substrate SUB1 includes an insulating substrate 10, insulating films 11 to 14, a second transistor TR2, a capacitor wiring CW, and a pixel electrode PE. It should be noted that the structure of the second transistor TR2 is shown in a simplified manner. In addition, the insulating films 11 to 14 are also shown in a simplified manner.

[0030] The insulating substrate 10 is formed of an insulating material such as resin or glass. Details of the second transistor TR2 will be described later, but the second transistor TR2 includes a second gate electrode GE2 integrated with the gate line GL, a second source electrode SE2 integrated with the source line SL, a second drain electrode DE2, and a second oxide semiconductor SC2. In this specification, the electrode on the side electrically connected to the source line SL is referred to as the second source electrode SE2, and the electrode on the side electrically connected to the pixel electrode PE is referred to as the second drain electrode DE2.

[0031] An insulating film 11 is interposed between the second gate electrode GE2 and the second oxide semiconductor SC2. Insulating films 12 are respectively interposed between the second oxide semiconductor SC2 and the second source electrode SE2, and between the second oxide semiconductor SC2 and the second drain electrode DE2. An insulating film 13 covers the second source electrode SE2 and the second drain electrode DE2. It should be noted that the insulating film 11 and the insulating film 12 are inorganic insulating films, but they may be a single layer or a laminate composed of multiple inorganic insulating films. The insulating film 13 is, for example, a laminate of one or more inorganic insulating films and an organic insulating film. One inorganic insulating film contained in the insulating film 13 directly covers the second source electrode SE2 and the second drain electrode DE2.

[0032] The capacitor wiring CW is disposed on the insulating film 13 and covered by an insulating film 14. The pixel electrode PE is disposed on the insulating film 14. The pixel electrode PE is in contact with the second drain electrode DE2 and electrically connected to the second transistor TR2.

[0033] The second substrate SUB2 includes an insulating substrate 20, a common electrode CE, and an electrophoretic element 21. The insulating substrate 20 is formed of an insulating material such as resin or glass. The common electrode CE is located between the insulating substrate 20 and the electrophoretic element 21. The electrophoretic element 21 is located between the pixel electrode PE and the common electrode CE. The electrophoretic element 21 is formed by a plurality of microcapsules 30 arranged with almost no gap.

[0034] The first substrate SUB1 and the second substrate SUB2 are bonded together by an adhesive layer 40. In the illustrated example, the adhesive layer 40 is located between the pixel electrode PE and the electrophoretic element 21.

[0035] The microcapsules 30 have a particle diameter of about 20 μm to 70 μm, for example. A plurality of microcapsules 30 are disposed between one pixel electrode PE and the common electrode CE. The microcapsules 30 include a dispersion medium 31, a plurality of black particles 32, and a plurality of white particles 33. The black particles 32 and the white particles 33 are sometimes referred to as electrophoretic particles.

[0036] The outer shell 34 of the microcapsule 30 is formed of a transparent resin such as an acrylic resin. The dispersion medium 31 is a liquid that disperses the black particles 32 and the white particles 33 within the microcapsule 30. The black particles 32 and the white particles 33 have opposite-polarity charges to each other. For example, the black particles 32 are positively charged and the white particles 33 are negatively charged.

[0037] In the electrophoretic element 21 having the above structure, when the pixel PX displays black, the pixel electrode PE is held at a relatively high potential higher than that of the common electrode CE. That is, when the potential of the common electrode CE is used as the reference potential, the pixel electrode PE is held at a positive polarity. As a result, the positively charged black particles 32 are attracted to the common electrode CE, while the negatively charged white particles 33 are attracted to the pixel electrode PE. As a result, when the pixel PX is viewed from above the second substrate SUB2, it is visually recognized as black.

[0038] On the other hand, when the pixel PX displays white, the pixel electrode PE is held at a relatively low potential lower than that of the common electrode CE. That is, when the potential of the common electrode CE is used as the reference potential, the pixel electrode PE is held at a negative polarity. As a result, the negatively charged white particles 33 are attracted to the common electrode CE side, while the positively charged black particles 32 are attracted to the pixel electrode PE. As a result, when the pixel PX is observed, it is visually recognized as white.

[0039] It should be noted that the electrophoretic display device described here is not limited to a monochromatic specification, and can also be used in a color specification in which a plurality of color particles including red particles, green particles, and blue particles are actuated by electrophoresis. In particular, in the case of a color specification, there are the following advantages: by applying a high voltage, the originally slow electrophoresis speed can be increased, and high-speed rewriting of a color image can be performed.

[0040] Figure 3 It is a cross-sectional view showing an example of the first transistor TR1.

[0041] The first transistor TR1 is disposed in the peripheral area SA and is included in Figure 1 the gate drivers GD1 and GD2 shown. The first transistor TR1 includes a first gate electrode GE1, a first oxide semiconductor SC1, a first source electrode SE1, and a first drain electrode DE1. In this specification, in the shift register SR, the electrode on the side (input side) electrically connected to the power supply line is referred to as the first source electrode SE1, and the electrode on the side (output side) electrically connected to the gate line GL of the display area DA is referred to as the first drain electrode DE1.

[0042] The first gate electrode GE1 is disposed above the insulating substrate 10. In Figure 3In the example shown, the first gate electrode GE1 is in contact with the insulating substrate 10, but other insulating films may also be interposed between the insulating substrate 10 and the first gate electrode GE1.

[0043] The insulating film 11 is an inorganic insulating film and covers the first gate electrode GE1. Figure 3 In the example shown, the insulating film 11 is a laminate of a thin film 11A and a thin film 11B. The thin film 11A is formed of silicon nitride (SiN) and directly covers the insulating substrate 10 and the first gate electrode GE1. The thin film 11B is formed of silicon oxide (SiO) and is directly laminated on the thin film 11A. For example, the film thickness of the thin film 11B is thinner than that of the thin film 11A. For example, the film thickness of the thin film 11A is 50 to 400 nm, and the film thickness of the thin film 11B is 20 to 300 nm. The film thickness of the insulating film 11 is 300 nm or more. It should be noted that the insulating film 11 may also be a single layer of a thin film formed of silicon oxide.

[0044] The first oxide semiconductor SC1 is disposed above the first gate electrode GE1 and is in contact with the insulating film 11. In other words, the lower surface SCB1 of the first oxide semiconductor SC1 is in contact with the insulating film 11 which is silicon oxide.

[0045] The insulating film 12 directly covers the first oxide semiconductor SC1 and the insulating film 11. The insulating film 12 is an inorganic insulating film formed of silicon oxide (SiO). In other words, the upper surface SCT1 and the side surface SCS1 of the first oxide semiconductor SC1 are in contact with the insulating film 12 which is silicon oxide.

[0046] The first source electrode SE1 and the first drain electrode DE1 are disposed on the insulating film 12 and are in contact with the insulating film 12. In addition, the first source electrode SE1 is separated from the first drain electrode DE1.

[0047] The first source electrode SE1 is in contact with the first oxide semiconductor SC1 in the first opening CH1 of the insulating film 12. The first drain electrode DE1 is in contact with the first oxide semiconductor SC1 in the second opening CH2 of the insulating film 12.

[0048] The insulating film 13 directly covers the first source electrode SE1 and the first drain electrode DE1. The insulating film 13 is, for example, an inorganic insulating film formed of silicon oxide (SiO). In addition, the insulating film 13 is in contact with the insulating film 12 between the first source electrode SE1 and the first drain electrode DE1.

[0049] The first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1 are formed of, for example, metal materials such as aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), silver (Ag), copper (Cu), chromium (Cr), alloys combining these metal materials, etc.

[0050] The first oxide semiconductor SC1 has a first channel region C1, a first low-resistance region LS1, a first low-drainage resistance region LD1, a first source region S1, and a first drain region D1. The first low-resistance region LS1 and the first low-drainage resistance region LD1 are adjacent to the first channel region C1. The first low-resistance region LS1 is located between the first channel region C1 and the first source region S1. The first low-drainage resistance region LD1 is located between the first channel region C1 and the first drain region D1.

[0051] The first channel region C1 is the region with the highest resistance in the first oxide semiconductor SC1 and overlaps the gap between the first source electrode SE1 and the first drain electrode DE1 (or the part where the insulating film 13 is directly laminated on the insulating film 12).

[0052] The first low-resistance region LS1 and the first low-drainage resistance region LD1 are regions with lower resistance than the first channel region C1. The first low-resistance region LS1 is between the first opening CH1 and the second opening CH2 and overlaps the laminate LMS1 of the insulating film 12 and the first source electrode SE1. The first low-drainage resistance region LD1 is between the first opening CH1 and the second opening CH2 and overlaps the laminate LMD1 of the insulating film 12 and the first drain electrode DE1.

[0053] The first source region S1 is a region with lower resistance than the first low-resistance region LS1 and contacts the first source electrode SE1 in the first opening CH1. The first drain region D1 is a region with lower resistance than the first low-drainage resistance region LD1 and contacts the first drain electrode DE1 in the second opening CH2.

[0054] At least the first channel region C1, the first low-resistance region LS1, and the first low-drainage resistance region LD1 in the first oxide semiconductor SC1 are located directly above the first gate electrode GE1. In addition, the laminate LMS1 and the laminate LMD1 are also located directly above the first gate electrode GE1. Figure 3 In the example shown, almost the entire first oxide semiconductor SC1 including the first source region S1 and the first drain region D1 is located directly above the first gate electrode GE1.

[0055] The length L1S of the laminate LMS1 is equal to the length L11S of the first low-resistance region LS1. The length L1D of the laminate LMD1 is equal to the length L11D of the first low-drainage resistance region LD1. In addition, in one example, the length L1S is equal to the length L1D, and the length L11S is equal to the length L11D.

[0056] Among them, depending on the film thickness of the first oxide semiconductor SC1, it is not necessarily limited to the length L1S being equal to the length L11S, nor is it necessarily limited to the length L1D being equal to the length L11D. For example, when the film thickness of the first oxide semiconductor SC1 is 50 nm or less, the length L1S may be greater than the length L11S, and similarly, the length L1D may be greater than the length L11D.

[0057] Figure 4 is a cross-sectional view showing an example of the second transistor TR2. The insulating films 11 to 13 extend not only in Figure 3 the peripheral region SA shown, but also to Figure 4 the display region DA shown.

[0058] The second transistor TR2 is disposed in the display region DA and is included in Figure 1 the pixel PX shown. The second transistor TR2 includes a second gate electrode GE2, a second oxide semiconductor SC2, a second source electrode SE2, and a second drain electrode DE2.

[0059] The second gate electrode GE2 is disposed above the insulating substrate 10 and is on the same plane as the first gate electrode GE1. In Figure 4 the example shown, the second gate electrode GE2 is in contact with the insulating substrate 10, but another insulating film may be interposed between the insulating substrate 10 and the second gate electrode GE2. The second gate electrode GE2 is covered by the insulating film 11.

[0060] The second oxide semiconductor SC2 is disposed above the second gate electrode GE2 and is on the same plane as the first oxide semiconductor SC1. The second oxide semiconductor SC2 is covered by the insulating film 12. In other words, the second oxide semiconductor SC2 is in contact with the insulating film 11 and the insulating film 12, which are silicon oxides.

[0061] The second source electrode SE2 and the second drain electrode DE2 are disposed on the insulating film 12 and are in contact with the insulating film 12. In other words, the second source electrode SE2 and the second drain electrode DE2 are on the same plane as the first source electrode SE1 and the first drain electrode DE1. The second source electrode SE2 is separated from the second drain electrode DE2.

[0062] The second source electrode SE2 is in contact with the second oxide semiconductor SC2 in the third opening CH3 of the insulating film 12. The second drain electrode DE2 is in contact with the second oxide semiconductor SC2 in the fourth opening CH4 of the insulating film 12. The second source electrode SE2 and the second drain electrode DE2 are covered by the insulating film 13. In addition, the insulating film 13 is in contact with the insulating film 12 between the second source electrode SE2 and the second drain electrode DE2.

[0063] The second gate electrode GE2 is formed of the same material as the first gate electrode GE1. The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 are formed of the same material. The second oxide semiconductor SC2 is formed of the same material as the first oxide semiconductor SC1.

[0064] The second oxide semiconductor SC2 has a second channel region C2, second low-resistance regions LS2 and LD2, a second source region S2, and a second drain region D2. The second low-resistance regions LS2 and LD2 are adjacent to the second channel region C2. The second low-resistance region LS2 is located between the second channel region C2 and the second source region S2. The second low-resistance region LD2 is located between the second channel region C2 and the second drain region D2.

[0065] The second channel region C2 is the region with the highest resistance in the second oxide semiconductor SC2 and overlaps the gap between the second source electrode SE2 and the second drain electrode DE2.

[0066] The second low-resistance regions LS2 and LD2 are regions with lower resistance than the second channel region C2. The second low-resistance region LS2 is between the third opening CH3 and the fourth opening CH4 and overlaps the laminate LMS2 of the insulating film 12 and the second source electrode SE2. The second low-resistance region LD2 is between the third opening CH3 and the fourth opening CH4 and overlaps the laminate LMD2 of the insulating film 12 and the second drain electrode DE2.

[0067] The second source region S2 is a region with lower resistance than the second low-resistance region LS2 and is in contact with the second source electrode SE2 in the third opening CH3. The second drain region D2 is a region with lower resistance than the second low-resistance region LD2 and is in contact with the second drain electrode DE2 in the fourth opening CH4.

[0068] At least the second channel region C2, the second low-resistance regions LS2 and LD2 in the second oxide semiconductor SC2 are located directly above the second gate electrode GE2. In addition, the laminate LMS2 and the laminate LMD2 are also located directly above the second gate electrode GE2. In Figure 4 the example shown, almost the entire second oxide semiconductor SC2 including the second source region S2 and the second drain region D2 is located directly above the second gate electrode GE2.

[0069] The length L2S of the laminate LMS2 is equal to the length L21S of the second low-resistance region LS2. The length L2D of the laminate LMD2 is equal to the length L21D of the second low-resistance region LD2. Additionally, in one example, the length L2S is equal to the length L2D, and the length L21S is equal to the length L21D. Here, depending on the film thickness of the second oxide semiconductor SC2, it is not necessarily limited to the length L2S being consistent with the length L21S, and it is not necessarily limited to the length L2D being consistent with the length L21D.

[0070] Here, compare the Figure 3 first transistor TR1 shown with the Figure 4 second transistor TR2 shown.

[0071] The length L1S of the laminate LMS1 is greater than the length L2S of the laminate LMS2 (L1S > L2S). In other words, the length L11S of the first low-resistance region LS1 is greater than the length L21S of the second low-resistance region LS2 (L11S > L21S).

[0072] Additionally, the length L1D of the laminate LMD1 is greater than the length L2D of the laminate LMD2 (L1D > L2D). In other words, the length L11D of the first low-resistance region LD1 is greater than the length L21D of the second low-resistance region LD2 (L11D > L21D).

[0073] In one example, the lengths L1S, L11S, L1D, and L11D are 2 μm or more.

[0074] In this specification, for example, the insulating film 11 corresponds to the first insulating film (or the first inorganic insulating film), the insulating film 12 corresponds to the second insulating film (or the second inorganic insulating film), and the insulating film 13 corresponds to the third insulating film (or the third inorganic insulating film).

[0075] The above-mentioned first transistor TR1 and second transistor TR2 can be manufactured by, for example, the following manufacturing method. Here, only the main processes in the manufacturing method of the first transistor TR1 will be described. It should be noted that the second transistor TR2 is manufactured through the same processes as the first transistor TR1, so the description here is omitted.

[0076] After forming the first oxide semiconductor SC1 on the insulating film 11, the insulating film 12 is formed. After that, after forming the first opening CH1 and the second opening CH2, the first source electrode SE1 and the first drain electrode DE1 are formed. After that, the insulating film 13 is formed. Both the insulating film 12 and the insulating film 13 are silicon oxides.

[0077] Between the first source electrode SE1 and the first drain electrode DE1, oxygen is supplied to the first oxide semiconductor SC1 from the insulating film 13 via the insulating film 12. As a result, the region of the first oxide semiconductor SC1 that overlaps the gap between the first source electrode SE1 and the first drain electrode DE1 is sufficiently oxidized, and the first channel region C1 is formed.

[0078] In the region adjacent to the first channel region C1, the first source electrode SE1 and the first drain electrode DE1 respectively serve as masks, and the amount of oxygen supplied from the insulating film 13 is reduced. Therefore, oxidation of the regions of the first oxide semiconductor SC1 that respectively overlap the first source electrode SE1 and the first drain electrode DE1 can be suppressed, and the first low-resistance region LS1 and the first low-resistance region LD1 having a lower resistance than the first channel region C1 are formed.

[0079] As another manufacturing method, after the first oxide semiconductor SC1 is formed on the insulating film 11, the insulating film 12 is formed. Thereafter, a resist layer having openings in the regions where the first low-resistance region LS1 and the first low-resistance region LD1 should be formed is formed on the insulating film 12. Thereafter, boron (B) or phosphorus (P) is implanted into the first oxide semiconductor SC1 using the resist layer as a mask. As a result, the first low-resistance region LS1 and the first low-resistance region LD1 are formed.

[0080] A transistor having a structure with an oxide semiconductor as a semiconductor (referred to as an oxide semiconductor transistor) has characteristics such as an extremely small off-leakage current. Therefore, the oxide semiconductor transistor can hold the charge written to the pixel capacitor for a long time, can continuously hold the desired voltage, and is applicable as a switching element (second transistor TR2) of the pixel PX.

[0081] On the other hand, as the first transistor TR1 included in the shift register SR of the gate driver GD1 and the gate driver GD2, a high mobility and a high breakdown voltage characteristic are required. For example, in an electrophoretic display device which is an example of the display device DSP, in the first transistor TR1 included in the shift register SR, a high voltage of 70 V or more (±35 V or more) is applied between the source and the drain. Therefore, the first transistor TR1 requires a high breakdown voltage characteristic.

[0082] When the first transistor TR1 is configured to include polysilicon (p-Si) as a semiconductor, it is difficult to obtain a high breakdown voltage characteristic of 70 V or more. In addition, when the first transistor TR1 is configured to include amorphous silicon (a-Si) as a semiconductor, it is difficult to achieve the required mobility.

[0083] Therefore, in the present embodiment, an oxide semiconductor transistor is applied as the first transistor TR1. And, in the first transistor TR1, a first low-resistance region LS1 and a first low-resistance region LD1 larger than the second low-resistance region LS2 and the second low-resistance region LD2 of the second transistor TR2 are provided. Therefore, the first transistor TR1 can obtain a breakdown voltage characteristic higher than that of the second transistor TR2 with respect to a high voltage that can be applied between the source and the drain.

[0084] As an example, when a high voltage of 70 V or more (±35 V or more) is applied between the source and the drain, it is preferable that the length of each of the first low-resistance region LS1 and the first low-resistance region LD1 is 2 μm or more. Here, the lower limit of the length required for each of the first low-resistance region LS1 and the first low-resistance region LD1 varies depending on the magnitude of the voltage applied between the source and the drain, and it may be allowed even if it is less than 2 μm.

[0085] In addition, in the present embodiment, the first transistor TR1 has a bottom gate structure in which a first gate electrode GE1 is provided between the first oxide semiconductor SC1 and the insulating substrate 10. Further, the first low-resistance region LS1 and the first low-resistance region LD1 are located directly above the first gate electrode GE1. And, the insulating film 11 sandwiched between the first gate electrode GE1 and the first oxide semiconductor SC1 has a film thickness of 300 nm or more. Therefore, the first transistor TR1 can obtain a high breakdown voltage characteristic with respect to a high voltage that can be applied to the first gate electrode GE1.

[0086] According to such a present embodiment, the gate driver GD1 and the gate driver GD2 can be configured using the first transistor TR1 including the first oxide semiconductor SC1. Thereby, as the gate driver, the area of the peripheral region SA can be reduced as compared with the structure in which an IC chip is mounted. Therefore, the display device DSP can be miniaturized. In addition, the number of mounted IC chips can be reduced, and the cost can be reduced.

[0087] In this way, miniaturization and low cost of the display device DSP can be achieved, and thus application of the display device DSP described in the present embodiment to a personal terminal can be achieved.

[0088] Next, the inventors conducted a reliability test related to the first transistor TR1. The conditions for applying stress to the first transistor TR1 were as follows. The voltage applied to the first gate electrode GE1 was 40 V, the voltage applied between the first source electrode SE1 and the first drain electrode DE1 was ±38 V, and the voltage was continuously applied for 1000 sec in an environment of 60°C.

[0089] In the reliability test, the Vg-Id characteristics in the initial state before applying stress were compared with the Vg-Id characteristics after applying stress. It should be noted that Vg is the voltage (V) applied to the first gate electrode GE1, and Id is the current (A) output from the first drain electrode DE1. With the voltage Vg as the horizontal axis and the current Id as the vertical axis, the results of the reliability test were plotted on a coordinate graph.

[0090] As the Vg-Id characteristics, cases where the voltage between the source and drain was set to 0.1V (A), 10V (B), and 20V (C) were plotted on the coordinate graph before and after applying stress, respectively.

[0091] Figure 5 It is a graph showing the results of the reliability test of the first transistor TR1 related to the comparative example. In the first transistor TR1 related to the comparative example, the lengths of the first low-resistance region LS1 and the first low-resistance region LD1 were each 1.5μm.

[0092] When comparing the Vg-Id characteristics before and after applying stress, it was confirmed that the gate voltage (threshold voltage) for outputting the drain current shifted significantly.

[0093] Figure 6 It is a graph showing the results of the reliability test of the first transistor TR1 related to the present embodiment. In the first transistor TR1 related to the present embodiment, the lengths of the first low-resistance region LS1 and the first low-resistance region LD1 were each 2μm.

[0094] When comparing the Vg-Id characteristics before and after applying stress, it was confirmed that the gate voltage (threshold voltage) for outputting the drain current hardly shifted. In other words, according to the first transistor TR1 related to the present embodiment, even after applying a high voltage of 70V or more between the source and drain for a long time or repeatedly, the threshold hardly changes, and high reliability is obtained.

[0095] As described above, according to the present embodiment, a display device that can be miniaturized can be provided.

[0096] It should be noted that the present invention is not limited to the above-described embodiment itself, and the constituent elements can be modified and embodied within the scope of not departing from the gist thereof at the stage of its implementation. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above-described embodiment. For example, several structural elements can also be deleted from all the constituent elements shown in the embodiment. Moreover, constituent elements from different embodiments can be appropriately combined.

[0097] In addition, in the present embodiment, an electrophoretic display device that requires a high driving voltage has been described. However, the present invention can also be applied to polymer-dispersed liquid crystals and high-speed driving displays using the same as liquid crystal displays that require an applied voltage higher than that of ordinary liquid crystal displays and liquid crystal displays for high-speed response.

Claims

1. A display device, characterized in that, Comprising: An insulating substrate; A first gate electrode disposed in a peripheral region above the insulating substrate and included in a gate driver; A second gate electrode disposed in a display region above the insulating substrate and integral with a gate line driven by the gate driver; A first insulating film covering the first gate electrode and the second gate electrode; A first oxide semiconductor disposed above the first gate electrode and in contact with the first insulating film; A second oxide semiconductor disposed above the second gate electrode and in contact with the first insulating film; A second insulating film covering the first oxide semiconductor and the second oxide semiconductor; A first source electrode in contact with the second insulating film and in contact with the first oxide semiconductor at a first opening of the second insulating film; A first drain electrode in contact with the second insulating film and in contact with the first oxide semiconductor at a second opening of the second insulating film; A second source electrode in contact with the second insulating film and in contact with the second oxide semiconductor at a third opening of the second insulating film; And A second drain electrode in contact with the second insulating film and in contact with the second oxide semiconductor at a fourth opening of the second insulating film, When oxygen is supplied to the first oxide semiconductor and the second oxide semiconductor via the second insulating film, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode respectively serve as masks, The length of the laminate of the second insulating film and the first source electrode between the first opening and the second opening is greater than the length of the laminate of the second insulating film and the second source electrode between the third opening and the fourth opening, The length of the laminate of the second insulating film and the first drain electrode between the first opening and the second opening is greater than the length of the laminate of the second insulating film and the second drain electrode between the third opening and the fourth opening, The first oxide semiconductor has: A first channel region overlapping the gap between the first source electrode and the first drain electrode; and A first low-resistance region overlapping the laminate of the second insulating film and the first source electrode and the laminate of the second insulating film and the first drain electrode, and having a lower resistance than the first channel region, The second oxide semiconductor has: A second channel region overlapping the gap between the second source electrode and the second drain electrode; and A second low-resistance region overlapping the laminate of the second insulating film and the second source electrode and the laminate of the second insulating film and the second drain electrode, and having a lower resistance than the second channel region.

2. The display device according to claim 1, characterized in that, The length of the laminate of the second insulating film and the first source electrode, and the length of the laminate of the second insulating film and the first drain electrode are 2 μm or more.

3. The display device according to claim 1, characterized in that, The first oxide semiconductor and the second oxide semiconductor are located on the same plane, The laminate of the second insulating film and the first source electrode, and the laminate of the second insulating film and the first drain electrode are located directly above the first gate electrode, The laminate of the second insulating film and the second source electrode, and the laminate of the second insulating film and the second drain electrode are located directly above the second gate electrode.

4. The display device according to any one of claims 1 to 3, characterized in that, The display device further includes a third insulating film that contacts the second insulating film between the first source electrode and the first drain electrode. The third insulating film is formed of silicon oxide.

5. The display device according to any one of claims 1 to 3, characterized in that, The thickness of the first insulating film sandwiched between the first gate electrode and the first oxide semiconductor is 300 nm or more.

6. A display device, characterized in that, Comprising: An insulating substrate; A first gate electrode disposed in a peripheral region above the insulating substrate and included in a gate driver; A second gate electrode disposed in a display region above the insulating substrate and integrated with a gate line driven by the gate driver; A first insulating film covering the first gate electrode and the second gate electrode; A first oxide semiconductor disposed above the first gate electrode and in contact with the first insulating film; And A second oxide semiconductor disposed above the second gate electrode and in contact with the first insulating film. The first oxide semiconductor has: a first source region; a first drain region; a first channel region; and a first low-resistance region adjacent to the first channel region and having a lower resistance than the first channel region. The second oxide semiconductor has: a second source region; a second drain region; a second channel region; and a second low-resistance region adjacent to the second channel region and having a lower resistance than the second channel region. The first low-resistance region has a low-resistance region between the first channel region and the first source region and a low-resistance region between the first channel region and the first drain region. The second low-resistance region has a low-resistance region between the second channel region and the second source region and a low-resistance region between the second channel region and the second drain region. The length of the first low-resistance region is greater than the length of the second low-resistance region.

7. The display device according to claim 6, wherein, The length of the first low-resistance region is 2 μm or more.

8. The display device according to claim 6, wherein, The first oxide semiconductor and the second oxide semiconductor are located on the same plane. The first low-resistance region is located directly above the first gate electrode. The second low-resistance region is located directly above the second gate electrode.

9. The display device according to any one of claims 6 to 8, wherein, The thickness of the first insulating film sandwiched between the first gate electrode and the first oxide semiconductor is 300 nm or more.

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