Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, including: a substrate, the substrate having a fin on the substrate; an isolation layer on the substrate; a gate structure on the substrate, the gate structure crossing over the fin; a second source-drain opening in the fin on both sides of the gate structure, the second source-drain opening including a first region and a second region on the first region, the first region having a first dimension in a second direction, the second region having a second dimension in the second direction, the first dimension being greater than the second dimension. By exposing more of the second source-drain opening through the isolation layer, the restriction of the isolation layer on the subsequent source-drain doping layer formed by epitaxial growth is reduced, so that the volume of the source-drain doping layer is increased. By the first dimension being greater than the second dimension, the distance between the source-drain doping layer formed in the first region and the channel region is reduced, so that the source-drain doping layer provides greater stress to the channel region, thereby improving the mobility of the carriers in the channel region and improving the performance of the final semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] MOS (Metal-Oxide-Semiconductor) transistors are among the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure comprising: a gate dielectric layer on the surface of the semiconductor substrate and a gate electrode layer on the surface of the gate dielectric layer; and source / drain doped regions located in the semiconductor substrate on both sides of the gate structure.

[0003] With the development of semiconductor technology, the traditional planar MOS transistor has become less able to control the channel current, resulting in severe leakage current. Fin field-effect transistors (Fin FETs) are a new type of multi-gate device. They generally include fins protruding from the surface of a semiconductor substrate, a gate structure covering part of the top surface and sidewalls of the fins, and source / drain doped regions located in the fins on both sides of the gate structure.

[0004] However, the performance of semiconductor devices composed of fin field-effect transistors in the existing technology still needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the final semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate having a plurality of fins arranged parallel to each other along a first direction, the fins extending along a second direction perpendicular to the second direction; an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the fins, and the top surface of the isolation layer being lower than the top surface of the fins; a gate structure on the substrate, the gate structure spanning the fins along the first direction; and second source / drain openings located within the fins on both sides of the gate structure, the second source / drain openings comprising a first region and a second region located on the first region, the first region having a first dimension along the second direction, the second region having a second dimension along the second direction, the first dimension being larger than the second dimension.

[0007] Optionally, it also includes an insulating layer located on the bottom surface of the second source / drain opening.

[0008] Optionally, the insulating layer may be made of silicon oxide.

[0009] Optionally, the bottom surface of the second source drain opening is higher than the top surface of the isolation layer.

[0010] Optionally, it may also include: a source / drain doped layer located within the second source / drain opening, the source / drain doped layer having source / drain ions.

[0011] Optionally, the source / drain ions include N-type ions or P-type ions.

[0012] Optionally, it may also include: a dielectric layer located on the substrate, the dielectric layer covering the sidewalls of the gate structure.

[0013] Optionally, the thickness of the isolation layer is less than 10 angstroms.

[0014] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate having a plurality of fins arranged parallel to each other along a first direction, the fins extending along a second direction, the first direction being perpendicular to the second direction; forming an initial isolation layer on the substrate, the initial isolation layer covering a portion of the sidewalls of the fins, and the top surface of the initial isolation layer being lower than the top surface of the fins; forming a plurality of gate structures on the substrate, the gate structures spanning the fins along the first direction; forming initial source / drain openings in the fins on both sides of the gate structures, the bottom surface of the initial source / drain openings being lower than the top surface of the initial isolation layer; expanding the sidewalls of the initial source / drain openings to form a first source / drain opening, the first source / drain opening including a first region and a second region located on the first region, the first region having a first dimension along the second direction, the second region having a second dimension along the second direction, the first dimension being larger than the second dimension; and etching back the initial isolation layer using a first etching process to form an isolation layer, the thickness of the isolation layer being smaller than the thickness of the initial isolation layer.

[0015] Optionally, before forming the first source-drain opening, the method further includes forming a protective layer on the bottom surface of the initial source-drain opening.

[0016] Optionally, the material of the protective layer includes silicon nitride.

[0017] Optionally, the method for forming the protective layer includes: performing a first oxidation treatment on the fin exposed at the bottom of the initial source drain opening to form the protective layer.

[0018] Optionally, the parameters of the first oxidation treatment include: the oxidizing gas includes oxygen, and the oxidation time is 10 seconds to 300 seconds.

[0019] Optionally, during the process of etching back the initial isolation layer, the process further includes: the first etching process also removes the protective layer and a portion of the fins exposed by the first source / drain opening to form a second source / drain opening.

[0020] Optionally, the bottom surface of the second source drain opening is higher than the top surface of the isolation layer.

[0021] Optionally, the thickness of the isolation layer is less than 10 angstroms.

[0022] Optionally, the first etching process employs an asynchronous pulse etching process, the parameters of which include: the reaction gases used include CH3F, CH4, and He, wherein the flow rate of CH3F is 5 standard milliliters / minute to 100 standard milliliters / minute, the flow rate of CH4 is 5 standard milliliters / minute to 200 standard milliliters / minute, and the flow rate of He is 100 standard milliliters / minute to 1000 standard milliliters / minute.

[0023] Optionally, after forming the second source-drain opening, the method further includes forming an insulating layer on the bottom surface of the second source-drain opening.

[0024] Optionally, the insulating layer may be made of silicon oxide.

[0025] Optionally, the method for forming the insulating layer includes: performing a second oxidation treatment on the fin exposed by the second source drain opening to form the insulating layer.

[0026] Optionally, the parameters of the second oxidation treatment include: the oxidizing gas includes oxygen, and the oxidation time is 10 seconds to 600 seconds.

[0027] Optionally, the expansion process includes a dry etching process.

[0028] Optionally, the parameters of the dry etching process include: the etching gases used include NF3, Cl2, H2, He and N2, wherein the flow rates of NF3, Cl2 and H2 are 5 standard milliliters / minute to 500 standard milliliters / minute, and the flow rates of He and N2 are 100 standard milliliters / minute to 1000 standard milliliters / minute, respectively.

[0029] Optionally, before forming the gate structure, the method further includes forming a plurality of dummy gate structures on the substrate, the dummy gate structures extending across the fin along the first direction.

[0030] Optionally, the method for forming the initial source / drain opening includes: etching the fin using the pseudo-gate structure as a mask to form the initial source / drain opening within the fin.

[0031] Optionally, after forming the second source / drain opening, the method further includes: forming a source / drain doped layer within the second source / drain opening, wherein the source / drain doped layer contains source / drain ions.

[0032] Optionally, the source / drain ions include N-type ions or P-type ions.

[0033] Optionally, the method for forming the source / drain doped layer includes: forming an epitaxial layer in the second source / drain opening using an epitaxial growth process; and, during the epitaxial growth process, incorporating the source / drain ions into the epitaxial layer using an in-situ doping process to form the source / drain doped layer.

[0034] Optionally, after forming the source / drain doped layers, the method further includes forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the dummy gate structure.

[0035] Optionally, the method for forming the gate structure includes: removing the dummy gate structure and forming a gate opening in the dielectric layer; forming a gate structure in the gate opening.

[0036] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0037] In the structure of this invention, an isolation layer is located on the substrate, covering part of the sidewalls of the fin, and the top surface of the isolation layer is lower than the top surface of the fin. This exposes more second source / drain openings in the isolation layer, thereby reducing the restriction imposed by the isolation layer on the subsequent source / drain doped layers formed by epitaxial growth, and increasing the volume of the source / drain doped layers. As the volume of the source / drain doped layers increases, the corresponding dose of source / drain ions incorporated into the doped layers also increases, thereby increasing the current between the source / drain doped layers and improving the performance of the final semiconductor structure.

[0038] The second source / drain openings are located within the fins on both sides of the gate structure. The bottom surface of the second source / drain opening is higher than the top surface of the isolation layer. The second source / drain opening includes a first region and a second region located on the first region. The first region has a first dimension along the second direction, and the second region has a second dimension along the second direction, where the first dimension is larger than the second dimension. This reduces the distance between the source / drain doped layer formed in the first region and the channel region. The source / drain doped layer can provide greater stress to the channel region, thereby increasing the carrier mobility in the channel region and improving the performance of the final semiconductor structure.

[0039] Furthermore, it also includes an insulating layer located on the bottom surface of the second source / drain opening. By forming an insulating layer on the bottom surface of the second source / drain opening, leakage current problems between the source / drain doped layer and the substrate can be effectively reduced, thereby improving the performance of the finally formed semiconductor structure.

[0040] In the method for forming the technical solution of this invention, a first etching process is used to remove part of the initial isolation layer to form an isolation layer, wherein the bottom surface of the second source / drain opening is higher than the top surface of the isolation layer. This exposes more of the second source / drain openings in the isolation layer, thereby reducing the restriction of the isolation layer on the subsequent source / drain doped layers formed by epitaxial growth, and increasing the volume of the source / drain doped layers. When the volume of the source / drain doped layers increases, the corresponding dose of source / drain ions incorporated into the source / drain doped layers also increases, thereby increasing the current between the source / drain doped layers and improving the performance of the final semiconductor structure.

[0041] Furthermore, the sidewalls of the initial source / drain opening are expanded to form a first source / drain opening. This first source / drain opening includes a first region and a second region located on the first region. The first region has a first dimension along the second direction, and the second region has a second dimension along the second direction, where the first dimension is larger than the second dimension. This reduces the distance between the source / drain doped layer formed in the first region and the channel region. The source / drain doped layer can provide greater stress to the channel region, thereby increasing the carrier mobility in the channel region and ultimately improving the performance of the final semiconductor structure.

[0042] Furthermore, before forming the first source / drain opening, a protective layer is formed on the bottom surface of the initial source / drain opening. This protective layer prevents damage to the bottom of the initial source / drain opening during the expansion process, increases the spacing between the subsequently formed second source / drain opening and the substrate, and reduces the risk of leakage between the subsequently formed source / drain doped layer and the substrate.

[0043] Furthermore, after forming the second source / drain opening, the method further includes forming an insulating layer on the bottom surface of the second source / drain opening. By forming an insulating layer on the bottom surface of the second source / drain opening, leakage current between the source / drain doped layer and the substrate can be effectively reduced, thereby improving the performance of the final semiconductor structure. Attached Figure Description

[0044] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure.

[0045] Figures 3 to 15 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0046] As described in the background section, the performance of semiconductor devices constructed from fin field-effect transistors in the prior art still needs improvement. The following will provide a detailed explanation in conjunction with the accompanying drawings.

[0047] Please refer to Figure 1 and Figure 2 , Figure 1 This is a top view of the semiconductor structure. Figure 2 yes Figure 1 A schematic cross-sectional view along line AA shows a substrate 100 with a plurality of fins 101 arranged parallel to a first direction X and extending along a second direction Y, the first direction X being perpendicular to the second direction Y. An isolation layer 102 is formed on the substrate 100, covering part of the sidewalls of the fins 101, with the top surface of the isolation layer 102 being lower than the top surface of the fins 101. A plurality of gate structures 103 are formed on the substrate 100, the gate structures 103 spanning across the fins 101 along the first direction X. Source / drain openings 104 are formed in the fins 101 on both sides of the gate structures 103, with the bottom surface of the source / drain openings 104 being lower than the top surface of the isolation layer 102.

[0048] In this embodiment, since the bottom surface of the source / drain opening 104 is lower than the top surface of the isolation layer 102, the isolation layer 102 will restrict the growth of the source / drain doped layer when it is subsequently formed within the source / drain opening 104, resulting in a smaller volume of the final source / drain doped layer. When the volume of the source / drain doped layer is small, the amount of source / drain ions in the doped layer is also small, resulting in a smaller current between the source / drain doped layers, which reduces the performance of the final semiconductor structure.

[0049] In addition, due to the limitations of the manufacturing process, during the etching process to form the gate structure, as the etching depth increases, more etching solution will accumulate. Therefore, the gate structure at the bottom will be etched more, resulting in the bottom dimension of the gate structure being smaller than the top dimension. The bottom cross-section of the gate structure 103 formed along the second direction Y presents an inverted trapezoidal structure, which in turn causes the channel region A formed by the fin 101 covered by the gate structure 103 to also form an inverted trapezoidal structure.

[0050] To achieve a better morphology for the source / drain doped layer, the source / drain opening 104 is etched into a "U" shape during fabrication. When the source / drain opening 104 is "U" shaped, the distance d1 between the top edge of the source / drain opening 104 and the corresponding edge of the channel region A is smaller than the distance d2 between the bottom edge of the source / drain opening 104 and the corresponding edge of the channel region A. This results in a smaller compressive stress exerted on the channel region A by the source / drain doped layer at the bottom of the source / drain opening 104. For a PMOS transistor structure, a smaller compressive stress on the channel region A reduces the carrier mobility in the channel region A, thereby affecting the performance of the final semiconductor structure.

[0051] Based on this, the present invention provides a semiconductor structure and its formation method. By etching back the initial isolation layer to form an isolation layer, more second source / drain openings are subsequently exposed in the isolation layer. This reduces the restriction imposed by the isolation layer on the subsequent source / drain doped layers formed by epitaxial growth, allowing the volume of the source / drain doped layers to increase. Furthermore, the sidewalls of the initial source / drain openings are expanded, reducing the distance between the source / drain doped layers formed in the first region and the channel region. The source / drain doped layers provide greater stress to the channel region, increasing the carrier mobility in the channel region and thus improving the performance of the final semiconductor structure.

[0052] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0053] Figures 3 to 15 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0054] Please refer to Figure 3 and Figure 4 , Figure 3 This is a top view of the semiconductor structure. Figure 4 yes Figure 3 A schematic cross-sectional view along the BB line shows a substrate 200 having a plurality of fins 201 arranged in parallel along a first direction X, the fins 201 extending along a second direction Y, the first direction X being perpendicular to the second direction Y.

[0055] In this embodiment, the method for forming the substrate 200 and the fin 201 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, the patterned layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form the substrate 200 and the fin 201; and removing the patterned layer after forming the substrate 200 and the fin 201.

[0056] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0057] In this embodiment, the fin 201 is made of silicon; in other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0058] Please refer to Figure 5 , Figure 5 and Figure 4 With the view orientation consistent, an initial isolation layer 202 is formed on the substrate 200, the initial isolation layer 202 covers part of the sidewall of the fin 201, and the top surface of the initial isolation layer 202 is lower than the top surface of the fin 201.

[0059] In this embodiment, the method for forming the initial isolation layer 202 includes: forming an isolation material layer (not shown) on the substrate 200, the isolation material layer covering the sidewall of the fin 201; removing a portion of the isolation material layer to form the initial isolation layer 202, the top surface of the initial isolation layer 202 being lower than the top surface of the fin 201.

[0060] The initial isolation layer is made of an insulating material, including silicon oxide, silicon nitride, or silicon oxynitride; in this embodiment, the initial isolation layer 202 is made of silicon oxide.

[0061] After forming the initial isolation layer 202, the process further includes: forming a plurality of gate structures on the substrate 200, the gate structures spanning the fin 201 along the first direction X. For details of the formation process, please refer to [link / reference needed]. Figures 6 to 15 .

[0062] Please refer to Figure 6 and Figure 7 , Figure 6 This is a top view of the semiconductor structure. Figure 7 yes Figure 6 A cross-sectional view along the CC line shows that several pseudo-gate structures 203 are formed on the substrate 200, and the pseudo-gate structures 203 span the fin 201 along the first direction X.

[0063] In this embodiment, the pseudo-gate structure 203 includes: a pseudo-gate dielectric layer, which covers part of the sidewall and top surface of the fin 201, a pseudo-gate layer located on the pseudo-gate dielectric layer, and a sidewall (not shown) located on the pseudo-gate dielectric layer and the sidewall of the pseudo-gate layer.

[0064] In this embodiment, the dummy gate dielectric layer is made of silicon oxide; in other embodiments, the dummy gate dielectric layer may also be made of silicon oxynitride.

[0065] In this embodiment, the pseudo-gate layer is made of polycrystalline silicon.

[0066] In this embodiment, the sidewall is made of silicon nitride.

[0067] In this embodiment, the method for forming the sidewall includes: forming a sidewall material layer (not shown) on the sidewall surfaces of the pseudo-gate dielectric layer, the pseudo-gate layer, and the pseudo-gate layer, as well as on the top surface of the pseudo-gate layer and the initial isolation layer; and etching the sidewall material layer back until the top surface of the pseudo-gate layer and the initial isolation layer is exposed to form the sidewall.

[0068] In this embodiment, the process for forming the sidewall material layer includes atomic layer deposition.

[0069] Please refer to Figure 8 , Figure 8 and Figure 7 With the view direction consistent, the fin 201 is etched using the pseudo-gate structure 203 as a mask, and the initial source-drain opening 204 is formed in the fin 201.

[0070] In this embodiment, the bottom surface of the initial source / drain opening 204 is lower than the top surface of the initial isolation layer 202.

[0071] Please refer to Figure 9 A protective layer 205 is formed on the bottom surface of the initial source drain opening 204.

[0072] In this embodiment, the protective layer 205 prevents damage to the bottom of the initial source / drain opening 204 during subsequent expansion processing, increases the spacing between the subsequently formed second source / drain opening and the substrate 200, and reduces the leakage problem between the subsequently formed source / drain doped layer and the substrate 200.

[0073] In this embodiment, the material of the protective layer 205 includes silicon nitride.

[0074] In this embodiment, the method for forming the protective layer 205 includes: performing a first oxidation treatment on the fin 201 exposed at the bottom of the initial source drain opening 204 to form the protective layer 205.

[0075] In this embodiment, the parameters of the first oxidation treatment include: the oxidizing gas includes oxygen, and the oxidation time is 10 seconds to 300 seconds.

[0076] Please refer to Figure 10After the protective layer 205 is formed, the sidewall of the initial source drain opening 204 is expanded to form a first source drain opening 206. The first source drain opening 206 includes a first region I and a second region II located on the first region I. The first region I has a first dimension D1 along the second direction Y, and the second region II has a second dimension D2 along the second direction Y. The first dimension D1 is larger than the second dimension D2.

[0077] In this embodiment, by expanding the initial source / drain opening 204, the distance between the source / drain doped layer formed in the first region I and the channel region is reduced. The source / drain doped layer can provide greater stress to the channel region, thereby increasing the mobility of charge carriers in the channel region and improving the performance of the final semiconductor structure.

[0078] In this embodiment, the expansion process includes a dry etching process.

[0079] In this embodiment, the parameters of the dry etching process include: the etching gases used include NF3, Cl2, H2, He, and N2, wherein the flow rates of NF3, Cl2, and H2 are 5 standard milliliters / minute to 500 standard milliliters / minute, and the flow rates of He and N2 are 100 standard milliliters / minute to 1000 standard milliliters / minute, respectively. In the dry etching process, the NF3 and Cl2 gases can etch the sidewalls of the first region I along the second direction Y, thereby making the first dimension D1 larger than the second dimension D2.

[0080] Please refer to Figure 11 After the first source drain opening 206 is formed, the initial isolation layer 202 is etched back using the first etching process to form an isolation layer 207, the thickness of which is less than the thickness of the initial isolation layer 202.

[0081] In this embodiment, the first etching process adopts an asynchronous pulse etching process. The parameters of the asynchronous pulse etching process include: the reaction gases used include CH3F, CH4 and He, wherein the flow rate of CH3F is 5 standard ml / min to 100 standard ml / min, the flow rate of CH4 is 5 standard ml / min to 200 standard ml / min, and the flow rate of He is 100 standard ml / min to 1000 standard ml / min.

[0082] In this embodiment, during the process of etching back the initial isolation layer 202, the process further includes: the first etching process removing the protective layer 205 and a portion of the fin 201 exposed by the first source / drain opening 206 to form a second source / drain opening 208.

[0083] Since the first etching process is mainly used to etch back the initial isolation layer 202, the etching rate of the protective layer 205 and the fin 201 is relatively small, so that the bottom surface of the finally formed second source drain opening 208 is higher than the top surface of the isolation layer 207.

[0084] In this embodiment, a portion of the initial isolation layer 202 is removed using a first etching process to form an isolation layer 207, wherein the bottom surface of the second source / drain opening 208 is higher than the top surface of the isolation layer 207. This exposes more of the second source / drain opening 208 in the isolation layer, thereby reducing the restriction imposed by the isolation layer 207 on the subsequent source / drain doped layers formed by epitaxial growth, and increasing the volume of the source / drain doped layers. As the volume of the source / drain doped layers increases, the corresponding dose of source / drain ions incorporated into the doped layers also increases, thereby increasing the current between the source / drain doped layers and improving the performance of the final semiconductor structure.

[0085] In this embodiment, the thickness of the isolation layer 207 is less than 10 angstroms.

[0086] Please refer to Figure 12 After the second source-drain opening 208 is formed, an insulating layer 209 is formed on the bottom surface of the second source-drain opening 208.

[0087] In this embodiment, by forming an insulating layer 209 on the bottom surface of the second source / drain opening 208, the leakage problem between the subsequently formed source / drain doped layer and the substrate 200 can be effectively reduced, thereby improving the performance of the final semiconductor structure.

[0088] In this embodiment, the insulating layer 209 is made of silicon oxide.

[0089] In this embodiment, the method for forming the insulating layer 209 includes: performing a second oxidation treatment on the fin portion 201 exposed by the second source drain opening 208 to form the insulating layer 209.

[0090] In this embodiment, the parameters of the second oxidation treatment include: the oxidizing gas includes oxygen, and the oxidation time is 10 seconds to 600 seconds.

[0091] Please refer to Figure 13 After the second source / drain opening 208 is formed, a source / drain doped layer 210 is formed within the second source / drain opening 208, and the source / drain doped layer 210 contains source / drain ions.

[0092] The source / drain ions include N-type ions or P-type ions. In this embodiment, the source / drain ions are P-type ions.

[0093] In this embodiment, the method for forming the source / drain doped layer 210 includes: forming an epitaxial layer (not shown) in the second source / drain opening 208 using an epitaxial growth process; and, during the epitaxial growth process, in-situ doping of the source / drain ions into the epitaxial layer to form the source / drain doped layer 210.

[0094] Please refer to Figure 14 After forming the source / drain doped layer 210, a dielectric layer 211 is formed on the substrate 200, the dielectric layer 211 covering the sidewalls of the pseudo-gate structure 203.

[0095] In this embodiment, the dielectric layer 211 is made of silicon oxide; in other embodiments, the dielectric layer may also be made of low-K dielectric material (low-K dielectric material refers to dielectric material with a relative permittivity of less than 3.9) or ultra-low-K dielectric material (ultra-low-K dielectric material refers to dielectric material with a relative permittivity of less than 2.5).

[0096] Please refer to Figure 15 After forming the dielectric layer 211, the dummy gate structure 203 is removed, and a gate opening is formed in the dielectric layer 211; a gate structure 212 is formed in the gate opening.

[0097] In this embodiment, the gate structure 212 includes: a gate dielectric layer and a gate layer (not shown) located on the gate dielectric layer.

[0098] In this embodiment, the material of the gate dielectric layer includes a high-k dielectric material.

[0099] The gate layer is made of a metal, including tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the gate layer is made of tungsten.

[0100] Accordingly, this invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 15The device includes: a substrate 200 having a plurality of fins 201 arranged parallel to each other along a first direction X, the fins 201 extending along a second direction Y, the first direction X being perpendicular to the second direction Y; an isolation layer 207 located on the substrate 200, the isolation layer 207 covering a portion of the sidewalls of the fins 201, and the top surface of the isolation layer 207 being lower than the top surface of the fins 201; a gate structure 212 located on the substrate 200, the gate structure 212 spanning across the fins 201 along the first direction X; and second source / drain openings 208 located in the fins 201 on both sides of the gate structure 212, the second source / drain openings 208 including a first region I and a second region II located on the first region I, the first region I having a first dimension D1 along the second direction Y, the second region II having a second dimension D2 along the second direction Y, the first dimension D1 being larger than the second dimension D2.

[0101] In this embodiment, an isolation layer 207 is located on the substrate 200. The isolation layer 207 covers part of the sidewall of the fin 201, and the top surface of the isolation layer 207 is lower than the top surface of the fin 201. This exposes more second source / drain openings 208 in the isolation layer 207, thereby reducing the restriction imposed by the isolation layer 207 on the subsequent source / drain doped layer 210 formed by epitaxial growth, and increasing the volume of the source / drain doped layer 210. When the volume of the source / drain doped layer 210 increases, the corresponding dose of source / drain ions incorporated into the source / drain doped layer 210 also increases, thereby increasing the current between the source / drain doped layers 210 and improving the performance of the final semiconductor structure.

[0102] Additionally, a second source / drain opening 208 is located within the fins 201 on both sides of the gate structure 212. The bottom surface of the second source / drain opening 208 is higher than the top surface of the isolation layer 207. The second source / drain opening 208 includes a first region I and a second region II located on the first region I. The first region I has a first dimension D1 along the second direction Y, and the second region II has a second dimension D2 along the second direction Y. The first dimension D1 is larger than the second dimension D2. This reduces the distance between the source / drain doped layer 210 formed in the first region I and the channel region. The source / drain doped layer 210 can provide greater stress to the channel region, thereby increasing the carrier mobility in the channel region and improving the performance of the final semiconductor structure.

[0103] In this embodiment, an insulating layer 209 is also included, located on the bottom surface of the second source / drain opening 208. By forming the insulating layer 209 on the bottom surface of the second source / drain opening 208, leakage current between the source / drain doped layer 210 and the substrate 200 can be effectively reduced, thereby improving the performance of the final semiconductor structure.

[0104] In this embodiment, the insulating layer 209 is made of silicon oxide.

[0105] In this embodiment, the bottom surface of the second source drain opening 208 is higher than the top surface of the isolation layer 207.

[0106] In this embodiment, it further includes a source / drain doped layer 210 located within the second source / drain opening 208, wherein the source / drain doped layer 210 contains source / drain ions.

[0107] In this embodiment, the source / drain ions include N-type ions or P-type ions.

[0108] In this embodiment, a dielectric layer 211 is also included, located on the substrate 200, the dielectric layer 211 covering the sidewall of the gate structure 212.

[0109] In this embodiment, the thickness of the isolation layer 207 is less than 10 angstroms.

[0110] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a plurality of fins arranged in parallel along a first direction, the fins extending along a second direction, the first direction being perpendicular to the second direction; An initial isolation layer is formed on the substrate, the initial isolation layer covering a portion of the sidewall of the fin, and the top surface of the initial isolation layer is lower than the top surface of the fin; A plurality of gate structures are formed on the substrate, the gate structures extending across the fin along the first direction; Initial source / drain openings are formed in the fins on both sides of the gate structure, and the bottom surface of the initial source / drain openings is lower than the top surface of the initial isolation layer; The sidewall of the initial source-drain opening is expanded to form a first source-drain opening. The first source-drain opening includes a first region and a second region located on the first region. The first region has a first dimension along the second direction, and the second region has a second dimension along the second direction. The first dimension is larger than the second dimension. The initial isolation layer is etched back using a first etching process to form an isolation layer, the thickness of which is less than the thickness of the initial isolation layer; wherein... The bottom cross-section of the gate structure formed along the second direction presents an inverted trapezoidal structure, and the gate structure covering the channel region formed by the fins also presents an inverted trapezoidal structure. As the depth of the first region increases, the first dimension gradually increases, and the trend of the sidewall of the first region tends to be consistent with the trend of the sidewall of the channel region. This reduces the distance between the source / drain doped layer and the channel region located in the first region, allowing the source / drain doped layer to provide greater stress to the channel region and improve the carrier mobility in the channel region. Before forming the first source-drain opening, a protective layer is formed on the bottom surface of the initial source-drain opening; During the process of etching back the initial isolation layer, the first etching process also removes the protective layer and a portion of the fins exposed by the first source / drain opening, forming a second source / drain opening.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes silicon nitride.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the protective layer includes: performing a first oxidation treatment on the fin exposed at the bottom of the initial source drain opening to form the protective layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The parameters of the first oxidation treatment include: the oxidizing gas includes oxygen, and the oxidation time is 10 seconds to 300 seconds.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The bottom surface of the second source drain opening is higher than the top surface of the isolation layer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the isolation layer is less than 10 angstroms.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first etching process employs an asynchronous pulse etching process. The parameters of the asynchronous pulse etching process include: the reaction gases used include CH3F, CH4, and He, wherein the flow rate of CH3F is 5 standard milliliters / minute to 100 standard milliliters / minute, the flow rate of CH4 is 5 standard milliliters / minute to 200 standard milliliters / minute, and the flow rate of He is 100 standard milliliters / minute to 1000 standard milliliters / minute.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the second source-drain opening, the method further includes forming an insulating layer on the bottom surface of the second source-drain opening.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The insulating layer is made of silicon oxide.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the insulating layer includes: performing a second oxidation treatment on the fin exposed by the second source drain opening to form the insulating layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The parameters for the second oxidation treatment include: the oxidizing gas is oxygen, and the oxidation time is 10 seconds to 600 seconds.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The expansion process includes a dry etching process.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The parameters of the dry etching process include: the etching gases used include NF3, Cl2, H2, He and N2, wherein the flow rates of NF3, Cl2 and H2 are 5 standard milliliters / minute to 500 standard milliliters / minute, and the flow rates of He and N2 are 100 standard milliliters / minute to 1000 standard milliliters / minute, respectively.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the gate structure, the method further includes forming a plurality of dummy gate structures on the substrate, the dummy gate structures spanning the fin along the first direction.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method for forming the initial source / drain opening includes: etching the fin using the pseudo-gate structure as a mask, and forming the initial source / drain opening within the fin.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the second source / drain opening, the method further includes: forming a source / drain doped layer within the second source / drain opening, wherein the source / drain doped layer contains source / drain ions.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The source / drain ions include N-type ions or P-type ions.

18. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the source / drain doped layer includes: forming an epitaxial layer in the second source / drain opening using an epitaxial growth process; and, during the epitaxial growth process, incorporating the source / drain ions into the epitaxial layer using an in-situ doping process to form the source / drain doped layer.

19. The method for forming a semiconductor structure as described in claim 14, characterized in that, After forming the source / drain doped layers, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the dummy gate structure.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The method for forming the gate structure includes: removing the dummy gate structure and forming a gate opening in the dielectric layer; forming a gate structure in the gate opening.

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