Analog-to-digital converter system and associated calibration method

Abstract

An analog-to-digital converter (ADC) system and related calibration method are provided. The ADC system includes a main ADC, a reference ADC, a sampling control circuit, and a calibration circuit. The main ADC samples an analog input according to a first sampling clock to obtain a first sampled voltage, and performs analog-to-digital conversion on the first sampled voltage to generate a first sample value. The reference ADC samples the analog input according to a second sampling clock to obtain a second sampled voltage, and performs analog-to-digital conversion on the second sampled voltage to generate a second sample value. The sampling control circuit controls the second sampling clock such that the second sampling clock has a same frequency but a different phase as the first sampling clock, and adjusts the second sample value to generate a reference sample value. The calibration circuit calibrates the main ADC according to the first sample value and the reference sample value.

Description

Technical Field

[0001] This invention relates to analog-to-digital conversion, and more specifically, to an analog-to-digital converter (ADC) system utilizing a reference ADC with sampling point shifting and an associated calibration method. Background Technology

[0002] Since analog-to-digital converters (ADCs) ultimately limit the performance of today's systems, high-speed and high-resolution ADCs are required. One possibility for overcoming these performance limitations is to use parallelism. For example, time-interleaved ADCs can be used to meet the requirements of high speed and high resolution. However, time-interleaved ADCs are susceptible to offsets, gain, and timing mismatches between sub-DACs on different channels. A traditional timing-skew calibration design uses a reference ADC. However, the sampling timing of the reference ADC needs to be consistent with that of the sub-DAC being calibrated, which can lead to some side effects. For example, the reference ADC can pull or disturb the sampling network and introduce spurious signals. Therefore, a new ADC calibration method and associated ADC system are needed to achieve reference ADC-based timing-skew calibration in a way that introduces no side effects or is unlikely to introduce side effects. Summary of the Invention

[0003] In view of this, one of the objectives of the present invention is to provide an analog-to-digital converter (ADC) system and an associated calibration method, which utilizes a reference ADC with sampling point shift to achieve calibration.

[0004] According to a first aspect of the present invention, an exemplary analog-to-digital converter (ADC) system is disclosed. The ADC system includes a main ADC, a reference ADC, a sampling control circuit, and a calibration circuit. The main ADC is used to sample an analog input according to a first sampling clock to obtain a first sampled input voltage, and to perform an analog-to-digital conversion on the first sampled voltage to generate a first sample value. The reference ADC is used to sample the analog input according to a second sampling clock to obtain a second sampled voltage, and to perform an analog-to-digital conversion on the second sampled voltage to generate a second sample value. The sampling control circuit is used to control the second sampling clock to ensure / make the second sampling clock have the same frequency but different phase from the first sampling clock, and the sampling control circuit is also used to adjust the second sample value to generate a reference sample value. The calibration circuit is used to calibrate the main ADC according to the first sample value and the reference sample value.

[0005] In some embodiments, the sampling control circuit generates the second sampling clock based on a reference clock, wherein the reference clock and the second sampling clock have the same frequency but different phases.

[0006] In some embodiments, the sampling control circuit includes a delay circuit for generating the second sampling clock by applying a delay amount to the reference clock to perform sampling point shifting.

[0007] In some embodiments, the delay is a fixed value.

[0008] In some embodiments, the sampling control circuit further includes a compensation circuit for determining a compensation value and generating a reference sample value by combining the compensation value and the second sample value to compensate for the sample value offset caused by the sampling point shift.

[0009] In some embodiments, the calibration circuit includes: a subtractor circuit for calculating the error between the first sample value and the reference sample value; a skew estimation circuit for estimating timing skew based on the error and generating a first control signal and a second control signal based on the timing skew; a first skew correction circuit for adjusting the phase of the first sampling clock based on the first control signal; and a second skew correction circuit for adjusting the digital output of the main ADC based on the second control signal.

[0010] In some embodiments, the first skew correction circuit includes: a numerically controlled delay line for generating the first sampling clock by applying an adjustable delay amount to a reference clock, wherein the adjustable delay amount is set by the first control signal.

[0011] In some embodiments, the ADC system includes a plurality of master ADCs, and a reference ADC is used to calibrate each of the plurality of master ADCs.

[0012] In some embodiments, the ADC system includes a time-interleaved ADC utilizing the plurality of master ADCs.

[0013] According to a second aspect of the present invention, an exemplary analog-to-digital converter (ADC) calibration method is disclosed. The exemplary ADC calibration method includes: a main ADC performing an analog-to-digital conversion on a first sampled voltage to generate a first sample value, wherein the first sampled input voltage is obtained by sampling an analog input according to a first sampling clock of the main ADC; a reference ADC performing an analog-to-digital conversion on a second sampled voltage to generate a second sample value, wherein the second sampled voltage is obtained by sampling the analog input according to a second sampling clock of the reference ADC; controlling the second sampling clock to ensure / make the second sampling clock have the same frequency but different phase from the first sampling clock; adjusting the second sample value to generate a reference sample value; and calibrating the main ADC based on the first sample value and the reference sample value.

[0014] In some embodiments, controlling the second sampling clock to have the same frequency but different phase as the first sampling clock includes: generating the second sampling clock according to a reference clock, wherein the reference clock has the same frequency but different phase as the second sampling clock.

[0015] In some embodiments, generating the second sampling clock according to the reference clock includes generating the second sampling clock by applying a delay to the reference clock to perform sampling point shifting.

[0016] In some embodiments, the delay is a fixed value.

[0017] In some embodiments, adjusting the second sample value to generate the reference sample value includes: determining a compensation value; and generating the reference sample value by combining the compensation value and the second sample value to compensate for the sample value offset caused by the sampling point shift.

[0018] In some embodiments, calibrating the main ADC based on the first sample value and the reference sample value includes: calculating the error between the first sample value and the reference sample value; estimating timing skew based on the error; generating a first control signal and a second control signal based on the timing skew; adjusting the phase of the first sampling clock based on the first control signal; and adjusting the digital output of the main ADC based on the second control signal.

[0019] In some embodiments, adjusting the phase of the first sampling clock according to the first control signal includes: generating the first sampling clock by applying an adjustable delay amount to a reference clock through a digitally controlled delay line, wherein the adjustable delay amount is set by the first control signal.

[0020] In some embodiments, the master ADC is any one of a plurality of master ADCs, and the reference ADC is used to calibrate each of the plurality of master ADCs.

[0021] In some embodiments, the plurality of master ADCs are included in a time-interleaved ADC.

[0022] These and other objects of the invention will be readily understood by those skilled in the art upon reading the following detailed description of the preferred embodiments illustrated in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings. Attached Figure Description

[0023] A more complete understanding of the invention can be obtained by reading the following detailed description and referring to the examples given in the accompanying drawings, wherein:

[0024] Figure 1 This is a schematic diagram of an analog-to-digital converter (ADC) system according to an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram illustrating the concept of calibrating a master ADC using a reference ADC with a proposed sampling point shift, according to an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of another ADC system according to an embodiment of the present invention.

[0027] In the following detailed description, numerous specific details are set forth for illustrative purposes so that those skilled in the art can more thoroughly understand the embodiments of the invention. However, it will be apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments illustrated in the accompanying drawings. Detailed Implementation

[0028] The following description illustrates preferred embodiments of the present invention and is intended only to exemplify the technical features of the invention, not to limit the scope of the invention. Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, this specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "element," "system," and "device" used in this invention can refer to computer-related entities, where the computer can be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are open-ended terms and should be interpreted as "comprising, but not limited to...". Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0029] Unless otherwise indicated, the corresponding numbers and symbols in the various figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0030] The terms "basically" or "roughly" as used in this document mean that, within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the desired technical effect. For example, "roughly equal to" means a method that a person skilled in the art can accept with a certain margin of error from "exactly equal to" without affecting the correctness of the result.

[0031] Figure 1 This is a schematic diagram of an analog-to-digital converter (ADC) system according to an embodiment of the present invention. The ADC system 100 includes at least one main ADC 102_i, a reference ADC 104, a sampling control circuit 106, and a calibration circuit 108. The ADC system 100 converts an analog input V... IN (t) is converted to a digital output and then passed to the next stage for further processing. From the analog input V... IN The digital output obtained from the analog-to-digital conversion of (t) depends on the digital output of the main ADC 102_i. However, the digital output of the reference ADC 104 is used for the calibration of the main ADC 102_i (e.g., timing skew calibration). In other words, the digital output of the reference ADC 104 is not involved in setting it as an analog input V. INThe digital output is represented by the number (t). In this embodiment, the reference ADC 104 operates according to a sampling clock CK_Ref, and the main ADC 102_i operates according to another sampling clock CK_i. Instead of aligning the sampling timing of the main ADC 102_i with that of the reference ADC 104, this invention proposes to apply sampling point shifting to the reference ADC 104 using a sampling control circuit 106 to ensure / make the sampling clocks CK_i and CK_Ref have the same frequency but different phases. More specifically, the phase of the sampling clock CK_Ref is intentionally deviated from the phase of the sampling clock CK_i, such that the rising edge of the sampling clock CK_Ref is not aligned with the rising edge of the sampling clock CK_i, and the falling edge of the sampling clock CK_Ref is not aligned with the falling edge of the sampling clock CK_i. In simple terms, the sampling control circuit 106 ensures that the reference ADC 104 and the main ADC 102_i have the same sampling rate but different sampling timing.

[0032] The digital output of the reference ADC 104 includes multiple sample values ​​D_r, each generated by performing an analog-to-digital conversion on a sampled input voltage (or sampling voltage), which is based on the sampling clock CK_Ref applied to the analog input V. IN (t) is obtained through sampling. For example, at each rising edge of the sampling clock CK_Ref, a sampled input voltage is obtained and converted by the reference ADC 104. Similarly, the digital output of the main ADC 102_i includes multiple sample values ​​D_i, each sample value D_i being generated by performing an analog-to-digital conversion on a sampled input voltage, which is converted according to the sampling clock CK_i for the same analog input V. IN (t) is obtained by sampling. For example, at each rising edge of the sampling clock CK_i, a sampled input voltage is obtained and converted by the main ADC 102_i.

[0033] Because the sampling timing of the reference ADC 104 is intentionally shifted to be misaligned with that of the main ADC 102_i, the reference ADC 104 does not perturb or interfere with the sampling operation performed at the main ADC 102_i. However, due to the timing discrepancy of the reference ADC 104, sample value compensation is required to compensate for the sample value offset caused by the sampling point shift. For example, the reference ADC 104 performs a sampling operation slightly later than the main ADC 102_i, but still measures the same data as the main ADC 102_i.

[0034] In this embodiment, the sampling control circuit 106 is used to control the sampling clock CK_Ref to ensure / make the sampling clocks CK_Ref and CK_i have the same frequency but different phases, and is also used to adjust each sample value D_r contained in the digital output of the reference ADC 104 to produce the corresponding reference sample value D_Ref actually used for the calibration (e.g., timing skew calibration) of the main ADC 102_i. Figure 1 As shown, the sampling control circuit 106 may include a delay circuit 112 and a compensation circuit 114. The delay circuit 112 is used to add an offset on the analog side, and the compensation circuit 114 is used to add an offset on the digital side. For sampling point shifting, the delay circuit 112 is used to generate the sampling clock CK_Ref by applying a delay amount Δt to the reference clock CLK. For example, the reference clock CLK may be generated by a clock generator. Figure 1 The sampling clock CK_Ref (labeled "CK generator") 101 is provided. In this embodiment, the delay Δt is a fixed value, resulting in a fixed phase delay between the sampling clock CK_Ref and the reference clock CLK. In this embodiment, the sampling clock CK_i used by the master ADC 102_i is also obtained from the reference clock CLK. By appropriately setting the delay Δt, the sampling operation performed at the master ADC 102_i will not interfere with the sampling operation performed at the reference ADC 104. Thus, the reference ADC 104 will not introduce disturbances or interference when the master ADC 102_i performs a sampling operation.

[0035] Compensation circuit 114 is used to determine the compensation value D_c and generate a reference sample value D_Ref by combining the compensation value D_c and the sample value D_r to compensate for the sample value offset caused by the sampling point shift. For example, the differentiator-based circuit 116 multiplies the derivative of the analog input by the delay Δt to estimate / obtain the compensation value D_c (i.e., ), and subtractor circuit 118 (which may be implemented by an adder configured to perform subtraction) subtracts compensation value D_c from sample value D_r to produce reference sample value D_Ref (i.e., ).

[0036] The calibration circuit 108 is arranged to apply / calibrate (e.g., timing skew calibration) the main ADC 102_i based on the sample value D_i and the reference sample value D_Ref. Figure 2 This is a schematic diagram illustrating the concept of calibrating a main ADC using a reference ADC that utilizes a proposed sampling point shift, according to an embodiment of the present invention. The sample value D_i is obtained at time instant T1, defined by the sampling clock CK_i. After a delay Δt from the sampling operation performed by the main DAC 102_i at time T1, the sample value D_r is obtained at time T2 (T2 = T1 + Δt), defined by the sampling clock CK_Ref. The derivative of the analog input... The sign of the input determines how to compensate for the sample values ​​generated from the reference ADC 104. For example, if the derivative of the analog input... If it is positive, then the reference sample value D_Ref is less than the sample value D_r. For example, if the derivative of the simulated input... If the value is negative, then the reference sample value D_Ref is greater than the sample value D_r. Figure 2 In the example shown, the derivative of the simulated input It is negative at time T2. Therefore, this is attributed to sample value offset compensation (e.g., The reference sample value D_Ref is greater than the sample value D_r. The calibration circuit 108 checks whether the sample value D_i matches the reference sample value D_Ref. If the sample value D_i matches the reference sample value D_Ref, it means that the sampling timing of the sampling clock CK_i is aligned with the reference timing, and the main ADC 102_i does not require timing skew calibration. If the sample value D_i does not match the reference sample value D_Ref, it means that the sampling timing of the sampling clock CK_i deviates from the reference timing, and the main ADC 102_i requires timing skew calibration.

[0037] For example, regarding the calibration of the main ADC 102_i (e.g., timing skew calibration), an offset can be added to the analog side and / or an offset can be added to the digital side. In this embodiment, the calibration circuit 108 can employ a hybrid approach, different from both all-digital and all-analog schemes. Figure 1 As shown, the calibration circuit 108 may include a subtractor circuit (which may be implemented by an adder configured to perform subtraction) 122, and a skew estimation circuit. Figure 2 The circuit includes 124 (labeled "skew estimation"), 126 (skew correction circuit for analog-side correction), and another skew correction circuit for digital-side correction. Figure 2 The circuit is labeled "skew correction" 128. A subtractor circuit 122 calculates the error D_err between the sample value D_i and the reference sample value D_Ref. A skew estimation circuit 124 estimates the timing skew based on the error D_err and generates two control signals C1 and C2 based on the estimated timing skew. Since the digital correction of the digital output performed at the skew correction circuit 128 has limited coverage, the proposed hybrid scheme further uses a skew correction circuit 126 to provide analog correction for the sample clock CK_i. The skew correction circuit 126 adjusts the phase of the sample clock CK_i according to the control signal C1. In this embodiment, the skew correction circuit 126 may include a digitally controlled delay line (DCDL) 127 arranged to generate the sample clock CK_i by applying an adjustable delay amount to the reference clock REF provided by the clock generator 101, wherein the adjustable delay amount is set by the control signal C1. The skew correction circuit 128 is used to adjust the digital output of the main ADC 102_i according to the control signal C2. In simple terms, the calibration of the main ADC 102_i (e.g., timing skew calibration) is achieved by combining digital correction (e.g., adjusting the digital output of the main ADC 102_i via control signal C2) and analog correction (e.g., adjusting the delay of the digitally controlled delay line 127 via control signal C1), which can reduce or eliminate the error D_err between the sample value D_i and the reference sample value D_Ref. In this way, the final digital output generated by the skew correction circuit 128 can be considered as the digital output generated by the main ADC 102_i with the sampling timing aligned with the reference timing.

[0038] The same concept of calibrating a master ADC by using a reference ADC that utilizes the sampling point shift proposed in this invention can be extended to calibrating multiple master ADCs by using a single reference ADC that utilizes the proposed sampling point shift. Figure 3 This is a schematic diagram of another ADC system according to an embodiment of the present invention. The ADC system 300 includes multiple main ADCs 102_1-102_N (N≥2), a multiplexer (labeled "MUX") 302, and the aforementioned reference ADC 104, sampling control circuit 106, and calibration circuit 108. In this embodiment, the reference ADC 104 is used to calibrate the time-interleaved ADC 301 utilizing the main ADCs 102_1-102_N, wherein the multiplexer inputs M_1-M_N obtained from the digital outputs of the main ADCs 102_1-102_N are combined by the multiplexer 302 to form the digital output D_OUT of the time-interleaved ADC 301. Figure 1 The main ADC 102_i shown can be any one of the main ADCs 102_1-102_N (i = 1, ..., N). In this embodiment, the same reference ADC 104 is used to calibrate all the main ADCs 102_1-102_N. It should be noted that the sampling control circuit 106 controls the sampling clock CK_Ref to ensure that the sampling clock CK_Ref used by the reference ADC 104 has the same frequency but a different phase than each of the sampling clocks CK_1-CK_N used by the main ADCs 102_1-102_N. This achieves a sampling point shift of the reference ADC 104 to prevent the sampling operation of the main ADCs 102_1-102_N from being affected by the sampling operation of the reference ADC 104. Furthermore, the digital output of the reference ADC 104 is appropriately adjusted to compensate for the sample value offset caused by this sampling point shift, so that the calibration of the main ADCs 102_1-102_N (e.g., timing skew calibration) can operate as expected.

[0039] Compared to splitting the reference ADC into multiple reference ADCs for calibration of the main ADCs 102_1-102_N (e.g., timing skew calibration), calibrating all the main ADCs 102_1-102_N using a single reference ADC 104 requires less area. Furthermore, using the sampling control circuit 106 to delay the sampling clock of the reference ADC and apply compensation to the digital output of the reference ADC is more cost-effective than using a resistor-capacitor (RC) network to delay the analog input and the sampling clock of the reference ADC.

[0040] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various variations and similar structures (as will be apparent to those skilled in the art), such as combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such variations and similar structures.

Claims

1. An analog-to-digital converter (ADC) system, characterized in that, The ADC system includes: The main ADC is used to sample the analog input according to the first sampling clock to obtain the first sample voltage, and to perform analog-to-digital conversion on the first sample voltage to generate the first sample value; The reference ADC is used to sample the analog input according to the second sampling clock to obtain a second sample voltage, and to perform analog-to-digital conversion on the second sample voltage to generate a second sample value; The sampling control circuit is used to control the second sampling clock so that the second sampling clock has the same frequency but a different phase from the first sampling clock. The sampling control circuit also includes a compensation circuit for determining a compensation value applied to the second sample value to compensate for the sample value offset of the reference ADC, and adjusting the second sample value by combining the compensation value and the second sample value to generate a reference sample value. A calibration circuit is used to calibrate the main ADC based on the first sample value and the reference sample value.

2. The ADC system as described in claim 1, characterized in that, The sampling control circuit generates the second sampling clock based on a reference clock, wherein the reference clock and the second sampling clock have the same frequency but different phases.

3. The ADC system as described in claim 2, characterized in that, The sampling control circuit includes: A delay circuit is used to generate the second sampling clock by applying a delay to the reference clock in order to shift the sampling point.

4. The ADC system as described in claim 3, characterized in that, The delay is a fixed value.

5. The ADC system as described in claim 3, characterized in that, The compensation value is determined based on the derivative of the analog input and the delay.

6. The ADC system as described in claim 1, characterized in that, The calibration circuit includes: A subtractor circuit is used to calculate the error between the first sample value and the reference sample value; A skew estimation circuit is used to estimate timing skew based on the error, and to generate a first control signal and a second control signal based on the timing skew. A first skew correction circuit is used to adjust the phase of the first sampling clock according to the first control signal; and, The second skew correction circuit is used to adjust the digital output of the main ADC according to the second control signal.

7. The ADC system as described in claim 6, characterized in that, The first skew correction circuit includes: A numerically controlled delay line is used to generate the first sampling clock by applying an adjustable delay to a reference clock, wherein the adjustable delay is set by the first control signal.

8. The ADC system as described in claim 1, characterized in that, The ADC system includes multiple master ADCs, and a reference ADC used to calibrate each of the multiple master ADCs.

9. The ADC system as described in claim 8, characterized in that, The ADC system includes a time-interleaved ADC utilizing the multiple master ADCs.

10. A method for calibrating an analog-to-digital converter (ADC), comprising: The main ADC performs analog-to-digital conversion on the first sampled voltage to generate a first sample value, wherein the first sample value is obtained by sampling the analog input according to the first sampling clock of the main ADC; The reference ADC performs analog-to-digital conversion on the second sampled voltage to generate a second sample value, wherein the second sample value is obtained by sampling the analog input according to the second sampling clock of the reference ADC; The second sampling clock is controlled so that it has the same frequency as the first sampling clock but a different phase. Determine the compensation value to be applied to the second sample value to compensate for the sample value offset of the reference ADC; The second sample value is adjusted by combining the compensation value and the second sample value to generate a reference sample value; and, The main ADC is calibrated based on the first sample value and the reference sample value.

11. The ADC calibration method as described in claim 10, characterized in that, Controlling the second sampling clock to have the same frequency but different phase as the first sampling clock includes: The second sampling clock is generated based on a reference clock, wherein the reference clock and the second sampling clock have the same frequency but different phases.

12. The ADC calibration method as described in claim 11, characterized in that, Generating the second sampling clock based on the reference clock includes: The second sampling clock is generated by applying a delay to the reference clock to perform sampling point shifting.

13. The ADC calibration method as described in claim 12, characterized in that, The delay is a fixed value.

14. The ADC calibration method as described in claim 12, characterized in that, The compensation value is determined based on the derivative of the analog input and the delay.

15. The ADC calibration method as described in claim 10, characterized in that, The main ADC is calibrated based on the first sample value and the reference sample value, including: Calculate the error between the first sample value and the reference sample value; The timing skew is estimated based on this error. The first and second control signals are generated based on the timing skew. The phase of the first sampling clock is adjusted according to the first control signal; and, The digital output of the main ADC is adjusted according to the second control signal.

16. The ADC calibration method as described in claim 15, characterized in that, Adjusting the phase of the first sampling clock according to the first control signal includes: A first sampling clock is generated by applying an adjustable delay to a reference clock via a numerically controlled delay line, wherein the adjustable delay is set by the first control signal.

17. The ADC calibration method as described in claim 10, characterized in that, The master ADC is any one of a plurality of master ADCs, and the reference ADC is used to calibrate each of the plurality of master ADCs.

18. The ADC calibration method as described in claim 17, characterized in that, These multiple main ADCs are included in the time-interleaved ADC.

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