Data forwarding system, method, computing device and programmable logic device

Abstract

The embodiment of the present application is applicable to the field of computer network technology, and provides a data forwarding system, method, computing device and programmable logic device, the system includes: a main network port, at least one sub-network port, and a sub-network port switching module, the sub-network port switching module includes an uplink arbitration sub-module and a downlink arbitration sub-module; the uplink arbitration sub-module includes a sub-network port receiving processing unit, a cache array data polling unit and a sending data cache array; the downlink arbitration sub-module includes a data forwarding control unit and a main network port receiving processing unit; the uplink arbitration sub-module can be used to forward the uplink datagram received by the sub-network port to the main network port; the downlink sub-module can be used to forward the downlink datagram received by the main network port to the corresponding sub-network port. The system can flexibly control the network port corresponding to the data forwarding, accurately forward the datagram, thereby reducing the system energy consumption.

Description

Technical Field

[0001] This application belongs to the field of computer network technology, and in particular relates to a data forwarding system, method, computing device and programmable logic device. Background Technology

[0002] Currently, almost all domestically produced switching chips are multi-port universal structures. While these chips offer the advantage of versatility, their large number of ports can lead to idle ports in applications with limited network port requirements, resulting in excessive power consumption. Furthermore, their universal data switching function cannot accurately forward packets to specific ports based on the given physical address. Summary of the Invention

[0003] In view of this, embodiments of this application provide a data forwarding system, method, computing device, and programmable logic device to achieve high-performance, low-power data forwarding.

[0004] A first aspect of this application provides a data forwarding system, including: a main network port, at least one sub-network port, and a sub-network port switching module. The sub-network port switching module includes an uplink arbitration sub-module and a downlink arbitration sub-module. The uplink arbitration sub-module includes a sub-network port receiving and processing unit, a buffer array data polling unit, and a transmitting data buffer array. The downlink arbitration sub-module includes a data forwarding control unit and a main network port receiving and processing unit.

[0005] The sub-port is used to receive uplink data packets and forward downlink data packets;

[0006] The main network port is used to receive the downlink data packets and forward the uplink data packets in the transmit data buffer array;

[0007] The sub-port receiving and processing unit is used to buffer the uplink data packets;

[0008] The buffer array data polling unit is used to poll the uplink data packets in the sub-network interface receiving and processing unit, and store the uplink data packets in the sending data buffer array;

[0009] The main network port receiving and processing unit is used to buffer the downlink data packets received by the main network port;

[0010] The data forwarding control unit is used to forward the downlink datagrams cached by the main network port receiving and processing unit to the corresponding sub-network port.

[0011] A second aspect of this application provides a data forwarding method applied to a data forwarding system, the method comprising:

[0012] Use the subnet port to receive uplink data packets;

[0013] The uplink datagram is cached in the sub-network port receiving and processing unit corresponding to the sub-network port;

[0014] The uplink data packets in the sub-interface receiving and processing unit are polled using a cache array data polling unit.

[0015] Store the uplink datagram in the transmit data buffer array;

[0016] The main network interface is used to forward the uplink datagrams in the data transmission buffer array;

[0017] The main network port is used to receive downlink data packets;

[0018] The downlink datagram is cached in the main network port receiving and processing unit;

[0019] The data forwarding control unit forwards the downlink datagrams cached by the main network port receiving and processing unit to the corresponding sub-network port.

[0020] The downlink datagram is forwarded using the sub-network interface.

[0021] A third aspect of this application provides a computing device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in the second aspect above.

[0022] A fourth aspect of this application provides a programmable logic device that, when executed, implements the method described in the second aspect above.

[0023] A fifth aspect of this application provides a computer program product that, when run on a computing device, causes the computing device to perform the method described in the first aspect.

[0024] Compared with the prior art, the embodiments of this application have the following advantages:

[0025] In this embodiment, the data forwarding system includes a main network port, at least one sub-network port, and a sub-network port switching module. The sub-network port switching module includes an uplink arbitration sub-module and a downlink arbitration sub-module. The uplink arbitration sub-module includes a sub-network port receiving and processing unit, a buffer array data polling unit, and a transmitting data buffer array. The downlink arbitration sub-module includes a data forwarding control unit and a main network port receiving and processing unit. The uplink arbitration sub-module forwards uplink datagrams received by the sub-network port to the main network port; the downlink sub-module forwards downlink datagrams received by the main network port to the corresponding sub-network port. This achieves precise forwarding of data packets; each datagram is forwarded by only one sub-network port, effectively reducing data exchange transactions, lowering the signal flip-flop rate within the digital chip, and thus reducing system power consumption. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a structural diagram of a data forwarding system provided in an embodiment of this application;

[0028] Figure 2 This is a schematic diagram of the data flow of an uplink arbitration submodule provided in an embodiment of this application;

[0029] Figure 3 This is a schematic diagram of the data flow of a downlink arbitration submodule provided in an embodiment of this application;

[0030] Figure 4 This is a flowchart illustrating the steps of a data forwarding method provided in an embodiment of this application;

[0031] Figure 5 This is a schematic diagram of a computing device provided in an embodiment of this application. Detailed Implementation

[0032] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0033] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0034] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0035] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0036] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0037] References to "provided in an embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in provided in an embodiment," "in some embodiments," "in other embodiments," and "in still other embodiments" appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0038] The technical solution of this application will be described below through specific embodiments.

[0039] Figure 1 This is a structural diagram of a data forwarding system provided in an embodiment of this application; as shown... Figure 1 As shown, the data forwarding system includes: a main network port, at least one sub-network port, and a sub-network port switching module. The sub-network port switching module includes an uplink arbitration sub-module and a downlink arbitration sub-module. The uplink arbitration sub-module includes a sub-network port receiving and processing unit, a buffer array data polling unit, and a sending data buffer array. The downlink arbitration sub-module includes a data forwarding control unit and a main network port receiving and processing unit. Figure 1 The data forwarding system shown is based on a system with two sub-ports, and does not mean that the system can only have two sub-ports; there is no limit to the number of sub-ports in this data forwarding system, and it can be set according to the actual application scenario.

[0040] In a data forwarding system, a subnet port is used to receive uplink data packets and forward downlink data packets. For example, when a terminal device sends information, the subnet port can receive the uplink data packets sent by the terminal device; when a terminal device receives information, downlink data packets can reach the terminal device through the subnet port.

[0041] The aforementioned uplink arbitration submodule is used to forward uplink datagrams received by the sub-port to the main port. Within the uplink arbitration submodule, each sub-port corresponds to a sub-port receiving and processing unit, used to buffer the uplink datagrams received by that sub-port. The sub-port receiving and processing unit may include a data receiving subunit and a buffer array, which may include a first memory and a second memory. The data receiving subunit parses the uplink datagrams received by the sub-port to obtain message information and message data. The first memory can be used to store the message information of the uplink datagram, which includes the length and starting address of the uplink datagram. The second memory can be used to store the message data of the uplink datagram. For example, the first memory can be a FIFO (First-In-First-Out) memory, and the second memory can be RAM (Random Access Memory). When writing message data to RAM, it can be written with a width of 64 bits; when writing message information to FIFO, it can be written with a width of 32 bits.

[0042] The aforementioned buffer array data polling unit is used to poll the uplink data packets in each sub-port receiving and processing unit, and store the uplink data packets in the transmitting data buffer array. Specifically, the buffer array data polling unit can sequentially check whether the sub-port receiving and processing unit is empty according to a preset order. If the sub-port receiving and processing unit is not empty, it reads the packet data from the second memory according to the packet information in the first memory; stores the packet information and packet data in the transmitting data buffer array; and then continues to check whether the next sub-port receiving and processing unit is empty. If the sub-port receiving and processing unit is empty, it continues to check whether the sub-port receiving and processing unit is empty.

[0043] The aforementioned data buffer array may include a third memory and a fourth memory. The third memory is used to receive message information from the buffer array data polling unit and buffer the message information; the fourth memory is used to receive message data from the buffer array data polling unit and buffer the message data.

[0044] Figure 2This is a schematic diagram of the data flow of an uplink arbitration submodule provided in an embodiment of this application. Figure 2 This example illustrates a system with two sub-ports. The uplink data forwarding arbitration submodule connects to the transmission timing of the two sub-ports and the reception timing of the main port. This uplink data forwarding arbitration submodule can consist of two port receiving processing units and a buffer array polling unit. The buffer arrays of the two port receiving processing units buffer packet data from sub-port 1 and sub-port 2, respectively. The buffer array polling module reads the data from the two buffer arrays and merges them before sending them to the main port using a ping-pong operation. Figure 2 As shown, the system includes sub-port 1 and sub-port 2, each with its own corresponding receive data buffer array. Sub-port 1 receives uplink datagrams. The sub-port 1 receiving processing unit parses the RMII_tx_S1 timing sequence, shifts the data in the RMII TX timing sequence using a shift register, and concatenates them into a 64-bit width. The sub-port 1 receiving processing unit then sequentially fills the 64-bit width message data output from the shift register into RAM. Simultaneously, at the end of datagram reception, the starting position of the current frame message in RAM is stored in the lower 16 bits of the FIFO, and the length of the current message in RAM is stored in the higher 16 bits of the FIFO. Essentially, the FIFO stores the uplink datagram length len1 and the starting address pos1, while RAM stores the message data. Here, RMII stands for Simplified Media Independent Interface (MII). TX stands for Transmit Transport.

[0045] The buffer array polling module polls the receive data buffer arrays of network port 1 and network port 2. First, it checks if the FIFO in the receive data buffer array of network port 1 is empty. If not, it determines the location of the packet data in RAM based on the starting address in the packet information within the FIFO. Then, it reads data matching the packet length from that location in RAM as the packet data, and caches the packet data and packet information into the transmit data buffer list. The buffer array polling module can use a ping-pong mechanism to alternately poll the receive data buffer arrays of network port 1 and network port 2. First, it checks if the receive data buffer array of network port 1 is empty; if not, it reads and caches data. Then it checks the receive data buffer array of network port 2. This process is repeated, summarizing the data received from sub-network ports 1 and 2 and writing it into the transmit data buffer array.

[0046] In the data transmission buffer array, FIFO is used to store message information, and RAM is used to store message data.

[0047] The RMII timing generation unit can sequentially read 64 bits of data from RAM based on the information in the transmit data buffer array FIFO, and convert the data into RMII RX timing output via a shift register to the main network interface, thus completing the forwarding of uplink datagrams. Here, RX stands for receive.

[0048] In the downlink arbitration submodule, the main network port receive processing unit is used to buffer downlink datagrams received by the main network port. The main network port receive processing unit may include a receive data buffer array, which may include a fifth memory and a sixth memory. The fifth memory can be a FIFO, and the sixth memory can be RAM. The FIFO can be used to store the message information of the downlink datagram, including the physical address, message length, and start position. The RAM can be used to store the message data of the downlink datagram.

[0049] The data forwarding control unit is used to forward downlink datagrams buffered by the main network interface receiving and processing unit to the corresponding sub-network interface. Specifically, the data forwarding control unit may include a packet forwarding configuration table, which stores the association between physical addresses and sub-network interfaces. That is, the sub-network interface can be used to forward downlink datagrams corresponding to the associated physical address. The data forwarding control unit may also include a packet forwarding control sub-unit, which can determine the sub-network interface corresponding to the downlink datagram from the packet forwarding configuration table based on the physical address of the downlink datagram; and forward the downlink datagram to the data buffer array of the sub-network interface corresponding to that sub-network interface.

[0050] Figure 3 This is a schematic diagram of the data flow of a downlink arbitration submodule provided in an embodiment of this application. Figure 3 This example illustrates a system with two sub-network ports. The downlink data forwarding arbitration submodule connects the receive timing of the two sub-network ports and the transmit timing of the main network port. This downlink data forwarding arbitration submodule consists of a network port receive processing unit and a data forwarding control unit. During packet forwarding, the forwarding control unit performs precise packet forwarding based on the packet forwarding configuration table. The packet forwarding configuration table includes the mapping between physical addresses and sub-network ports. Figure 3As shown, when the main network interface receives a downlink data packet, it inputs the packet to be sent into the receive data buffer array of the data switching module via the RMII TX timing. The receive buffer array sequentially stores multiple consecutive frames of data into the RAM of the buffer array without processing, with a bit width of 64 bits. After a frame of data ends, the starting address of each frame of data in RAM is stored in bits [15:00] of the message information; the length of each frame of data in RAM is stored in bits [31:16] of the message information; and the physical address of each frame of data is stored in bits [79:32] of the message information. In this way, the position of the message data in RAM can be determined according to the starting address and length in the message information.

[0051] The data forwarding module forwards data from the main network interface to the sub-network interface. The forwarding process is as follows: The forwarding control module actively reads the data from the FIFO in the receive data buffer array and extracts bits [79:32] of the read data, which is the physical address of the packet. The [79:32] bits read from the FIFO are compared with the configuration information in the packet forwarding configuration table in the forwarding control module to obtain the forwarding target sub-network interface of the current frame packet. Based on the obtained forwarding target sub-network interface information and bits [31:00] stored in the FIFO, the packet is forwarded to the designated sub-network interface.

[0052] exist Figure 3 In this system, the FIFO of the main network port receive data buffer array includes three data packets, corresponding to three physical addresses: mac_addr1, mac_addr2, and mac_addr13. The packet forwarding configuration table includes information associating mac_addr1 with sub-port 1 and mac_addr2 with sub-port 2. This means that data packets corresponding to mac_addr1 are forwarded to sub-port 1, and data packets corresponding to mac_addr2 are forwarded to sub-port 2. Since mac_addr13 does not have a corresponding sub-port, its data packets will not be forwarded. This ensures accurate data packet forwarding and reduces system power consumption. The data forwarding system in this embodiment can be applied to 100Mbps dual-port networks. This system can rely on domestically produced programmable logic devices, such as CPLDs or FPGAs, to precisely customize data forwarding functions, achieving low-power, high-performance data forwarding capabilities.

[0053] Unlike general-purpose switching chips, data switching modules designed using programmable logic devices can flexibly adjust the number of network ports according to actual application scenarios. They can preprocess packets during data exchange according to actual application needs, such as adding measurable delays and filtering duplicate frames. Furthermore, they can accurately forward packets through a configurable packet forwarding mechanism. In the data switching system, a data packet only needs to be forwarded if its physical address is in the packet forwarding configuration table. Moreover, unlike existing technologies, only one sub-port forwards a data packet, effectively reducing data exchange transactions, lowering the signal toggle rate within the digital chip, and thus reducing system power consumption.

[0054] In addition, each sub-port forwards packets corresponding to the physical address, which allows the packets received in the system to be distributed more evenly among the sub-ports, thus making the forwarding tasks of each sub-port relatively even and reducing the idle rate of the sub-ports.

[0055] Reference Figure 4 The diagram illustrates a step-by-step flowchart of a data forwarding method provided in an embodiment of this application, which may specifically include the following steps:

[0056] S401 uses a subnet port to receive uplink datagrams.

[0057] The data forwarding method in this embodiment can be applied to the data forwarding system described in the foregoing embodiments. The method in this embodiment can be implemented using a programmable logic device.

[0058] The aforementioned uplink datagram refers to the datagram received from the sub-port; this uplink datagram needs to be forwarded to the main port using the method described in this embodiment. The data forwarding system may include multiple sub-ports, each capable of receiving uplink datagrams and forwarding downlink datagrams.

[0059] S402, the uplink datagram is cached in the sub-network port receiving and processing unit corresponding to the sub-network port.

[0060] Specifically, in this embodiment, each sub-port has a corresponding sub-port receiving and processing unit. The sub-port receiving and processing unit may include a data receiving sub-unit and a buffer array, which is used to store uplink data packets.

[0061] When the subnet port receives an uplink datagram, it can parse the uplink datagram using the receiving timing sequence to obtain the uplink datagram's message information and message data; then, it stores the message information in the first memory of the buffer array and stores the message data in the second memory of the buffer array.

[0062] The message information can be considered as an index for the message. The message information can include the message length and starting address. The message data can be read from the second memory through the message information.

[0063] S403, the buffer array data polling unit polls the uplink data packets in the sub-network port receiving and processing unit.

[0064] Specifically, the buffer array polling unit can use a ping-pong operation mechanism to poll the buffer array models in the sub-network port receiving and processing unit in turn. The polling array unit can read the corresponding message data from the second memory through message information, thereby summarizing the uplink data packets received by each sub-network port.

[0065] Accordingly, uplink datagrams in the cache array can be deleted after being polled, freeing up storage space.

[0066] S404, the uplink datagram is stored in the transmit data buffer array.

[0067] Specifically, after completing one poll, the data polling unit of the cache array can store the summarized uplink data packets into the data cache array. Then, the polling continues in a loop.

[0068] In a data buffer array, uplink data packets can also be stored separately for packet information and packet data. The data buffer array may include a third memory and a fourth memory; the third memory can be used to store packet information, and the fourth memory can be used to store packet data.

[0069] S405 uses the main network port to forward the uplink datagrams in the data transmission buffer array.

[0070] Specifically, the data forwarding system may also include an RMII timing generation unit. This unit can retrieve packet information from the third memory in the data buffer array, and then retrieve packet data from the fourth memory based on the packet information. The packet data is then converted into RMII RX timing and output to the main network interface. The main network interface forwards the uplink data packets.

[0071] S406, using the main network port to receive downlink datagrams.

[0072] Specifically, the downlink datagram is the datagram received by the main network interface and forwarded to the sub-network interface.

[0073] S407, the downlink datagram is cached in the main network port receiving and processing unit.

[0074] Specifically, the main network port receiving and processing unit may include a fifth memory and a sixth memory. The fifth memory can be used to store the message information of downlink data packets, and the sixth memory can be used to store the message data corresponding to the downlink data packets.

[0075] The message information may include the physical address of the downlink datagram, the message length, and the starting address in the sixth memory; the message data can be read from the sixth memory based on the message length and starting address in the message information.

[0076] S408, the data forwarding control unit forwards the downlink datagrams cached by the main network port receiving and processing unit to the corresponding sub-network port.

[0077] Specifically, the data forwarding control unit may include a packet forwarding configuration table, which includes the correspondence between physical addresses and subnet ports. Based on the physical address in the packet information, the corresponding subnet port can be obtained from the packet forwarding configuration table. Then, the downlink datagram is forwarded to that subnet port.

[0078] S409, the sub-network interface is used to forward the downlink datagram.

[0079] Specifically, the downlink datagrams received by the subnet port can be forwarded to the device corresponding to the physical address.

[0080] In this embodiment, the sub-port is associated with the physical address. Each sub-port will only forward the datagram corresponding to the associated physical address. Each datagram will only be forwarded in the corresponding sub-port, thereby achieving accurate forwarding of datagrams and avoiding repeated forwarding of datagrams by the sub-port during the forwarding process. This can effectively reduce data exchange transactions, reduce the signal flip rate inside the digital chip, and thus reduce system power consumption.

[0081] It should be noted that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0082] Figure 5 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Figure 5 As shown, the computing device 5 of this embodiment includes: at least one processor 50 ( Figure 5 (Only one is shown) a processor, a memory 51, and a computer program 52 stored in the memory 51 and executable on the at least one processor 50, wherein the processor 50 executes the computer program 52 to implement the steps in any of the above method embodiments.

[0083] The computing device 5 can be a desktop computer, laptop, handheld computer, or cloud server, etc. This computing device may include, but is not limited to, a processor 50 and a memory 51. Those skilled in the art will understand that... Figure 5 This is merely an example of computing device 5 and does not constitute a limitation on computing device 5. It may include more or fewer components than shown in the figure, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0084] The processor 50 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0085] In some embodiments, the memory 51 may be an internal storage unit of the computing device 5, such as a hard disk or memory of the computing device 5. In other embodiments, the memory 51 may be an external storage device of the computing device 5, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the computing device 5. Furthermore, the memory 51 may include both internal and external storage units of the computing device 5. The memory 51 is used to store the operating system, applications, bootloader, data, and other programs, such as the program code of the computer program. The memory 51 can also be used to temporarily store data that has been output or will be output.

[0086] This application also provides a programmable logic device, which stores a computer program. When the computer program is executed by a processor, it can implement the steps in the above-described method embodiments.

[0087] This application provides a computer program product that, when run on a computing device, enables the computing device to implement the steps described in the various method embodiments above.

[0088] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable programmable logic device (CLPD). Based on this understanding, all or part of the processes in the above-described embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a CLPD, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The CLPD can include at least: any entity or device capable of carrying computer program code to a photographic device / computing device, a recording programmable logic device, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution programmable logic device. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable programmable logic devices cannot be electrical carrier signals or telecommunication signals.

[0089] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0090] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0091] In the embodiments provided in this application, it should be understood that the disclosed apparatus / computing device and method can be implemented in other ways. For example, the apparatus / computing device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0092] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0093] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A data forwarding system, characterized in that: include: A main network port, at least one sub-network port, and a sub-network port switching module, wherein the sub-network port switching module includes an uplink arbitration sub-module and a downlink arbitration sub-module; The uplink arbitration submodule includes a subnet port receiving processing unit, a cache array data polling unit and a transmission data cache array; The downlink arbitration submodule includes a data forwarding control unit and a primary network port receiving processing unit; wherein: The subnet port is used to receive uplink datagrams and forward downlink datagrams; The primary network port is used to receive the downlink datagram and forward the uplink datagram in the transmission data buffer array; The sub-network port receiving processing unit is used to cache the uplink datagram, and the sub-network port receiving processing unit includes a first memory and a second memory; wherein the first memory is used to store the message information of the uplink datagram; and the second memory is used to store the message data of the uplink datagram; The cache array data polling unit is used to poll the uplink datagrams in each of the sub-network port receiving processing units through a ping-pong operation mechanism, and store the uplink datagrams in the sending data cache array; The primary network port receiving processing unit is used to buffer the downlink datagram received by the primary network port; The data forwarding control unit is used to forward the downlink datagram cached by the main network port receiving processing unit to the corresponding sub-network port; the data forwarding control unit includes a message forwarding configuration table, and the message forwarding configuration table is used to store the association relationship between the sub-network port and the physical address; the data forwarding control unit also includes a message forwarding control subunit, and the message forwarding control subunit is used to determine the sub-network port corresponding to the downlink datagram from the message forwarding configuration table according to the physical address of the downlink datagram; and forward the downlink datagram to the sub-network port sending data cache array corresponding to the sub-network port; the data forwarding system only forwards the datagram whose physical address is in the message forwarding configuration table; Wherein, the main network port receiving processing unit includes a receiving data cache array, and the receiving data cache array includes a fifth memory and a sixth memory; The fifth memory is used to store message information of the downlink datagram, the message information includes a physical address of the downlink datagram, the physical address of the downlink datagram is used by the data forwarding control unit to determine the subnet port corresponding to the downlink datagram, and each of the downlink datagrams is forwarded through the corresponding unique subnet port; The sixth memory is used to store the message data of the downlink data packet; the message information also includes the message length of the downlink data packet and the starting address in the sixth memory; the message length and the starting address are used to read the message data from the sixth memory; The cache array data polling unit is used to poll the uplink datagram in each of the sub-network ports receiving processing units through a ping-pong operation mechanism, including: Detect whether the first sub-network port receiving processing unit is not empty; if the first sub-network port receiving processing unit is not empty, read the message data from the second memory of the first sub-network port receiving processing unit according to the message information in the first memory of the first sub-network port receiving processing unit; the first sub-network port receiving processing unit is any of the sub-network port receiving processing units in the system; Detect whether the second sub-network port receiving processing unit is not empty; if the second sub-network port receiving processing unit is not empty, read the message data from the second memory of the second sub-network port receiving processing unit according to the message information in the first memory of the second sub-network port receiving processing unit; the second sub-network port receiving processing unit is the next sub-network port receiving processing unit of the first sub-network port receiving processing unit; The transmission data buffer array includes a third memory and a fourth memory, wherein: The third memory is used to receive the message information from the cache array data polling unit and cache the message information; The fourth memory is used to receive the message data from the cache array data polling unit and cache the message data.

2. A data forwarding method, characterized in that: Applied to a data forwarding system, the method comprises: Use the subnet port to receive uplink datagrams; Cache the uplink datagram to the sub-network port receiving processing unit corresponding to the sub-network port, wherein the sub-network port receiving processing unit includes a first memory and a second memory; wherein the first memory is used to store the message information of the uplink datagram; and the second memory is used to store the message data of the uplink datagram; Using a cache array data polling unit to poll the uplink datagram in each of the sub-network ports receiving processing units through a ping-pong operation mechanism; Storing the uplink data in a transmit data buffer array; Using a primary network port to forward the uplink datagram in the sending data cache array; Using the primary network port to receive downlink datagrams; Cache the downlink datagram to the primary network port receiving processing unit; A data forwarding control unit is used to forward the downlink datagram cached by the main network port receiving processing unit to the corresponding sub-network port; the data forwarding control unit includes a message forwarding configuration table, and the message forwarding configuration table is used to store the association relationship between the sub-network port and the physical address; the data forwarding control unit also includes a message forwarding control subunit, and the message forwarding control subunit is used to determine the sub-network port corresponding to the downlink datagram from the message forwarding configuration table according to the physical address of the downlink datagram; and forward the downlink datagram to the sub-network port sending data cache array corresponding to the sub-network port; the data forwarding system only forwards the datagram whose physical address is in the message forwarding configuration table; Using the subnet port to forward the downlink datagram; Wherein, the main network port receiving processing unit includes a receiving data cache array, and the receiving data cache array includes a fifth memory and a sixth memory; The fifth memory is used to store message information of the downlink datagram, the message information includes a physical address of the downlink datagram, the physical address of the downlink datagram is used by the data forwarding control unit to determine the subnet port corresponding to the downlink datagram, and each of the downlink datagrams is forwarded through the corresponding unique subnet port; The sixth memory is used to store the message data of the downlink data packet; the message information also includes the message length of the downlink data packet and the starting address in the sixth memory; the message length and the starting address are used to read the message data from the sixth memory; The method of using the cache array data polling unit to poll the uplink datagram in each of the sub-network ports receiving processing units through a ping-pong operation mechanism includes: Detect whether the first sub-network port receiving processing unit is not empty; if the first sub-network port receiving processing unit is not empty, read the message data from the second memory of the first sub-network port receiving processing unit according to the message information in the first memory of the first sub-network port receiving processing unit; the first sub-network port receiving processing unit is any of the sub-network port receiving processing units in the system; Detect whether the second sub-network port receiving processing unit is not empty; if the second sub-network port receiving processing unit is not empty, read the message data from the second memory of the second sub-network port receiving processing unit according to the message information in the first memory of the second sub-network port receiving processing unit; the second sub-network port receiving processing unit is the next sub-network port receiving processing unit of the first sub-network port receiving processing unit; The transmission data buffer array includes a third memory and a fourth memory, wherein: The third memory is used to receive the message information from the cache array data polling unit and cache the message information; The fourth memory is used to receive the message data from the cache array data polling unit and cache the message data.

3. A computing device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to claim 2 is implemented.

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