Data writing method and system and display panel

Abstract

The invention discloses a data writing method and system and a display panel. The method is used for the display panel, the display panel comprises M data lines and M * N pixel units arranged in an array, the M data lines are in one-to-one correspondence with the M rows of pixel units, each pixel unit comprises K bit storage units, and M, N and K are all integers greater than or equal to 2; the method comprises the steps that a target writing sequence S1, S2,..., SK is determined, S1, S2,..., SK belongs to [1, K], and S1 is not equal to S2,..., SK; and for each row of pixel units, sequentially writing data on a corresponding data line into the S1 bit storage units of the first to Nth columns of pixel units in the row, and then sequentially writing the data into the S2 bit storage units of the first to Nth columns of pixel units in the row until the data are sequentially written into the SK bit storage units of the first to Nth columns of pixel units in the row. According to the method, the data at the same bit position is transmitted at the same time, so that the flipping rate of a single data line can be reduced, and the flipping power consumption of the data line in the display panel can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a data writing method, system and display panel. Background Art

[0002] The driver backplane of Micro Light Emitting Diode Display (Micro LED) has large pixel data volume and high resolution. At present, the data line of the active area (AA) in the Micro LED driver backplane adopts a pixel-level data flipping solution, which has a high flipping rate, making pixel data refresh complicated and consuming a lot of power. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, the purpose of the present invention is to provide a data writing method, system and display panel to reduce the flip rate of the data line and reduce power consumption.

[0004] To solve the above technical problems, an embodiment of the first aspect of the present invention proposes a data writing method, which is used for a display panel, wherein the display panel includes M data lines and M*N pixel units arranged in an array, the M data lines correspond to M rows of pixel units one by one, the pixel units include K bit storage units, and M, N, and K are all integers greater than or equal to 2; the method comprises: determining a target writing sequence S1, S2, ..., S K , where S1, S2, …, S K ∈[1,K] and S1≠S2≠…≠S K For each row of pixel units, the data on the corresponding data line is first written into the S1th bit storage unit of the pixel units in the 1st to Nth columns of the row, and then written into the S2th bit storage unit of the pixel units in the 1st to Nth columns of the row, until the S2nd bit storage unit of the pixel units in the 1st to Nth columns of the row is completed. K bit storage unit.

[0005] In addition, the data writing method of the embodiment of the present invention may also have the following additional technical features:

[0006] According to one embodiment of the present invention, data on the corresponding data line is sequentially written into the same bit storage unit of the pixel units in the 1st to Nth columns of each row according to N write enable signals, wherein the N write enable signals correspond one-to-one to the N columns of pixel units.

[0007] According to an embodiment of the present invention, the write enable signal is a periodic signal, and the period is a signal period, each data writing period includes K signal periods, and the N write enable signals at any time in each signal period are complementary; wherein, in the i-th signal period, the data on the corresponding data line is written into the S-th pixel unit of the 1st to Nth columns of the corresponding row according to the N write enable signals in the signal period. i bit storage units, where i∈[1,K].

[0008] According to one embodiment of the present invention, the write enable signal is a periodic signal, and the period is a data writing period, each of the data writing periods includes a write enable signal generation period and K-1 counting periods, and the N write enable signals at any time in the write enable signal generation period are complementary; wherein, in the write enable signal generation period, for each received write enable signal of the first level, counting is performed respectively, and according to the N write enable signals in the write enable signal generation period, the data on the corresponding data line is written into the S1th bit storage unit of the pixel unit in the 1st to Nth columns of the corresponding row; in the jth counting period, for each count value that reaches a preset value, re-counting is performed respectively, and according to the N count values ​​in the counting period, the data on the corresponding data line is written into the S1th bit storage unit of the pixel unit in the 1st to Nth columns of the corresponding row. j bit storage units, where j∈[2,K].

[0009] According to an embodiment of the present invention, the value of K is 2-16.

[0010] In order to solve the above technical problems, an embodiment of the second aspect of the present invention proposes a display panel, characterized in that it comprises: M data lines, a write control unit and M*N pixel units arranged in an array, the M data lines correspond one-to-one to the M rows of pixel units, the pixel units comprise an enable module and K bit storage units, M, N, K are all integers greater than or equal to 2; the write control unit is used to determine the target write sequence S1, S2, ..., S K , and for each row of pixel units, the data on the corresponding data line is first sequentially written into the S1th bit storage unit of the pixel units in the 1st to Nth columns of the row, and then sequentially written into the S2th bit storage unit of the pixel units in the 1st to Nth columns of the row, until the S2nd bit storage unit of the pixel units in the 1st to Nth columns of the row is completed. K bit storage units, where S1, S2, ..., S K ∈[1,K] and S1≠S2≠…≠S K .

[0011] In addition, the display panel of the embodiment of the present invention may also have the following additional technical features:

[0012] According to one embodiment of the present invention, the pixel unit also includes an enable module, which is respectively connected to the K bit storage units, and the write control unit has N write enable signal output terminals corresponding to the N columns of pixel units; wherein the write control unit is used to generate N write enable signals, and transmit the N write enable signals to the enable modules in the corresponding columns of pixel units through the N write enable signal output terminals, so as to write the data on the corresponding data line into the same bit storage unit of the pixel units in the 1st to Nth columns of the row in sequence through the N enable modules in each row.

[0013] According to an embodiment of the present invention, the write enable signal is a periodic signal, and the period is a signal period, each data write period includes K signal periods, and the write control unit is used to generate N complementary write enable signals in each signal period; the N enable modules in each row of the pixel units are used to write the data on the corresponding data line into the Sth pixel unit of the 1st to Nth columns of the corresponding row according to the N write enable signals in the signal period in the i-th signal period. i bit storage units, where i∈[1,K].

[0014] According to one embodiment of the present invention, the write enable signal is a non-periodic signal, and the period is a data writing period, each of the data writing periods includes a write enable signal generation period and K-1 counting periods, the write control unit is used to generate N complementary write enable signals in the write enable signal generation period; the N enable modules in each row of the pixel units are used to: in the write enable signal generation period, respectively count each received write enable signal of the first level, and write the data on the corresponding data line into the S1th bit storage unit of the pixel unit in the 1st to Nth columns of the corresponding row according to the N write enable signals in the write enable signal generation period; in the jth counting period, respectively re-count each count value that reaches a preset value, and write the data on the corresponding data line into the S1th bit storage unit of the pixel unit in the 1st to Nth columns of the corresponding row according to the N count values ​​in the counting period. j bit storage units, where j∈[2,K].

[0015] To solve the above technical problems, an embodiment of the third aspect of the present invention proposes a data writing system, comprising: the display panel described in the above second aspect embodiment; a processor, respectively connected to N data lines in the display panel, for writing data to the display panel through the data lines.

[0016] The data writing method, system and display panel of the embodiments of the present invention change the data transmission order so that the data on the data line is transmitted bit by bit without basically changing the original transmission architecture, and reduce the flipping rate of a single data line by simultaneously transmitting data at the same bit position, thereby reducing the data line flipping power consumption in the display panel.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flow chart of a data writing method according to an embodiment of the present invention;

[0019] Figure 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

[0020] Figure 3 is a schematic structural diagram of a pixel unit according to an embodiment of the present invention;

[0021] Figure 4 is a schematic diagram of a data writing process according to an embodiment of the present invention;

[0022] Figure 5 is a schematic diagram comparing an exemplary solution of the present invention with a conventional solution;

[0023] Figure 6 is another schematic diagram comparing the solution of the present invention and the traditional solution;

[0024] Figure 7 is a schematic diagram of a data writing process of an example conventional method;

[0025] Figure 8 is a structural schematic diagram of a data writing system of an example of the present invention;

[0026] Fig. 9 is a schematic structural diagram of a display panel according to another embodiment of the present invention;

[0027] Fig.10 It is a structural diagram of a data writing system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0029] The data writing method, system and display panel according to the embodiments of the present invention are described below with reference to the accompanying drawings.

[0030] Figure 1 is a flow chart of a data writing method according to an embodiment of the present invention.

[0031] In this embodiment, the data writing method is used for a display panel. Figure 2 As shown, the display panel 200 includes M data lines (respectively denoted as Data1, Data2, ..., DataM) and M*N (resolution) pixel units 210 arranged in an array, and the M data lines correspond to the M rows of pixel units 210 one by one. Figure 3 As shown, the pixel unit 210 includes K bit storage units 211. Wherein, M, N, and K are all integers greater than or equal to 2. Figure 2 Taking M=N as an example, Figure 3 In the figure, K=8 is taken as an example.

[0032] like Figure 1 As shown, the data writing method includes:

[0033] S101, determine the target writing sequence S1, S2, ..., S K , where S1, S2, …, S K ∈[1,K] and S1≠S2≠…≠S K .

[0034] The target writing sequence is S1, S2, ..., S K It may be a preset order, and the preset order may be determined according to the characteristics of the pixel data.

[0035] S102, for each row of pixel units, the data on the corresponding data line is first sequentially written into the S1th bit storage unit of the pixel units of the 1st to Nth columns in the row, and then sequentially written into the S2nd bit storage unit of the pixel units of the 1st to Nth columns in the row, until the S2nd bit storage unit of the pixel units of the 1st to Nth columns in the row is completed. K bit storage unit.

[0036] In some embodiments of the present invention, data on corresponding data lines can be sequentially written into the same bit storage unit of pixel units in the 1st to Nth columns of each row according to N write enable signals, wherein the N write enable signals correspond one-to-one to the pixel units in the N columns.

[0037] Specifically, see Figure 2 , Figure 3, corresponding to each column of pixel units, a write enable signal is applied, a total of N write enable signals, respectively recorded as wen1, wen2, ..., wenN. When writing data to each row of pixel units, the data on the corresponding data line can be written into the bit storage unit at the same position in each pixel unit of the row according to the N write enable signals, taking advantage of the high continuity of pixel data at the same position between adjacent pixel units. For example, for one Data line (i.e., data line) of each row of pixel units, the data on the data line can be written into the Sth bit storage unit of pixel units 1 to N (resolution) according to the N write enable signals. i bit storage unit, S i ∈[1,K]. For each pixel unit in each row with K bits of storage units, the above S can be performed K times continuously. i Position (S per transmission i Thus, compared with the traditional data pixel-level transmission (i.e., the data on the data line is flipped and transmitted inside each pixel unit), the data writing method of the present invention can realize data bit-level transmission, with low data line flip rate and low power consumption.

[0038] In some embodiments of the present invention, the write enable signal is a periodic signal, and the period is a signal period, each data writing period includes K signal periods, and the N-way write enable signals at any time in each signal period are complementary. Among them, in the i-th signal period, according to the N-way write enable signals in the signal period, the data on the corresponding data line is written into the S-th pixel unit of the 1st to Nth columns of the corresponding row. i bit storage units, where i∈[1,K].

[0039] The first level may be a high level or a low level, which may be specifically determined according to the structure of the bit storage unit.

[0040] Specifically, see Figure 4 Example 1, combined with Figure 3In the first signal cycle, the write enable signal wen1 corresponding to the pixel unit in the first column is at a high level, and the write enable signal wen2 corresponding to the pixel unit in the second column is at a low level. The data on Data1 is written into the first position bit storage unit 1-1(1) of the pixel unit in the first column and the first row, and the data on Data2 is written into the first position bit storage unit 2-1(1) of the pixel unit in the first column and the second row; the write enable signal wen1 corresponding to the pixel unit in the first column becomes a low level, and the write enable signal wen2 corresponding to the pixel unit in the second column becomes a high level. The data on Data1 is written into the first position bit storage unit 1-2(1) of the pixel unit in the second column and the first row, and the data on Data2 is written into the first position bit storage unit 2-2(1) of the pixel unit in the second column and the second row, and so on, until the data is written into the first position bit storage unit in the pixel units in each row and column.

[0041] In the second signal cycle, the write enable signal wen1 corresponding to the pixel unit in the first column is at a high level, and the write enable signal wen2 corresponding to the pixel unit in the second column is at a low level. The data on Data1 is written into the second position bit storage unit 1-1(2) of the pixel unit in the first column and the first row, and the data on Data2 is written into the second bit storage unit 2-1(2) of the pixel unit in the first column and the second row; the write enable signal wen1 corresponding to the pixel unit in the first column becomes a low level, and the write enable signal wen2 corresponding to the pixel unit in the second column becomes a high level. The data on Data1 is written into the second position bit storage unit 1-2(2) of the pixel unit in the second column and the first row, and the data on Data2 is written into the second position bit storage unit 2-2(2) of the pixel unit in the second column and the second row, and so on, until the data is written into the first position bit storage unit in the pixel units in each row and column.

[0042] By analogy, the data writing of the 8 position bit storage units in the pixel units of each row and column is completed, that is, one data writing cycle is completed.

[0043] In the above example, S1=1, S2=2, ..., S i =i, ..., S K = 8. The sequence 1, 2, ..., i, ..., 8 is exemplary and can be adjusted according to the characteristics of pixel data, such as writing data with a value of 0 first and then transmitting data with a value of 1, or writing data with a value of 1 first and then transmitting data with a value of 0, so as to make the signal flip rate better.

[0044] Since a complete frame of pixel data has 8-bit pixel data between adjacent pixels, the pixel data continuity of each bit is high and the flip rate is lower than the flip rate within the 8-bit data, thereby reducing the flip rate of the entire data line.

[0045] In this embodiment, each data is valid (i.e. needs to be written), and a valid wen signal (such as a high level) is given to achieve this, that is, each write enable signal flips K times, corresponding to writing K bits of pixel data. Compared with traditional pixel-level data transmission, although the write enable signal flip rate is increased in this embodiment, the number of nodes on the write enable signal line is 1 / K of the number of nodes on the data line, so there is a power consumption advantage; at the same time, this embodiment has a WEN Gen module (such as Figure 3 No new feature requirements are required.

[0046] In some other embodiments of the present invention, the write enable signal is a periodic signal, and the period is a data writing period, each data writing period includes a write enable signal generation period and K-1 counting periods, and the N write enable signals at any time in the write enable signal generation period are complementary; wherein, in the write enable signal generation period, for each received write enable signal of the first level, counting is performed respectively, and according to the N write enable signals in the write enable signal generation period, the data on the corresponding data line is written into the S1th bit storage unit of the pixel unit of the 1st to Nth columns of the corresponding row; in the jth counting period, for each count value reaching a preset value, re-counting is performed respectively, and according to the N count values ​​in the counting period, the data on the corresponding data line is written into the S1th bit storage unit of the pixel unit of the 1st to Nth columns of the corresponding row. j bit storage units, where j∈[2,K].

[0047] The first level may be a high level or a low level, which may be specifically determined according to the structure of the bit storage unit.

[0048] Specifically, see Figure 4 Example 2 in , combined with Figure 3, during the write enable signal generation period, the write enable signal wen1 corresponding to the pixel unit in the first column is at a high level, each WEN Gen module in the pixel unit in the first column starts counting, the write enable signal wen2 corresponding to the pixel unit in the second column is at a low level, the data on Data1 is written into the 7th position bit storage unit 1-1(7) of the pixel unit in the first column and the first row, and the data on Data2 is written into the 7th position bit storage unit 2-1(7) of the pixel unit in the first column and the second row; the write enable signal wen1 corresponding to the pixel unit in the first column becomes a low level, the write enable signal wen2 corresponding to the pixel unit in the second column becomes a high level, each WEN Gen module in the pixel unit in the second column starts counting, the data on Data1 is written into the 7th position bit storage unit 1-2(7) of the pixel unit in the second column and the first row, and the data on Data2 is written into the 7th position bit storage unit 2-2(7) of the pixel unit in the second column and the second row, and so on, until the data writing to the 7th position bit storage unit in the pixel units in each row and column is completed.

[0049] In the first counting cycle, the count value corresponding to wen1 reaches the preset value (the corresponding technical time can be equivalent to the signal cycle of the above embodiment), and the count value corresponding to wen2 does not reach the preset value, the data on Data1 is written into the 1st position bit storage unit 1-1(1) of the 1st column and 1st row pixel unit, and the data on Data2 is written into the 1st bit storage unit 2-1(1) of the 1st column and 2nd row pixel unit; the count value corresponding to wen1 is recounted, and the count value corresponding to wen2 reaches the preset value, the data on Data1 is written into the 1st position bit storage unit 1-2(1) of the 2nd column and 1st row pixel unit, and the data on Data2 is written into the 1st position bit storage unit 2-2(1) of the 2nd column and 2nd row pixel unit, and so on, until the data is written into the 1st position bit storage unit in each row and column of the pixel unit.

[0050] By analogy, the data writing of the 8 position bit storage units in the pixel units of each row and column is completed, that is, one data writing cycle is completed.

[0051] The above example transmits write data in the order of S1=7, S2=1, S3=3, S4=4, S5=5, S6=6, ... This order is exemplary and can be adjusted according to the characteristics of the pixel data, such as preferentially writing data with a value of 0 and then transmitting data with a value of 1, or preferentially writing data with a value of 1 and then transmitting data with a value of 0, so as to make the signal flip rate better.

[0052] In this embodiment, the bit position data to be written to each pixel unit can be selected by counting inside the WEN Gen module. This embodiment can maintain the write enable signal line flip rate unchanged while reducing the data line flip.

[0053] The above scheme uses different signal transmission methods to enable the data bits of the same pixel unit to be refreshed and written after N data cycles.

[0054] The following describes the data continuity in the above embodiment:

[0055] Figure 5 Take the resolution of 2*2, 8bit display pixel data as 1010_1010 as an example. Figure 6 For example, the resolution is 2*2, and the 16-bit display pixel data is 1010_1010_1010_1010. Figure 5 , Figure 6 As shown, the conventional scheme transmits data at the pixel level, while the scheme of the present invention transmits data at the bit level. Compared with the conventional scheme, the data line flip rate of the scheme of the present invention is half of that of the conventional scheme, which can significantly reduce the data line flip rate.

[0056] like Figure 7 As shown, in the pixel-level data transmission method in the traditional scheme, each bit storage unit in each row of pixel units writes data one by one. Taking the resolution N*N, the entire backplane displays 1010_1010 with a total of 8 bits of pixel data as an example, the total number of node flips in the traditional scheme is: 8*N (number of nodes)*8*N (number of data flips)*N (N data lines); the total number of node flips in the scheme of the present invention is: 8*N (number of nodes)*8 (number of data flips)*N (N data lines). Obviously, the total number of node flips in the scheme of the present invention is 1 / N of the traditional scheme, which can reduce the dynamic power consumption caused by data line flipping compared to the window scheme.

[0057] In some embodiments of the present invention, Figure 8 As shown, the data on the data line can be packaged and transmitted by the System on Chip (SoC). Before the data is packaged and transmitted, the SoC can process the pixel data into the required format package by bit through the instruction software operation, and transmit it through the Mobile Industry Processor Interface (MIPI). Specifically, the MIPI interface for the display panel (Display Serial Interface, DSI) internal storage module and control module and other hardware circuits can be used to directly package the pixel data bits into the required format package for transmission. After the data is transmitted to the display panel, it is written according to the above data writing method Figure 8 AA area in.

[0058] In summary, the data writing method of the embodiment of the present invention aims at the problem that the data line flip rate of the Active Area of ​​the Micro LED driving backplane is high, resulting in large corresponding dynamic power consumption. Considering the complexity of data line routing and layout design, serial input data is adopted and written into the SRAM inside the Pixel by bit. It is specifically proposed to change the data transmission order, adapt a certain write enable signal on the basis of basically not changing the original transmission architecture, so that the data on the data line is transmitted by bit, that is, the data is first transmitted to the bit storage unit of a certain bit position of each pixel unit in the corresponding row, and then the data is transmitted to the bit storage unit of another bit position of each pixel unit in the corresponding row, and so on, to complete the data transmission of the entire display panel. Therefore, this method utilizes the characteristic that the data at the same bit position of adjacent pixel units is relatively continuous, and by simultaneously transmitting the data at the same bit position, the flip rate of a single data line is reduced, thereby reducing the data line flip power consumption in the display panel.

[0059] Fig. 9 is a schematic structural diagram of a display panel according to another embodiment of the present invention.

[0060] like Fig. 9 As shown, the display panel 200 includes: M data lines (respectively denoted as Data1, Data2, ..., DataM), a write control unit 220, and M*N pixel units 210 arranged in an array, and the M data lines correspond to the M rows of pixel units 210 one by one. Figure 3 As shown, the pixel unit 210 includes K bit storage units 211. Wherein, M, N, and K are all integers greater than or equal to 2. Fig. 9 Taking M=N as an example, Figure 3 In the figure, K=8 is taken as an example.

[0061] In this embodiment, the write control unit 220 is used to determine the target write sequence S1, S2, . . . , S K , and for each row of pixel units 210, the data on the corresponding data line is first sequentially written into the S1th bit storage unit 211 of the 1st to Nth column pixel units 210 of the row, and then sequentially written into the S2th bit storage unit 211 of the 1st to Nth column pixel units 210 of the row, until the S2nd bit storage unit 211 of the 1st to Nth column pixel units 210 of the row is completed. K bit storage units 211, where S1, S2, ..., S K ∈[1,K] and S1≠S2≠…≠S K .

[0062] In some embodiments of the present invention, see Figure 3The pixel unit 210 further includes an enabling module 212, which is respectively connected to the K bit storage units 211. The write control unit 220 has N write enable signal output terminals, which correspond to the N columns of pixel units 210 one by one.

[0063] The write control unit 220 is used to generate N write enable signals, and transmit the N write enable signals to the enable modules 212 in the corresponding columns of pixel units 210 through N write enable signal output terminals. The N enable modules 212 in each row of pixel units are used to write the data on the corresponding data line into the same bit storage unit 211 in the 1st to Nth columns of the row of pixel units 210 according to the N write enable signals.

[0064] In some embodiments of the present invention, the write enable signal is a periodic signal, and the period is a signal period. Each data write period includes K signal periods. The write control unit 220 is used to generate N complementary write enable signals in each signal period.

[0065] The N enable modules 212 in each row of pixel units 210 are used to write the data on the corresponding data line into the Sth pixel unit 210 of the 1st to Nth columns of the corresponding row according to the N write enable signals in the signal cycle in the i-th signal cycle. i bit storage units 211, where i∈[1,K].

[0066] In some other embodiments of the present invention, the write enable signal is a periodic signal, and the period is a data write period, each data write period includes a write enable signal generation period and K-1 counting periods, the write control unit 220 is used to generate N complementary write enable signals in the write enable signal generation period; the N enable modules 212 in each row of pixel units are used to:

[0067] In the write enable signal generation period, for each received write enable signal of the first level, counts are performed respectively, and the data on the corresponding data line is written into the S1-th bit storage unit 211 of the pixel unit 210 of the 1st to Nth columns of the corresponding row according to the N-way write enable signal in the write enable signal generation period;

[0068] In the jth counting cycle, for each count value reaching the preset value, the counting is performed again, and the data on the corresponding data line is written into the Sth pixel unit 210 of the 1st to Nth columns of the corresponding row according to the N count values ​​in the counting cycle. j bit storage units 211, where j∈[2,K].

[0069] It should be noted that, for other specific implementations of the display panel 200 of the embodiment of the present invention, reference may be made to the specific implementation of the data writing method of the above embodiment of the present invention.

[0070] Fig.10 It is a structural diagram of a data writing system according to an embodiment of the present invention.

[0071] like Fig.10 As shown, the data writing system 1000 includes: a processor 300 and the display panel 200 of the above embodiment. The processor 300 is respectively connected to N data lines in the display panel 200, and is used to write data to the display panel 200 through the data lines.

[0072] The processor 300 may adopt a system on chip.

[0073] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory unit (RAM), a read-only memory unit (ROM), an erasable and editable read-only memory unit (EPROM or flash memory unit), an optical fiber device, and a portable compact disk read-only memory unit (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then storing it in a computer storage unit.

[0074] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiment, a plurality of steps or methods can be implemented by software or firmware stored in a storage unit and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0075] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0076] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0077] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0078] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0079] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0080] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A data writing method, characterized in that: The method is used for a display panel, the display panel includes M data lines and M*N pixel units arranged in an array, the M data lines correspond one-to-one to M rows of pixel units, the pixel units include K bit storage units, M, N, K are all integers greater than or equal to 2; the method includes: Determine the target write order S1, S2, ..., S K , where S1, S2, …, S K ∈[1,K] and S1≠S2≠…≠S K ; For each row of pixel units, the data on the corresponding data line is first written into the S1th bit storage unit of the pixel units in the 1st to Nth columns of the row, and then written into the S2th bit storage unit of the pixel units in the 1st to Nth columns of the row, until the S2nd bit storage unit of the pixel units in the 1st to Nth columns of the row is completed. K bit storage unit.

2. The data writing method according to claim 1, characterized in that: The data on the corresponding data line are sequentially written into the same bit storage unit of the pixel units in the 1st to Nth columns of each row according to N write enable signals, wherein the N write enable signals correspond one-to-one to the Nth columns of the pixel units.

3. The data writing method according to claim 2, characterized in that: The write enable signal is a periodic signal, and the period is a signal period, each data write period includes K signal periods, and the N write enable signals at any time in each signal period are complementary; wherein, In the ith signal cycle, the data on the corresponding data line is written into the Sth pixel unit of the 1st to Nth columns of the corresponding row according to the N write enable signals in the signal cycle. i bit storage units, where i∈[1,K].

4. The data writing method according to claim 2, characterized in that: The write enable signal is a periodic signal, and the period is a data write period, each of the data write periods includes a write enable signal generation period and K-1 counting periods, and the N channels of the write enable signals at any time in the write enable signal generation period are complementary; wherein, In the write enable signal generation period, for each received write enable signal of the first level, counting is performed respectively, and according to the N write enable signals in the write enable signal generation period, the data on the corresponding data line is written into the S1th bit storage unit of the pixel unit in the 1st to Nth columns of the corresponding row; In the jth counting cycle, for each count value that reaches the preset value, re-counting is performed, and the data on the corresponding data line is written into the Sth pixel unit in the 1st to Nth columns of the corresponding row according to the N count values ​​in the counting cycle. j bit storage units, where j∈[2,K].

5. The data writing method according to claim 1, characterized in that: The value of K ranges from 2 to 16.

6. A display panel, characterized in that: include: M data lines, a write control unit, and M*N pixel units arranged in an array, wherein the M data lines correspond one-to-one to the M rows of pixel units, the pixel units include K bit storage units, and M, N, and K are all integers greater than or equal to 2; The write control unit is used to determine the target write sequence S1, S2, ..., S K , and for each row of pixel units, the data on the corresponding data line is first sequentially written into the S1th bit storage unit of the pixel units in the 1st to Nth columns of the row, and then sequentially written into the S2th bit storage unit of the pixel units in the 1st to Nth columns of the row, until the S2nd bit storage unit of the pixel units in the 1st to Nth columns of the row is completed. K bit storage units, where S1, S2, ..., S K ∈[1,K] and S1≠S2≠…≠S K .

7. The display panel according to claim 6, characterized in that: The pixel unit further includes an enabling module, the enabling module is connected to the K bit storage units respectively, and the write control unit has N write enable signal output terminals corresponding to the N columns of pixel units one by one; Among them, the write control unit is used to generate N write enable signals, and transmit the N write enable signals to the enable modules in the corresponding columns of pixel units through the N write enable signal output terminals, so as to write the data on the corresponding data line into the same bit storage unit of the pixel units in the 1st to Nth columns of the row in sequence through the N enable modules in each row.

8. The display panel according to claim 7, characterized in that: The write enable signal is a periodic signal, and the period is a signal period, each data write period includes K signal periods, and the write control unit is used to generate N complementary write enable signals in each signal period; The N enabling modules in each row of the pixel units are used to write the data on the corresponding data line into the Sth pixel units in the 1st to Nth columns of the corresponding row according to the N write enable signals in the signal cycle in the i-th signal cycle. i bit storage units, where i∈[1,K].

9. The display panel according to claim 7, characterized in that: The write enable signal is a periodic signal, and the period is a data write period, each of the data write periods includes a write enable signal generation period and K-1 counting periods, the write control unit is used to generate N complementary write enable signals in the write enable signal generation period; the N enable modules in each row of the pixel units are used to: In the write enable signal generation period, for each received write enable signal of the first level, counting is performed respectively, and according to the N write enable signals in the write enable signal generation period, the data on the corresponding data line is written into the S1th bit storage unit of the pixel unit in the 1st to Nth columns of the corresponding row; In the jth counting cycle, for each count value that reaches the preset value, re-counting is performed, and the data on the corresponding data line is written into the Sth pixel unit of the 1st to Nth columns of the corresponding row according to the N count values ​​in the counting cycle. j bit storage units, where j∈[2,K].

10. A data writing system, characterized in that: include: The display panel according to any one of claims 6 to 9; The processor is connected to the N data lines in the display panel respectively, and is used to write data to the display panel through the data lines.

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