Power consumption optimization method, device, apparatus and storage medium

Abstract

The application discloses a power consumption optimization method and device, equipment and a storage medium, and the method comprises the following steps: obtaining an RTL backward SAIF file based on a preset RTL design file of a target integrated circuit, reading the RTL backward SAIF file into a preset back-end design software to perform timing unit layout on the target integrated circuit; and performing power consumption optimization on the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimization command when the timing unit layout is performed. The application can generate an RTL backward SAIF file based on a preset RTL design file, obtain the switching behavior of the preset RTL design file through the RTL backward SAIF file, perform power consumption analysis based on the RTL backward SAIF file and the preset power consumption driving optimization command, and finally, the timing units with high flip rates in the target integrated circuit are gathered and configured through the switching behavior and the power consumption analysis result, so that the power consumption of the target integrated circuit is reduced.

Description

Technical Field

[0001] This invention relates to the field of electronic digital data processing technology, and in particular to a power consumption optimization method, apparatus, device, and storage medium. Background Technology

[0002] In the process of integrated circuit chip design, the power consumption of the designed integrated circuit must be considered. Since the clock signal is the signal with the highest switching frequency, the largest driving load and the longest transmission distance in the entire chip, clock tree design is one of the main directions of low-power physical design of integrated circuits.

[0003] Currently, gated clocks are typically used to shut down unnecessary clocks through logic operations; or traditional low-power design methods such as multi-voltage domain technology and power-off technology are used to reduce circuit power consumption.

[0004] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this invention is to provide a power consumption optimization method, apparatus, device, and storage medium, specifically a power consumption optimization method based on SAIF files for timing cell layout optimization. To achieve the above objective, this invention provides a power consumption optimization method. The method includes the following steps:

[0006] Based on the pre-defined RTL design file of the target integrated circuit, obtain the RTL backward SAIF file;

[0007] The RTL backward SAIF file is read into the preset back-end design software by a preset read command. The preset back-end design software is used to perform timing cell placement on the target integrated circuit.

[0008] During the timing cell layout, power optimization is performed on the target integrated circuit based on the RTL backward SAIF file and the preset power driving optimization command optDynamicPower.

[0009] Optionally, the step of obtaining an RTL backward SAIF file based on a preset RTL design file of the target integrated circuit includes:

[0010] Based on the pre-defined RTL design file of the target integrated circuit, obtain the RTL forward SAIF file;

[0011] Input the initial testbench test platform file, the preset RTL design file, and the RTL forward SAIF file into VCS to obtain the RTL backward SAIF file.

[0012] Optionally, the step of obtaining an RTL forward SAIF file based on a preset RTL design file of the target integrated circuit includes:

[0013] The preset RTL design file of the target integrated circuit is loaded into the VCS. The VCS is used to convert the preset RTL design file into a gate-level netlist and output an RTL forward SAIF file after the preset RTL design file is converted.

[0014] Optionally, the step of inputting the initial testbench test platform file, the preset RTL design file, and the RTL forward SAIF file into the VCS to obtain the RTL backward SAIF file includes:

[0015] Import the initial testbench test platform file into VCS and start the testbench;

[0016] The testbench calls the RTL forward SAIF file and the preset RTL design file, so that the RTL forward SAIF file and the preset RTL design file are loaded into the VCS;

[0017] In the testbench, a preset PLI system function is called to obtain the node flip rate of the RTL forward SAIF file;

[0018] Based on the node flip rate of the RTL forward SAIF file, the preset RTL design file is simulated in the VCS to obtain the RTL backward SAIF file.

[0019] Optionally, the step of optimizing the power consumption of the target integrated circuit based on the RTL backward SAIF file and the preset power consumption drive optimization command optDynamicPower during the timing cell layout includes:

[0020] Based on the RTL backward SAIF file, obtain the switching behavior information of the integrated invariant in the preset RTL design file;

[0021] The preset power consumption drive optimization command optDynamicPower is invoked to obtain the power consumption analysis results of the preset RTL design file;

[0022] Based on the power consumption analysis results and the switching behavior information of the integrated invariant in the preset RTL design file, the timing cells in the target integrated circuit that exceed the preset toggle rate are obtained;

[0023] When performing the timing cell layout, timing cells in the target integrated circuit that exceed a preset flip-flop rate are grouped together.

[0024] Optionally, the step of calling the preset power consumption drive optimization command optDynamicPower to obtain the power consumption analysis results of the preset RTL design file includes:

[0025] The preset power consumption drive optimization command optDynamicPower is invoked to analyze the component information of the preset RTL design file and obtain the component power consumption analysis of the preset RTL design file.

[0026] The preset power consumption drive optimization command optDynamicPower is invoked to analyze the node information of the preset RTL design file and obtain the component switching power consumption analysis of the preset RTL design file.

[0027] Based on the power consumption analysis of the components and the power consumption analysis of the component switches, the power consumption analysis results of the preset RTL design file are obtained.

[0028] Optionally, the step of calling the preset power consumption drive optimization command optDynamicPower to analyze the node information of the preset RTL design file and obtain the component switching power consumption analysis of the preset RTL design file includes:

[0029] The preset power consumption driver optimization command optDynamicPower is invoked to read the RTL backward SAIF file, and the toggle ratio in the RTL backward SAIF file is back-annotated to the file node of the preset RTL design file.

[0030] The file nodes in the preset RTL design file are traversed to obtain the back-annotation rate of each file node, and the component switching power consumption analysis of the preset RTL design file is obtained.

[0031] Furthermore, to achieve the above objectives, the present invention also proposes a power consumption optimization device, the power consumption optimization device comprising:

[0032] The analysis module is used to obtain an RTL backward SAIF file based on a preset RTL design file of the target integrated circuit.

[0033] The reading module is used to read the RTL backward SAIF file into a preset back-end design software through a preset reading command. The preset back-end design software is used to perform timing cell placement on the target integrated circuit.

[0034] An optimization module is used to optimize the power consumption of the target integrated circuit based on the RTL backward SAIF file and the preset power consumption drive optimization command optDynamicPower when performing the timing cell layout.

[0035] Furthermore, to achieve the above objectives, the present invention also proposes a power optimization device, the device comprising: a memory, a processor, and a power optimization program stored in the memory and executable on the processor, the power optimization program being configured to implement the steps of the power optimization method as described above.

[0036] Furthermore, to achieve the above objectives, the present invention also proposes a storage medium storing a power optimization program, which, when executed by a processor, implements the steps of the power optimization method described above.

[0037] This invention generates an RTL backward SAIF file based on a preset RTL design file of the target integrated circuit. A preset read command is used to read the RTL backward SAIF file into back-end design software, which is then used for timing cell placement of the target integrated circuit. During timing cell placement, power optimization is performed on the target integrated circuit based on the RTL backward SAIF file and the preset power-driven optimization command `optDynamicPower`. This invention can generate an RTL backward SAIF file based on the preset RTL file of the target integrated circuit, obtain the switching behavior of the preset RTL design file through the RTL backward SAIF file, perform power analysis based on the RTL backward SAIF file and the preset power-driven optimization command, and finally, based on the switching behavior and power analysis results, cluster high-flip-rate timing cells in the target integrated circuit, thereby reducing the wiring length between high-flip-rate timing cells and reducing switching power consumption. Therefore, this invention can reduce the power consumption of the target integrated circuit. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the power consumption optimization device for the hardware operating environment involved in the embodiments of the present invention;

[0039] Figure 2 This is a flowchart illustrating the first embodiment of the power consumption optimization method of the present invention;

[0040] Figure 3 This is a flowchart illustrating the second embodiment of the power consumption optimization method of the present invention;

[0041] Figure 4 This is a flowchart illustrating the third embodiment of the power consumption optimization method of the present invention;

[0042] Figure 5 This is a structural block diagram of the first embodiment of the power consumption optimization device of the present invention.

[0043] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0044] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0045] Reference Figure 1 , Figure 1 This is a schematic diagram of the power consumption optimization device structure for the hardware operating environment involved in the embodiments of the present invention.

[0046] like Figure 1 As shown, the power optimization device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wireless-Fidelity (Wi-Fi) interface). The memory 1005 may be high-speed random access memory (RAM) or stable non-volatile memory (NVM), such as a disk drive. The memory 1005 may also optionally be a storage device independent of the aforementioned processor 1001.

[0047] Those skilled in the art will understand that Figure 1 The structure shown does not constitute a limitation on the power optimization device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0048] like Figure 1 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a data storage module, a network communication module, a user interface module, and a power optimization program.

[0049] exist Figure 1 In the power optimization device shown, the network interface 1004 is mainly used for data communication with the network server; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in the power optimization device of the present invention can be set in the power optimization device, and the power optimization device calls the power optimization program stored in the memory 1005 through the processor 1001 and executes the power optimization method provided in the embodiment of the present invention.

[0050] This invention provides a power consumption optimization method, referring to... Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the power consumption optimization method of the present invention.

[0051] In this embodiment, the power consumption optimization method includes the following steps:

[0052] Step S10: Obtain the RTL backward SAIF file based on the preset RTL design file of the target integrated circuit;

[0053] It should be noted that the executing entity of the method in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer or personal computer, or other electronic devices capable of performing the same or similar functions. Here, the power optimization methods provided in this embodiment and the following embodiments will be specifically described using the aforementioned power optimization device (hereinafter referred to as the optimization device).

[0054] It's important to understand that digital integrated circuits consist of two basic types of devices. One type consists of logic devices whose output signals are only affected by the current state of the input signals; these are called combinational logic devices. These devices have no memory function; the output signal changes with the input signal. The other type consists of logic devices whose output signals depend not only on the current state of the input signal but also on its previous state; these are called sequential logic devices. These devices have memory function. RTL (Register Transfer Level) design refers to using a hardware description language (a language that can describe logic devices, such as Verilog HDL) to describe circuits containing these two types of devices. This description is based on the transfer between registers, hence the name RTL (Register Transfer Level) design. The aforementioned preset RTL design file can be a file generated based on the functional requirements of the target integrated circuit through RTL design.

[0055] It should be noted that the aforementioned preset RTL design file still needs to undergo behavioral simulation, timing simulation, and post-simulation before it can be converted into the target integrated circuit. During the behavioral simulation of the preset RTL design file, a SAIF file is generated. SAIF (Switching Activity Interchange Format) is an ASCII file (or an internal exchange format file recording the switching behavior of an integrated circuit) used to record information exchanged between the simulator and power analysis. After simulating the RTL code, the SAIF file records the static probability and toggle rate of signals on interconnects and cell pins over a period of time under a certain operating scenario. SAIF files can be generated from gate-level netlists or RTL code. The aforementioned RTL backward SAIF file can be obtained by simulating the RTL code in the preset RTL design file. It can be a switching behavior file recording the overall invariant toggle rate in the preset RTL design file. The switching behavior can be the toggle rate and static probability in the preset RTL design file. Toggle refers to a change in the logic value of a node signal, while static refers to the node signal logic value remaining unchanged. Synthesis refers to translating HDL language, schematic diagrams, and other design inputs into gate-level connections (or gate-level netlists) composed of basic logic units such as AND, OR, and NOT gates, optimizing the generated logic connections according to design goals and requirements (or constraints), and outputting a gate-level netlist file. Before and after synthesis, the number and structure of registers in the design remain unchanged, as do the input / output ports and hierarchical boundaries. The black boxes in the design remain unchanged; these invariant objects are the synthesis invariants mentioned above.

[0056] Step S20: The RTL backward SAIF file is read into the preset back-end design software by a preset read command. The preset back-end design software is used to perform timing cell placement on the target integrated circuit.

[0057] It should be noted that after obtaining the aforementioned RTL backward SAIF file, the preset back-end design software can read the RTL backward SAIF file through preset read commands pre-configured within the optimized device. This preset back-end software can be placement and routing tools such as Cadence Innovus or Synopsys ICC2; the specific type of preset back-end software is not limited in this embodiment. Furthermore, the aforementioned timing unit refers to the clock logic device of the integrated circuit.

[0058] Step S30: When performing the timing cell layout, power optimization is performed on the target integrated circuit based on the RTL backward SAIF file and the preset power driving optimization command optDynamicPower.

[0059] It is important to understand that during chip design, once the standard cell placement and clock tree design are completed, the clock lines are generally not modified on a large scale during subsequent optimization to avoid affecting timing. Therefore, the chip power consumption generally does not increase significantly. Thus, the approximate power consumption can be obtained after the timing cell layout is completed.

[0060] It is important to understand that the aforementioned preset power consumption-driven optimization command `optDynamicPower` is an integrated command within Cadence Innovus that can be used to replace cells in the target integrated circuit and optimize power consumption while meeting timing requirements. This embodiment employs a design method that coordinates flip-flop rate and load optimization during the placement phase of the timing cells to achieve low-power design. Specifically, this can be achieved through low-power co-optimization using the preset power consumption-driven optimization command `optDynamicPower`, the command mentioned above (which performs cell replacement and optimizes power consumption while meeting timing requirements), and the aforementioned RTL backward SAIF file.

[0061] This embodiment obtains an RTL backward SAIF file based on a preset RTL design file of the target integrated circuit. A preset read command is used to read the RTL backward SAIF file into preset back-end design software, which is used for timing cell placement of the target integrated circuit. During timing cell placement, power optimization is performed on the target integrated circuit based on the RTL backward SAIF file and the preset power-driven optimization command `optDynamicPower`. This embodiment can generate an RTL backward SAIF file based on the preset RTL file of the target integrated circuit, then obtain the switching behavior of the preset RTL design file through the RTL backward SAIF file, and then perform power analysis based on the RTL backward SAIF file and the preset power-driven optimization command. Finally, based on the switching behavior and power analysis results, the timing cells with high switching rates in the target integrated circuit are clustered together, i.e., the wiring length between high switching rate timing cells is reduced, thereby reducing switching power consumption. Therefore, this embodiment can reduce the power consumption of the target integrated circuit.

[0062] Reference Figure 3 , Figure 3 This is a flowchart illustrating the second embodiment of the power consumption optimization method of the present invention, based on the above. Figure 2 The illustrated embodiment presents a second embodiment of the power consumption optimization method of the present invention.

[0063] like Figure 3 As shown, step S10 in this embodiment includes:

[0064] Step S101: Obtain the RTL forward SAIF file based on the preset RTL design file of the target integrated circuit;

[0065] It should be noted that the aforementioned RTL formward SAIF file can be generated directly from the RTL code of a preset RTL file, or it can be generated during synthesis (the process of converting the RTL code in the preset RTL design file into a gate-level netlist). The RTL formward SAIF file generated during synthesis contains more specific switching activity information from the preset RTL design file, thus improving the accuracy of subsequent power consumption analysis.

[0066] It is important to understand that, specifically, the method for obtaining an RTL-formward SAIF file based on a preset RTL design file of the target integrated circuit can be as follows: In this embodiment, the preset RTL design file can be synthesized using simulation and synthesis tools such as Cadence Genus to obtain the aforementioned RTL-formward SAIF file. Alternatively, the preset RTL design file can be loaded into a VCS (Verilog Compiler Simulator), which can be used to convert the preset RTL design file into a gate-level netlist and output the RTL-formward SAIF file after the conversion is complete.

[0067] Step S102: Input the initial testbench test platform file, the preset RTL design file, and the RTLforward SAIF file into VCS to obtain the RTL backward SAIF file.

[0068] It should be noted that a testbench is a verification method, a "virtual platform" that simulates input stimuli and output verification in a real-world environment. Because there are no input stimuli in a software environment, it's impossible to evaluate the correctness of the design's output, but on a testbench, the design can be analyzed and verified at the software level. In this embodiment, the testbench can run in a VCS, which can be enabled by importing the initial testbench test platform file into the VCS.

[0069] Further, in this embodiment, step S102 includes:

[0070] Step S1021: Input the initial testbench test platform file into VCS and enable the testbench;

[0071] Step S1022: In the testbench, call the RTL forward SAIF file and the preset RTL design file to load the RTL forward SAIF file and the preset RTL design file into the VCS;

[0072] Step S1023: In the testbench, call the preset PLI system function to obtain the node flip rate of the RTL forwardSAIF file;

[0073] Step S1024: Based on the node flip rate of the RTL forward SAIF file, simulate the preset RTL design file in the VCS to obtain the RTL backward SAIF file.

[0074] It should be noted that the testbench can be started after the initial testbench test platform file is imported into VCS. Then, the aforementioned RTL forward SAIF file and the aforementioned preset RTL design file can be called within the testbench to load the RTL forward SAIF file and the preset RTL design file into VCS. Furthermore, the aforementioned preset PLI system functions can be directly called through the testbench. The PLI system functions can detect the flipping of nodes within the file, thereby obtaining the flipping rate of each node within the file. Therefore, in this embodiment, the node flipping rate of the RTL forward SAIF file can be obtained by calling the preset PLI system functions within the testbench.

[0075] It is important to understand that after obtaining the node flip rate of the RTL forward SAIF file, the node flip rate of the RTL forward SAIF file can be loaded into the VCS by inputting the testbench test file again. Simulations can then be run on both the testbench test file and the preset RTL design file simultaneously through the VCS to obtain the RTL backward SAIF file.

[0076] Understandably, after simulating the RTL code in the preset RTL design file, the resulting RTL backwardSAIF file contains the switching behavior information of the synthesis invariants in the preset RTL design. During subsequent power analysis, the tool uses its internal simulator to propagate the toggle rates of the synthesis invariants, thereby obtaining the toggle rates of all other nodes and performing power analysis on the gate-level circuit.

[0077] This embodiment loads a preset RTL design file of the target integrated circuit into a VCS (Virtual Server Controller). The VCS converts the preset RTL design file into a gate-level netlist and outputs an RTL forward SAIF file after the conversion is complete. An initial testbench file is input into the VCS, and the testbench is activated. The RTL forward SAIF file and the preset RTL design file are called within the testbench, loading them into the VCS. A preset PLI (Power Injection Link) system function is called within the testbench to obtain the node toggle rate of the RTL forward SAIF file. Based on the node toggle rate of the RTL forward SAIF file, the preset RTL design file is simulated in the VCS to obtain the RTL backward SAIF file. This embodiment can obtain more switching activity information from the preset RTL design file by generating an RTL forward SAIF file, thus improving the accuracy of the comprehensive invariant toggle rate analysis in the RTL forward SAIF file. This, in turn, improves the accuracy of subsequent power consumption analysis. Therefore, this embodiment can obtain a more accurate power consumption value by improving the accuracy of power consumption calculation, thereby further effectively reducing power consumption.

[0078] Reference Figure 4 , Figure 4 This is a flowchart illustrating the third embodiment of the power consumption optimization method of the present invention, based on the above. Figure 2 Alternatively, as shown in embodiment 3, a third embodiment of the power consumption optimization method of the present invention is proposed. Figure 4 Based on Figure 1 The embodiments shown are examples of the proposed embodiments.

[0079] Furthermore, as one possible implementation, step S30 in this embodiment includes:

[0080] Step S301: Based on the RTL backward SAIF file, obtain the switching behavior information of the integrated invariant in the preset RTL design file;

[0081] Step S302: Call the preset power consumption drive optimization command optDynamicPower to obtain the power consumption analysis results of the preset RTL design file;

[0082] It should be noted that after calling the aforementioned preset power consumption drive optimization command optDynamicPower, CadenceInnovus can perform power consumption analysis on the target integrated circuit based on the component and node information in the preset RTL design file.

[0083] Therefore, further in this embodiment, step S301 includes:

[0084] Step S3021: Call the preset power consumption drive optimization command optDynamicPower to analyze the component information of the preset RTL design file and obtain the component power consumption analysis of the preset RTL design file;

[0085] It should be noted that the component information in the aforementioned preset RTL design file can be a process library containing power consumption information, usually provided by the component foundry; or it can be parasitic parameters such as wiring in the preset RTL design file, such as parasitic capacitance and parasitic resistance. Parasitic parameters are generally provided by backend RC parasitic parameter tools, and simple power consumption analysis usually does not require the analysis of this information.

[0086] Step S3022: Call the preset power consumption drive optimization command optDynamicPower to analyze the node information of the preset RTL design file and obtain the component switching power consumption analysis of the preset RTL design file;

[0087] It should be noted that the node information in the aforementioned preset RTL design file can be the gate-level netlist circuit of the preset RTL design file, which can be obtained by synthesizing the preset RTL design file; it can also be a file containing the switching behavior of each node in the preset RTL design file, such as the node's toggle rate (the number of toggles of clock, data, and other signals per unit time); or it can be a file that calculates the toggle rate of each node. Among these, the analysis of the toggle rate can include three cases:

[0088] (1) If a VCD / SAIF file is provided, the actual flip rate can be back-annotated to the node of the file, and then the power consumption value can be reported by checking the back-annotation rate of the file.

[0089] (2) Manually set the node toggle rate: Set the toggle rate of registers, clock gates and rural memory / black box according to empirical values.

[0090] (3) Use the default flip rate: Use the default flip rate of the simulation tool by setting a variable.

[0091] It is important to understand that, in this embodiment, after obtaining the RTL backward SAIF file, the preset power consumption driven optimization command `optDynamicPower` can be called to read the RTL backward SAIF file and back-annotate the toggle rates in the RTL backward SAIF file to the file nodes of the preset RTL design file. The file nodes in the preset RTL design file are then traversed to obtain the back-annotation rates of each file node, thereby obtaining the component switching power consumption analysis of the preset RTL design file. Specifically, a simulation tool is used to propagate the toggle rates of the synthesized invariant objects in the RTL backward SAIF file through its internal simulator, thereby obtaining the toggle rates of all other nodes in the preset RTL design file, and thus obtaining the component switching power consumption analysis of the preset RTL design file.

[0092] Step S3023: Based on the power consumption analysis of the components and the power consumption analysis of the component switches, obtain the power consumption analysis results of the preset RTL design file.

[0093] Step S303: Based on the power consumption analysis results and the switching behavior information of the integrated invariant in the preset RTL design file, obtain the timing cells in the target integrated circuit that exceed the preset toggle rate;

[0094] It should be noted that after obtaining the power consumption analysis results of the preset RTL design file, the preset toggle rate corresponding to the low power consumption requirement can be obtained based on the power consumption analysis results. Then, based on the switching behavior information of the integrated invariant in the preset RTL design file, the toggle rate of all nodes in the preset RTL design file can be obtained, and the timing cells in the target integrated circuit that exceed the preset toggle rate can be obtained.

[0095] Step S304: When laying out the timing cells, group together the timing cells in the target integrated circuit that exceed the preset flip-flop rate.

[0096] It should be noted that the above-mentioned clustering configuration may refer to reducing the wiring length between timing units with a higher than preset flip-flop rate, thereby reducing the line delay between timing units with high flip-flop rates, and thus reducing the power consumption of the target integrated circuit.

[0097] This embodiment, based on the RTL backward SAIF file, obtains the switching behavior information of the synthesized invariants in the preset RTL design file; it calls the preset power consumption driver optimization command `optDynamicPower` to analyze the component information of the preset RTL design file, obtaining the component power consumption analysis; it calls the preset power consumption driver optimization command `optDynamicPower` to analyze the node information of the preset RTL design file, obtaining the component switching power consumption analysis; based on the component power consumption analysis and the component switching power consumption analysis, it obtains the power consumption analysis result of the preset RTL design file; based on the power consumption analysis result and the switching behavior information of the synthesized invariants in the preset RTL design file, it obtains the timing cells in the target integrated circuit that exceed the preset flip-flop rate; during timing cell placement, it clusters and configures the timing cells in the target integrated circuit that exceed the preset flip-flop rate. Therefore, this embodiment, combining the RTL backward SAIF file and the power consumption driver command, can obtain not only the component power consumption analysis of the preset RTL design file, but also the component switching power consumption analysis of the preset RTL design file. After obtaining a more accurate preset toggle rate based on the combined analysis results of the two types of power consumption analysis, the placement and routing tool will combine the switching behavior information in the RTL backward SAIF file to make the clustering effect between timing cells with toggle rates greater than the preset toggle rate more obvious, which is also conducive to the timing convergence of the target integrated circuit. Therefore, this embodiment can achieve the goal of reducing the power consumption of the target integrated circuit.

[0098] Furthermore, this embodiment of the invention also proposes a storage medium storing a power optimization program, which, when executed by a processor, implements the steps of the power optimization method described above.

[0099] refer to Figure 5 , Figure 5 This is a structural block diagram of the first embodiment of the power consumption optimization device of the present invention.

[0100] like Figure 5 As shown, the power consumption optimization device proposed in this embodiment of the invention includes:

[0101] Analysis module 501 is used to obtain an RTL backwardSAIF file based on a preset RTL design file of the target integrated circuit;

[0102] The reading module 502 is used to read the RTL backward SAIF file into a preset back-end design software through a preset reading command. The preset back-end design software is used to perform timing cell placement on the target integrated circuit.

[0103] The optimization module 503 is used to optimize the power consumption of the target integrated circuit based on the RTL backward SAIF file and the preset power consumption drive optimization command optDynamicPower when performing the timing cell layout.

[0104] This embodiment obtains an RTL backward SAIF file based on a preset RTL design file of the target integrated circuit. A preset read command is used to read the RTL backward SAIF file into preset back-end design software, which is used for timing cell placement of the target integrated circuit. During timing cell placement, power optimization is performed on the target integrated circuit based on the RTL backward SAIF file and the preset power-driven optimization command `optDynamicPower`. This embodiment can generate an RTL backward SAIF file based on the preset RTL file of the target integrated circuit, then obtain the switching behavior of the preset RTL design file through the RTL backward SAIF file, and then perform power analysis based on the RTL backward SAIF file and the preset power-driven optimization command. Finally, based on the switching behavior and power analysis results, the timing cells with high switching rates in the target integrated circuit are clustered together, i.e., the wiring length between high switching rate timing cells is reduced, thereby reducing switching power consumption. Therefore, this embodiment can reduce the power consumption of the target integrated circuit.

[0105] Other embodiments or specific implementations of the power consumption optimization device of the present invention can be found in the above-described method embodiments, and will not be repeated here.

[0106] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0107] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0108] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0109] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A power consumption optimization method, characterized in that, The power consumption optimization method includes the following steps: Based on the pre-defined RTL design file of the target integrated circuit, obtain the RTL backward SAIF file; The RTL backward SAIF file is read into the preset back-end design software by a preset read command. The preset back-end design software is used to perform timing cell placement on the target integrated circuit. During the timing cell layout, power optimization is performed on the target integrated circuit based on the RTL backward SAIF file and the preset power driving optimization command optDynamicPower. The step of optimizing the power consumption of the target integrated circuit based on the RTL backward SAIF file and the preset power consumption drive optimization command optDynamicPower during the timing cell placement includes: Based on the RTL backward SAIF file, obtain the switching behavior information of the integrated invariant in the preset RTL design file; The preset power consumption drive optimization command optDynamicPower is invoked to obtain the power consumption analysis results of the preset RTL design file; Based on the power consumption analysis results and the switching behavior information of the integrated invariant in the preset RTL design file, the timing cells in the target integrated circuit that exceed the preset toggle rate are obtained; When performing the timing cell layout, timing cells in the target integrated circuit that exceed a preset flip-flop rate are grouped together.

2. The power consumption optimization method as described in claim 1, characterized in that, The steps for obtaining an RTL backward SAIF file based on the preset RTL design file of the target integrated circuit include: Based on the pre-defined RTL design file of the target integrated circuit, obtain the RTL forward SAIF file; Input the initial testbench test platform file, the preset RTL design file, and the RTL forward SAIF file into VCS to obtain the RTL backward SAIF file.

3. The power consumption optimization method as described in claim 2, characterized in that, The steps for obtaining an RTL forward SAIF file based on the preset RTL design file of the target integrated circuit include: The preset RTL design file of the target integrated circuit is loaded into the VCS. The VCS is used to convert the preset RTL design file into a gate-level netlist and output an RTL forward SAIF file after the preset RTL design file is converted.

4. The power consumption optimization method as described in claim 2, characterized in that, The step of inputting the initial testbench test platform file, the preset RTL design file, and the RTL forward SAIF file into the VCS to obtain the RTL backward SAIF file includes: Import the initial testbench test platform file into VCS and start the testbench; The testbench calls the RTL forward SAIF file and the preset RTL design file, so that the RTL forward SAIF file and the preset RTL design file are loaded into the VCS; In the testbench, a preset PLI system function is called to obtain the node flip rate of the RTL forward SAIF file; Based on the node flip rate of the RTL forward SAIF file, the preset RTL design file is simulated in the VCS to obtain the RTL backward SAIF file.

5. The power consumption optimization method as described in claim 1, characterized in that, The step of calling the preset power consumption driver optimization command optDynamicPower to obtain the power consumption analysis results of the preset RTL design file includes: The preset power consumption drive optimization command optDynamicPower is invoked to analyze the component information of the preset RTL design file and obtain the component power consumption analysis of the preset RTL design file. The preset power consumption drive optimization command optDynamicPower is invoked to analyze the node information of the preset RTL design file and obtain the component switching power consumption analysis of the preset RTL design file. Based on the power consumption analysis of the components and the power consumption analysis of the component switches, the power consumption analysis results of the preset RTL design file are obtained.

6. The power consumption optimization method as described in claim 5, characterized in that, The step of calling the preset power consumption drive optimization command optDynamicPower to analyze the node information of the preset RTL design file and obtain the component switching power consumption analysis of the preset RTL design file includes: The preset power consumption drive optimization command optDynamicPower is invoked to read the RTL backward SAIF file, and the toggle ratio in the RTL backward SAIF file is back-annotated to the file node of the preset RTL design file. The file nodes in the preset RTL design file are traversed to obtain the back-annotation rate of each file node, and the component switching power consumption analysis of the preset RTL design file is obtained.

7. A power consumption optimization device, characterized in that, The power consumption optimization device includes: The analysis module is used to obtain an RTL backward SAIF file based on a preset RTL design file of the target integrated circuit. The reading module is used to read the RTL backward SAIF file into a preset back-end design software through a preset reading command. The preset back-end design software is used to perform timing cell placement on the target integrated circuit. The optimization module is used to optimize the power consumption of the target integrated circuit based on the RTL backward SAIF file and the preset power consumption drive optimization command optDynamicPower when performing the timing cell layout. The optimization module is further configured to: obtain the switching behavior information of the integrated invariant in the preset RTL design file based on the RTL backward SAIF file; call the preset power consumption drive optimization command optDynamicPower to obtain the power consumption analysis results of the preset RTL design file; obtain the timing cells in the target integrated circuit that exceed the preset toggle rate based on the power consumption analysis results and the switching behavior information of the integrated invariant in the preset RTL design file; and cluster the timing cells in the target integrated circuit that exceed the preset toggle rate when performing the timing cell layout.

8. A power consumption optimization device, characterized in that, The device includes: a memory, a processor, and a power optimization program stored in the memory and executable on the processor, the power optimization program being configured to implement the steps of the power optimization method as described in any one of claims 1 to 6.

9. A storage medium, characterized in that, The storage medium stores a power optimization program, which, when executed by a processor, implements the steps of the power optimization method as described in any one of claims 1 to 6.

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