Semiconductor device

Abstract

Provided is a semiconductor device with higher reliability. The semiconductor device of the present invention includes: a semiconductor substrate having a first main surface and a second main surface facing each other; a dielectric layer laminated on the first main surface of the semiconductor substrate; a first electrode layer laminated on the dielectric layer; a protective layer covering at least the outer peripheral end portions of the dielectric layer and the first electrode layer, and configured to expose the outer peripheral end portion of the first main surface of the semiconductor substrate; and a high-resistance region located at least directly below the outer peripheral end portion of the protective layer.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] In Patent Document 1, as an example of a semiconductor device, a thin-film capacitor is described, wherein a substrate that also serves as a lower electrode layer, a dielectric layer, and an upper electrode layer are stacked sequentially, and a protective layer is formed on the upper electrode layer to expose the ends of the substrate.

[0003] Patent document 1: Japanese Patent Application Publication No. 2016-25310.

[0004] When the semiconductor device described in Patent Document 1 is used in inverter circuits or the like under DC or AC bias, it suffers from structural defects in the protective layer, leading to reduced reliability of the semiconductor device. In particular, structural defects are prone to occur when used under DC bias. Summary of the Invention

[0005] Therefore, the object of the present invention is to provide a semiconductor device with higher reliability.

[0006] As the inventors know, when a semiconductor device as described in Patent Document 1 is used in inverter circuits or the like under DC or AC bias, if the substrate is on the anode side and in a high-humidity environment, the substrate portion in contact with the outer periphery of the protective film is oxidized due to anodic oxidation, resulting in volume expansion of that substrate portion and structural defects at the outer periphery of the protective layer. In particular, when used under DC bias, since the substrate is always on the anode side, structural defects are prone to occur. These structural defects reduce the moisture resistance and discharge prevention function of the protective layer, thus reducing the reliability of the semiconductor device.

[0007] To address this, if a protective layer is applied to the ends of the substrate, cracks may form in the protective layer due to damage during cutting. Moisture can then enter through these cracks, promoting anodizing and resulting in structural defects in the protective layer. Furthermore, if the ends of the substrate are covered with a metal protective ring, there is a risk of surface discharge in high-humidity environments. Surface discharge differs from air discharge; it depends on the degree of contamination and electrochemical properties of the protective layer acting as an insulating layer, making it difficult to address through design changes. Therefore, the measures taken to address substrate anodizing are insufficient.

[0008] In view of this, the inventors of this application conducted in-depth research on the anodizing of the substrate, thereby completing the present invention.

[0009] That is, the semiconductor device of the present invention is characterized by comprising: a semiconductor substrate having a first main surface and a second main surface opposite to each other; a dielectric layer stacked on the first main surface of the semiconductor substrate; a first electrode layer stacked on the dielectric layer; and a protective layer covering at least the outer peripheral ends of the dielectric layer and the first electrode layer, and configured to expose the outer peripheral ends of the first main surface of the semiconductor substrate, wherein the semiconductor substrate has a high-resistance region located at least directly below the outer peripheral ends of the protective layer.

[0010] According to the present invention, by suppressing the anodizing of the substrate of the semiconductor device, a semiconductor device with higher reliability can be provided. Attached Figure Description

[0011] Figure 1 This is a schematic perspective view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0012] Figure 2 This is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0013] Figure 3 This is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0014] Figure 4 This is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0015] Figure 5A This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 1.

[0016] Figure 5B This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 1.

[0017] Figure 5C This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 1.

[0018] Figure 5D This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 1.

[0019] Figure 5E This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 1.

[0020] Figure 6A This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 2.

[0021] Figure 6B This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 2.

[0022] Figure 6C This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 2.

[0023] Figure 6D This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 2.

[0024] Figure 6E This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 2.

[0025] Figure 6F This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 2.

[0026] Figure 6G This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 2.

[0027] Figure 6H This is a schematic cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to Embodiment 2.

[0028] Figure 7 This is a circuit diagram illustrating an example of the configuration of the semiconductor module involved in Embodiment 3. Detailed Implementation

[0029] The following is a brief reference to the appendix. Figure 1 The embodiments of the present invention will be described below. The following description is provided to enable those skilled in the art to fully understand the invention and is not intended to limit the invention to the following content. Furthermore, in the following description, substantially identical components are labeled with the same reference numerals, and repeated descriptions are sometimes omitted.

[0030] (Implementation Method 1)

[0031] Figure 1 This is a schematic perspective view showing an example of the structure of the semiconductor device according to Embodiment 1. Figure 2 yes Figure 1 The schematic cross-sectional view of the semiconductor device taken along line X-X' is an LT cross-sectional view centered in the W direction. Here, the L direction is the length direction of the semiconductor device 1, the W direction is the width direction of the semiconductor device 1, and the T direction is the height direction of the semiconductor device 1.

[0032] Semiconductor device 1 includes: a semiconductor substrate 10 having a first main surface 10a and a second main surface 10b facing each other, and an outer peripheral surface 10A formed by four side surfaces located between the first main surface and the second main surface; a dielectric layer 11 stacked on the first main surface 10a of the semiconductor substrate 10; a first electrode layer 12 stacked on the dielectric layer 11; an annular protective layer 13 covering the outer peripheral ends of the dielectric layer 11 and the first electrode layer 12; and a second electrode layer 14 formed on the second main surface 10b. The outer peripheral end 13a of the protective layer 13 is located inside the outer peripheral surface 10A of the semiconductor substrate 10, and has an opening 13b at its center.

[0033] The semiconductor substrate 10 has a rectangular shape when viewed from above, and has a first main surface 10a and a second main surface 10b facing each other in the T direction, a pair of side surfaces 10c and 10d facing each other in the L direction, and a pair of side surfaces (not shown) facing each other in the W direction. Here, the pair of side surfaces 10c and 10d facing each other in the L direction and the pair of side surfaces facing each other in the W direction constitute the outer peripheral surface 10A of the semiconductor substrate 10.

[0034] The semiconductor substrate 10 can be, for example, a silicon substrate. There is no particular limitation on the conductivity type of the silicon substrate; both p-type and n-type can be used. As a p-type impurity, boron (B) can be used, and as an n-type impurity, phosphorus (P), ascorbyl chloride (As), slb, etc., can be used.

[0035] The semiconductor substrate 10 has a high-resistivity region 10e located at least directly below the outer peripheral end 13a of the protective layer 13. Here, the outer peripheral end 13a of the protective layer 13 refers to the portion including the end face of the protective layer 13 and a predetermined position from the outermost peripheral end to the inner side, forming the boundary with the semiconductor substrate when viewed from above. Furthermore, "at least directly below the outer peripheral end 13a of the protective layer 13" means at least below the outer peripheral end 13a of the protective layer 13 (in the depth direction). Additionally, the high-resistivity region 10e refers to a region having a resistivity higher than that of the region other than the high-resistivity region 10e in the semiconductor substrate 10 (the low-resistivity region), having a resistivity of 10... 2 Ω·cm or more and 10 9 Below Ω·cm, preferably 10 3 Ω·cm or more and 10 5 The resistivity is in the range below Ω·cm. Here, the resistivity of the low-resistivity region is 10 as mentioned above. -5 Ω·cm or higher and less than 10 2 Ω·cm, preferably 10 -3 Ω·cm or more and 10 1 Below Ω·cm. The resistivity can be measured using well-known methods such as the four-probe method.

[0036] Furthermore, the high-resistivity region 10e only needs to be located directly below the outer peripheral end 13a of the protective layer 13, and the depth (or thickness) of the high-resistivity region 10e is not particularly limited. In cross-sectional view, the thickness T1 of the high-resistivity region 10e is preferably from the surface of the semiconductor substrate 10 to at least 1 μm, and more preferably extends throughout the entire thickness direction of the semiconductor substrate 10. Alternatively, when the thickness of the semiconductor substrate 10 is T2, (T1 / T2) is 0.0001 or more and 1 or less. Additionally, in cross-sectional view, when the width of the high-resistivity region 10e is L1 and the width of the semiconductor substrate 10 is L2, (L1 / L2) is 0.001 or more and 0.1 or less, preferably 0.01 or more and 0.05 or less. Unless otherwise stated, in this specification, cross-sectional view refers to a cross-sectional view in the thickness direction of the semiconductor device 1.

[0037] Furthermore, the high-resistance region 10e is preferably located closer to the outer peripheral end of the semiconductor substrate 10 than the outer peripheral end of the first electrode layer 12 in cross-section. Also, the high-resistance region 10e is preferably located closer to the outer side than the outer peripheral end of the dielectric layer 11. This is because if the high-resistance region 10e is located closer to the center of the semiconductor substrate 10 than the outer peripheral end of the first electrode layer 12 in cross-section, the capacitance density of the semiconductor device 1 will decrease. For example, the high-resistance region 10e may also be formed in a ring shape in top view, surrounding the first electrode layer 12. Figure 2 This is an example of a high-resistance region 10e. In cross-section, the high-resistance region 10e has an inner peripheral end 10e1 and an outer peripheral end 10e2. The inner peripheral end 10e1 is located closer to the outer peripheral surface of the semiconductor substrate 10 than the end of the first electrode layer 12, and the outer peripheral end 10e2 reaches the outer peripheral surface of the semiconductor substrate 10. Figure 1 (Side surfaces 10c, 10d). By providing the outer peripheral end 10e2 to the outer peripheral surface of the semiconductor substrate 10, a high-resistance region 10e is formed at the end of the substrate 10. Therefore, the discharge distance between the electrode 12 and the substrate 10 can be extended, resulting in a structure that is beneficial for suppressing surface discharge. When the high-resistance region 10e is formed into a ring shape when viewed from above, the ring shape includes not only a circular shape but also a polygonal shape. The polygonal shape includes not only a shape with rectangular corners but also a shape with curved corners.

[0038] in addition, Figure 3In another example, in cross-section, the high-resistivity region 10f has an inner peripheral end 10f1 and an outer peripheral end 10f2. The inner peripheral end 10f1 is located closer to the outer peripheral surface of the semiconductor substrate 10 than the end of the first electrode layer 12, and the outer peripheral end 10f2 reaches the outer peripheral surface of the semiconductor substrate 10 and is formed throughout the entire thickness direction of the semiconductor substrate 10. By increasing the thickness of the high-resistivity region 10f, anodizing of the semiconductor substrate 10 can be further suppressed. Furthermore, Figure 4 As another example, in cross-section, the high-resistivity region 10g has an inner peripheral end 10g1 and an outer peripheral end 10g2. The inner peripheral end 10g1 is located closer to the outer peripheral surface of the semiconductor substrate 10 than the end of the first electrode layer 12. The outer peripheral end 10g2 is separated from the outer peripheral surface of the semiconductor substrate 10 and is formed throughout the entire thickness direction of the semiconductor substrate 10. By separating the outer peripheral end 10g2 from the peripheral surface of the semiconductor substrate 10, the high-resistivity region 10g is not present on the cutting line, thus reducing damage caused by debris during cutting of the high-resistivity region 10g.

[0039] High-resistivity regions can be formed, for example, by doping oxygen ions using ion implantation followed by high-temperature heat treatment. This method is known as separation by implanted oxygen, forming a high-resistivity silicon oxide film in a silicon substrate. Specifically, for example, the following method can be used. As a semiconductor substrate, for example, a 5 × 10⁻⁶ ohmmeter is used... 16 cm -3 The above impurity concentrations are for silicon substrates doped with p-type or n-type impurities. Oxygen ions are introduced at approximately 4 × 10⁻⁶. 17 cm -3 The implantation density is high, and the substrate is annealed at 1300°C. The implantation depth can be adjusted by changing implantation conditions such as implantation energy.

[0040] The dielectric layer 11 can be formed from insulating silicon oxide, such as SiO2. The dielectric layer 11 can be formed, for example, by oxidation methods such as thermal oxidation of the silicon substrate or by CVD. The thickness of the dielectric layer 11 is 0.01 μm or more and 10 μm or less, preferably 0.1 μm or more and 3 μm or less. Furthermore, the dielectric layer 11 is not limited to a single layer, but can also be a stacked structure composed of multiple dielectrics. By employing a stacked structure, relatively arbitrary capacitance and voltage withstand designs can be achieved.

[0041] The first electrode layer 12 can be made of metallic materials such as molybdenum, aluminum, gold, tungsten, platinum, and titanium. The first electrode layer can be formed using sputtering or vacuum evaporation. The thickness of the first electrode layer is 0.1 μm or more and 10 μm or less, preferably 0.5 μm or more and 3 μm or less.

[0042] The protective layer 13 can be made of inorganic insulating materials such as silicon nitride oxide and silicon nitride, or insulating resin materials such as polyimide. The thickness of the protective layer 13 is 0.2 μm or more and 30 μm or less, preferably 0.5 μm or more and 10 μm or less. Preferably, the protective layer 13 has an annular shape when viewed from above. This annular shape includes not only circular shapes but also polygonal shapes, and the polygonal shapes include not only shapes with rectangular corners but also shapes with curved corners.

[0043] The second electrode layer 14 can be made of the same material as the first electrode layer 12. The thickness of the second electrode layer 14 is 0.1 μm or more and 10 μm or less, preferably 0.5 μm or more and 3 μm or less. In this embodiment, the semiconductor substrate 10 is a p-type or n-type conductive silicon substrate, and the low-resistance region of the semiconductor substrate 10 can also function as an electrode, so the second electrode layer 14 can be omitted.

[0044] The semiconductor device of this embodiment can be used under either DC bias or AC bias, and is particularly suitable for use under DC bias. In this case, the semiconductor substrate is connected to the positive terminal of the DC power supply as the positive electrode, and the first electrode layer is connected to the negative terminal of the DC power supply as the negative electrode. Where the semiconductor substrate has a second electrode layer, the second electrode layer is connected to the positive terminal of the DC power supply as the positive electrode.

[0045] (Manufacturing method)

[0046] The semiconductor device of this embodiment can be manufactured, for example, using the following method. (Refer to...) Figures 5A-5E The following explanation is provided. First, using a low-resistivity silicon substrate 10 having a first main surface 10a and a second main surface 10b that are opposite to each other, oxygen ions are implanted into the component end region including the dicing line by ion implantation, and then heat treatment is performed, thereby forming a high-resistivity region 10e in a defined area of ​​the first main surface 10a of the silicon substrate 10. Figure 5A Next, a dielectric film composed of SiO2 is formed on the first main surface 10a of the silicon substrate 10 using CVD, and patterned by photolithography and dry etching to form the dielectric layer 11. Figure 5B Next, a metal film is formed on the dielectric layer 11 using sputtering, and then patterned by photolithography and wet etching to form the first electrode layer 12. Figure 5C Here, in cross-section, the first electrode layer 12 is formed as a high-resistivity region located closer to the peripheral surface of the semiconductor substrate 10 than the end of the first electrode layer 12. Next, a silicon nitride film (Si3N4) is formed using CVD, and patterned by photolithography and dry etching to form a protective layer 13 with an opening in the center when viewed from above. Figure 5DThe protective layer 13 covers the end of the first electrode layer 12. Here, the protective layer 13 is formed such that the high-resistance region 10e is located at least directly below the outer peripheral end of the protective layer 13. Next, the second main surface 10b of the semiconductor substrate 10 is polished, and a second electrode layer 14 composed of a metal film is formed by sputtering. Figure 5E Next, the semiconductor substrate is cut to monolithize it, thereby obtaining semiconductor device 1.

[0047] The reason for the reduced reliability of semiconductor devices due to anodizing of the substrate is considered to be that if the substrate portion in contact with the outer peripheral end of the protective film is oxidized due to anodizing in a high humidity environment, the volume of the substrate portion expands, structural defects occur at the outer peripheral end of the protective layer, and moisture enters through the anodized portion of the substrate. According to this embodiment, the semiconductor substrate has a high-resistance region located at least directly below the outer peripheral end of the protective layer. Therefore, even when the semiconductor substrate is the anode, a potential is applied only between the first electrode layer and the low-resistance region of the semiconductor substrate via the dielectric layer, and almost no potential is applied to the high-resistance region. Therefore, the high-resistance region does not function as an anode, thus suppressing anodizing of the semiconductor substrate located at the boundary region with the protective layer. Consequently, no volume expansion due to anodizing occurs at the boundary region between the semiconductor substrate and the protective layer, thus preventing structural defects at the outer peripheral end of the protective layer. Furthermore, moisture can be prevented from entering the dielectric film through the anodized portion of the substrate. Through these effects, the reliability of the semiconductor device can be improved.

[0048] (Implementation Method 2)

[0049] In this embodiment, a semiconductor device in which a trench is formed on the first main surface of a semiconductor substrate will be described. Figures 6A-6H This is a schematic cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 4 according to this embodiment.

[0050] First, the structure of semiconductor device 4 will be explained. For example... Figure 6HAs shown, for example, the semiconductor device 4 includes: a semiconductor substrate 20 having a first main surface 20a and a second main surface 20b facing each other, an outer peripheral surface 20A formed by four side surfaces located between the first main surface 20a and the second main surface 20b, and having a plurality of trenches 20d formed on the first main surface 20a; a dielectric layer 21 formed along the plurality of trenches 20d and stacked on the first main surface 20a; a first electrode layer 24 stacked on the dielectric layer 21; and a protective layer 25 covering at least the ends of the dielectric layer 21 and the first electrode layer 24. Furthermore, the semiconductor substrate 20 has a high-resistance region 20c located at least directly below the outer peripheral end 25a of the protective layer 25. Additionally, the first electrode layer 24 has a first conductive layer 22 stacked on the dielectric layer 21 and a second conductive layer 23 stacked on the first conductive layer 22.

[0051] Similar to Embodiment 1, the semiconductor substrate 20 can be a p-type or n-type conductive silicon substrate. The thickness of the semiconductor substrate is 10 μm or more and 1000 μm or less, preferably 50 μm or more and 400 μm or less.

[0052] At least one trench 20d may be formed on the first main surface 20a of the semiconductor substrate 20. The trench 20d is a groove or hole formed along a direction perpendicular to the first main surface 20a of the semiconductor substrate 20. Figure 6H The diagram shows an LT cross-section in which multiple rectangular grooves are formed as multiple trenches 20d when viewed from above, with the short sides of the multiple grooves parallel to the L direction. The multiple trenches 20d can also be formed into columnar holes in a matrix along the L and W directions. The depth of the trenches 20d is 5 μm or more and 100 μm or less, preferably 20 μm or more and 50 μm or less. Furthermore, the width of the trenches 20d, for example, the width of the grooves in the LT cross-section, or the diameter of the holes, is 1 μm or more and 10 μm or less, preferably 2 μm or more and 5 μm or less. The trenches 20d can be formed, for example, by dry etching.

[0053] The semiconductor substrate 20 has a high-resistance region 20c located at least directly below the outer peripheral end 25a of the protective layer 25. The high-resistance region 20c is formed in a ring shape when viewed from above to surround the first electrode layer 24. In cross-sectional view, the high-resistance region 20c has an inner peripheral end 20c1 and an outer peripheral end 20c2. The inner peripheral end 20c1 is located closer to the outer peripheral surface of the semiconductor substrate 20 than the end of the first electrode layer 24. The outer peripheral end 20c2 is separated from the outer peripheral surface of the semiconductor substrate 20 and is formed throughout the entire thickness direction of the semiconductor substrate 20. Because the semiconductor substrate has a high-resistance region located at least directly below the outer peripheral end of the protective layer, anodizing of the semiconductor substrate located at the boundary region with the protective layer can be suppressed even when the semiconductor substrate is an anode. Furthermore, by separating the outer peripheral end 20c2 from the outer peripheral surface of the semiconductor substrate 20, the high-resistance region 10g is absent along the dicing line, thus reducing damage caused by debris during dicing of the high-resistance region 20c. When the high-resistivity region 20c is viewed from above and forms a ring shape, the ring shape includes not only a circular shape but also a polygonal shape. The polygonal shape includes not only a shape with rectangular corners but also a shape with curved corners.

[0054] A dielectric layer 21 is formed along the trench 20d. The dielectric layer 21 can be formed from insulating silicon oxide, such as SiO2. The dielectric layer 21 can be formed, for example, by oxidation of the silicon substrate using methods such as thermal oxidation or CVD. The thickness of the dielectric layer 21 is 0.01 μm or more and 5 μm or less, preferably 0.1 μm or more and 3 μm or less. Furthermore, the dielectric layer 21 is not limited to a single layer, but can also be a stacked structure composed of multiple dielectrics. By employing a stacked structure, relatively arbitrary capacitance and voltage withstand designs can be achieved.

[0055] The first electrode layer 24 has a first conductive layer 22 stacked on the dielectric layer 21 and a second conductive layer 23 stacked on the first conductive layer 22. The first conductive layer 22 can be made of silicon-based conductive materials such as p-type or n-type polycrystalline silicon. The first conductive layer 22 can be formed using a CVD method. The thickness of the first conductive layer 22 is 0.1 μm or more and 3 μm or less, preferably 0.5 μm or more and 1 μm or less. On the other hand, the second conductive layer 23 can be made of metallic materials such as molybdenum, aluminum, gold, tungsten, platinum, and titanium. The second conductive layer 23 can be formed using a sputtering method or a vacuum evaporation method. The thickness of the second conductive layer 23 is 0.1 μm or more and 10 μm or less, preferably 0.5 μm or more and 3 μm or less. Where the adhesion between the second conductive layer 23 and the dielectric layer 21 is sufficiently high, and the second conductive layer 23 can also be formed on the dielectric layer 21 within the trench 20d with high coverage, the first conductive layer 22 can be omitted, and the second conductive layer 23 can be formed directly on the dielectric layer 21.

[0056] The protective layer 25 can be made of inorganic insulating materials such as silicon nitride oxide and silicon nitride, or insulating resin materials such as polyimide. The thickness of the protective layer 25 is 0.3 μm or more and 30 μm or less, preferably 1.2 μm or more and 10 μm or less. Preferably, the protective layer 25 has a ring-shaped form when viewed from above. This ring-shaped form includes not only circular shapes but also polygonal shapes, and the polygonal shape includes not only shapes with rectangular corners but also shapes with curved corners.

[0057] The second electrode layer 26 can be made of the same material as the first electrode layer. The thickness of the second electrode layer 26 is 0.1 μm or more and 10 μm or less, preferably 0.5 μm or more and 3 μm or less. In this embodiment, a p-type or n-type silicon substrate is used as the semiconductor substrate. Since the semiconductor substrate 20 can also function as an electrode, the second electrode layer can be omitted.

[0058] The semiconductor device 4 of this embodiment can be manufactured, for example, using the following method.

[0059] (Formation of high-resistivity regions)

[0060] First, using a low-resistivity silicon wafer 20 (e.g., with a resistivity of 5 Ω·cm) having a first main surface 20a and a second main surface 20b that are opposite to each other, oxygen ions are implanted into the region that includes the end of the component, which is the dicing line, by ion implantation, and then heat treatment is performed, thereby forming a high-resistivity region 20c in a specified area of ​​the wafer 20. Figure 6A ).

[0061] (The formation of trenches)

[0062] Next, using photolithography and Bosch processes, the wafer 20 is deeply etched to form multiple trenches 20d. Figure 6B ).

[0063] (Formation of the dielectric layer)

[0064] Next, a dielectric film composed of SiO2 is formed along multiple trenches 20d using CVD, and patterned by photolithography and dry etching to form the dielectric layer 21. Figure 6C ).

[0065] (Formation of the first conductive layer)

[0066] Next, a polycrystalline silicon film is formed on the dielectric layer 21 using CVD, and patterned by photolithography and dry etching to form the first conductive layer 22. Figure 6D ).

[0067] (Formation of the second conductive layer)

[0068] Next, an aluminum film is formed on the first conductive layer 22 by sputtering, and then patterned by photolithography and wet etching to form the second conductive layer 23. The first conductive layer 22 and the second conductive layer 23 constitute the first electrode layer 24. Here, the first electrode layer 24 is formed such that, in cross-section, the high-resistance region 20c is located closer to the peripheral surface of the semiconductor substrate 20 than the end of the first electrode layer 24. Figure 6E ).

[0069] (Formation of the protective layer)

[0070] Next, a silicon nitride film (Si3N4) is formed using CVD, and patterned by photolithography and dry etching to form a protective layer 25 with an opening 25b in the center when viewed from above. The protective layer 25 covers the end of the first electrode layer 24. Figure 6F Here, the protective layer 25 is formed as a high-resistivity region 20c located at least directly below the outer peripheral end 25a of the protective layer 25.

[0071] (Formation of the second electrode layer)

[0072] Next, the second main surface 20b of the semiconductor substrate 20 is polished, and a second electrode layer 26 composed of an aluminum film is formed by sputtering. Figure 6G ).

[0073] (Mono-chip)

[0074] Next, the wafer 20 is diced to monolithize it, thereby obtaining the semiconductor device 4. Figure 6H ).

[0075] The semiconductor device of this embodiment can be used under both DC bias and AC bias, and is particularly suitable for use under DC bias. In this case, the semiconductor substrate is connected to the positive terminal of the DC power supply as the positive electrode, and the first electrode layer is connected to the negative terminal of the DC power supply as the negative electrode. Where the semiconductor substrate has a second electrode layer, the second electrode layer is connected to the positive terminal of the DC power supply as the positive electrode.

[0076] According to this embodiment, similar to Embodiment 1, the semiconductor substrate has a high-resistance region located at least directly below the outer peripheral end of the protective layer. Therefore, even when the semiconductor substrate is an anode, anodizing of the semiconductor substrate located in the boundary region with the protective layer can be suppressed. This prevents structural defects at the ends of the protective layer, thereby improving the reliability of the semiconductor device. Furthermore, according to this embodiment, by providing trenches on the surface of the semiconductor substrate, the electrode area can be increased, thus also increasing the capacitance per unit area of ​​the semiconductor device.

[0077] Implementation Method 3

[0078] This embodiment relates to a semiconductor module including the semiconductor device of the present invention. Figure 7 This is an example of a semiconductor module. The semiconductor module 30 consists of a DC power supply 31, switching devices 32(H) and 32(L), diodes 34 connected to the switching devices 32(H) and 32(L) respectively, and capacitors 35 connected to the positive and negative terminals of the DC power supply 31. The capacitor 35 uses the semiconductor device of the present invention, for example, the semiconductor device of embodiments 1 and 2.

[0079] Each switching device 32 includes a switching element 33 such as a MOSFET and a freewheeling diode 34. The gate terminal 33g of the switching element 33 is controlled to be turned on and off by a control circuit (not shown). The DC voltage applied between the positive terminal 36 of the high-potential switching device 32H and the negative terminal 37 of the low-potential switching device 32L is converted into an AC voltage and output from the output terminal 38. Here, the positive terminal 36 is connected to the semiconductor substrate of the capacitor 35, and the negative terminal 37 is connected to the first electrode layer of the capacitor 35. Where the semiconductor substrate of the capacitor 35 is provided with a second electrode layer, the positive terminal 36 may also be connected to the second electrode layer of the capacitor 35.

[0080] As described in Embodiments 1 and 2, the semiconductor substrate of the semiconductor device in Embodiments 1 and 2 has a high-resistance region located at least directly below the outer peripheral end of the protective layer. Therefore, even when the semiconductor substrate is an anode, almost no potential is applied to the high-resistance region. This suppresses anodizing of the semiconductor substrate of the capacitor 35, thereby improving the reliability of the capacitor 35. According to this embodiment, a capacitor 35 capable of suppressing anodizing of the semiconductor substrate is used, thus improving the reliability of the semiconductor module.

[0081] Explanation of reference numerals in the attached figures

[0082] 1, 2, 3, 4… Semiconductor device; 10, 20… Semiconductor substrate; 11, 21… Dielectric layer; 12, 24… First electrode layer; 13, 25… Protective layer; 14, 26… Second electrode layer; 10A, 20A… Outer peripheral surface; 10a… First main surface; 10b… Second main surface; 10c, 10d… Side surface; 20c, 10e, 10f, 10g high resistance region; 20c1, 10e1, 10f1, 10g1 inner peripheral end; 20c2, 10e2, 10f2, 10g2 outer peripheral end; 30… Semiconductor module; 31… DC power supply; 32… Switching device; 33… Switching element; 33g… Gate terminal of switching element; 34… Diode; 35… Capacitor; 36… Positive terminal of switching element; 37… Negative terminal of switching element; 38… Output terminal.

Claims

1. A semiconductor device, wherein, This semiconductor device has: A semiconductor substrate having a first main surface and a second main surface that are opposite to each other; A dielectric layer is stacked on the first main surface of the semiconductor substrate; The first electrode layer is stacked on the dielectric layer; as well as A protective layer, at least covering the outer peripheral ends of the dielectric layer and the first electrode layer, is configured to expose the outer peripheral ends of the first main surface of the semiconductor substrate. The semiconductor substrate has a high-resistivity region located at least directly below the outer peripheral end of the protective layer.

2. The semiconductor device according to claim 1, wherein, In a cross-sectional view along the thickness direction of the semiconductor device, the high-resistance region is located closer to the outer peripheral end of the semiconductor substrate than the outer peripheral end of the first electrode layer.

3. The semiconductor device according to claim 1, wherein, In a cross-sectional view along the thickness direction of the semiconductor device, the high-resistivity region is located closer to the outer peripheral end of the semiconductor substrate than the outer peripheral end of the protective layer.

4. The semiconductor device according to claim 1, wherein, The resistivity of the high-resistivity region is above 102 Ω·cm and below 109 Ω·cm, and the resistivity of the low-resistivity region of the semiconductor substrate other than the high-resistivity region is above 10-5 Ω·cm and below 102 Ω·cm.

5. The semiconductor device according to claim 1, wherein, The semiconductor substrate is a silicon substrate. The high-resistivity region is silicon oxide.

6. The semiconductor device according to claim 1, wherein, At least one trench is formed on the first main surface, and the dielectric layer is formed along the trench.

7. The semiconductor device according to claim 6, wherein, The high-resistance region is configured to be shallower than the depth of the trench extending along the thickness direction of the semiconductor substrate.

8. The semiconductor device according to claim 2, wherein, The high-resistance region is provided throughout the entire thickness direction of the semiconductor substrate.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The semiconductor substrate is the positive electrode, and the first electrode layer is the negative electrode.

10. A semiconductor module, wherein, The semiconductor module includes a DC power supply, a switching device for connecting and disconnecting the DC power supply, and a semiconductor device according to claim 1 connected to the positive and negative terminals of the DC power supply. The positive terminal of the DC power supply is connected to the semiconductor substrate of the semiconductor device according to claim 1, and the negative terminal of the DC power supply is connected to the first electrode layer of the semiconductor device according to claim 1.

Images