Method and device for testing circuit model and non-transitory computer readable medium

Abstract

Disclosed herein are methods, devices, and non-transitory computer-readable media for testing circuit models. In one aspect, a corresponding virtual defect is assigned to each of a plurality of input condition sets for the circuit model. The virtual defects are generated without regard to the physical characteristics of an integrated circuit formed according to the circuit model. Each virtual defect can be associated with a corresponding input condition set. In one aspect, a table of the circuit model is generated that includes a plurality of logical behavioral models of the circuit model. Each of the plurality of logical behavioral models can include a corresponding set of the plurality of input condition sets, a corresponding output result, and the corresponding virtual defect. Based at least in part on the table of the circuit model, a test pattern for the circuit model can be generated.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and more particularly, to a method and device for testing a circuit model, and a non-transitory computer-readable medium. Background Art

[0002] Advances in integrated circuit design have made it possible to integrate a large number of circuit elements in a smaller form factor and perform various logical calculations. Often, some circuit elements of an integrated circuit may have defects, causing the circuit elements to perform incorrect logical calculations. For example, parasitic resistance or capacitance in a circuit element may cause an unexpected electrical signal (e.g., voltage or current) to be provided. For another example, an unexpected disconnect between two or more circuit elements may prevent the provision of an electrical signal (e.g., voltage or current). Such unintentional provision or unintentional blocking of electrical signals due to various defects in circuit elements can lead to erroneous logical calculations. Summary of the Invention

[0003] According to one aspect of an embodiment of the present invention, a method for testing a circuit model is provided, comprising: assigning a corresponding virtual defect to each of a plurality of input condition sets of the circuit model; generating a table of the circuit model, the table comprising a plurality of logical behavior models of the circuit model, each of the plurality of logical behavior models comprising a corresponding set of a plurality of input condition sets, a corresponding output result, and a corresponding virtual defect; and generating a test pattern for the circuit model based at least in part on the table of the circuit model.

[0004] According to another aspect of an embodiment of the present invention, a device for testing a circuit model is provided, comprising: one or more processors; and a non-transitory computer-readable medium storing instructions, which, when executed by the one or more processors, cause the one or more processors to perform the following operations: generate a table of the circuit model, the table comprising multiple logical behavioral models of the circuit model, each of the multiple logical behavioral models comprising a corresponding input condition set, a corresponding output result, and a corresponding virtual defect, perform a fault detection simulation on the circuit model according to one or more test patterns associated with the circuit model, generate a reduction table of the circuit model according to the fault detection simulation, and generate an additional test pattern according to the reduction table of the circuit model.

[0005] According to another aspect of an embodiment of the present invention, a non-transitory computer-readable medium is provided for storing instructions, which, when executed by one or more processors, cause the one or more processors to perform the following operations: generate a table of circuit models, the table including multiple logical behavioral models of the circuit model, each of the multiple logical behavioral models including a corresponding input condition set, a corresponding output result, and a corresponding virtual defect; simulate multiple instances of the circuit model according to one or more test modes associated with the circuit model; detect one instance of the multiple instances of the circuit model, the instance being simulated using the input condition set of the logical behavioral model in the table and presenting a fault result different from its corresponding output result; and exclude the detected logical behavioral model from the table of circuit models. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a diagram of a system for detecting defects in an integrated circuit based on virtual defects associated with the integrated circuit, according to one embodiment.

[0008] Figure 2 is a diagram of a test pattern generator according to one embodiment.

[0009] Figure 3A is a diagram illustrating an example of a circuit model according to an embodiment.

[0010] Figure 3B According to one embodiment Figure 3A Schematic diagram of an example circuit model.

[0011] Figure 4 is a table of examples of logical behavioral models of circuit models with virtual defects according to one embodiment.

[0012] Figure 5 is a table of examples of logic behavior models of a dynamic logic circuit model with virtual defects according to one embodiment.

[0013] Figure 6A are example results of a fault detection simulation performed on multiple instances of a circuit model according to one embodiment.

[0014] Figure 6B According to one embodiment, Figure 6A Instance reduction table of the logical behavior model of the fault simulation results.

[0015] Figure 7Ais another example result of a fault detection simulation performed on multiple instances of a circuit model according to one embodiment.

[0016] Figure 7B According to one embodiment, Figure 7A Another example reduction table of the logical behavior model of the fault simulation results.

[0017] Figure 8A is an example circuit model according to one embodiment.

[0018] Figure 8B is a circuit model modified according to an example of an embodiment.

[0019] Figure 9 is a flow chart of generating a test pattern based on a virtual defect according to some embodiments.

[0020] Figure 10 is an example block diagram of a computing system according to some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples of different components for implementing the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component is in direct contact with the second component, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component is not in direct contact with the second component. In addition, the present invention may repeat reference numerals and / or characters in various examples. Such repetition is for the purpose of simplicity and clarity and does not, in itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or more) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0023] Disclosed herein are methods, devices, and non-transitory computer-readable media for testing integrated circuits. In one aspect, a single corresponding virtual defect is assigned to each of a plurality of input condition sets for a circuit model. In another aspect, virtual defects are generated without regard to physical characteristics of an integrated circuit formed according to the circuit model. Each virtual defect can be associated with a corresponding input condition set. In another aspect, a table is generated that includes a plurality of logical behavioral models for the circuit model. Each of the plurality of logical behavioral models can include or indicate a corresponding set of a plurality of input condition sets, a corresponding output result, and a corresponding virtual defect. Based at least in part on the table of circuit models, a test pattern for the circuit model can be generated.

[0024] Advantageously, generating test patterns based on virtual defects disclosed herein allows circuit elements to detect erroneous calculations despite the presence of unmodeled defects. In one implementation, a test pattern is generated by modeling one or more defects based on the physical properties of the circuit element (e.g., resistance, capacitance, etc.). For example, defects such as parasitic resistance, parasitic capacitance, and / or disconnections between two or more elements can be modeled to predict or simulate the impact of these defects on logical calculations. In one implementation, one or more input condition sets that allow detection of modeled defects can be determined, and a test pattern can be generated based on the one or more input condition sets. However, such test patterns generated based on modeled defects may not be able to detect unmodeled defects of circuit elements. In some embodiments, possible input condition sets for the circuit element are determined, and each input condition set is assigned to a unique virtual defect, regardless of any physical defects of the circuit element. In addition, one or more test patterns can be generated based on different input condition sets with virtual defects. One or more test patterns generated based on different input condition sets with virtual defects can allow detection of unmodeled defects.

[0025] Advantageously, virtual defects allow test patterns to be generated in an efficient manner. On the one hand, generating test patterns based on modeled defects based on the physical characteristics of circuit elements can be computationally exhaustive. For example, a model of a physical defect can be generated and the impact of the modeled defect can be predicted by a Simulation Program with Integrated Circuit Emphasis (SPICE) simulation. However, performing such a simulation can take a long time (e.g., hours to days). By assigning a unique virtual defect to each of the corresponding input condition sets without considering the physical characteristics of the circuit model, and generating test patterns based on different input condition sets and corresponding virtual defects, cost-inefficient simulations (e.g., SPICE simulations) to predict the impact of the physical defect can be avoided. Therefore, by omitting such cost-inefficient simulations, test patterns can be generated in a computationally efficient manner.

[0026] In one aspect, the disclosed methods, devices, and non-transitory computer-readable media can generate additional test patterns that can compensate for or supplement deficiencies in one or more test patterns (e.g., existing test patterns). In one aspect, a table of circuit models is generated, including multiple logical behavioral models of the circuit model. Each of the multiple logical behavioral models can include a corresponding set of input conditions, an output result, and a virtual defect. In one aspect, a fault detection simulation of the circuit model is performed based on one or more test patterns associated with the circuit model. The one or more test patterns can be existing test patterns of the generated circuit model. In one example, multiple instances of the circuit model can be simulated based on the one or more test patterns associated with the circuit model. Based on the simulation, one or more instances that exhibit a fault result in response to the input condition set of the logical behavioral model in the table can be detected. Such input condition set that exhibits a fault result can be determined as a tested input condition. Then, from the multiple logical behavioral models in the table, logical behavioral models having the input condition set (or the tested input condition) can be excluded to generate a reduction table. Furthermore, additional test patterns can be generated based on the reduction table including the remaining logical behavioral models. Thus, one or more additional test patterns can be generated that can test for defects that cannot be detected by one or more test patterns (e.g., existing test patterns). Thus, a circuit model can be tested based on one or more test patterns (e.g., existing test patterns) and the additional test patterns. In one aspect, one or more test patterns (e.g., existing test patterns) can be used (or reused) to improve efficiency, wherein the additional test patterns can be used to supplement the deficiencies of one or more test patterns (e.g., test patterns).

[0027] Figure 1 is a diagram of a system 100 for detecting defects in an integrated circuit (IC) 190 based on virtual defects 115 associated with the integrated circuit, according to one embodiment. In some embodiments, the system 100 includes a test pattern generator 110, a circuit test system 170, and the IC 190. In one configuration, the test pattern generator 110 generates a test pattern 125 for testing the functionality of the IC 190 and provides the test pattern 125 to the circuit test system 170. In one configuration, the circuit test system 170 receives the test pattern 125 from the test pattern generator 110 and generates input conditions 178 based on the test pattern 125. The circuit test system 170 may apply the input conditions 178 to the IC 190 and receive an output result 175. Based on the output result 175, the circuit test system 170 may determine whether the IC 190 operates as designed. In other embodiments, the system 100 includes a comparison Figure 1 More, fewer, or different elements may be shown.In some embodiments, test pattern generator 110 and circuit testing system 170 are integrated into a single computing device.

[0028] In some embodiments, the test pattern generator 110 is an element that generates a test pattern 125 that indicates a vector or sequence of different sets of input conditions 178 to test the functionality of the IC 190. The test pattern generator 110 may be embodied as a computing system (e.g., Figure 10 1000). In other embodiments, the test pattern generator 110 may be replaced by other components that perform the functions of the test pattern generator 110. In one aspect, the test pattern generator 110 generates the test pattern 125 based on the virtual defect 115 associated with the IC 190, as described below with respect to Figures 2 to 9 In one aspect, each virtual defect 115 is generated without regard to the physical characteristics of IC 190, and each virtual defect 115 is associated with a single corresponding set of input conditions 178 for IC 190. Advantageously, the test patterns 125 generated based on the virtual defects 115 allow for the detection of defects that may not be anticipated or modeled based on the physical characteristics of IC 190. The test pattern generator 110 may also generate an output pattern 128 that indicates a vector or sequence of expected output results associated with the different sets of input conditions 178 indicated by the test pattern 125, and provide the output pattern 128 to the circuit test system 170.

[0029] In one aspect, circuit testing system 170 is a component that receives test pattern 125 and output pattern 128 and tests IC 190 according to test pattern 125. Circuit testing system 170 may be embodied as a computing system. In other embodiments, circuit testing system 170 may be replaced by other components that perform the functions of circuit testing system 170. In one aspect, circuit testing system 170 generates a vector or sequence of sets of multiple input conditions 178 (e.g., voltages or currents) according to test pattern 125 and applies the vector or sequence of sets of multiple input conditions 178 to IC 190. In response to the vector or sequence of sets of multiple input conditions 178 applied to IC 190, circuit testing system 170 may receive a vector or sequence of output results 175. Circuit testing system 170 may compare the received vector or sequence of output results 175 with the vector or sequence of expected output results indicated by output pattern 128. Based on this comparison, circuit testing system 170 may determine whether IC 190 is operating correctly. For example, in response to the vector or sequence of received output results 175 matching the vector or sequence of expected output results indicated by output pattern 128, circuit testing system 170 may determine that no faults have been detected. For example, in response to the vector or sequence of received output results 175 not matching the vector or sequence of expected output results indicated by output pattern 128, circuit testing system 170 may determine that one or more faults have been detected.

[0030] Figure 2is a diagram of a test pattern generator 110 according to one embodiment. In some embodiments, the test pattern generator 110 includes a logical behavioral model generator 220, a fault detection simulator 230, a table reducer 240, a vector generator 250, a logic modifier 270, and a test pattern memory 280. These elements can operate together to assign a virtual defect 115 to each logical behavioral model of the circuit model and generate a test pattern based on the logical behavioral model. The virtual defect 115 can be an arbitrarily generated defect assigned to or corresponding to a unique set of input conditions, regardless of the physical characteristics of the integrated circuit. In one aspect, each virtual defect 115 serves as an identifier for the corresponding input condition set. By using the virtual defect 115 and testing the additional input condition set, incorrect operation of the IC 190 due to unmodeled defects can be detected, which may not be detected by existing or pre-generated test patterns. In some embodiments, these elements can be embodied in hardware, software, or a combination of hardware and software. In some embodiments, the test pattern generator 110 includes a virtual defect generator. Figure 2 More, fewer or different elements may be shown.

[0031] In some embodiments, logical behavioral model generator 220 is a component that generates a behavioral model of a circuit model based on virtual defects. In other embodiments, logical behavioral model generator 220 may be replaced by another component that performs the functions of logical behavioral model generator 220. In one aspect, a circuit model electrically models a circuit. For example, a circuit model may electrically model a NAND gate, an AND gate, an OR gate, an XOR gate, an XNOR gate, a multiplexer, a latch, a flip-flop, or any other circuit. In one aspect, a behavioral model indicates different sets of input conditions applied to the circuit model, corresponding output results, and corresponding virtual defects. In one aspect, virtual defects 115 are generated without regard to the physical characteristics of the circuit formed according to the circuit model. In some embodiments, logical behavioral model generator 220 determines possible sets of input conditions for the circuit model. For each set of input conditions, logical behavioral model generator 220 may determine the expected corresponding output result and the corresponding virtual defect 115. Logical behavioral model generator 220 may generate a table including the behavioral model. Assuming that the integrated circuit has two inputs and the inputs have four possible input condition sets

[00] ,

[01] ,

[10] ,

[11] , the logical behavior model generator 220 can assign the virtual defect D1 to the first input condition set (e.g.,

[00] ), the virtual defect D2 to the second input condition set (e.g.,

[01] ), the virtual defect D3 to the third input condition set (e.g.,

[10] ), and the virtual defect D4 to the fourth input condition set (e.g.,

[11] ).

[0032] In some embodiments, the fault detection simulator 230 is a component that performs fault detection simulation on the circuit model. In other embodiments, the fault detection simulator 230 may be replaced by another component that performs the functions of the fault detection simulator 230. In one method, the fault detection simulator 230 obtains one or more test patterns from the test pattern memory 280. The test patterns may indicate vectors or sequences of different sets of input conditions. Some of the test patterns stored in the test pattern memory 280 may be generated based on the logical behavioral model generated by the logical behavioral model generator 220. Some of the test patterns stored in the test pattern memory 280 may be predetermined or generated by other components. In one method, the fault detection simulator 230 simulates the circuit model based on the test patterns and determines whether a fault is detectable. For example, if the simulated output differs from the vector of expected output corresponding to the vector of different sets of input conditions, the fault detection simulator 230 may determine that a fault is detected. For example, if the simulated output matches the vector of expected output, the fault detection simulator 230 may determine that no fault is detected.

[0033] In some embodiments, table reducer 240 is a component that reduces the table from logical-behavioral model generator 220 based on a fault detection simulation. In other embodiments, table reducer 240 may be replaced by another component that performs the functions of table reducer 240. In some embodiments, table reducer 240 configures fault detection simulator 230 or causes fault detection simulator 230 to perform fault detection simulation on multiple instances of a circuit model using existing test patterns, and reduces the table of the circuit model from logical-behavioral model generator 220 based on the fault detection simulation. In one approach, table reducer 240 detects one of the multiple instances of the circuit model that exhibits a fault result different from the corresponding output result when simulated using a set of input conditions for the logical-behavioral model in the table. Table reducer 240 then excludes the logical-behavioral model that was applied to the instance and exhibited a fault result from the multiple logical-behavioral models in the table. In one approach, table reducer 240 detects each of the multiple instances that exhibits a fault result different from the corresponding output result when simulated using a set of input conditions for the logical-behavioral model in the table. Then, the table reducer 240 may exclude the logical behavioral models that are applied to the plurality of instances of the circuit model and present the fault results from the plurality of logical behavioral models in the table.

[0034] In some embodiments, vector generator 250 is a component that generates a test pattern based on the reduction table from table reducer 240. In other embodiments, vector generator 250 may be replaced by another component that performs the function of vector generator 250. In some embodiments, vector generator 250 generates a vector or sequence of input condition sets for the circuit model based on different input condition sets in the logical behavior model of the circuit model in the reduction table. Assuming that the reduction table includes a first input condition set

[01] for two inputs of a NAND gate and a second input condition set

[11] for the two inputs of the NAND gate, vector generator 250 may generate a vector or sequence of input condition sets

[01] and

[11] for the two inputs of the NAND gate. Vector generator 250 may store the test pattern in test pattern memory 280.

[0035] Advantageously, additional test patterns can be generated in an efficient manner that allow for unmodeled defects that cannot be detected based on one or more existing test patterns. For example, one or more existing test patterns are generated to detect one or more physical defects of a circuit model, but may not be able to detect unmodeled defects. On the one hand, the fault detection simulator 230 performs fault detection simulation on the circuit model based on one or more existing test patterns and determines one or more input condition sets or logical behavior models, thereby allowing for the detection of one or more defects of the circuit model. The table reducer 240 can then generate a reduction table by excluding one or more logical behavior models. The vector generator 250 can generate additional test patterns based on one or more input condition sets or logical behavior models in the reduction table. Therefore, additional test patterns can be generated that can compensate for the shortcomings of one or more existing test patterns.

[0036] In some embodiments, logic modifier 270 is a component that modifies the circuit design based on fault detection simulation generation. In other embodiments, logic modifier 270 may be replaced by another component that performs the functions of logic modifier 270. In some embodiments, logic modifier 270 configures fault detection simulator 230 to perform fault detection simulation on multiple instances of the circuit model using the additional test patterns generated by vector generator 250, and detects one or more input condition sets in the reduction table that fail to detect any faults. If fault detection based on the additional test patterns fails to detect a fault, logic modifier 270 may modify the circuit model for one or more input condition sets in the reduction table. For example, logic modifier 270 may add logic circuit models (e.g., sequential logic circuit models and / or control logic circuit models) to the input ports of the circuit model to adaptively configure the input conditions at the input ports. By adaptively configuring the input conditions at the input ports, incorrect circuit operation caused by faults that were undetectable by the original circuit model can be detected. If fault detection based on the additional test patterns detects at least one corresponding fault for each input condition set in the reduction table, logic modifier 270 may verify the additional test patterns without modifying the circuit model.

[0037] Figure 3A is an example diagram of a circuit model 310 according to one embodiment, and Figure 3B According to one embodiment Figure 3A An example schematic diagram 320 of a circuit model 310 is shown. In one aspect, the circuit model 310 is a computer-generated model that electrically represents an AND gate having input ports A and B and an output port Z. In one configuration, the AND gate can be implemented as P-type transistors M1 and M2 (e.g., P-channel field-effect transistors) and N-type transistors M3 and M4 (e.g., N-channel field-effect transistors). In one configuration, the P-type transistors M1 and M2 are connected in parallel between a ground rail providing a ground voltage GND and the output port Z, and the N-type transistors M3 and M4 are connected in series between a power rail providing a power supply voltage VDD and the output port Z. In one configuration, input port A is coupled to the gate electrodes of transistors M1 and M4, and input port B is coupled to the gate electrodes of transistors M2 and M3. In this configuration, transistors M1-M4 can perform an AND logic operation based on the input conditions received at input ports A and B, and output the result of the AND logic operation at output port Z.

[0038] In some embodiments, an AND gate implemented according to the circuit model 310 may have various defects. For example, the AND gate may have parasitic resistances R1-R4 and an open circuit B1. In one approach, some defects of the AND gate may be modeled, and a test pattern may be generated to detect the modeled defects. For example, a test pattern having input condition

[00] applied to input ports A and B of the AND gate 310 may be used to detect any physical defects R1-R4 and / or open circuit B1. However, such a test pattern generated based on the modeled defects based on the physical characteristics of the AND gate may not detect unmodeled defects. In some embodiments, by assigning virtual defects to different sets of input conditions of the circuit model and generating test patterns based on the virtual defects disclosed herein, new or updated test patterns may be generated to test the integrated circuit using input conditions not covered by pre-generated or existing test patterns. Therefore, incorrect circuit operation due to defects that may not have been modeled can be detected by applying the new or updated test pattern to the integrated circuit.

[0039] Figure 4 4 is an example table 410 of a logical behavioral model with virtual defects according to one embodiment. The logical behavioral model generator 220 may determine all possible input condition sets for the integrated circuit and generate a table including corresponding output results for each input condition set. For each input condition set, the logical behavioral model generator 220 may generate and assign a unique virtual defect to identify the input condition set. Figure 4 In the example shown, the logical behavior model generator 220 may generate a table 410 including different input condition sets at input ports A and B, wherein each input condition set is associated with a corresponding output result and a corresponding virtual defect D. A virtual defect D may be an arbitrarily generated defect assigned to or corresponding to a unique input condition set, regardless of the physical characteristics of the integrated circuit. In one aspect, each virtual defect D serves as an identifier for the corresponding input condition set. For example, input condition set

[00] is associated with output result [0] and virtual defect D1; input condition set

[01] is associated with output result [0] and virtual defect D2; input condition set

[10] is associated with output result [0] and virtual defect D3; and input condition set

[11] is associated with output result [1] and virtual defect D4. In one aspect, each input condition set is associated with a unique virtual defect. By assigning a virtual defect to each input condition set regardless of the physical characteristics of the circuit, and generating test patterns based on different input conditions assigned with different virtual defects, new or updated test patterns may be generated to test the integrated circuit using input conditions that are not covered by pre-generated or existing test patterns. Therefore, incorrect circuit operation due to unmodeled defects can be detected according to the test pattern based on the virtual defects.

[0040] Figure 5 is an example table 510 of a logic behavior model for a dynamic logic circuit model with virtual defects according to one embodiment. In one aspect, table 510 is similar to Figure 4 Table 410, except that table 510 includes a logic behavioral model with input conditions, where the input conditions have dynamic states. For example, table 510 includes a state [R] corresponding to a rising edge of the input signal and a state [F] corresponding to a falling edge of the input signal. In one aspect, logic behavioral model generator 220 can generate table 510, which includes different sets of input conditions with different dynamic states at input ports A and B, where each input condition set is associated with a corresponding virtual defect. Thus, the table can include behavioral models for various sets of input conditions, including static states (e.g., [0] or [1]), dynamic states (e.g., [R] or [F]), any different logic states, or any combination thereof. By assigning virtual defects to different sets of input conditions for a circuit model and generating test patterns based on the virtual defects disclosed herein, new or updated test patterns can be generated to test integrated circuits using input conditions that are not covered by pre-generated or existing test patterns. Thus, by generating test patterns based on table 510, incorrect circuit operation due to defects that may be difficult to model or predict can be detected.

[0041] Figure 6A 600 are example results of a fault detection simulation performed on a circuit model according to one embodiment. Figure 6B According to one embodiment, Figure 6A 6. In one embodiment, the table reducer 240 generates a reduction table 650 of instances of logical behavioral models based on the results 600 of the fault detection simulation in the table. In one method, the table reducer 240 generates a reduction table 650 from the table of logical behavioral models, the reduction table 650 including one or more input condition sets that cannot detect any fault by any instance based on one or more predetermined or existing test patterns. In one embodiment, the test pattern generator 110 determines whether there are untested behavioral models in the table. The test pattern generator 110 may determine to make one or more behavioral models with input condition sets that produce one or more instances (which present fault simulation results) as tested behavioral models. The test pattern generator 110 may determine to make one or more behavioral models with input condition sets that cannot detect any fault as untested behavioral models. In one method, the test pattern generator 110 may exclude tested logical behavioral models (or logical behavioral models that are applied to one or more instances and present fault results) from the plurality of logical behavioral models in the table. Based on one or more input condition sets in reduction table 650 , vector generator 250 may generate additional test patterns that may allow detection of incorrect circuit operation due to one or more faults not detected by pre-generated or existing test patterns.

[0042] In one example, the IC design includes instances 1-4 of a three-input AND gate model. In one approach, a fault detection simulation is performed according to a test pattern (e.g., a pre-generated or existing test pattern). In one approach, the fault detection simulator 230 simulates the IC design according to the test pattern. Additionally, the fault detection simulator 230 obtains a table of eight behavioral models, for example, from the logical behavioral model generator 220. For each set of input conditions for the corresponding behavioral model in the table, the fault detection simulator 230 may determine whether any faults can be detected by any instance of the AND gate model. For example, if the simulation output is different from a vector of expected outputs corresponding to vectors of different input condition sets, the test pattern generator 110 may determine that a fault is detected. For example, if the simulation output matches a vector of expected outputs, the test pattern generator 110 may determine that no fault is detected. In Figure 6A In the example shown, for input condition set

[000] , instance 1 detects a fault, while for input condition set

[001] , instance 4 detects a fault. For input condition sets

[010] ,

[011] ,

[100] , instances 3 and 4 detect a fault. For input condition set

[101] , instance 4 detects a fault. In addition, for input condition sets

[110] and

[111] , no fault is detected. Therefore, the fault detection simulator 230 can detect one or more input condition sets (e.g.,

[110] and

[111] ) that cannot detect any fault based on pre-generated or existing test patterns. Figure 6A As shown in the results 600 of the fault detection simulation, the table reducer 240 generates a reduction table 650 that includes behavioral models associated with the input condition sets

[110] and

[111] for which no faults can be detected according to previously generated or existing test patterns. In one approach, the table reducer 240 may delete or exclude behavioral models associated with the input condition sets

[000] ,

[001] ,

[010] ,

[011] ,

[100] ,

[101] for which any faults can be detected according to the pre-generated or existing test patterns in the table 600. In addition, the vector generator 250 may generate additional test patterns based on the input condition sets

[110] and

[111] in the reduction table 650, which may allow one or more faults that cannot be detected by the pre-generated or existing tests to be detected.

[0043] Figure 7A 700 is an example result of a fault detection simulation performed on a circuit model according to one embodiment. Figure 7B is an example reduction table 750 of a logical behavioral model of a circuit model with virtual defects according to one embodiment. The result 700 is similar to Figure 6AResult 600, except that for each of the input condition sets

[010] ,

[011] ,

[100] ,

[101] , a fault is detected by performing fault simulation on instances 1-4. Figure 6A Unlike the examples shown, the fault detection simulator 230 may detect one or more input condition sets (e.g.,

[000] ,

[101] ,

[110] , and

[111] ) for which no faults can be detected by each of the examples 1-4 according to pre-generated or existing test patterns. The table reducer 240 may generate a reduction table 750 from the table of the logical behavioral model, the reduction table 750 including one or more input condition sets (e.g.,

[000] ,

[101] ,

[110] , and

[111] ) for which all faults cannot be detected by each of the examples 1-4 according to one or more pre-generated or existing test patterns. Based on the one or more input condition sets in the reduction table 750, the vector generator 250 may generate one or more additional test patterns, which may allow for detection of incorrect circuit operation due to one or more faults that cannot be detected by the pre-generated or existing test patterns. By generating reduction table 750 based on one or more input condition sets (e.g.,

[000] ,

[101] ,

[110] , and

[111] ), additional test patterns can be generated that allow instances 1-4 to consistently detect one or more faults that cannot be detected by each of instances 1-4 based on pre-generated or existing test patterns.

[0044] Figure 8A is an example circuit model 800 according to one embodiment. Figure 8B860 is a modified circuit model according to an example of one embodiment. A circuit designer can generate a model of any logic circuit that can predict the logical behavior of the logic circuit in response to different sets of input conditions. For example, assume that circuit model 800 includes AND gate 810 and inverter 820, wherein a first input port of AND gate 810 is coupled to an input port of inverter 820, and an output port of inverter 820 is coupled to a second input port of AND gate 810. If logic modifier 270 determines that a test pattern generated based on a reduction table with virtual defects cannot detect a fault for one or more input conditions, logic modifier 270 can add other circuit models. For example, logic modifier 270 can add latch 880 and AND gate 870 to modified circuit design model 860. In one aspect, latch 880 and AND gate 870 are operable to adaptively change or control the input signal applied to AND gate 810. For example, the output port of inverter 820 is coupled to the first input port of AND gate 870, the output port of latch 880 is coupled to the second input port of AND gate 870, and the output port of AND gate 870 is coupled to the second input port of AND gate 810. By adding latch 880 and AND gate 870, the input conditions at the input ports of AND gate 810 can be adaptively configured. In some cases, latch 880 and AND gate 870 can be replaced by other logic gates that can configure or change the inputs applied to the integrated circuit to be tested. By adaptively configuring the input conditions at the input ports, various input conditions can be applied to the integrated circuit with greater flexibility. For example, without latch 880 and AND gate 870, an input condition set

[01] or

[10] can be applied to AND gate 870. By adding latch 880 and AND gate 870, a different or additional input condition set (e.g.,

[00] or

[11] ) can be applied to AND gate 810. Thus, improper circuit operation due to one or more faults that could not be detected by circuit model 800 may be detected.

[0045] Figure 9 is a flow chart of a method 900 for generating a test pattern based on a virtual defect according to some embodiments. The method 900 may be Figure 1 In one aspect, the test pattern generator 110 determines whether one or more input test patterns (e.g., existing test patterns) can test various defects of the circuit model and generates one or more additional test patterns to detect defects that cannot be detected by the one or more input test patterns. In some embodiments, the method 900 is performed by other entities. In some embodiments, the method 900 includes: Figure 9 More, fewer, or different operations than those shown.

[0046] In operation 905, the test pattern generator 110 receives an input test pattern for testing a circuit model. The input test pattern may be an existing test pattern generated based on physical properties of the circuit model and / or based on predicted logical properties of the circuit model.

[0047] In operation 910, the test pattern generator 110 assigns virtual defects. A virtual defect can be an arbitrarily generated defect assigned to or corresponding to a unique set of input conditions, regardless of the physical characteristics of the integrated circuit. In one aspect, each virtual defect serves as an identifier of the corresponding input condition set. In one method, the test pattern generator 110 determines a possible set of input conditions for a circuit model and assigns a virtual defect to the corresponding set of input conditions. The test pattern generator 110 may generate a behavioral model for the corresponding set of input conditions. For example, the behavioral model includes a corresponding set of input conditions, a corresponding output result, and a corresponding virtual defect. In one aspect, the virtual defects are generated without regard to the physical characteristics of the integrated circuit formed according to the circuit model. Each virtual defect can be associated with a single corresponding set of input conditions. In operation 920, the test pattern generator 110 generates a table (e.g., 410, 510) of logical behavioral models.

[0048] In operation 930, the test pattern generator 110 performs a fault detection simulation. In one method, the test pattern generator 110 simulates the circuit model based on the input test pattern and determines whether a fault can be detected. For example, if the simulated output differs from the vector of the expected output corresponding to the vector of the different input condition sets, the test pattern generator 110 may determine that a fault has been detected. For example, if the simulated output matches the vector of the expected output, the test pattern generator 110 may determine that a fault has not been detected.

[0049] In operation 940, the test pattern generator 110 determines whether there are untested behavioral models in the table. In one approach, the test pattern generator 110 detects one of the multiple instances of the circuit model that is simulated using a set of input conditions for the logical behavioral model in the table (e.g., 410, 510) and exhibits a fault result that differs from the corresponding output result. In one approach, the table reducer 240 detects each of the multiple instances that is simulated using a set of input conditions for the logical behavioral model in the table (e.g., 410, 510) and exhibits a fault result that differs from the corresponding output result. The test pattern generator 110 may determine that one or more behavioral models with input condition sets that produce one or more instances exhibiting fault simulation results are tested behavioral models. The test pattern generator 110 may determine that one or more behavioral models with input condition sets that fail to detect any faults are untested behavioral models. In response to determining that there are no untested behavioral models, the test pattern generator 110 may end process 900 in operation 945. In one example, the test pattern generator 110 may determine that the input test pattern is sufficient to test various defects of the circuit model.

[0050] In response to determining that an untested behavioral model exists in the table, the test pattern generator 110 generates a reduction table (e.g., 650, 750) of logical behavioral models in operation 950. In one approach, the test pattern generator 110 may exclude tested logical behavioral models (or logical behavioral models that have been applied to one or more instances and exhibited a failure result) from the plurality of logical behavioral models in the table. In operation 960, the test pattern generator 110 generates additional test patterns based on the reduction table. In one approach, the test pattern generator 110 generates a vector or sequence of input condition sets for the circuit model based on different input condition sets in the logical behavioral model of the circuit model in the reduction table (e.g., 650, 750).

[0051] In operation 970, the test pattern generator 110 performs a fault detection simulation based on the additional test pattern. In one approach, the test pattern generator 110 simulates the circuit model based on the additional test pattern and determines whether a fault can be detected. In operation 980, the test pattern generator 110 may determine whether there are untested behavioral models in the reduction table (e.g., 650, 750). In response to determining that there are no untested behavioral models, in operation 990, the test pattern generator 110 may verify the additional test pattern and store it, for example, via the test pattern memory 280. After storing the test pattern in operation 990, the test pattern generator 110 may proceed to operation 945 and generate a report on how many units remain to be fully tested and how many test patterns (e.g., existing test patterns and / or additional test patterns) are needed to test the remaining units.

[0052] In response to determining that an untested behavioral model exists in the reduction table, the test pattern generator 110 may modify the circuit model in operation 985. For example, the test pattern generator 110 may add a sequential logic circuit model (e.g., 880) and an AND gate model (e.g., 870) to the input port of the circuit model and return to operation 950. By adding a sequential logic circuit, various input conditions can be applied to the integrated circuit with greater flexibility.

[0053] Advantageously, generating test patterns based on virtual defects disclosed herein allows circuit elements to detect erroneous calculations despite the presence of unmodeled defects. In one aspect, the test pattern generator 110 determines whether one or more input test patterns (e.g., existing test patterns) can test various defects of the circuit model and generates one or more additional test patterns to detect defects that cannot be detected by the one or more input test patterns. In some embodiments, a set of possible input conditions for the circuit element is determined, and each set of input conditions is assigned to a unique virtual defect, regardless of any physical defects of the circuit element. In addition, test patterns can be generated based on different sets of input conditions with virtual defects. Test patterns based on different sets of input conditions with virtual defects can allow detection of incorrect circuit operation due to unmodeled defects.

[0054] Advantageously, virtual defects allow for efficient test pattern generation. By assigning a unique virtual defect to each corresponding set of input conditions, regardless of the physical characteristics of the circuit model, and generating test patterns based on different sets of input conditions and corresponding virtual defects, cost-inefficient simulations (e.g., SPICE simulations) to predict the effects of physical defects can be avoided. Thus, by omitting such cost-inefficient simulations, test patterns can be generated in a computationally efficient manner.

[0055] Advantageously, additional test patterns can be generated in an efficient manner that allow for detection of unmodeled defects that cannot be detected based on one or more existing test patterns. For example, one or more existing test patterns may be generated to detect one or more physical defects of a circuit model, but the existing test patterns may not be able to detect the unmodeled defects. Based on the existing test patterns, a fault detection simulation can be performed on the circuit model. Furthermore, one or more input condition sets or logical behavior models can be determined that cannot detect defects in the circuit model through fault detection simulation based on the existing test patterns. Furthermore, based on the determined one or more input condition sets or logical behavior models that cannot detect defects in the circuit model through fault detection simulation based on the existing test patterns, an additional test pattern capable of detecting defects in the circuit model can be generated.

[0056] Now refer to Figure 10 , shows an example block diagram of a computing system 1000 according to some embodiments of the present invention. A circuit or layout designer may use the computing system 1000 for integrated circuit design. As used herein, a "circuit" is an interconnection of electrical elements, such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices configured to implement a desired function. The computing system 1000 includes a host device 1005 associated with a memory device 1010. In some embodiments, the host device 1005 is implemented as Figure 1 The host device 1005 may be configured to receive input from one or more input devices 1015 and provide output to one or more output devices 1020. The host device 1005 may be configured to communicate with the memory device 1010, the input device 1015, and the output device 1020 via appropriate interfaces 1025A, 1025B, and 1025C, respectively. The computing system 1000 may be implemented in various computing devices, such as computers (e.g., desktops, laptops, servers, data centers, etc.), tablets, personal digital assistants, mobile devices, other handheld or portable devices, or any other computing unit suitable for performing schematic design and / or layout design using the host device 1005.

[0057] Input device 1015 may include any of a variety of input technologies, such as a keyboard, a stylus, a touch screen, a mouse, a trackball, a keypad, a microphone, voice recognition, motion recognition, a remote control, an input port, one or more buttons, a dial, a joystick, and any other input peripheral device associated with host device 1005 and allowing an external source, such as a user (e.g., a circuit or layout designer), to input information (e.g., data) into the host device and to send instructions to the host device. Similarly, output device 1020 may include a variety of output technologies, such as external memory, a printer, a speaker, a display, a microphone, a light-emitting diode, a headset, a video device, and any other output peripheral device configured to receive information (e.g., data) from host device 1005. "Data" input to and / or output from host device 1005 may include any of the following: various text data, circuit data, signal data, semiconductor device data, graphics data, combinations thereof, or other types of analog and / or digital data suitable for processing using computing system 1000.

[0058] Host device 1005 includes or is associated with one or more processing units / processors, such as central processing unit ("CPU") cores 1030A-1030N. CPU cores 1030A-1030N may be implemented as an application-specific integrated circuit ("ASIC"), a field-programmable gate array ("FPGA"), or any other type of processing unit. Each of CPU cores 1030A-1030N may be configured to execute instructions for running one or more applications of host device 1005. In some embodiments, the instructions and data for running one or more applications may be stored within storage device 1010. Host device 1005 may also be configured to store the results of running one or more applications within storage device 1010. Thus, host device 1005 may be configured to request storage device 1010 to perform various operations. For example, host device 1005 may request storage device 1010 to read data, write data, update or delete data, and / or perform management or other operations. One such application that host device 1005 may be configured to run may be test mode application 1035. Test pattern application 1035 may be part of a computer-aided design or electronic design automation software suite that a user of host device 1005 may use to generate test patterns for testing integrated circuits. In some embodiments, instructions for executing or running test pattern application 1035 may be stored within memory device 1010. Test pattern application 1035 may be executed by one or more CPU cores 1030A-1030N using instructions associated with generating test patterns from memory device 1010.

[0059] Still refer to Figure 10 Memory device 1010 includes a memory controller 1040 configured to read data from or write data to a memory array 1045. Memory array 1045 may include various volatile and / or non-volatile memories (or non-transitory computer-readable media). For example, in some embodiments, memory array 1045 may include NAND flash memory cores. In other embodiments, memory array 1045 may include NOR flash memory cores, static random access memory (SRAM) cores, dynamic random access memory (DRAM) cores, magnetoresistive random access memory (MRAM) cores, phase change memory (PCM) cores, resistive random access memory (ReRAM) cores, 3D XPoint memory cores, ferroelectric random access memory (FeRAM) cores, and other types of memory cores suitable for use within the memory array. The memories within memory array 1045 may be individually and independently controlled by memory controller 1040. In other words, memory controller 1040 may be configured to communicate individually and independently with each memory within memory array 1045. By communicating with the memory array 1045, the memory controller 1040 can be configured to read data from the memory array or write data to the memory array in response to instructions received from the host device 1005. Although shown as being part of the memory device 1010, in some embodiments, the memory controller 1040 can be part of the host device 1005 or part of another element of the computing system 1000 and associated with the memory device. The memory controller 1040 can be implemented as logic circuitry in software, hardware, firmware, or a combination thereof to perform the functions described herein. For example, in some embodiments, the memory controller 1040 can be configured to retrieve instructions associated with the test mode application 1035 stored in the memory array 1045 of the memory device 1010 after receiving a request from the host device 1005.

[0060] Understandably, Figure 10 Only some of the elements of computing system 1000 are shown and described herein. However, computing system 1000 may include other elements, such as various batteries and power supplies, network interfaces, routers, switches, external storage systems, controllers, and the like. In general, computing system 1000 may include any of the various hardware, software, and / or firmware elements deemed necessary or desirable in performing the functions described herein. Similarly, host device 1005, input device 1015, output device 1020, and storage device 1010, including memory controller 1040 and memory array 1045, may include any of the various hardware, software, and / or firmware elements deemed necessary or desirable in performing the functions described herein.

[0061] One aspect of the present disclosure relates to an integrated circuit. In some embodiments, a corresponding virtual defect is assigned to each of a plurality of input condition sets of a circuit model. In some embodiments, a table of circuit models is generated that includes a plurality of logical behavioral models of the circuit model. Each of the plurality of logical behavioral models may include a corresponding set of a plurality of input condition sets, a corresponding output result, and a corresponding virtual defect. In some embodiments, a test pattern is generated for the circuit model based at least in part on the table of circuit models.

[0062] One aspect of this specification relates to a device for testing integrated circuits. In some embodiments, the device includes one or more processors and a non-transitory computer-readable medium. The non-transitory computer-readable medium may store instructions that, when executed by the one or more processors, cause the one or more processors to generate a table of circuit models comprising logical behavioral models of multiple circuit models. Each of the multiple logical behavioral models may include a corresponding set of input conditions, an output result, and a virtual defect. The non-transitory computer-readable medium may store instructions that, when executed by the one or more processors, cause the one or more processors to perform a fault detection simulation on the circuit model according to one or more test patterns associated with the circuit model. The non-transitory computer-readable medium may store instructions that, when executed by the one or more processors, cause the one or more processors to generate a reduction table for the circuit model based on the fault detection simulation. The non-transitory computer-readable medium may store instructions that, when executed by the one or more processors, cause the one or more processors to generate additional test patterns based on the reduction table of the circuit model.

[0063] One aspect of this specification relates to a non-transitory computer-readable medium for testing integrated circuits. The non-transitory computer-readable medium may store instructions that, when executed by one or more processors, cause the one or more processors to generate a table of circuit models, the table including multiple logical behavioral models of the circuit models. Each of the multiple logical behavioral models may include a corresponding set of input conditions, an output result, and a virtual defect. The non-transitory computer-readable medium may store instructions that, when executed by the one or more processors, cause the one or more processors to simulate multiple instances of the circuit model according to one or more test patterns associated with the circuit model. The non-transitory computer-readable medium may store instructions that, when executed by the one or more processors, cause the one or more processors to detect a first instance of the multiple instances of the circuit model. The first instance may be simulated using the input condition set of the logical behavioral models in the table and present a fault result that is different from the corresponding output result. The non-transitory computer-readable medium may store instructions that, when executed by the one or more processors, cause the one or more processors to exclude the detected logical behavioral model from the table of circuit models.

[0064] One aspect of the present specification relates to a method for testing a circuit model, comprising: assigning a corresponding virtual defect to each of a plurality of input condition sets of the circuit model; generating a table of the circuit model, the table comprising a plurality of logical behavior models of the circuit model, each of the plurality of logical behavior models comprising a corresponding set of a plurality of input condition sets, a corresponding output result, and a corresponding virtual defect; and generating a test pattern for the circuit model based at least in part on the table of the circuit model.

[0065] In the above method, virtual defects are generated without considering the physical characteristics of the integrated circuit formed according to the circuit model.

[0066] The above method further includes: testing the integrated circuit formed based on the circuit model according to a test mode.

[0067] In the above method, the test pattern includes vectors of two or more different sets of the plurality of input condition sets.

[0068] In the above method, it also includes: performing a fault detection simulation on the circuit model according to one or more different test patterns associated with the circuit model; and generating a reduction table of the circuit model according to the fault detection simulation, wherein the test pattern is generated based on the reduction table of the circuit model.

[0069] In the above method, performing fault detection simulation on the circuit model includes: simulating multiple instances of the circuit model according to one or more different test modes associated with the circuit model; and detecting one instance among the multiple instances of the circuit model, where the instance is simulated using a set of input conditions of a logical behavior model in a table and presents a fault result different from the corresponding output result.

[0070] In the above method, generating a reduction table of the circuit model according to the fault detection simulation includes: excluding a logical behavioral model that is applied to an instance and presents a fault result from a plurality of logical behavioral models in the table.

[0071] In the above method, simulating fault detection on a circuit model includes: simulating multiple instances of the circuit model according to one or more different test modes associated with the circuit model, and detecting multiple instances of the circuit model, each of the multiple instances is simulated using a set of input conditions of a logical behavior model in a table, and presenting a fault result different from the corresponding output result, wherein the logical behavior model is determined to be one or more of the multiple logical behavior models.

[0072] In the above method, generating a reduction table of the circuit model according to the fault detection simulation includes excluding logical behavioral models that are applied to multiple instances of the circuit model and present fault results from multiple logical behavioral models in the table.

[0073] In the above method, it also includes: simulating multiple instances of the circuit model according to the test pattern; detecting one instance among the multiple instances of the circuit model, simulating the one instance using the input condition set of the logical behavior model in the reduction table, and presenting a result that matches the corresponding output result; and adding test logic to each of the multiple instances.

[0074] One aspect of the present specification relates to a device for testing a circuit model, comprising: one or more processors; and a non-transitory computer-readable medium storing instructions that, when executed by the one or more processors, cause the one or more processors to perform the following operations: generate a table of the circuit model, the table including multiple logical behavioral models of the circuit model, each of the multiple logical behavioral models including a corresponding input condition set, a corresponding output result, and a corresponding virtual defect; perform a fault detection simulation on the circuit model according to one or more test patterns associated with the circuit model; generate a reduction table of the circuit model according to the fault detection simulation; and generate an additional test pattern based on the reduction table of the circuit model.

[0075] In the above device, the non-transitory computer-readable medium stores instructions that, when executed by one or more processors, cause the one or more processors to test an integrated circuit formed based on the circuit model according to an additional test pattern.

[0076] In the above device, the additional test pattern includes vectors of two or more different sets of the plurality of sets of input conditions.

[0077] In the above-mentioned device, when executed by one or more processors that cause the one or more processors to perform fault detection simulation on the circuit model, the instructions further cause the one or more processors to: simulate multiple instances of the circuit model according to one or more test patterns associated with the circuit model, and detect one of the multiple instances of the circuit model, where the instance is simulated using the input condition set of the logical behavior model in the table and presents a fault result different from the corresponding output result.

[0078] In the above device, when executed by one or more processors to cause the one or more processors to generate a reduction table of a circuit model based on a fault detection simulation, the instructions further cause the one or more processors to: exclude a logical behavioral model that is applied to an instance and exhibits a fault result from a plurality of logical behavioral models in the table.

[0079] In the above-mentioned device, when executed by one or more processors that cause the one or more processors to perform fault detection simulation on the circuit model, the instructions also cause the one or more processors to: simulate multiple instances of the circuit model according to one or more test patterns associated with the circuit model, and detect multiple instances of the circuit model, each of the multiple instances being simulated using a set of input conditions of a logical behavioral model in a table and presenting a fault result different from a corresponding output result, wherein the logical behavioral model is determined to be one or more of the multiple logical behavioral models.

[0080] In the above device, when executed by one or more processors to cause the one or more processors to generate a reduction table for the circuit model based on a fault detection simulation, the instructions further cause the one or more processors to: exclude, from the plurality of logical behavioral models in the table, the logical behavioral models that are applied to the plurality of instances of the circuit model and present fault results.

[0081] One aspect of the present specification relates to a non-transitory computer-readable medium for storing instructions that, when executed by one or more processors, cause the one or more processors to perform the following operations: generate a table of circuit models, the table including multiple logical behavioral models of the circuit model, each of the multiple logical behavioral models including a corresponding input condition set, a corresponding output result, and a corresponding virtual defect; simulate multiple instances of the circuit model according to one or more test patterns associated with the circuit model; detect one of the multiple instances of the circuit model, the one instance being simulated using the input condition set of the logical behavioral model in the table and presenting a fault result different from its corresponding output result; and exclude the detected logical behavioral model from the table of circuit models.

[0082] In the non-transitory computer-readable medium, virtual defects are generated without considering physical characteristics of an integrated circuit formed according to a circuit model.

[0083] The non-transitory computer-readable medium further includes instructions that, when executed by one or more processors, cause the one or more processors to perform the following operations:

[0084] After the elimination operation, other test patterns are generated based on the remaining behavioral models in the table.

[0085] The features of several embodiments have been summarized above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for testing a circuit model, comprising: assigning a corresponding virtual defect to each of a plurality of input condition sets of the circuit model; generating a table of the circuit model, the table including a plurality of logical behavior models of the circuit model, each of the plurality of logical behavior models including a corresponding set of the plurality of input condition sets, a corresponding output result, and the corresponding virtual defect; performing a fault detection simulation by simulating a plurality of instances of the circuit model including logic gates according to the table, wherein simulating the plurality of instances of the circuit model comprises applying a plurality of existing test patterns to the circuit model to simulate behavior of the logic gates, each of the existing test patterns being associated with a corresponding virtual defect, and generating a plurality of simulation outputs in response to applying the plurality of existing test patterns; detecting at least one instance in the plurality of instances in which a fault is absent in response to a match between at least one simulation output and the vectors of the plurality of logical behavioral models in the table; In response to performing the detecting, determining that at least one of the plurality of logical behavioral models is untested based on the detected absence of a fault in the at least one instance of the plurality of instances corresponding to the at least one logical behavioral model of the plurality of logical behavioral models; in response to determining that the at least one of the plurality of logical behavioral models is untested, modifying the circuit model by adding one or more logic components based on an input condition that fails to detect a fault associated with the at least one of the plurality of logical behavioral models that is untested; generating a modified circuit model for physical implementation of the integrated circuit based on the modification; and A test pattern is generated for the circuit model based at least in part on the table of the circuit model, wherein the test pattern is different from the plurality of existing test patterns.

2. The method for testing a circuit model according to claim 1, wherein: The virtual defects are generated without considering physical characteristics of an integrated circuit formed according to the circuit model.

3. The method for testing a circuit model according to claim 1 , further comprising: An integrated circuit formed based on the circuit model is tested according to the test pattern.

4. The method for testing a circuit model according to claim 1, wherein: The test pattern includes vectors of two or more different sets of the plurality of sets of input conditions.

5. The method for testing a circuit model according to claim 1 , further comprising: performing a fault detection simulation on the circuit model according to one or more different test patterns associated with the circuit model; as well as A reduction table of the circuit model is generated according to the fault detection simulation, wherein the test pattern is generated based on the reduction table of the circuit model.

6. The method for testing a circuit model according to claim 5, wherein: Performing fault detection simulation on the circuit model includes: simulating multiple instances of the circuit model according to the one or more different test modes associated with the circuit model; and An instance of the plurality of instances of the circuit model is detected, the instance being simulated using the set of input conditions of the logical behavior model in the table and presenting a fault result different from the corresponding output result.

7. The method for testing a circuit model according to claim 6, wherein: Generating the reduction table of the circuit model according to the fault detection simulation includes: The logical behavioral model that is applied to the one instance and presents the fault result is excluded from the plurality of logical behavioral models in the table.

8. The method for testing a circuit model according to claim 5, wherein: Performing the fault detection simulation on the circuit model includes: simulating multiple instances of the circuit model according to the one or more different test modes associated with the circuit model, and Detecting the plurality of instances of the circuit model, each of the plurality of instances being simulated using a set of input conditions of a logical behavioral model in the table and presenting a fault result different from the corresponding output result, wherein the logical behavioral model is determined to be the one or more of the plurality of logical behavioral models.

9. The method for testing a circuit model according to claim 8, wherein: Generating the reduction table of the circuit model according to the fault detection simulation includes: The logical behavioral models that are applied to the plurality of instances of the circuit model and exhibit the fault result are excluded from the plurality of logical behavioral models in the table.

10. The method for testing a circuit model according to claim 5, further comprising: simulating multiple instances of the circuit model according to the test pattern; detecting one of the plurality of instances of the circuit model, the one instance being simulated using the set of input conditions of the logical behavior model in the reduction table and presenting a result that matches the corresponding output result; as well as Testing logic is added to each of the plurality of instances.

11. A device for testing a circuit model, comprising: one or more processors; as well as A non-transitory computer-readable medium storing instructions that, when executed by the one or more processors, cause the one or more processors to: generating a table of a circuit model, the table comprising a plurality of logical behavioral models of the circuit model, each of the plurality of logical behavioral models comprising a corresponding input condition set, a corresponding output result, and a corresponding virtual defect, performing a fault detection simulation on the circuit model including logic gates according to one or more test patterns associated with the circuit model, wherein simulating the plurality of instances of the circuit model comprises applying a plurality of existing test patterns to the circuit model to simulate behavior of the logic gates, each of the existing test patterns being associated with a corresponding virtual defect, and generating a plurality of simulation outputs in response to applying the plurality of existing test patterns, detecting at least one instance in the plurality of instances in which a fault is absent in response to a match between at least one simulation output and the vectors of the plurality of logical behavioral models in the table; In response to performing the detecting, determining that at least one of the plurality of logical-behavioral models associated with at least one of the one or more test patterns is untested based on the detected absence of a fault in the at least one of the plurality of instances corresponding to the at least one logical-behavioral model of the plurality of logical-behavioral models; generating a reduction table of the circuit model according to the detection, wherein at least one instance of the plurality of instances does not have a fault and at least one of the plurality of logical behavior models is untested, modifying the circuit model by adding one or more logic components based on an input condition that fails to detect a fault associated with at least one of the plurality of untested logic behaviors according to the reduction table; generating a modified circuit model for physical implementation of the integrated circuit based on the modification; and An additional test pattern is generated based on the modified circuit model, wherein the additional test pattern is different from the plurality of existing test patterns.

12. The device for testing a circuit model according to claim 11, wherein: The non-transitory computer-readable medium stores instructions that, when executed by the one or more processors, cause the one or more processors to test an integrated circuit formed based on the circuit model according to the additional test pattern.

13. The device for testing a circuit model according to claim 11, wherein: The additional test pattern includes vectors of two or more different sets of the plurality of sets of input conditions.

14. The device for testing a circuit model according to claim 11, wherein: When executed by the one or more processors causing the one or more processors to perform the fault detection simulation on the circuit model, the instructions further cause the one or more processors to: simulate multiple instances of the circuit model according to the one or more test patterns associated with the circuit model, and An instance of the plurality of instances of the circuit model is detected, the instance being simulated using the set of input conditions of the logical behavior model in the table and presenting a fault result different from the corresponding output result.

15. The device for testing a circuit model according to claim 14, wherein: When executed by the one or more processors, the instructions cause the one or more processors to generate the reduction table of the circuit model based on the fault detection simulation, further causing the one or more processors to: The logical behavioral model that is applied to the one instance and presents the fault result is excluded from the plurality of logical behavioral models in the table.

16. The device for testing a circuit model according to claim 14, wherein: When executed by the one or more processors, the instructions cause the one or more processors to perform the fault detection simulation on the circuit model, further causing the one or more processors to: simulating multiple instances of the circuit model according to the one or more test patterns associated with the circuit model, and Detecting the plurality of instances of the circuit model, each of the plurality of instances being simulated using a set of input conditions of a logical behavioral model in the table and presenting a fault result different from the corresponding output result, wherein the logical behavioral model is determined to be the one or more of the plurality of logical behavioral models.

17. The device for testing a circuit model according to claim 16, wherein: The instructions, when executed by the one or more processors causing the one or more processors to generate the reduction table of the circuit model based on the fault detection simulation, further cause the one or more processors to: The logical behavioral models that are applied to the plurality of instances of the circuit model and exhibit the fault result are excluded from the plurality of logical behavioral models in the table.

18. A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to: generating a table of a circuit model, the table comprising a plurality of logical behavioral models of the circuit model, each of the plurality of logical behavioral models comprising a corresponding input condition set, a corresponding output result, and a corresponding virtual defect; Simulating multiple instances of the circuit model including logic gates according to one or more test patterns associated with the circuit model, wherein simulating the plurality of instances of the circuit model includes applying a plurality of existing test patterns to the circuit model to simulate behavior of the logic gates, each of the existing test patterns being associated with a corresponding virtual defect, and generating a plurality of simulation outputs in response to applying the plurality of existing test patterns; detecting an instance of the plurality of instances of the circuit model, the instance being simulated using the set of input conditions of the logic behavior model in the table and presenting a fault result different from its corresponding output result; responsive to a match between at least one simulation output and the vectors of the plurality of logical behavioral models in the table, determining that the at least one other instance in the plurality of instances is untested based on the at least one other instance in the plurality of instances corresponding to the at least one other logical behavioral model not having a fault; as well as excluding the logical behavioral model from the table of circuit models based on the detected one instance; in response to the at least one other instance of the plurality of instances being untested, modifying the circuit model by adding one or more logic components based on input conditions that fail to detect a fault associated with the other logical behavioral models in which the fault is not present; generating a modified circuit model for physical implementation of the integrated circuit based on the modification; An additional test pattern is generated based on the modified circuit model, wherein the additional test pattern is different from the plurality of existing test patterns.

19. The non-transitory computer-readable medium of claim 18, wherein: The virtual defects are generated without considering physical characteristics of an integrated circuit formed according to the circuit model.

20. The non-transitory computer-readable medium of claim 18, further comprising instructions that, when executed by the one or more processors, cause the one or more processors to: After the elimination operation, other test patterns are generated according to the remaining behavior models in the table.

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