Overload protection method, shutdown protection method and circuit protection system

Abstract

The application discloses an overload protection method, a system enters a start mode; the working voltage is charged; it is judged whether the feedback voltage is kept less than the second voltage within the first time value; a latch signal is output according to the detection result of the feedback voltage; the OLP protection is started and the delay time of the OLP protection is selected according to the latch signal. The application also discloses a shutdown protection method, a system enters a shutdown mode; the system triggers the OLP protection for the first time and waits for a debounce cycle for the first time; the OLP protection is delayed for the first delay time; the system triggers the OLP protection for the second time and waits for the debounce cycle for the second time; before the end of the debounce cycle for the second time, the first input signal is input, and the system enters a normal start. The application also discloses a circuit protection system. The application can avoid the false start of the OLP protection by adjusting the response time between the start and shutdown in the shutdown mode.

Description

Technical Field

[0001] This invention relates to the field of electronic information, and in particular to an overload protection method, a shutdown protection method, and a circuit protection system. Background Technology

[0002] In typical SSR secondary-side feedback systems, OLP (Optical Line Protection) is a core performance indicator. OLP protection monitors the line in real time and automatically shuts down the main power switch when an anomaly is detected, thus providing protection. Therefore, OLP protection is an essential requirement for SSR IC circuits. In traditional applications, OLP protection generally does not cause additional OLP false protection issues in the system because its protection method is directly linked to the output voltage and is independent of the input energy: when the optocoupler feedback voltage remains consistently higher than a certain threshold for SSR Low Side connection or consistently lower than a certain threshold for SSR High Side connection, and this continues for one debounce cycle T_debounce, the OLP protection system stops switching (i.e., shuts down the main power switch) and then enters the restart phase.

[0003] In a typical VDD RC boot system, as shown in the attached... Figure 1 As shown, after the OLP protection stops the switch, the system needs to perform a UVLO reset and restart (UVLO is short for "undervoltage lockout"). During the UVLO reset and restart process, the operating voltage VDD will drop, and the restart time is relatively long. Therefore, during the UVLO reset and restart process, there will be no OLP false protection due to rapid power-on / off; that is, the system does not respond to rapid input changes during the restart phase.

[0004] In a typical high-voltage self-powered SSR system, as shown in the attached... Figure 2 As shown, with the SSR IC circuit system transitioning from a typical VDDRC boot system to a high-voltage self-powered system, the OLP protection restart logic can no longer use the original ULVO zero-restart method. This is because the VDD of the high-voltage self-powered system is continuously powered by the JEFT transistor and stabilized at a constant value.

[0005] Therefore, the OLP protection logic designed in existing high-voltage self-powered systems generally exhibits the following sequence: (1) Entering the output overload state; (2) Maintaining for more than one debounce cycle T_debounce; (3) Triggering OLP protection (while VDD is stabilized at a constant value); (4) Timing a certain time as the delay time T_delay for OLP protection; (5) The system enters the power-on restart, and all protections are cleared (i.e., OLP protection stops).

[0006] When OLP protection is triggered due to output overload and VDD is stabilized at a constant value, OLP protection will be delayed. After the OLP protection delay ends, the system will enter normal boot-up and restart.

[0007] In a high-voltage self-powered system, a continuously high FB will trigger the OLP protection logic. However, insufficient input energy in shutdown mode can also cause FB to go high, making the condition that "FB going high" triggers "OLP protection" not unique. If the OLP protection logic is triggered in shutdown mode, and the auxiliary winding charge is sufficient to maintain VDD for a relatively long time (>T_debounce) to prevent the system from dropping to UVLO, then as the input AC OFF and BUS energy drop, the system will enter an OLP protection delay state (i.e., OLP Delay state, extending the OLP protection time) due to failure to shut down normally. In this state, fast power-on / off will be exempt from response. Because the IC does not respond to input power-on during the OLP protection delay, the system cannot respond to output in a timely manner, thus losing the ultra-fast start-up advantage inherent in high-voltage self-powered systems.

[0008] When OLP protection is triggered in shutdown mode, and VDD is stabilized at a constant value for a relatively long period, OLP protection delay will also occur. However, the delay time is longer in this case, preventing the system from entering fast boot mode. Therefore, this type of OLP protection delay is considered a false OLP protection event.

[0009] As explained above, existing technologies lack a clear method for distinguishing between OLP protection triggered by power-off and OLP protection triggered by overload. Furthermore, existing technologies typically extend the OLP protection debounce period (OLP debounce time) to discharge more VDD charge, thereby enabling a faster UVLO reset and restart after AC OFF. This approach has significant limitations. This is because: the size of the auxiliary winding capacitor and the load both require the system's minimum OLP debounce time to be much higher than practically acceptable, but the practically acceptable OLP debounce time cannot be significantly affected by short-circuit peak power consumption. Additionally, the system's heat generation during a short circuit also constrains the OLP debounce time. In summary, this ultimately leads to an unreasonable design, resulting in false OLP protection due to rapid power-on and power-off, thus impacting the customer's user experience. Summary of the Invention

[0010] This invention addresses the shortcomings of existing technologies by providing an overload protection method, a shutdown protection method, and a circuit protection system.

[0011] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0012] This invention discloses an overload protection method, which includes the following steps when the system enters the power-on mode:

[0013] Once the operating voltage has been cleared to zero, the system enters power-on mode.

[0014] The system soft start is completed when the operating voltage rises and exceeds the first voltage.

[0015] A first time value is timed and the feedback voltage is detected. It is determined whether the feedback voltage is less than the second voltage within the first time value; the first time value is not greater than the debouncing period.

[0016] A latch signal is output based on the detection result of the feedback voltage;

[0017] The OLP protection is initiated based on the latch signal, and the delay time of the OLP protection is selected; initiating the OLP protection includes stopping the main power switch.

[0018] Optionally, when it is determined that the feedback voltage is less than the second voltage within the first time value, a latch signal is output; when it is determined that the feedback voltage is not less than the second voltage within the first time value, a latch signal is not output.

[0019] Optionally, when a latch signal is detected, the OLP protection is not activated; when no latch signal is detected, the OLP protection is activated, and the delay time is selected as the second delay time.

[0020] Optionally, when a latching signal is detected and the OLP protection is in the activated state, the delay time is selected as a first delay time; the second delay time is greater than the first delay time.

[0021] Optionally, when a load overload occurs after the system enters boot mode, the following steps are included:

[0022] Upon receiving the first input signal, the system enters power-on mode and begins normal operation.

[0023] When the load overload occurs, the OLP protection is triggered and the system waits for one debouncing cycle for the first time.

[0024] Once the first waiting period for the dejittering cycle ends, the OLP protection is activated and the first delay time is applied for the first time.

[0025] The OLP protection ends when the first delay time of the first delay period ends.

[0026] Optionally, if the load overload is not relieved after the first delay time of the first delay, the following steps are further repeated:

[0027] If the overload is not relieved, the OLP protection is triggered again and another debouncing cycle is waited for.

[0028] After the de-jittering cycle ends again, the OLP protection is activated and the delay time is extended. During the de-jittering cycle, if the load remains overloaded within the first time value, the delay time is set to the second delay time. If the load is de-loaded within the first time value, the delay time is set to the first delay time.

[0029] When the delay period ends, the OLP protection ends.

[0030] This invention also discloses a shutdown protection method, which includes the following steps when the system enters shutdown mode:

[0031] When the system is working normally, if a second input signal is input, the system will enter shutdown mode.

[0032] The system triggers OLP protection for the first time and waits for a debounce cycle for the first time. The operating voltage drops during the first debounce cycle.

[0033] When the first debounce cycle ends and the operating voltage has dropped below the third voltage, the OLP protection is activated, the main power switch stops, and after the first input signal is input, the system enters normal startup, and the main power switch restarts; when the first debounce cycle ends and the operating voltage has not dropped below the third voltage, the OLP protection is activated and delayed for a first delay time, the main power switch stops and remains stopped for the first delay time;

[0034] When the first delay time ends and the operating voltage has dropped below the third voltage, the OLP protection stops, the main power switch is released from its held stop state, and after the first input signal is input, the system enters normal startup and the main power switch restarts; when the first delay time ends and the operating voltage has not dropped below the third voltage, the system triggers the OLP protection for the second time and waits for the second debouncing cycle.

[0035] Before the end of the second de-jittering cycle, the first input signal is input, and the system enters normal startup after the end of the second de-jittering cycle, and the main power switch is restarted.

[0036] Optionally, the time difference between the second input signal and the first input signal is the response time, and the response time is not greater than the sum of the first delay time and twice the dejittering period; the sum of the first delay time and twice the dejittering period is not greater than 500 milliseconds.

[0037] The present invention also discloses a circuit protection system, including

[0038] The OLP protection module is used to start or stop OLP protection.

[0039] A feedback voltage detection module is used to detect the feedback voltage and output a latch signal when the feedback voltage is detected to be less than a second voltage; the feedback voltage detection module is coupled to the OLP protection module and controls the OLP protection module to start the OLP protection when the feedback voltage is detected to be greater than the second voltage.

[0040] A latch signal detection module, coupled to the feedback voltage detection module, is used to acquire and process the latch signal output by the feedback voltage detection module; the latch signal detection module is also coupled to the OLP protection module, and controls the OLP protection module to start the OLP protection according to the latch signal;

[0041] The power control module is coupled to the auxiliary winding and obtains power to control the rise and fall of the operating voltage.

[0042] The power-on module is used to output the first input signal for powering on the control circuit system.

[0043] The shutdown module is used to output a second input signal to control the shutdown of the circuit system.

[0044] The power-on module is coupled to the feedback voltage detection module, which starts detecting the feedback voltage after receiving the first input signal; the power-on module is also coupled to the power control module, which controls the operating voltage to rise after receiving the first input signal.

[0045] The shutdown module is coupled to the OLP protection module, which activates the OLP protection after receiving the second input signal; the shutdown module is also coupled to the power control module, which controls the operating voltage to decrease after receiving the second input signal.

[0046] Optionally, the OLP protection module includes a delay time selection module, a main power switch control module, an OLP control module, and a debouncing module;

[0047] The OLP control module is coupled to the delay time selection module and is used to control the delay time selection module to select the delay time of the OLP protection.

[0048] The OLP control module is also coupled to the main power switch control module and is used to control the main power switch control module to select to turn on or off the main power switch transistor.

[0049] The debounce module is coupled to the OLP control module and is used to control the OLP control module to activate the OLP protection only after waiting for one debounce cycle.

[0050] The activation of the OLP protection includes the delay time selection module selecting the delay time and the main power switch control module selecting to stop the main power switch.

[0051] This invention selects different delay times based on different load overload and feedback voltage conditions during power-on mode, thereby maintaining normal OLP delay protection and avoiding unnecessary long OLP delay protection times.

[0052] This invention also avoids a second delay time with a long OLP protection false entry time by adjusting the response time between power-on and power-off in power-off mode, thereby achieving fast power-on.

[0053] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0054] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0055] Figure 1 The circuit diagram of a typical VDD RC starting system is shown.

[0056] Figure 2 A typical circuit diagram of a high-voltage self-powered system is shown.

[0057] Figure 3 A logic diagram of the overload protection method in power-on mode according to Embodiment 1 is shown;

[0058] Figure 4 A time flow diagram of the overload protection method for load overload in Embodiment 1 is shown;

[0059] Figure 5 A flowchart illustrating the steps of the overload protection method for load overload in Embodiment 1 is shown.

[0060] Figure 6 A time flow diagram of the shutdown protection method in shutdown mode according to Embodiment 2 is shown;

[0061] Figure 7 A flowchart illustrating the steps of the shutdown protection method in shutdown mode according to Embodiment 2 is shown.

[0062] Figure 8 A flowchart illustrating the steps of a circuit protection method according to Embodiment 3 is shown.

[0063] Figure 9 A schematic diagram of the modules of a circuit protection system according to Embodiment 4 is shown. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0065] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0066] To address the problem of OLP protection malfunction caused by the inability of the working voltage VDD to be quickly cleared to zero, which prevents the high-voltage self-powered system from quickly switching on and off, this invention adjusts the debounce cycle length and delay time of the OLP protection based on the behavioral and time characteristics of rapid switching on and off, thereby avoiding the problem of OLP protection malfunction caused by rapid switching on and off.

[0067] In this invention, the delay time for continuous protection during the OLP protection process can be selected in two different states, including a first delay time T_delay1 and a second delay time T_delay2, wherein the first delay time T_delay1 is less than the second delay time T_delay2.

[0068] It should be understood that the operating characteristic of OLP protection is that it triggers the OLP protection logic when an anomaly is detected (output overload), protecting the chip by turning off the main power switch. Specifically, the output overload state is characterized by the feedback voltage VFB. When the feedback voltage VFB is detected to be greater than the second voltage VFB_OLP, it indicates that the load has been overloaded. After maintaining a debounce cycle T_debounce, OLP protection is executed. The way OLP protection is executed is by stopping the main power switch (i.e., the main power MOSFET).

[0069] Example 1:

[0070] This embodiment discloses an overload protection method applied to the start-up mode of a high-voltage self-powered system. When the high-voltage self-powered system is started, the OLP protection is triggered due to load overload. The OLP protection is activated by detecting the magnitude of the feedback voltage VFB and selecting an appropriate OLP protection delay time.

[0071] As attached Figure 3 As shown, the specific steps include:

[0072] Step S110: The process of clearing the working voltage VDD to zero is completed, and the system enters the power-on mode. Therefore, the system enters the power-on or restart operation.

[0073] Step S120: The system enters the charging state of the operating voltage VDD, the voltage of the operating voltage VDD rises, and the system's soft start is activated. When the operating voltage VDD rises above the first voltage VDD_ON, the system's soft start operation is completed.

[0074] Step S130: Time a period of time not greater than the debounce period T_debounce as the first time value T, and detect the feedback voltage VFB to determine whether the feedback voltage VFB < the second voltage VFB_OLP within the first time value T1. Wherein, the first time value T1 ≤ the debounce period T_debounce.

[0075] When the feedback voltage VFB is detected to be lower than the second voltage VFB_OLP within the first time value T1, it indicates that no continuous load overload has occurred within the first time value T1, and the system latches the data. Although no continuous load overload has occurred at this time, there is a possibility of short-term load overload. If a load overload occurs within the first time value T1, the load overload at this time will be treated as a short-term load overload.

[0076] When it is detected that the feedback voltage VFB does not fall below the second voltage VFB_OLP within the first time value T1, that is, the feedback voltage VFB continuously exceeds the second voltage VFB_OLP within the first time value T, it indicates that the load is continuously overloaded within the first time value T, so the system does not latch at this time.

[0077] In this embodiment, the first time value T1 is 100ms, and the first time value T1 ≤ debounce period T_debounce. It should be understood that in other embodiments, the specific values ​​of the first time value T1 and the debounce period T_debounce are not limited to this embodiment, as long as the first time value T1 satisfies the condition of not being greater than the debounce period T_debounce.

[0078] Step S140: Detect the latch signal and start OLP protection based on the latch signal.

[0079] When a latch signal is detected, it indicates that there is no sustained overload at the output, and the system does not need to activate OLP protection. However, if OLP protection does activate at this time, it will be handled as an OLP protection triggered by a short-term overload. Therefore, the delay time for OLP protection is selected as a shorter first delay time T_delay1. After the first delay time T_delay1 ends, OLP protection stops. If the overload has been relieved, the system can restart normally after the latch is released. If the overload has not been relieved after the first delay time T_delay1 ends, the feedback voltage VFB will be checked again within the first time value T.

[0080] When a no-latch signal is detected, it indicates a sustained overload at the output. Therefore, the system needs to trigger the OLP protection logic to activate OLP protection and stop the main power switch (i.e., stop the switch). In this case, the OLP protection delay time is set to the longer second delay time, T_delay2. It should be understood that since the first time value T is not greater than the debounce period T_debounce, the system triggers the OLP protection logic when a no-latch signal is detected after the first time value T ends, but only activates OLP protection after one debounce period T_debounce has elapsed.

[0081] Based on the above overload protection method, it can be seen that after the system starts up and operates, within the first time value T1 (≤T_debounce):

[0082] If the feedback voltage VFB < the second voltage VFB_OLP, the OLP protection will not be actively activated. However, if the OLP protection exists at this time, the delay time of the OLP protection will be selected as the first delay time T_delay1.

[0083] If the feedback voltage VFB is kept greater than or equal to the second voltage VFB_OLP, then the OLP protection is actively started after the debounce cycle T_debounce ends, and the delay time of the OLP protection is selected as the second delay time T_delay2.

[0084] In summary, after the high-voltage self-powered system enters the start-up mode, the system outputs a latching signal by judging the relationship between the feedback voltage VFB and the second voltage VFB_OLP within the first time value T. Then, it starts the OLP protection by detecting whether the latching signal exists, and distinguishes the delay time of the OLP protection under different feedback voltage VFB states. This allows the delayed protection state of the OLP protection to be quickly ended even in the case of a brief overload (i.e., an overload occurs but is relieved after a period of time), enabling the system to start up quickly.

[0085] Example 2:

[0086] This embodiment specifically discloses an overload protection method, which selects the delay time according to the duration of the load overload, thereby avoiding unnecessary long-term delays in OLP protection when the load is overloaded for a short time, and ensuring that the system can start up normally.

[0087] This embodiment employs the overload protection method described in Embodiment 1, which activates OLP protection by determining the magnitude of the feedback voltage VFB, when the load is continuously overloaded. (See attached diagram.) Figure 4 and attached Figure 5 As shown, the specific steps include:

[0088] Step S210: The first input signal AC_ON is input, and the system enters normal operation after power-on. After the system's operating voltage VDD is cleared to zero, the system receives the first input signal AC_ON, performs a normal power-on or restart, and then enters normal operation.

[0089] Step S220: When a load overload occurs, the OLP protection logic is triggered, and it is maintained for more than one debounce cycle T_debounce for the first time. When a load overload is detected, that is, when a feedback voltage VFB is detected to be greater than the second voltage VFB_OLP, the OLP protection logic is triggered, but it needs to wait for a complete debounce cycle T_debounce to end before starting OLP protection.

[0090] Step S230: After the first debounce cycle T_debounce ends, OLP protection is activated, the main power switch is turned off, and a first delay time T_delay1 is applied. During the first delay time T_delay1, the system maintains the OLP protection state, i.e., the main power switch remains off, thereby protecting the chip. Specifically, when the OLP protection logic is triggered for the first time after a load overload, the delay time selected after the first debounce cycle T_debounce ends is the first delay time T_delay1.

[0091] Step S240: The first delay time T_delay1 ends, the OLP protection delayed within the current first delay time T_delay1 ends, and the main power switch ends its closed state.

[0092] If the overload has been relieved by the end of the first delay time T_delay1 in step S240, the system will enter normal restart after the OLP protection ends, and the main power switch will restart due to the effect of the first input signal AC_ON.

[0093] If the overload has not been relieved by the end of the first delay time T_delay1 in step S240, the OLP protection logic will be triggered again, and the process will proceed to step S250.

[0094] Step S250: The logic for triggering OLP protection again due to unresolved overload occurs. The load remains overloaded and sustains this state for a second time for more than one debounce cycle T_debounce. After the first delay time T_delay1 ends, if the feedback voltage VFB is detected to be greater than the second voltage VFB_OLP again due to unresolved overload, the logic for triggering OLP protection will be triggered again. OLP protection will then be activated after the debounce cycle T_debounce ends, and the main power switch will be turned off. This step S250 assumes that no feedback voltage VFB is less than the second voltage VFB_OLP within the first time value T1 (≤ T_debounce), therefore proceeding to step S260.

[0095] However, it should be understood that, according to the overload protection method in Embodiment 1, in this step S250, if after the first delay time T_delay1 ends, the feedback voltage VFB is detected to be greater than the second voltage VFB_OLP again because the load overload has not been relieved, and the feedback voltage VFB is less than the second voltage VFB_OLP within the first time value T1, then the system latches and selects the first delay time T_delay1 after the second debounce cycle T_debounce ends.

[0096] Step S260: After the second debounce cycle T_debounce ends, OLP protection is activated, the main power switch is turned off, and a second delay time T_delay2 is applied. During the second delay time T_delay2, the system maintains the OLP protection state, i.e., the main power switch remains off, thereby protecting the chip.

[0097] Step S270: The second delay time T_delay2 ends, the OLP protection delayed within the current second delay time T_delay1 ends, and the main power switch ends its closed state.

[0098] If the overload continues after step S270, that is, if the overload is not relieved after the second delay time T_delay2 ends, the system will repeat the process of steps S250, S260 and S270 again, that is, repeat the cycle of "T_debounce-T_delay2 or T_delay1".

[0099] Step S280: The load overload is released, the last delay time (T_delay1 or T_delay2) ends, the OLP protection delayed during the last delay time ends, the main power switch ends being kept in the off state, and the main power switch restarts due to the effect of the first input signal AC_ON.

[0100] If the overload is relieved before the end of a certain delay time (T_delay1 or T_delay2), then after the end of that delay time, the OLP protection will stop and the main power switch will stop being kept off.

[0101] If, during a debounce cycle T_debounce, the overload is relieved before the end of the first time value T1, then after the end of that debounce cycle T_debounce, OLP protection is activated and a first delay time T_delay1 is selected. After the end of the first delay time T_delay1, OLP protection is stopped.

[0102] In summary, in this embodiment, when a load overload occurs after the first input signal AC_ON, after the logic for triggering OLP protection for the first time, the delay time for OLP protection is selected as the first delay time T_delay1. If the load is relieved of the overload before the end of the first delay time T_delay1, then after the end of the first delay time T_delay1, OLP protection stops, the main power switch ends its closed state and restarts, and the system powers on or restarts normally. This is OLP protection for short-term load overload. If the load is not relieved of the overload after the end of the first delay time T_delay1, then after the logic for triggering OLP protection for the nth time (n≥2), OLP protection for continuous load overload will be implemented.

[0103] If the load overload is relieved before the end of the first time value T1 within the nth debounce cycle T_debounce, then after the nth debounce cycle T_debounce ends, OLP protection is activated and the first delay time T_delay1 is selected. After the first delay time T_delay1 ends, OLP protection is stopped, the main power switch ends the state of being kept off and restarts.

[0104] If the overload is not relieved and remains above the first time value T1 during the nth debounce cycle T_debounce, then OLP protection is activated after the nth debounce cycle T_debounce ends and the second delay time T_delay2 is selected. After the second delay time T_delay2 ends, OLP protection is stopped and the main power switch ends its closed state.

[0105] Therefore, this embodiment can activate OLP protection when an overload is detected. Different delay times for OLP protection are selected according to different overload conditions, so as to avoid false protection of OLP protection even when the load is short-term overload, thereby avoiding the problem of excessive delay time when the load is short-term overload, and realizing fast power-on or restart.

[0106] Example 3:

[0107] This embodiment discloses a shutdown protection method applied to the shutdown mode of a high-voltage self-powered system. When the high-voltage self-powered system shuts down, the OLP protection will enter a delay phase because the operating voltage VDD cannot be de-energized in time, causing the high-voltage self-powered system to be unable to quickly complete shutdown and startup after entering the shutdown mode. This embodiment achieves fast startup by adjusting the response time between fast power-on and power-off after the system enters the shutdown mode, specifically the response time between the second input signal AC_OFF and the first input signal AC_ON.

[0108] As attached Figure 6As shown, after the second input signal AC_OFF is input, the operating voltage VDD will drop. If the OLP protection is triggered in the shutdown mode, under normal circumstances, the operating voltage VDD will drop to a state lower than (or equal to) the third voltage V_UVLO before the end of the first debounce cycle T_debounce. The system will then enter the undervoltage lockout (UVLO) state, and the main power switch will stop until the first input signal AC_ON is input, at which point the system will restart, and the main power switch will restart.

[0109] Therefore, under normal circumstances, the operating voltage VDD can complete the power-down process within the first debounce cycle T_debounce, as shown in the attached figure. Figure 7 As shown, the shutdown protection method is in the following order: step S301, step S302, step S303, step S304, step S305.

[0110] When the auxiliary winding power supply is in a critical state, that is, when the operating voltage VDD is not powered down during the debounce period T_debounce, but only during the first delay time T_delay1, as shown in the attached figure. Figure 7 As shown, the shutdown protection method is in the following order: step S301, step S302, step S303, step S306, step S307, step S308.

[0111] When the auxiliary winding power supply is in a sufficient power supply state, that is, the working voltage VDD is always higher than the third voltage V_UVLO, then as shown in the appendix. Figure 7 As shown, the shutdown protection method is in the following order: step S301, step S302, step S303, step S306, step S307, step S309, step S310.

[0112] Details are as attached Figure 7 The steps shown are as follows:

[0113] Step S301: When the system is working normally, input the second input signal AC_OFF and the system enters the shutdown mode.

[0114] Step S302: The system triggers the OLP protection logic for the first time and waits for a debounce cycle T_debounce for the first time. The operating voltage VDD drops during the first debounce cycle T_debounce.

[0115] Step S303: After the first debounce cycle T_debounce ends, determine whether the working voltage VDD has dropped below (or equal to) the third voltage V_UVLO.

[0116] When the judgment result is yes, that is, the working voltage VDD has dropped to a voltage lower than (or equal to) the third voltage V_UVLO, proceed to steps S304 and S305. At this time, it is the OLP protection under normal conditions.

[0117] If the judgment result is negative, that is, the working voltage VDD has not dropped to a voltage lower than (or equal to) the third voltage V_UVLO, the working voltage VDD is still higher than the third voltage V_UVLO, and proceed to steps S306 and S307.

[0118] Step S304: When the operating voltage VDD drops below (or equal to) the third voltage V_UVLO at the end of the first debounce cycle T_debounce, the OLP protection is activated, stopping the main power switch, but the OLP protection does not have a delay protection. Specifically, if the operating voltage VDD drops below (or equal to) the third voltage V_UVLO before (or at) the end of the first debounce cycle T_debounce, the system enters an undervoltage lockout (UVLO) state, and the power supply chip does not operate. The system remains in the undervoltage lockout (UVLO) state until the first input signal AC_ON arrives.

[0119] Step S305: The first input signal AC_ON is input, the system enters normal power-on or restart, the main power switch also restarts (restarts the switch), and the operating voltage VDD is recharged and rises.

[0120] Specifically, if the first input signal AC_ON arrives at the end of the first debounce cycle T_debounce, the system restarts immediately upon the end of T_debounce. If the first input signal AC_ON arrives during a debounce cycle T_debounce or a first delay time T_delay1, the system restarts only after the end of that debounce cycle T_debounce or the first delay time T_delay1. Before the first input signal AC_ON arrives, the system enters an undervoltage lockout (UVLO) state due to the power loss of the operating voltage VDD, so the power supply chip remains inactive until the first input signal AC_ON is input, at which point the system restarts, and the main power switch also restarts.

[0121] Step S306: When the first debounce cycle T_debounce ends and the operating voltage VDD has not dropped below (or equal to) the third voltage V_UVLO, OLP protection is activated, the main power switch is turned off, and a first delay time T_delay1 is applied. During the first delay time T_delay1, the OLP protection state is maintained, and the main power switch remains in a stopped state (No Gate Switch).

[0122] Step S307: At the end of the first delay time T_delay1, determine whether the operating voltage VDD has dropped below the third voltage V_UVLO. When the first delay time T_delay1 ends, the OLP protection delayed during the first delay time T_delay1 period stops, and the main power switch is kept in a stopped state.

[0123] When the judgment result is yes, that is, the working voltage VDD has dropped to below the third voltage V_UVLO, proceed to step S308. At this time, it is the OLP protection situation when the auxiliary winding power supply is in a critical state, that is, the working voltage VDD has not dropped completely during the debounce period T_debounce, but only dropped completely during the first delay time T_delay1.

[0124] When the judgment result is negative, that is, the working voltage VDD has not dropped below the third voltage V_UVLO, proceed to step S309 and step S310. At this time, it is the OLP protection situation when the auxiliary winding power supply is in a sufficient power supply state, that is, the OLP protection situation when the working voltage VDD is always higher than the third voltage V_UVLO.

[0125] Step S308: When the first delay time T_delay1 ends and the working voltage VDD has dropped to below (or equal to) the third voltage V_UVLO, the first input signal AC_ON is input, the system enters normal power-on or restart, the working voltage VDD is recharged and rises, and the main power switch also restarts (restarts the Switch).

[0126] If, before the first delay time T_delay1 ends, the operating voltage VDD drops to below (or equal to) the third voltage V_UVLO, the system enters an undervoltage lockout (UVLO) state. The power supply chip is inactive but maintains OLP protection, and the main power switch remains off (No Gate Switch). OLP protection is released only after the first delay time T_delay1 ends, and the main power switch is then kept off. Before the first input signal AC_ON arrives, the system enters an undervoltage lockout (UVLO) state due to the drop in operating voltage VDD, so the power supply chip remains inactive until the first input signal AC_ON is input, at which point the system restarts, and the main power switch also restarts.

[0127] Step S309: When the first delay time T_delay1 ends and the working voltage VDD has not dropped below (or equal to) the third voltage V_UVLO, the logic of OLP protection is triggered for the second time and a second debounce cycle T_debounce is waited.

[0128] Step S310: Before the end of the second debounce cycle T_debounce, input the first input signal AC_ON. After the system finishes the current debounce cycle (or delay time) delay state, it enters normal power-on and the main power switch restarts.

[0129] From the appendix Figure 6 It can be seen that when the system triggers OLP protection for the second time and the operating voltage VDD is still higher than the third voltage V_UVLO at the end of the second debounce cycle T_debounce, the system's OLP protection will enter the second delay time T_delay2. During the second delay time T_delay2, the first input signal (see attached...) is input... Figure 6 The AC_ON1 signal in the first input signal (attached) will not immediately drive the system to restart due to OLP protection (because the main power switch remains stopped). Instead, the system will only restart after the second delay time T_delay2 ends, and the main power switch will also restart, which prolongs the system's boot time. Therefore, in the first input signal (attached) Figure 6 After inputting AC_ON1, the main power switch should have restarted, but because the OLP protection requires a full second delay time T_delay2, it remains in the OLP protection state, thus triggering a false OLP protection.

[0130] Therefore, the first input signal (attached) Figure 6 The AC_ON1 signal is input during the second delay time T_delay2, causing the OLP protection to restart incorrectly and extending the power-on time; the first input signal (attached) Figure 6 Inputting AC_ON2 before the start of the second delay time T_delay2 can prevent OLP protection from entering the second delay time T_delay2, thus avoiding erroneous restarts of OLP protection. It should be understood that... (The rest of the text is missing.) Figure 6 If AC_ON2 is entered before the debounce cycle ends or before the first delay time T_delay1 ends, then a restart is required after the debounce cycle ends or the first delay time T_delay1 ends.

[0131] When the auxiliary winding power supply is in a sufficient power supply state, that is, the working voltage VDD is always higher than the third voltage V_UVLO, by adjusting the response time Tsum between the second input signal AC_OFF and the first input signal AC_ON, the system's OLP protection can be prevented from entering the second delay time T_delay2, thereby avoiding false OLP protection.

[0132] Specifically, this embodiment adjusts the response time Tsum by adjusting the input timing of the first input signal AC_ON, thereby solving the problem of false protection in OLP protection. In this embodiment, the debounce period T_debounce is 80ms, the first delay time T_delay1 is 240ms, and the second delay time T_delay2 is 2s. Since the first input signal AC_ON needs to be input before the start of the second delay time T_delay2, the maximum range of the response time Tsum between the second input signal AC_OFF and the first input signal AC_ON is:

[0133] Tsum = 2 × T_debounce + T_delay1

[0134] Tsum=2×80+240=400ms(<500ms)

[0135] Since the classic understanding considers the time range of 0-500ms as the time characteristic range for fast power-on and power-off, if the response time between power-off and power-on exceeds 500ms, it is considered not to fall under the category of fast power-on and power-off, and the circuit loses its startup advantage. Therefore, the 80ms debounce period T_debounce, 240ms first delay time T_delay1, and 2s second delay time T_delay2 settings in this embodiment can ensure that the response time Tsum is less than 500ms and does not enter the second delay time T_delay2, thereby achieving fast power-on and power-off. By ensuring that the first input signal AC_ON is input before the start of the second delay time T_delay2, a second trigger of the OLP protection can be avoided, thus preventing erroneous restarts of the OLP protection.

[0136] It should be understood that the debounce period T_debounce can also be selected from 80ms to 200ms, the first delay time T_delay1 can also be selected from 0ms to 500ms, and the second delay time T_delay2 can also be selected from 1s to 2s. That is, the specific values ​​of the debounce period T_debounce, the first delay time T_delay1, and the second delay time T_delay2 are not limited to this embodiment, and satisfy the following:

[0137] The second delay time T_delay2 > the first delay time T_delay1;

[0138] Tsum=(2×T_debounce+T_delay1)<500ms;

[0139] The value of the debounce period T_debounce needs to be selected based on the actual circuit performance, and should not be too constrained by the influence of short-circuit peak power consumption and the degree of short-circuit heat generation of the system.

[0140] All three conditions above must be met.

[0141] Example 4:

[0142] This embodiment discloses a circuit protection method, including the overload protection method in the power-on mode of Embodiment 2 and the power-off protection method in the power-off mode of Embodiment 3. This embodiment can avoid false triggering of OLP protection in both power-on and power-off modes, thereby achieving rapid power-on and rapid power-off. While ensuring the normal operation of OLP protection, it also retains the rapid power-on and power-off characteristics of the high-voltage self-powered system. This embodiment is referenced in the appendix. Figure 6 Time flow diagram of circuit protection method when the auxiliary winding is adequately powered (with appendix) Figure 6 The timeline diagram in the third row, and as attached. Figure 8 The flowchart shown includes the following steps:

[0143] Step S501: When the system is working normally, it acquires the second input signal AC_OFF and enters the shutdown mode.

[0144] Step S502: The system triggers the OLP protection logic and waits for a debounce cycle T_debounce. The operating voltage VDD is powered down during the debounce cycle T_debounce.

[0145] Step S503: After the debounce cycle T_debounce ends, if the operating voltage VDD has not dropped to below (or equal to) the third voltage V_UVLO, or if the operating voltage VDD is still above the third voltage V_UVLO, then the system's OLP protection is activated and maintained for the first delay time T_delay1. During the first delay time T_delay1, the OLP protection remains in the protected state, that is, it remains in the state of stopping the main power switching transistor.

[0146] Step S504: During the first delay time T_delay1, the first input signal AC_ON is input, and the operating voltage VDD remains higher than the third voltage V_UVLO. When the first input signal AC_ON is input during the first delay time T_delay1, the system will not restart until the first delay time T_delay1 ends. The OLP protection remains in a no-gate switch state during the first delay time T_delay1.

[0147] Step S505: The first delay time T_delay1 ends, the currently delayed OLP protection also ends, and the main power switch is kept in a stopped state. Because the first input signal AC_ON is input during the first delay time T_delay1, the system restarts at this time, and the main power switch restarts (Gate Switch).

[0148] Step S506: After the system restarts, a load overload occurs, triggering the OLP protection logic. The overload state is maintained for more than one debounce cycle T_debounce. After the system restarts, a first time value T1 is timed and the feedback voltage VFB is detected. Within the first time value T1, the feedback voltage VFB is less than the second voltage VFB_OLP, so the system does not actively activate OLP protection. However, a load overload occurs at this time, triggering the OLP protection logic. The delay time selected after the first trigger of the OLP protection logic due to the load overload is the first delay time T_delay1.

[0149] Step S507: After the first debounce cycle T_debounce after restarting, OLP protection is activated, the main power switch is stopped (No Gate Switch), and the OLP protection state lasts for the first delay time T_delay1.

[0150] Step S508: When the first delay time T_delay1 ends, the OLP protection ends, and the main power switch ends and remains in a stopped state. However, due to the overload not being relieved, the OLP protection logic is triggered again, and the overload state is maintained for more than one debounce cycle T_debounce.

[0151] Step S509: After the second debounce cycle T_debounce ends following the restart, the OLP protection is restarted, and the OLP protection status remains at the second delay time T_delay2. Since there is always a load overload during the second debounce cycle T_debounce, the feedback voltage VFB is always greater than the second voltage VFB_OLP. Therefore, the OLP protection is executed and delayed again, this time for the second delay time T_delay2.

[0152] Step S510: The second delay time T_delay2 ends, and the OLP protection delayed within the current second delay time T_delay2 ends.

[0153] If the overload continues, meaning the overload is not relieved after the second delay time T_delay2, the system will repeat the process of "maintaining the debounce cycle T_debounce" and "delaying the second delay time T_delay2", that is, repeating the cycle of "T_debounce-T_delay2" until the overload is relieved, at which point the system can shut down and restart normally.

[0154] Step S511: Overload is relieved, the last delay time (T_delay1 or T_delay2) ends, and the OLP protection delayed during the last delay time ends.

[0155] In this implementation, when the auxiliary winding power supply is sufficient, after the first OLP protection is triggered and the first debounce cycle T-_debounce ends, the first input signal AC_ON is input during the first delay time T_delay1. This enables rapid system startup in shutdown mode, avoiding the problem of the system entering the second delay time T_delay2 and needing to wait for a period (or multiple periods) of the second delay time T_delay2 before restarting. This prevents false OLP protection and achieves rapid power-on and power-off. This embodiment adjusts the response time between power-on and power-off in shutdown mode to avoid the OLP protection mistakenly entering the long second delay time T_delay2, thereby achieving rapid power-on.

[0156] This embodiment selects different delay times based on the duration of load overload in power-on mode. The first delay time T_delay1 is selected when the logic is triggered for the first time and OLP protection is started; the second delay time T_delay2 is selected only when the overload continues, thereby maintaining normal OLP delay protection and avoiding unnecessary long OLP delay protection.

[0157] Example 4:

[0158] This invention also discloses a circuit protection system, as shown in the attached diagram. Figure 9 As shown, it includes an OLP protection module 400, a feedback voltage detection module 620, a latch signal detection module 610, a power control module 650, a power-on module 630, and a power-off module 640.

[0159] Specifically, the OLP protection module 400 includes a delay time selection module 440, a main power switch control module 430, an OLP control module 420, and a debounce module 410.

[0160] The OLP control module 420 is coupled to the delay time selection module 440 and is used to control the delay time selection module 440 to select the delay time of OLP protection. The delay time of OLP protection includes a first delay time T_delay1 and a second delay time T_delay2, where the first delay time T_delay1 is less than the second delay time T_delay2.

[0161] The OLP control module 420 is also coupled to the main power switch control module 430 and is used to control the main power switch control module 430 to select whether to turn on or off the main power switch transistor.

[0162] The debounce module 410 is coupled to the OLP control module 420 and is used to control the OLP control module 420 to activate OLP protection only after waiting for one debounce cycle. After the OLP protection module 400 obtains the signal for activating OLP protection, it activates OLP protection only after waiting for one debounce cycle by the debounce module 410, which helps to prevent the effects of circuit jitter and instability.

[0163] The activation of OLP protection includes: the delay time selection module 440 selecting the delay time, and the main power switch control module 430 selecting to stop the main power switch.

[0164] The feedback voltage detection module 620 is used to detect the feedback voltage VFB and outputs a latch signal when the feedback voltage VFB is less than the second voltage VFB_OLP. Furthermore, the feedback voltage detection module 620 is also coupled to the OLP protection module 400, and controls the OLP protection module 400 to activate OLP protection when the feedback voltage VFB is detected to be greater than the second voltage VFB_OLP.

[0165] The latch signal detection module 610 is coupled to the feedback voltage detection module 620 and is used to acquire and process the latch signal output by the feedback voltage detection module 620. The latch signal detection module 610 is also coupled to the OLP protection module 400 and controls the OLP protection module 400 to start OLP protection according to the latch signal.

[0166] When a latching signal is detected, the OLP protection module 400 is not actively controlled to start OLP protection; when no latching signal is detected, the OLP protection module 400 is actively controlled to start OLP protection, the delay time selection module 440 selects the second delay time T_delay2, and within the second delay time T_delay2, the main power switch control module 430 stops the main power switch transistor.

[0167] When a latching signal is detected, if OLP protection occurs, the OLP protection is caused by load overload. That is, when the load is overloaded, the feedback voltage detection module 620 detects that the feedback voltage VFB is greater than the second voltage VFB_OLP, so it controls the OLP protection module 400 to start OLP protection. The delay time selection module 440 selects the first delay time T_delay1. Within the first delay time T_delay1, the main power switch control module 430 stops the main power switch.

[0168] The power control module 650 is coupled to the auxiliary winding and draws power from the auxiliary winding. The power control module 650 is used to control the rise and fall of the operating voltage VDD.

[0169] The power-on module 630 is used to output the first input signal AC_ON for powering on the control circuit system; the power-off module 640 is used to output the second input signal AC_OFF for powering off the control circuit system.

[0170] The power-on module 630 is coupled to the feedback voltage detection module 620. Upon receiving the first input signal AC_ON, the feedback voltage detection module 620 initiates detection of the feedback voltage VFB. Therefore, in power-on mode, this embodiment can control the OLP protection based on the load condition detected by the feedback voltage detection module 620, selecting an appropriate delay time to avoid unnecessary long-term OLP false protection. The power-on module 630 is also coupled to the power control module 650. Upon receiving the first input signal AC_ON, the power control module 650 controls the operating voltage to rise; that is, during power-on, the power control module 650 controls the operating voltage VDD to rise.

[0171] The shutdown module 640 is coupled to the OLP protection module 400, which activates OLP protection upon receiving the second input signal AC_OFF. The shutdown module 640 is also coupled to the power control module 650, which controls the operating voltage to decrease upon receiving the second input signal AC_OFF; that is, during shutdown, the power control module 650 controls the operating voltage VDD to decrease.

[0172] After the power-off module 640 outputs the second input signal AC_OFF, the time when the power-on module 630 outputs the first input signal AC_ON can be adjusted to avoid unnecessary extension of OLP protection.

[0173] In this embodiment, the OLP protection module 400 is simultaneously controlled by the feedback voltage detection module 620, the latch signal detection module 610, the power control module 650, and the shutdown module 640. This allows the main power switch to restart in shutdown mode even if the operating voltage VDD fails to drop in time, as long as the power-on module 630 outputs the first input signal AC_ON. It also allows for different delay times to be selected based on load overload and feedback voltage conditions in power-on mode, thus avoiding unnecessary extension of OLP protection. Specifically, by adjusting the response time between power-on and power-off in shutdown mode, the OLP protection is prevented from mistakenly entering the longer second delay time T_delay2, thereby achieving fast power-on.

[0174] This embodiment also selects different delay times based on different load overload and feedback voltage conditions in the power-on mode, thereby maintaining normal OLP delay protection and avoiding unnecessary long OLP delay protection times.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

[0176] In summary, the above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the present invention.

Claims

1. An overload protection method, characterized in that, When the system enters boot mode, the following steps are included: Once the operating voltage has been cleared to zero, the system enters power-on mode. The system soft start is completed when the operating voltage rises and exceeds the first voltage. A first time value is timed and the feedback voltage is detected. It is determined whether the feedback voltage is less than the second voltage within the first time value; the first time value is not greater than the debouncing period. A latch signal is output based on the detection result of the feedback voltage. When it is determined that the feedback voltage is less than the second voltage within the first time value, a latch signal is output; when it is determined that the feedback voltage is not less than the second voltage within the first time value, no latch signal is output. The OLP protection is activated based on the latch signal and the delay time of the OLP protection is selected. When a latch signal is detected, the OLP protection is not activated; when no latch signal is detected, the OLP protection is activated and the delay time is selected as a second delay time; when a latch signal is detected and the OLP protection is in the activated state, the delay time is selected as a first delay time; the second delay time is greater than the first delay time. Activating the OLP protection includes stopping the main power switch.

2. The overload protection method according to claim 1, characterized in that, When a system experiences overload after entering boot mode, the following steps are involved: Upon receiving the first input signal, the system enters power-on mode and begins normal operation. When the load overload occurs, the OLP protection is triggered and the system waits for one debouncing cycle for the first time. Once the first waiting period for the dejittering cycle ends, the OLP protection is activated and the first delay time is applied for the first time. The OLP protection ends when the first delay time of the first delay period ends.

3. The overload protection method according to claim 2, characterized in that, If the load overload is not relieved after the first delay time of the first delay, the following steps are also repeated: If the overload is not relieved, the OLP protection is triggered again and another debouncing cycle is waited for. Once the dejittering cycle ends again, the OLP protection is activated and the delay time is extended. During the de-jittering cycle during the waiting period, if the load overload remains constant within the first time value, the delay time is selected as the second delay time; if the load overload is de-loaded within the first time value, the delay time is selected as the first delay time. When the delay period ends, the OLP protection ends.

4. A shutdown protection method, characterized in that, When the system enters shutdown mode, the following steps are included: When the system is working normally, if a second input signal is input, the system will enter shutdown mode. The system triggers OLP protection for the first time and waits for a debounce cycle for the first time. The operating voltage drops during the first debounce cycle. When the first debounce cycle ends and the operating voltage has dropped below the third voltage, the OLP protection is activated, the main power switch stops, and after the first input signal is input, the system enters normal startup, and the main power switch restarts; when the first debounce cycle ends and the operating voltage has not dropped below the third voltage, the OLP protection is activated and delayed for a first delay time, the main power switch stops and remains stopped for the first delay time; When the first delay time ends and the operating voltage has dropped below the third voltage, the OLP protection stops, the main power switch is released from its held stop state, and after the first input signal is input, the system enters normal startup and the main power switch restarts; when the first delay time ends and the operating voltage has not dropped below the third voltage, the system triggers the OLP protection for the second time and waits for the second debouncing cycle. When the system triggers the OLP protection for the second time and the operating voltage is still higher than the third voltage at the end of the second debouncing cycle, the system's OLP protection enters a second delay time, which is longer than the first delay time. To prevent the OLP protection from entering the second delay time, the shutdown protection method further includes... Before the end of the second de-jittering cycle, the first input signal is input, and the system enters normal startup after the end of the second de-jittering cycle, and the main power switch is restarted.

5. The shutdown protection method according to claim 4, characterized in that, The time difference between the second input signal and the first input signal is the response time, which is no greater than the sum of the first delay time and twice the dejittering period; the sum of the first delay time and twice the dejittering period is no greater than 500 milliseconds.

6. A circuit protection system for implementing the overload protection method according to any one of claims 1-3 and the shutdown protection method according to any one of claims 4-5, characterized in that, include The OLP protection module is used to start or stop OLP protection. A feedback voltage detection module is used to detect the feedback voltage and output a latch signal when the detected feedback voltage is less than a second voltage. The feedback voltage detection module is coupled to the OLP protection module. When the feedback voltage is detected to be greater than the second voltage, the OLP protection module is controlled to start the OLP protection. A latch signal detection module, coupled to the feedback voltage detection module, is used to acquire and process the latch signal output by the feedback voltage detection module; the latch signal detection module is also coupled to the OLP protection module, and controls the OLP protection module to start the OLP protection according to the latch signal; The power control module is coupled to the auxiliary winding and obtains power to control the rise and fall of the operating voltage. The power-on module is used to output the first input signal for powering on the control circuit system. The shutdown module is used to output a second input signal to control the shutdown of the circuit system. The power-on module is coupled to the feedback voltage detection module, which starts detecting the feedback voltage after receiving the first input signal; the power-on module is also coupled to the power control module, which controls the operating voltage to rise after receiving the first input signal. The shutdown module is coupled to the OLP protection module, which activates the OLP protection upon receiving the second input signal; the shutdown module is also coupled to the power control module, which controls the operating voltage to decrease upon receiving the second input signal.

7. A circuit protection system according to claim 6, characterized in that, The OLP protection module includes a delay time selection module, a main power switch control module, an OLP control module, and a debounce module; The OLP control module is coupled to the delay time selection module and is used to control the delay time selection module to select the delay time of the OLP protection. The OLP control module is also coupled to the main power switch control module and is used to control the main power switch control module to select to turn on or off the main power switch transistor. The debounce module is coupled to the OLP control module and is used to control the OLP control module to activate the OLP protection only after waiting for one debounce cycle. The activation of the OLP protection includes the delay time selection module selecting the delay time and the main power switch control module selecting to stop the main power switch.

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