An adjustable delay driver circuit for silicon photonic segmented MZM

Abstract

The present invention provides an adjustable delay driver circuit for a silicon photonic segmented MZM, comprising an input buffer module, a pre-adjustment module, at least one segment driver module, and a load resistor module. The pre-adjustment module includes a first variable capacitor and a first transmission line; the segment driver module includes a second variable capacitor, a second transmission line, and an output op amp; the output op amp receives a signal and modulates the corresponding modulator segment through the output op amp; the load resistor module is connected to at least one of the segment driver modules to complete the circuit. By adding variable capacitors between the transmission lines in the driver circuit, the wave velocity of the transmission line can be fine-tuned using the variable capacitors, thereby achieving the driver circuit's adjustable delay function.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an adjustable delay driver circuit for a silicon photonic segmented MZM. Background Art

[0002] Optical modulators play an indispensable role in optical communication systems. Optical modulators are devices used to modulate electrical data signals onto optical carriers to generate optical signals. Compared to electro-absorption modulators (EAMs) and ring resonant modulators (RRMs), Mach-Zehnder modulators (MZMs) offer advantages such as low drive voltage, compact size, and low capacitive loading. Based on their structural characteristics, MZMs can be categorized as traveling-wave electrode (TWE) MZMs and segmented MZMs. Segmented MZMs consist of several segmented phase shifters (less than 1 / 10 of the wavelength), each driven by a separate driver. Therefore, the number of segments in a segmented MZM is equal to the number of driver segments. Compared to TWE MZMs, segmented MZMs can utilize a larger number of phase shifters to achieve optical modulation, resulting in lower drive voltages. In segmented MZMs, the propagation speed of optical signals is slower than that of electrical signals, requiring additional driver delay to ensure proper matching of the optical and electrical signals.

[0003] To achieve additional delay time in the driver, existing literature has disclosed the use of RC delay at the input of each driver to achieve photoelectric signal matching. However, low-pass filters inevitably reduce the driver's bandwidth and damage signal integrity. In addition, existing literature also discloses the addition of transmission lines between each driver unit. By properly designing the transmission lines, arbitrary delay time can be generated. However, once the transmission line is selected, the delay time cannot be adjusted. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome at least one or all of the defects in the prior art, namely, unadjustable delay time, reduced driver bandwidth, and reduced driver signal integrity, thereby providing an adjustable delay driver circuit for a silicon photonic segmented MZM.

[0005] It should be noted that the present invention is an improved invention based on the existing technology; for the convenience of description, the present invention has technical features or solutions such as electronic components and product processes that are not mentioned, which does not mean that this technical solution is not adopted.

[0006] The present invention provides an adjustable delay driver circuit for a silicon photonic segmented MZM, comprising an input buffer module, a pre-adjustment module, at least one segment driver module, and a load resistor module, wherein:

[0007] The pre-adjustment module includes a first variable capacitor and a first transmission line for receiving the input buffer module signal and realizing adjustable delay;

[0008] The segment driving module includes a second variable capacitor, a second transmission line and an output operational amplifier; it is used to receive the input signal of the pre-adjustment module or the segment driving module of the previous stage and realize the adjustable delay; the output operational amplifier receives the signal and modulates the corresponding modulator segment through the output operational amplifier;

[0009] The load resistance module is used to be connected to at least one of the segment driving modules to complete the circuit.

[0010] The present invention adjusts signal transmission by adding a variable capacitor to the driver circuit, thereby achieving a signal-adjustable delay function. For each segment in a silicon photonic segmented MZM, a second variable capacitor is independently set in each segment to modulate the corresponding segment to achieve the signal-adjustable delay function.

[0011] Furthermore, in the present invention, the load resistance module is connected to at least one of the segment driving modules via a third transmission line, which can reduce signal reflection.

[0012] One embodiment of the present invention is that the driver circuit is a dual driver circuit, corresponding to the proximal light guide and distal light guide of the MZM in the prior art, the input buffer module is provided with a distal input, a proximal input, a distal output and a proximal output; the output operational amplifier is provided with a distal input, a proximal input, a distal output and a proximal output; the first transmission line in the driver circuit includes a first distal transmission line and a first proximal transmission line, and the second transmission line includes a second proximal transmission line and a second distal transmission line; the distal input of the input buffer module is connected to the distal output of the driver front-stage circuit, and the proximal input of the input buffer module is connected to the proximal output of the driver front-stage circuit; the proximal input of the pre-adjustment module is connected to the proximal output of the input buffer module, and the distal input of the pre-adjustment module is connected to the distal output of the input buffer module The first variable capacitor of the pre-adjustment module is arranged between the first proximal transmission line and the first distal transmission line; the distal input of the output operational amplifier of the segment driving module is connected to the first distal transmission line of the pre-adjustment module or the second distal transmission line of the segment driving module of the previous stage, the proximal input of the output operational amplifier is connected to the first proximal transmission line of the pre-adjustment module or the second proximal transmission line of the segment driving module of the previous stage, and the two poles of the second variable capacitor are respectively connected to the second proximal transmission line and the second distal transmission line of the segment driving module; the distal output and the proximal output of the output operational amplifier are connected to the modulator segment; the load resistor module is coupled to the second proximal transmission line and the second distal transmission line connected to at least one of the segment driving modules to realize circuit completion.

[0013] The third transmission line includes a third proximal transmission line and a third distal transmission line. The load resistor module is connected to the segment driver module via the third proximal transmission line and the third distal transmission line, respectively. The length of the third transmission line is greater than the length of the first transmission line or the length of the second transmission line. Signal reflections in the transmission line between the output op amps are absorbed by the extended third transmission line, thereby reducing signal reflections in the transmission line between the output op amps. Signals propagate along the transmission line, and the transmission line is extended after the transmission line of the last output op amp to reduce signal reflections in the transmission line.

[0014] Another embodiment of the present invention is a single driver circuit. In this embodiment, the input buffer module, the pre-adjustment module, and the like no longer distinguish between near-end and far-end circuits. The output op amp of the segment driver module is connected to the corresponding modulator in accordance with existing methods. One end of the first and second variable capacitors and the load resistor module are connected in accordance with the connection method of a dual driver circuit, while the other end is connected to ground or to an external circuit.

[0015] The driver circuit of the present invention can be designed using SiGe BiCMOS technology.

[0016] The input buffer module involved in the present invention includes a first common collector circuit and a first differential amplifier circuit.

[0017] The transmission line of the present invention is composed of a conductor strip, a dielectric layer and a ground plate, wherein the dielectric layer is located between the conductor strip and the ground plate.

[0018] The output operational amplifier of the driver circuit of the present invention is a two-stage circuit, including a second common-collector circuit and a second differential amplifier circuit.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] The driver circuit provided by the present invention includes an input buffer module, a pre-adjustment module, at least one segment drive module, and a load resistance module; by adding variable capacitors between the transmission lines in the driver circuit, the wave velocity of the transmission line can be fine-tuned by the variable capacitors, thereby realizing the adjustable delay function of the driver circuit.

[0021] Adding an input buffer module between the external signal source and the transmission line can achieve matching with the output impedance of the external signal source and the characteristic impedance of the transmission line, thereby reducing signal reflection. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 Schematic diagram of the driver circuit structure in an embodiment of the present invention;

[0024] Figure 2 Schematic diagram of the circuit structure of the input buffer module in an embodiment of the present invention;

[0025] Figure 3 A schematic structural diagram of a transmission line according to an embodiment of the present invention;

[0026] Figure 4 Schematic diagram of the structure of a variable capacitor in an embodiment of the present invention;

[0027] Figure 5 Schematic diagram of the circuit structure of the output operational amplifier in an embodiment of the present invention.

[0028] Reference numerals:

[0029] 1-input buffer module; 10-remote input of input buffer module; 20-proximal input of input buffer module; 12-remote output of input buffer module; 22-proximal output of input buffer module; 2-remote transmission line; 201-first remote transmission line; 202-second remote transmission line; 203-third remote transmission line; 3-proximal transmission line; 301-first proximal transmission line; 302-second proximal transmission line 303-third proximal transmission line; 41-first variable capacitor; 42-second variable capacitor; 5-output op amp; 11-remote input of output op amp; 21-proximal input of output op amp; 13-remote output of output op amp; 23-proximal output of output op amp; 6-load resistor module. DETAILED DESCRIPTION

[0030] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0031] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components; wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] Example 1

[0035] This embodiment provides a silicon photonic segmented MZM adjustable delay driver circuit, combined with Figure 1As shown, the driver circuit is a dual driver circuit. For the convenience of description in this embodiment, there may be a general term for a certain type of device. For example, for a transmission line, if the first or second transmission line is not specifically specified, it is accepted to be a general term according to the context. The driver circuit includes an input buffer module 1, a remote transmission line 2, a proximal transmission line 3, a variable capacitor and at least one output op amp 5; wherein: the remote input 10 of the input buffer module 1 is connected to the remote output of the driver front-stage circuit, and the proximal input 20 of the input buffer module 1 is connected to the proximal output of the driver front-stage circuit; the remote input and proximal input of the pre-adjustment module are respectively connected to the remote output 12 and proximal output 22 of the input buffer module, and the first variable capacitor 41 of the pre-adjustment module is arranged on the first proximal transmission line 301 and The first remote transmission line 201 is connected to the first segment driver module; the remote input 11 of the output op amp 5 of the first segment driver module connected to the pre-adjustment module is connected to the first remote transmission line 201 of the pre-adjustment module; the proximal input 21 of the output op amp 5 is connected to the first proximal transmission line 301 of the pre-adjustment module; the two poles of the second variable capacitor 42 are respectively connected to the second proximal transmission line 301 and the second remote transmission line 201 of the segment driver module; and the remote output 13 and the proximal output 23 of the output op amp are directly or indirectly connected to the modulator segment. In this embodiment, all segment driver modules are connected in series, that is, the second proximal transmission line 302 and the second remote transmission line 202 of the segment driver module following the first segment driver module are respectively connected to the second proximal transmission line 302 and the second remote transmission line 202 of the preceding segment driver module. The segment driver modules can also be connected in parallel, or partially in parallel and partially in series.

[0036] In this embodiment, the second remote transmission line 202 of the last stage segment driver module is coupled via the third remote transmission line 203, and the second proximal transmission line 302 is coupled via the third proximal transmission line 303, via two load resistors 6. It should be noted that the remote transmission line and the proximal transmission line in this embodiment are the same type of transmission line, and the different names are used herein only for the purpose of distinguishing them from each other.

[0037] The segmented MZM driver circuit includes an input buffer 1, a transmission line, a variable capacitor, and an output op amp 5 (S1-S12). The input terminals (10, 20) of the input buffer 1 receive a signal Vin from a digital-to-analog converter (DAC) or an external non-return-to-zero (NRZ) signal, and amplify the input signal Vin to drive two transmission lines (a near-end transmission line and a far-end transmission line). The input buffer 1 can be operated in conjunction with a grounded resistor (not shown) to perform impedance matching with the output impedance of the DAC or external NRZ signal. The output terminal of the input buffer 1 is connected to the transmission line, and its output impedance is approximately equal to the characteristic impedance of the transmission line to reduce reflections in the transmission line. The delay time between each output stage of the output op amp 5 is mainly generated by the transmission line. The variable capacitor between the transmission lines is used to control the wave velocity of the transmission line to fine-tune the delay time of each transmission line segment. The two load resistors at the ends of the transmission line are used to load match the transmission line. The output op amp 5 (S1-S12) collects the differential signal from the two transmission lines and amplifies it to the required voltage to drive the modulator. The input capacitance of output op amp 5 is very small, so it has almost no effect on the characteristic impedance of the transmission line.

[0038] Specifically, for example, an external NRZ signal or a pulse amplitude modulation (PAM) signal generated by a DAC is input to a driver. Adding an input buffer 1 between the external signal and the transmission line can achieve impedance matching with the output impedance of the external signal source and the characteristic impedance of the transmission line, thereby reducing signal reflection. A transmission line is added between two adjacent output op amps 5, and the transmission line is used to generate a delay time to complete the matching of the photoelectric signal. In order to achieve adjustable delay, a variable capacitor is added between each section of the transmission line. It should be noted that the first variable capacitor 41 and the second variable capacitor 42 are the same type of variable capacitors. The sequential description and different numbering used in the text are only for the convenience of describing the circuit structure. The variable capacitors between the transmission lines are used to control the wave velocity of the transmission line to fine-tune the delay time of each section of the transmission line.

[0039] Assuming that the size of the variable capacitor is C1 and the length of each transmission line is L1, the wave velocity v of the transmission line becomes:

[0040]

[0041] When C1 changes, the wave speed also changes, so the variable capacitor achieves the function of adjustable delay by changing the wave speed of the transmission line.

[0042] On the other hand, the variable capacitor will also change the characteristic impedance Z0 of the transmission line, which becomes:

[0043]

[0044] Therefore, the change of characteristic impedance will cause the impedance mismatch between the transmission line and the terminal resistance.

[0045] In this preferred embodiment, the length of the third far-end transmission line 203 is greater than the length of the first far-end transmission line 201 or the length of the second far-end transmission line 202; the length of the third near-end transmission line 303 is greater than the length of the first near-end transmission line 301 or the length of the second near-end transmission line 302; the signal propagates along the transmission line, and the transmission line (the third transmission line) is extended after the transmission line of the last-stage output operational amplifier 5 (S12) to reduce signal reflection in the transmission line.

[0046] The driver circuit in this embodiment is designed using SiGe BiCMOS technology, and utilizes its good frequency and noise characteristics to achieve high bandwidth and low noise design.

[0047] Example 2

[0048] The input buffer 1 of the adjustable delay driver circuit of the silicon photonic segmented MZM involved in this embodiment includes a first common collector circuit and a first differential amplifier circuit. The symmetrical structure of the differential input can effectively suppress power supply noise and substrate noise, improve the common mode rejection ratio of the output signal of the input buffer 1, and also improve the output dynamic range of the output voltage. Specifically, refer to Figure 2 Q1 and Q2 form the first common-collector circuit, and Q9 and Q10 form the first differential amplifier circuit. R1 is used for impedance matching with the output impedance of the signal source, and RCi is used for impedance matching with the transmission line. Vbias1 controls the current of the current mirror formed by Q3 and Q4, thereby controlling the gain of input buffer 1. Negative capacitor CE adjusts the bandwidth of input buffer 1 by introducing a zero point.

[0049] Example 3

[0050] The transmission line of the adjustable delay driver circuit of the silicon photonic segmented MZM involved in this embodiment is composed of a conductor strip 31, a dielectric layer 32 and a ground plane 33, wherein the dielectric layer is located between the conductor strip and the ground plane. Specifically, in the SiGe BiCMOS process, in order to prevent the signal from being interfered with by other signals, reference is made to Figure 3 , the top metal layer is usually selected as the conductor strip, and the ground plane is selected based on the characteristic impedance of the microstrip line.

[0051] Example 4

[0052] The variable capacitor of the adjustable delay driver circuit of the silicon photonic segmented MZM involved in this embodiment is a MOS capacitor. Specifically, refer to Figure 4The variable capacitor has three electrodes, G1, G2, and W. G1 and G2 are the electrodes on the two plates of the capacitor, and W is the control terminal. The MOS structure composed of G1 (G2), SiO2, and substrate silicon has two parts: one is the fixed capacitance Ci formed by G1 (G2), SiO2, and substrate silicon, and the other is the capacitance CD in the depletion region of the substrate silicon. When the potential of electrode W changes, the width of the depletion region in the substrate silicon changes accordingly. In other words, CD changes while Ci remains almost unchanged, so the capacitance between G1 and G2 also changes.

[0053] Example 5

[0054] The output operational amplifier 5 of the adjustable delay driver circuit of the silicon photonic segmented MZM involved in this embodiment is a two-stage circuit, including a second common collector circuit and a second differential amplifier circuit. Figure 5 Q12 and Q13 form the second common-collector circuit, and Q20 and Q21 form the second differential amplifier circuit. Vbias2 controls the current in the current mirror formed by Q14 and Q15, which in turn controls the gain of output op amp 5. Because output op amp 5 is loaded with a large capacitor, techniques such as negative Miller capacitance (Cneg) and inductive peaking (T-coil formed by L1 and L2, and L3) are employed to increase its bandwidth.

[0055] The adjustable delay driver circuit for a segmented silicon optical modulator provided by the present invention has the advantages of adjustable delay, high bandwidth and low noise.

[0056] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A silicon photonic segmented MZM adjustable delay driver circuit, comprising an input buffer module, a pre-adjustment module, at least one segment driver module, and a load resistor module, wherein: The pre-adjustment module includes a first variable capacitor and a first transmission line, which is used to receive the input buffer module signal and realize adjustable delay; The segment driving module includes a second variable capacitor, a second transmission line and an output operational amplifier; it is used to receive the input signal of the pre-adjustment module or the segment driving module of the previous stage and realize the adjustable delay; the output operational amplifier receives the signal and modulates the corresponding modulator segment through the output operational amplifier; The load resistance module is used to connect to at least one of the segment driving modules to complete the circuit; The driver circuit is a dual driver circuit, The input buffer module is provided with a remote input, a near-end input, a remote output and a near-end output; the output operational amplifier is provided with a remote input, a near-end input, a remote output and a near-end output; The first transmission line in the driver circuit includes a first far-end transmission line and a first near-end transmission line, and the second transmission line includes a second far-end transmission line and a second near-end transmission line; The far-end input of the input buffer module is connected to the far-end output of the driver front-stage circuit, and the near-end input of the input buffer module is connected to the near-end output of the driver front-stage circuit; The proximal input and the distal input of the pre-adjustment module are connected to the proximal output and the distal output of the input buffer module respectively, and the first variable capacitor of the pre-adjustment module is arranged between the first proximal transmission line and the first distal transmission line; The remote input of the output operational amplifier of the section driving module is connected to the first remote transmission line of the pre-adjustment module or the second remote transmission line of the section driving module of the previous stage, and the near-end input of the output operational amplifier is connected to the first near-end transmission line of the pre-adjustment module or the second near-end transmission line of the section driving module of the previous stage; The two electrodes of the second variable capacitor are respectively connected to the second proximal transmission line and the second distal transmission line of the segment driving module; The remote output and the proximal output of the output operational amplifier are connected to the modulator segment; the load resistor module is coupled to the second proximal transmission line and the second remote transmission line of at least one of the segment driver modules to complete the circuit.

2. The adjustable delay driver circuit of the silicon photonic segmented MZM according to claim 1, characterized in that: The load resistance module is connected to at least one of the segment driving modules via a third transmission line.

3. The adjustable delay driver circuit of silicon photonic segmented MZM according to claim 2, characterized in that: The third transmission line includes a third proximal transmission line and a third distal transmission line. The load resistance module is connected to the segment driving module through the third proximal transmission line and the third distal transmission line, respectively. The length of the third transmission line is greater than the length of the first transmission line or the length of the second transmission line.

4. The adjustable delay driver circuit of the silicon photonic segmented MZM according to any one of claims 1 to 3, characterized in that: The driver circuit is designed using SiGe BiCMOS technology.

5. The adjustable delay driver circuit of the silicon photonic segmented MZM according to any one of claims 1 to 3, characterized in that: The input buffer module includes a first common-collector circuit and a first differential amplifier circuit.

6. The adjustable delay driver circuit of the silicon photonic segmented MZM according to any one of claims 1 to 3, characterized in that: The transmission line is composed of a conductor strip, a dielectric layer and a ground plate, wherein the dielectric layer is located between the conductor strip and the ground plate.

7. The adjustable delay driver circuit of the silicon photonic segmented MZM according to any one of claims 1 to 3, characterized in that: The first variable capacitor and / or the second variable capacitor is a MOS capacitor.

8. The adjustable delay driver circuit of the silicon photonic segmented MZM according to any one of claims 1 to 3, characterized in that: The output operational amplifier is a two-stage circuit, including a second common-collector circuit and a second differential amplifier circuit.

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