An inverter

Abstract

The present invention relates to an inverter. The inverter includes: enhancement transistors Q1 and Q2, and a control circuit C. The drain of the enhancement transistor Q1 is connected to the bus voltage VD, the source is connected to the drain of the enhancement transistor Q2 and the voltage output terminal VOUT, and the gate is connected to the output of the control circuit C; the drain of the enhancement transistor Q2 is connected to the source of Q1 and the voltage output terminal VOUT, the source is grounded, and the gate is connected to the input voltage VIN; the control circuit C is connected to the gate of the enhancement transistor Q1, the input voltage VIN, and the bus voltage VD, and is used to invert the on states of the enhancement transistors Q1 and Q2. By using the embodiment of the present invention, since the enhancement transistor Q1 is not in a normally open state, circuit losses can be reduced.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to an inverter. Background Art

[0002] GaN HEMT (High Electron Mobility Transistor) devices have been widely used in both microwave and power fields due to their good low on-resistance and high-frequency characteristics. However, there are only enhancement-mode and depletion-mode GaN HEMT devices, and it is difficult to integrate them on the same wafer due to the inconsistent processes of enhancement-mode and depletion-mode devices. Therefore, how to implement GaN integrated circuits using enhancement-mode devices is a major challenge in both microwave and power electronics fields.

[0003] An inverter is a basic unit of an integrated circuit. Existing inverters based on enhancement-mode diodes and HEMTs have a large delay and high circuit power consumption. Summary of the Invention

[0004] The present invention is made in view of the above situations of the prior art, and is used to overcome or alleviate one or more technical problems existing in the prior art, and at least provides a beneficial option.

[0005] According to one aspect of the present invention, an inverter is provided. The inverter includes: enhancement-mode transistors Q1 and Q2, and a control circuit C. The drain of the enhancement-mode transistor Q1 is connected to the bus voltage VD, the source is connected to the drain of the enhancement-mode transistor Q2 and the voltage output terminal VOUT, and the gate is connected to the output of the control circuit C; the drain of the enhancement-mode transistor Q2 is connected to the source of Q1 and the voltage output terminal VOUT, the source is grounded, and the gate is connected to the input voltage VIN; and the control circuit C is connected to the gate of the enhancement-mode transistor Q1, the input voltage VIN, and the bus voltage VD, and is used to invert the on-states of the enhancement-mode transistors Q1 and Q2.

[0006] According to one embodiment, the control circuit C includes an enhancement-mode transistor Q3 and a voltage stabilization auxiliary control unit connected between the enhancement-mode transistor Q3 and the voltage bus. The voltage stabilization auxiliary control unit is used to stabilize the voltage applied to the voltage output terminal VOUT when the transistor Q1 is conducting. The drain of the enhancement-mode transistor Q3 is connected to the gate of the enhancement-mode transistor Q1, the gate of the enhancement-mode transistor Q3 is connected to the input voltage VIN, the source is connected to the ground, and the drain of the enhancement-mode transistor Q3 is connected to the voltage bus through the auxiliary control unit. The voltage stabilization auxiliary control unit may include a resistor or a diode, or a combination of a resistor and a capacitor.

[0007] Some embodiments of the present invention provide an inverter circuit integrating enhanced GaN, where the conduction times of the upper and lower transistors are opposite, and the circuit loss is smaller. The inverter circuits provided by some embodiments of the present invention all employ integrated enhanced GaN transistors and have a simple structure, thus being able to shorten the delay time. For example, it can be less than 5 ns. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments of the present invention can be better understood in conjunction with the accompanying drawings. These drawings are merely schematic, not drawn to scale, and do not show components that are not helpful for understanding the embodiments of the present invention. In the

[0009] In the figures:

[0010] Figure 1 shows a schematic structural diagram of an inverter according to an embodiment of the present invention;

[0011] Figure 2 shows an exemplary structural diagram of an inverter according to an embodiment of the present invention;

[0012] Figure 3 shows a schematic diagram of an inverter according to an embodiment of the present invention;

[0013] Figure 4 and Figure 5 shows a waveform schematic diagram of an inverter according to an embodiment of the present invention;

[0014] Figure 6 shows a schematic diagram of an inverter according to another embodiment of the present invention;

[0015] Figure 7 shows a schematic diagram of an inverter according to still another embodiment of the present invention; and

[0016] Figure 8 and Figure 9 shows a waveform schematic diagram of an inverter according to still another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The embodiments of the present invention will be further described below in conjunction with the accompanying drawings. These embodiments are all schematic and are not limitations on the protection scope of the present invention.

[0018] Figure 1 shows a schematic structural diagram of an inverter according to an embodiment of the present invention. As Figure 1As shown, an inverter according to an embodiment of the present invention includes an enhancement transistor Q1 (first enhancement transistor, upper transistor), an enhancement transistor Q2 (second enhancement transistor, lower transistor), and a control circuit C. The drain of the enhancement transistor Q1 is connected to the bus voltage (VD), the source is connected to the drain of the enhancement transistor Q2 and the voltage output terminal VOUT (output voltage), and the gate is connected to the output of the control circuit C. The drain of the enhancement transistor Q2 is connected to the source of the enhancement transistor Q1 and the voltage output terminal VOUT, the source is grounded, and the gate is connected to the input voltage VIN. The control circuit C is connected to the gate of the enhancement transistor Q1, the input voltage VIN, and the bus voltage VD. By controlling the conduction and cutoff of the upper transistor Q1, the on-states of the upper transistor Q1 and the lower transistor Q2 are inverted, that is, when the lower transistor Q2 is conducting, the upper transistor Q1 is cutoff, and when the lower transistor Q2 is cutoff, the upper transistor Q1 is conducting.

[0019] According to an embodiment, both the upper transistor Q1 and the lower transistor Q2 are GaN high electron mobility transistors, which conduct when a high voltage higher than its threshold voltage is applied to the gate. The control circuit C uses capacitors, resistors, and enhancement transistors to implement its functions. The enhancement transistors used are of the same type as the enhancement transistors Q1 and Q2, that is, they are all enhancement GaN high electron mobility transistors, which conduct when a voltage (high voltage) higher than its threshold voltage is applied to the gate.

[0020] Figure 2 An exemplary structural diagram of an inverter according to an embodiment of the present invention is shown. As Figure 2 shown, according to an embodiment, the control circuit C may include an enhancement transistor Q3 and a voltage stabilizing auxiliary control unit connected between the enhancement transistor Q3 and the voltage bus. The voltage stabilizing auxiliary control unit is used to stabilize the voltage applied to the voltage output terminal VOUT when the Q1 transistor is conducting. The drain of the enhancement transistor Q3 is connected to the gate of the enhancement transistor Q1, the gate of the enhancement transistor Q3 is connected to the input voltage VIN, and the source is connected to the ground. The drain of the enhancement transistor Q3 is also connected to the voltage bus VD through the voltage stabilizing auxiliary control unit. The voltage stabilizing auxiliary control unit may include a resistor, a diode, or a transistor, or a combination of a resistor and a capacitor, etc.

[0021] For the inverter according to this embodiment of the present invention, since enhancement transistors are used throughout, and only the upper transistor, the lower transistor, and the control circuit for controlling the lower transistor are used, the delay time can be shortened. In addition, since the on-states of the upper transistor Q1 and the lower transistor Q2 are inverted, circuit losses can be reduced.

[0022] Figure 3 A schematic diagram of an inverter according to an embodiment of the present invention is shown. As Figure 3As shown in the control Figure 1 , the control circuit C specifically includes an enhancement transistor Q3 (third enhancement transistor) and a resistor R1. One end of the resistor R1 is connected to the bus voltage VD, and the other end is connected to the drain of the enhancement transistor Q3 and the gate of the enhancement transistor Q1. The gate of the enhancement transistor Q3 is connected to the input voltage VIN, and the source is connected to the ground.

[0023] According to Figure 3 's implementation manner, when the input voltage VIN is at a low potential (a potential lower than the threshold voltage Vth of the enhancement transistor), the enhancement transistor Q3 is turned off, so that a high voltage is applied to the gate of the enhancement transistor Q1 and thus it is turned on. At the same time, since the input voltage VIN is connected to the gate of the enhancement transistor Q2, the enhancement transistor Q2 is turned off at this time. Therefore, the voltage output terminal VOUT is at a high voltage at this time. When the input voltage VIN is at a high potential (a potential greater than the threshold voltage Vth of the enhancement transistor), the enhancement transistor Q3 is turned on, so that a low voltage (equivalent to ground) is applied to the gate of the enhancement transistor Q1 and thus it is turned off. At the same time, since the input voltage VIN is connected to the gate of the enhancement transistor Q2, the enhancement transistor Q2 is turned on at this time. Therefore, the voltage output terminal VOUT is at a low voltage at this time. From the above description, it can be seen that according to this implementation manner of the present invention, the inversion of the input voltage VIN and the output voltage VOUT is realized, and when the output voltage VOUT is at a low voltage, the upper transistor Q1 is not turned on, so the upper transistor Q1 is not always in the on state, thereby reducing the circuit loss.

[0024] Figure 4 and Figure 5 show the waveform diagram of the inverter according to this implementation manner. From Figure 4 and Figure 5 , it can be seen that the output voltage VOUT and the input voltage VIN are well inverted, and the delay time is very short. Further, the switching state of the upper transistor Q1 is opposite to the switching state of the lower transistor Q2, and there is not always conduction loss, thus reducing the circuit loss of the entire circuit. In the implementation manner of the present invention, unless otherwise stated, the unit of time in the figure is microsecond (μs).

[0025] According to an implementation manner, the enhancement transistors Q1, Q2, and Q3 are all GaN high electron mobility transistors, and they are turned on when a high voltage is applied to the gate.

[0026] According to one embodiment, the gate width of the enhancement-mode transistor Q3 is the same as that of the enhancement-mode transistors Q1 and Q2, and the value of the resistor R1 is not greater than 100 times the on-resistance Rdson of the enhancement-mode transistor Q3 when it is fully turned on. By adjusting the gate width and the value of the resistor R1 in this way, the delay time can be better reduced, the response speed can be increased, and the performance can be improved.

[0027] Figure 6 FIG. shows a schematic diagram of an inverter according to another embodiment of the present invention. As Figure 6 shown, in contrast Figure 1 , the control circuit C includes an enhancement-mode transistor Q3 (third enhancement-mode transistor) and an enhancement-mode transistor Q4 (fourth enhancement-mode transistor). The gate of the enhancement-mode transistor Q3 is connected to the input voltage VIN, the source is grounded, and the drain is connected to the drain of the enhancement-mode transistor Q4 and the gate of the upper transistor Q1. The gate and the source of the enhancement-mode transistor Q4 are both connected to the bus voltage VD.

[0028] According to Figure 6 the embodiment shown, when the input voltage VIN is at a low potential, the enhancement-mode transistor Q3 is turned off. Since the enhancement-mode transistor Q4 is in a normally open state, a high voltage is applied to the gate of the enhancement-mode transistor Q1, and thus it is turned on. At the same time, since the input voltage VIN is connected to the gate of the enhancement-mode transistor Q2, the enhancement-mode transistor Q2 is turned off at this time. Therefore, the output voltage VOUT is at a high voltage at this time. When the input voltage VIN is at a high potential, the enhancement-mode transistor Q3 is turned on, so that a low voltage (grounded) is applied to the gate of the enhancement-mode transistor Q1, and thus it is turned off. At the same time, since the input voltage VIN is connected to the gate of the enhancement-mode transistor Q2, the enhancement-mode transistor Q2 is turned on at this time. Therefore, the output voltage VOUT is at a low voltage at this time. From the above description, it can be seen that according to this embodiment of the present invention, the inversion of the input voltage VIN and the output voltage VOUT is realized, and when the output voltage VOUT is output at a low voltage, the upper transistor Q1 is not turned on, that is, the upper transistor Q1 is not always in an on state, so that the circuit loss can be reduced.

[0029] According to one embodiment, the enhancement-mode transistors Q1, Q2, Q3, and Q4 are all GaN high electron mobility transistors.

[0030] According to one embodiment, the enhancement-mode transistor Q4 can also be replaced by a GaN diode. According to one embodiment, the gate width of the enhancement-mode transistor Q3 is the same as that of the enhancement-mode transistors Q1 and Q2, and the gate width of the enhancement-mode transistor Q4 is not greater than 0.1 times the gate width of the enhancement-mode transistor Q3. By setting the gate width in this way, the response speed can be increased and the performance can be improved.

[0031] Figure 7A schematic diagram of an inverter according to yet another embodiment of the present invention is shown. As Figure 7 shown, with reference to Figure 1 , the control circuit C includes an enhancement-type transistor Q3 (third enhancement-type transistor), a capacitor C1, and a resistor R1. The capacitor C1 and the resistor R1 are in parallel. One end of the parallel-connected resistor R1 and capacitor C1 is connected to the bus voltage VD, and the other end is connected to the drain of the enhancement-type transistor Q3 and the gate of the enhancement-type transistor Q1. The gate of the enhancement-type transistor Q3 is connected to the input voltage VIN, and the source is connected to the ground.

[0032] Similar to the Figure 3 embodiment, according to the Figure 7 embodiment shown, when the input voltage VIN is at a low potential, the enhancement-type transistor Q3 is turned off, so that a high voltage is applied to the gate of the enhancement-type transistor Q1 and thus it conducts. At the same time, since the input voltage VIN is connected to the gate of the enhancement-type transistor Q2, the enhancement-type transistor Q2 is turned off at this time. Therefore, the output voltage VOUT is at a high voltage at this time. When the input voltage VIN is at a high potential, the enhancement-type transistor Q3 conducts, so that a low voltage (grounded) is applied to the gate of the enhancement-type transistor Q1 and thus it is turned off. At the same time, since the input voltage VIN is connected to the gate of the enhancement-type transistor Q2, the enhancement-type transistor Q2 conducts at this time. Therefore, the output voltage VOUT is at a low voltage at this time. It can be seen from the above description that according to this embodiment of the present invention, the inversion of the input voltage VIN and the output voltage VOUT is achieved, and when the output voltage VOUT is output at a low voltage, the enhancement-type transistor Q1 does not conduct, so the enhancement-type transistor Q1 is not a normally-on device, thereby reducing the circuit loss. Since the capacitor C1 is added, the resistor R1 and the capacitor C1 form an RC delay network, which limits the voltage and current of the bus voltage VD applied to the upper transistor Q1, making the output voltage stable at VD - Vth.

[0033] Figure 8 And Figure 9 show the waveform diagram of the inverter according to this embodiment. It can be seen from Figure 8 and Figure 9 that the output voltage VOUT and the input voltage VIN are inverted well and the delay time is very short. Further, the voltage Vg of the upper transistor is in phase with the output voltage VOUT, and there is not always circuit loss, thus reducing the circuit loss of the entire circuit.

[0034] According to one embodiment, the gate width of the enhancement-mode transistor Q3 is the same as that of the enhancement-mode transistors Q1 and Q2, and the value of the resistor R1 is not greater than 100 times and not less than 3 times the on-resistance Rdson of the enhancement-mode transistor Q3 when it is fully turned on. The value of the capacitor C1 is not greater than 10 times that of the resistor R1. ^-15 The value of the capacitor C1 is generally in the order of fF and pF. For example, if the resistor R has a value of 1 ohm, then the value of the capacitor C1 is not greater than 1 fF. With such a setting, the response speed can be increased and the performance can be improved.

[0035] In the above embodiment, the enhancement-mode transistors Q1 to Q4 may all conduct when a high voltage is applied to the gate. Since the structures of some embodiments of the present invention are simple, the number of transistors is small, and all use enhancement-mode transistors (such as enhancement-mode GaN field-effect transistors), the delay time can be shortened. For example, the delay time can be shortened to 5 ns.

[0036] According to one embodiment of the present invention, the enhancement-mode transistors, capacitors (if any), and resistors (if any) involved in the above embodiments are all integrated in a single chip. The substrate material of the chip may include, but is not limited to, silicon, silicon carbide, aluminum nitride, or sapphire material.

[0037] Integrating these devices in a single chip can reduce the volume of the system.

[0038] The above detailed description of the present invention is only used to enable those skilled in the art to further understand the present invention for the purpose of implementing the present invention, and does not limit the scope of the present invention. Only the claims are used to determine the scope of protection of the present invention. Therefore, the combination of features in the foregoing detailed description does not necessarily represent the widest scope of the present invention. To obtain additional useful embodiments of the present invention, the various different features taught in the specification can be combined in various ways, and these combinations are all within the scope of the present invention.

Claims

1. An inverter, characterized in that, The inverter includes: an enhancement-mode transistor Q1, an enhancement-mode transistor Q2, and a control circuit C. Wherein, The drain of the enhancement-mode transistor Q1 is connected to the bus voltage VD, the source is connected to the drain of the enhancement-mode transistor Q2 and the voltage output terminal VOUT, and the gate is connected to the output of the control circuit C; The drain of the enhancement-mode transistor Q2 is connected to the source of the enhancement-mode transistor Q1 and the voltage output terminal VOUT, the source is grounded, and the gate is connected to the input voltage VIN; The control circuit C is connected to the gate of the enhancement-mode transistor Q1, the input voltage VIN, and the bus voltage VD, and is used to invert the on states of the enhancement-mode transistors Q1 and Q2; The control circuit C includes an enhancement-mode transistor Q3 and a resistor R1. One end of the resistor R1 is connected to the bus voltage VD, and the other end is connected to the drain of the enhancement-mode transistor Q3 and the gate of the enhancement-mode transistor Q1. The gate of the enhancement-mode transistor Q3 is connected to the input voltage VIN, and the source is connected to the ground; The enhancement-mode transistor Q3 is a GaN high electron mobility transistor, which conducts when a high voltage higher than its threshold voltage is applied to the gate. The gate width of the enhancement-mode transistor Q3 is the same as that of the enhancement-mode transistors Q1 and Q2, and the value of the resistor R1 is not greater than 100 times the on-resistance Rdson when the enhancement-mode transistor Q3 is fully turned on; and The control circuit C further includes a voltage stabilization auxiliary control unit connected between the enhancement-mode transistor Q3 and the voltage bus. The voltage stabilization auxiliary control unit is used to stabilize the voltage applied to the voltage output terminal VOUT when the enhancement-mode transistor Q1 is conducting.

2. An inverter, characterized in that, The inverter includes: an enhancement-mode transistor Q1, an enhancement-mode transistor Q2, and a control circuit C. Wherein, The drain of the enhancement-mode transistor Q1 is connected to the bus voltage VD, the source is connected to the drain of the enhancement-mode transistor Q2 and the voltage output terminal VOUT, and the gate is connected to the output of the control circuit C; The drain of the enhancement-mode transistor Q2 is connected to the source of the enhancement-mode transistor Q1 and the voltage output terminal VOUT, the source is grounded, and the gate is connected to the input voltage VIN; The control circuit C is connected to the gate of the enhancement-mode transistor Q1, the input voltage VIN, and the bus voltage VD, and is used to invert the on states of the enhancement-mode transistors Q1 and Q2; The control circuit C includes an enhancement-mode transistor Q3 and an enhancement-mode transistor Q4. The gate of the enhancement-mode transistor Q3 is connected to the input voltage VIN, the source is grounded, and the drain is connected to the drain of the enhancement-mode transistor Q4 and the gate of the upper transistor Q1; The gate and the source of the enhancement-mode transistor Q4 are both connected to the bus voltage VD; The gate width of the enhancement-mode transistor Q3 is the same as that of the enhancement-mode transistors Q1 and Q2, and the gate width of the enhancement-mode transistor Q4 is not greater than 0.1 times the gate width of the enhancement-mode transistor Q3; and The control circuit C further includes a voltage stabilization auxiliary control unit connected between the enhancement transistor Q3 and the voltage bus, and the voltage stabilization auxiliary control unit is configured to stabilize the voltage applied to the voltage output terminal VOUT when the enhancement transistor Q1 is turned on.

3. An inverter, characterized in that, The inverter includes: an enhancement transistor Q1, an enhancement transistor Q2, and a control circuit C. Wherein, The drain of the enhancement transistor Q1 is connected to the bus voltage VD, the source is connected to the drain of the enhancement transistor Q2 and the voltage output terminal VOUT, and the gate is connected to the output of the control circuit C. The drain of the enhancement transistor Q2 is connected to the source of the enhancement transistor Q1 and the voltage output terminal VOUT, the source is grounded, and the gate is connected to the input voltage VIN. The control circuit C is connected to the gate of the enhancement transistor Q1, the input voltage VIN, and the bus voltage VD, and is configured to invert the on states of the enhancement transistors Q1 and Q2. The control circuit C includes an enhancement transistor Q3, a capacitor C1, and a resistor R1. The capacitor C1 and the resistor R1 are in parallel, and one end of the parallel-connected resistor R1 and capacitor C1 is connected to the bus voltage VD, and the other end is connected to the drain of the enhancement transistor Q3 and the gate of the enhancement transistor Q1. The gate of the enhancement transistor Q3 is connected to the input voltage VIN, and the source is connected to the ground. The gate width of the enhancement-mode transistor Q3 is the same as that of the enhancement-mode transistors Q1 and Q2, and the value of the resistor R1 is not greater than 100 times and not less than 3 times the on-resistance Rdson of the enhancement-mode transistor Q3 when it is fully turned on. The value of the capacitor C1 is not greater than 10 times the value of the resistor R1 -15 times; and The control circuit C further includes a voltage stabilization auxiliary control unit connected between the enhancement transistor Q3 and the voltage bus, and the voltage stabilization auxiliary control unit is configured to stabilize the voltage applied to the voltage output terminal VOUT when the enhancement transistor Q1 is turned on.

4. The inverter according to claim 3, characterized in that, The enhancement transistors Q1, Q2, and Q3, as well as the capacitor C and the resistor R1 are all integrated in a single chip, and the substrate material of the chip is selected from the set including silicon, silicon carbide, aluminum nitride, and sapphire materials.

Images