A GaN transistor drive circuit

Abstract

The application relates to a GaN transistor driving circuit. It is used for a driven GaN transistor, and comprises upper and lower transistor circuits and upper and lower transistor control circuits. The upper and lower transistor circuits comprise upper and lower transistors, the upper and lower transistors are GaN transistors, the drain of the upper transistor is connected with a power voltage VCC, the gate is connected with a digital input VIN, the source is connected with the drain of the lower transistor, and is connected with the gate of the driven GaN transistor as the output of the GaN transistor driving circuit; the gate of the lower transistor is connected with the upper and lower transistor control circuits; the upper and lower transistor control circuits control the lower transistor by using a bus voltage VD, the power voltage VCC and the digital input VIN, so that the output of the GaN transistor driving circuit is in phase with the digital input VIN, the upper and lower transistor control circuits comprise transistors, the transistors are GaN transistors, and are turned on when the gate is applied with a voltage higher than a threshold voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to GaN transistors, and in particular to GaN transistor drive circuits. BACKGROUND

[0002] With the rapid development of power electronic systems, the market of power semiconductor devices has been rapidly developed. The performance of silicon-based devices has gradually reached the theoretical limit of the material, and more and more cannot meet the needs of modern high-power power electronic systems. In this case, the third generation of wide bandgap semiconductors represented by GaN and SiC gradually replaced Si materials and became the first choice for device design in high temperature and high frequency environments.

[0003] The existing gate driver of Si devices is not suitable for driving GaN devices, mainly in that the gate drive voltage of enhancement mode GaN transistors is low (6V), and the difference between the gate breakdown voltage and the fully on voltage is also low (3V). Although the traditional gate driver using Si MOSFET to generate gate voltage is effective for most Si MOSFET devices, it cannot provide low voltage gate voltage for GaN devices. Moreover, the existing drive is manufactured by Si process incompatible with GaN, so it will increase the inductance of the gate loop. Since the GaN device turn-on speed is in the nanosecond level, the power loop dV / dt is generally greater than 100V / ns, which will cause a huge oscillation in the gate loop inductance. Therefore, using the traditional gate driver to directly drive GaN devices not only may cause device breakdown, thereby causing system failure, but also introduces circuit oscillation to affect system efficiency improvement.

[0004] On the other hand, although the fully integrated GaN driver in the prior art can effectively drive the main GaN device to work normally, the internal structure of the driver is often complex, and the turn-on and turn-off delay is long. SUMMARY

[0005] The present application is made in view of the above circumstances of the prior art, for overcoming or alleviating one or more technical problems existing in the prior art, and at least providing a beneficial choice.

[0006] According to an aspect of the present application, there is provided a GaN transistor driving circuit, comprising an up-down transistor circuit and an up-down transistor control circuit, the up-down transistor circuit comprising an up transistor and a down transistor, both of which are GaN transistors, the drain of the up transistor being connected to a power supply voltage, the gate of the up transistor being connected to a digital input, the source of the up transistor being connected to the drain of the down transistor and serving as an output of the GaN transistor driving circuit and being connected to the gate of a driven GaN transistor; the gate of the down transistor being connected to the up-down transistor control circuit; the up-down transistor control circuit using a working voltage, a power supply voltage and a digital input to control the down transistor, so that the output of the GaN transistor driving circuit is in phase with the digital input, the up-down transistor control circuit comprising transistors, all of which are GaN transistors and are turned on when a voltage higher than a threshold voltage is applied to the gate.

[0007] According to the embodiment of the present application, the driving circuit is simple in structure and short in delay.

[0008] According to some embodiments of the present application, the GaN transistor driving circuit and the GaN power device are integrated in a single chip, so that the volume of the system can be reduced and the power consumption can be lowered. BRIEF DESCRIPTION OF DRAWINGS

[0009] The present application can be better understood in connection with the accompanying drawings, in which:

[0010] Figure 1 is a schematic diagram of a GaN transistor driving circuit according to an embodiment of the present application.

[0011] Figure 2 shows a schematic diagram of a GaN transistor driving circuit according to another embodiment of the present application.

[0012] Figure 3 shows a schematic diagram of a GaN transistor driving circuit according to Figure 4 shows the input and output waveforms of the embodiment shown.

[0013] Figure 4 shows a schematic diagram of a GaN transistor driving circuit according to another embodiment of the present application.

[0014] Figure 5 shows a schematic diagram of a GaN transistor driving circuit according to Figure 4 shows the input and output waveforms of the embodiment shown. DETAILED DESCRIPTION

[0015] Figure 1 is a schematic diagram of a GaN transistor driving circuit according to an embodiment of the present application. As shown in the figure, the GaN transistor driving circuit comprises an up-down transistor circuit and an up-down transistor control circuit. Figure 1As shown, the GaN transistor drive circuit 1 according to an embodiment of the present application is used to drive a driven GaN transistor Q1, the drain of the driven GaN transistor Q1 is connected to the bus voltage VD, and the source is connected to the ground. The GaN transistor drive circuit 1 comprises a push-pull circuit 10 and a push-pull control circuit 20. The push-pull circuit 10 comprises a pull-up transistor Q5 and a pull-down transistor Q6, both of which are GaN transistors, specifically, can be enhancement-mode GaN high electron mobility transistors (HEMTs) that are turned on when a high voltage higher than a threshold voltage is applied to the gate. Those skilled in the art should understand that in the present application, voltages higher than the threshold voltage of a transistor can be referred to as high voltages, and vice versa, can be referred to as low voltages. According to an embodiment of the present application, the bus voltage VD can be a high voltage of 100V-650V, the power supply voltage VCC can be 6V, and the logic high level of the digital input VIN is 12V, and the logic low level is 0V. Thus, the power supply voltage VCC and the logic high level of the digital input VIN are high voltages.

[0016] The drain of the pull-up transistor Q5 is connected to the power supply voltage VCC, the gate is connected to the digital input VIN, the source is connected to the drain of the pull-down transistor Q6, and as the output of the GaN transistor drive circuit 1, is connected to the gate of the driven GaN transistor Q1. The gate of the pull-down transistor Q6 is connected to the push-pull control circuit 20. The push-pull control circuit 20 controls the pull-down transistor using the bus voltage VD, the power supply voltage VCC, and the digital input VIN, so that the output of the GaN transistor drive circuit is in phase with the digital input VIN. The push-pull control circuit 20 comprises transistors, and all the transistors included are GaN transistors that are turned on when a voltage higher than a threshold voltage is applied to the gate.

[0017] According to this embodiment, the transistors used in the push-pull circuit 10 and the push-pull control circuit 20 are GaN transistors, and the functions are simple, so the entire circuit structure is simple and the delay is short.

[0018] Figure 2 A schematic diagram of a GaN transistor drive circuit according to an embodiment of the present application is shown. For comparison Figure 1 The push-pull control circuit 20 comprises a first transistor Q3, a second transistor Q4, and a third transistor Q2.

[0019] The drain of the first transistor Q3 is connected to the source of the third transistor Q2 and the gate of the pull-down transistor Q6, the gate of the first transistor Q3 is connected to the source of the second transistor Q4, and the source of the first transistor Q3 is grounded.

[0020] The drain of the second transistor Q4 is connected to the digital input VIN, the gate of the second transistor Q4 is connected to the power supply voltage VCC, and the source of the second transistor Q4 is connected to the gate of the first transistor Q3.

[0021] The drain of the third transistor Q2 is connected to the operating voltage VD, the gate of the third transistor Q2 is connected to the drain of the lower transistor Q6 and the source of the upper transistor Q5, and the source of the third transistor Q2 is connected to the drain of the first transistor Q3.

[0022] When VIN is high voltage, the upper transistor Q5 is turned on. At the same time, since the second transistor Q4 is in the always-on state, VIN is applied to the gate of the first transistor Q3 through the second transistor Q4, so that the first transistor Q3 is turned on. In this way, the gate of the lower transistor Q6 is applied with low voltage, so that the lower transistor Q6 is turned off. Since the upper transistor Q5 is turned on and the lower transistor Q6 is turned off as described above, the transistor Q2 is turned on, so that the gate of the driven GaN transistor Q1 is applied with high voltage. When VIN is low voltage, the upper transistor Q5 is turned off. At the same time, since the second transistor Q4 is in the always-on state, low voltage VIN is applied to the gate of the first transistor Q3 through the second transistor Q4, so that the first transistor Q3 is also turned off. At the moment when the transistor Q3 is turned off, due to the delay of the circuit, the transistor Q2 is still in the turned-on state, so that the gate of the lower transistor Q6 is at the same potential as the bus voltage. Since the protection diode D1 exists, the lower transistor Q6 is kept turned on and will not be broken down by the bus voltage. When the circuit is in a steady state, the upper transistor Q5 is turned off, the lower transistor Q6 is turned on, and thus the gate of the driven GaN transistor Q1 is applied with low voltage.

[0023] According to an embodiment of the present application, the gate width of the third transistor Q2, the first transistor Q3, the upper transistor Q5 and the lower transistor Q6 is the same, and the gate width of the second transistor Q4 is 5%-30% of the gate width of the third transistor Q2, more preferably 10%. By using such a technical solution, the response speed of the driving circuit can be improved. In the present application, the gate width of two transistors being the same means that the difference between the gate width of one transistor and the gate width of the other transistor is within 10% of the gate width of the one transistor.

[0024] According to an embodiment, the driven transistor Q1 and the GaN transistor driving circuit of the present application are integrated on a single chip.

[0025] Figure 3 The input and output waveforms of the embodiment shown in Figure 2 The input and output waveforms of the embodiment shown in Figure 3 It can be seen from the waveform diagram that the gate voltage of the driven device Q1 is very well in phase with the digital input VIN, the delay is short, and the output can be stabilized.

[0026] Figure 4A schematic diagram of a GaN transistor driver circuit according to still another embodiment of the present application is shown. As Figure 4 indicated, a voltage stabilizing circuit 30 is provided between the power supply voltage VCC and the upper and lower transistor circuits.

[0027] The structure in the dashed box is the same as that of the embodiment shown in Figure 2 and thus will not be described again.

[0028] The voltage stabilizing circuit outside the dashed box is composed of a transistor Q7, resistors R1 and R2, a capacitor C1 and a diode D2 to provide the voltage required by the drain of the upper transistor Q5.

[0029] In this embodiment, the drain of the transistor Q7 is connected to the power supply voltage VCC, the source is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded. The power supply voltage VCC is also connected to one end of the resistor R1, the other end of the resistor R1 is connected to the gate of the transistor Q7 and the anode of the diode D2, and the cathode of the diode D2 is grounded. The transistor Q7 has the same gate width as the transistor Q4, and the diode D2 is a clamping diode with a clamping voltage of 9V.

[0030] The capacitor C1 can be replaced by a source-drain shorted and gate enhanced device. In addition, the resistors R1 and R2, the capacitor C1 and the diode D2 can also be composed of discrete components outside the chip.

[0031] According to the present embodiment, the logic high voltage of the power supply voltage VCC and the digital input VIN is 12V on average, and the logic low voltage of the digital input VIN is 0V.

[0032] Figure 5 Input and output waveforms according to the embodiment shown in Figure 4 are shown. As can be seen from the waveform diagram Figure 5 , the gate voltage of the driven device Q1 is very well in phase with the digital input VIN, the delay is short, and the output is stable. At the same time, the voltage at the drain of the upper transistor Q5 is also very stable.

[0033] According to the embodiments of the present application, one or more of the following advantages can be achieved.

[0034] (1) All GaN transistors are used inside the whole chip, which is more conducive to monolithic integration of the gate drive circuit and the main device.

[0035] (2) The designed drive circuit can provide a more accurate gate voltage for the main device (transistor Q1), so that the main device can work safely and stably.

[0036] (3) Under the premise of providing the main device with the required gate voltage, the volume and power consumption of the driver are further reduced.

[0037] However, those skilled in the art will appreciate that some embodiments according to the present application can also be realized without any of the above advantages and only to provide an alternative.

[0038] The foregoing detailed description of the application has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. Various modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best illustrate the principles of the application and its practical application to thereby enable others skilled in the art to best utilize the application. It is intended that the scope of the application be defined by the claims appended hereto and their equivalents. Accordingly, the specification is to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A GaN transistor drive circuit for driving a driven GaN transistor (Ql), the drain of the driven GaN transistor (Ql) being connected to a bus voltage (VD), characterized in that The GaN transistor drive circuit comprises an up-down transistor circuit and an up-down transistor control circuit, the up-down transistor circuit comprises an up transistor (Q5) and a down transistor (Q6), both of which are GaN transistors, the drain of the up transistor is connected with a power supply voltage (VCC), the gate of the up transistor is connected with a digital input (VIN), the source of the up transistor is connected with the drain of the down transistor, and the output of the GaN transistor drive circuit is connected with the gate of the driven GaN transistor; the gate of the down transistor is connected with the up-down transistor control circuit, the up-down transistor control circuit comprises a first transistor (Q3), a second transistor (Q4) and a third transistor (Q2), the drain of the second transistor (Q4) is connected with the digital input (VIN), the gate of the second transistor (Q4) is connected with the power supply voltage VCC, the drain of the third transistor (Q2) is connected with a bus voltage (VD), the third transistor (Q2) is a high-voltage transistor, the first transistor (Q3), the second transistor (Q4), the up transistor (Q5) and the down transistor (Q6) are all low-voltage transistors, the up-down transistor control circuit controls the down transistor by using the power supply voltage (VCC) and the digital input (VIN), so that the output of the GaN transistor drive circuit is in phase with the digital input (VIN), the up-down transistor control circuit comprises transistors, and all the transistors are GaN transistors and are turned on when the gate is applied with a voltage higher than the threshold voltage; The gate width of the second transistor (Q4) is 5-30% of the gate width of the third transistor (Q2).

2. The GaN transistor drive circuit of claim 1, wherein, The up-down transistor circuit further comprises a GaN diode, the anode of the GaN diode is connected with the gate of the down transistor, and the cathode is connected with the ground.

3. The GaN transistor drive circuit of claim 1, wherein, The drain of the first transistor (Q3) is connected with the source of the third transistor (Q2) and the gate of the down transistor (Q6), the gate of the first transistor (Q3) is connected with the source of the second transistor (Q4), and the source of the first transistor (Q3) is grounded; the source of the second transistor (Q4) is connected with the gate of the first transistor (Q3); the gate of the third transistor (Q2) is connected with the drain of the down transistor (Q6), and the source of the third transistor (Q2) is connected with the drain of the first transistor (Q3).

4. The GaN transistor drive circuit of claim 1, wherein, A voltage stabilizing circuit is arranged between the power supply voltage (VCC) and the up-down transistor circuit (10).

5. The GaN transistor drive circuit of claim 4, wherein, The voltage stabilizing circuit comprises a GaN transistor (Q7), a first resistor (R1), a second resistor (R2), a capacitor (C1) and a diode (D2), the drain of the GaN transistor (Q7) is connected with the power voltage (VCC), the source is connected with one end of the capacitor (C1), the other end of the capacitor (C1) is connected with one end of the second resistor (R2), the other end of the second resistor (R2) is grounded, the power voltage (VCC) is also connected with one end of the first resistor (R1), the other end of the first resistor (R1) is connected with the gate of the GaN transistor (Q7) and the anode of the diode (D2), and the cathode of the diode (D2) is grounded.

6. The GaN transistor driver circuit of claim 1, wherein, The GaN transistor driving circuit and the driven GaN transistor are integrated on a single chip.

7. The GaN transistor drive circuit of claim 3, wherein, The gate widths of the third transistor (Q2), the first transistor (Q3), the upper transistor (Q5) and the lower transistor (Q6) are the same.

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