Differential delta-sigma modulator for a hearing aid

Abstract

A differential Δ-Σ modulator includes an integrator (49) comprising a pair of single-ended amplifiers (46, 47). The differential Δ-Σ modulator includes a sampling clock (50) that drives a first switchable capacitor configuration (31) and a second switchable capacitor configuration (32) at predetermined switching cycles. The second switchable capacitor configuration (32) is adapted to sample the corresponding outputs from the pair of single-ended amplifiers (46, 47) across a pair of output sampling capacitors (C3, C5) in a first portion (P1) of the switching cycle, and to charge a common-mode capacitor (C4) with the average voltage of the voltages sampled by the pair of output sampling capacitors (C3, C5) in a second portion (P2) of the switching cycle. The voltage across the common-mode capacitor (C4) represents the common-mode voltage of the integrator (49).

Description

Technical Field

[0001] This invention relates to hearing aids. More specifically, this invention relates to a hearing aid comprising a differential Δ-Σ modulator for providing a digitized signal. Background Technology

[0002] For sensitive analog circuits in complex mixed-mode integrated circuits, differential topologies are required. Differential topologies are highly immune to noise coupling from adjacent circuits. This immunity becomes increasingly important as the demand for integrating more functionality onto integrated circuits or chips continues to grow.

[0003] However, in power-sensitive applications such as hearing aids, using a single-ended topology may be advantageous because a single-ended amplifier with the same noise performance typically consumes less power compared to a differential amplifier.

[0004] The purpose of this invention is to provide a differential Δ-Σ modulator with low power consumption. There is a need to increase the integration of our audio converter with other circuits. Ease of integration and noise immunity are becoming increasingly important. Summary of the Invention

[0005] The object of the present invention is achieved by a differential Δ-Σ modulator comprising a pair of single-ended amplifiers. The invention is defined in claims 1, 8, 9, 16, and 25. Preferred embodiments are defined in the dependent claims.

[0006] Attached illustrations

[0007] The invention will be described in further detail with reference to preferred aspects and the accompanying drawings, wherein:

[0008] Figure 1 The basic principle of a Δ-Σ modulator is illustrated.

[0009] Figure 2 A basic single-stage single-ended amplifier is shown;

[0010] Figure 3 An embodiment of the differential Δ-Σ modulator according to the present invention is schematically illustrated;

[0011] Figure 4 An embodiment of the differential Δ-Σ modulator according to the present invention is illustrated, and

[0012] Figure 5a and Figure 5b The diagram illustrates the corresponding time period in two non-overlapping time periods of the sampling period. Figure 4 The differential Δ-Σ modulator shown;

[0013] Figure 6 An embodiment of the present invention, which includes a differential Δ-Σ modulator in a hearing aid device, is shown. Detailed Implementation

[0014] Δ-Σ modulation is a method for encoding analog signals into digital signals. In one embodiment of the invention, a Δ-Σ modulator is used to convert an analog input signal into a higher-frequency digital signal. According to one embodiment of the invention, a Δ-Σ modulator is used (e.g., in a hearing aid) to convert the output from a differential microphone into a 1-bit bitstream for further signal processing.

[0015] A Δ-Σ modulator according to one embodiment of the present invention includes an integrator, a quantizer, and a feedback loop. The number of integrators and the number of feedback loops determine the order of the Δ-Σ modulator. Generally, a first-order modulator is unconditionally stable, while the stability of higher-order modulators needs to be guaranteed through practical design.

[0016] In an ideal differential circuit, the output signal is represented by the differential voltage (difference), while the output common-mode voltage (sum) is ideally zero (because the two outputs are equal but have opposite signs). Similarly, the input signal is interpreted as a voltage difference. An ideal differential circuit responds only to the voltage difference and ignores the common-mode voltage.

[0017] The advantage of differential circuits is that external noise has the same effect on both outputs, so this noise enters as common-mode rather than differentially. This means that differential circuits suppress external noise sources. For example, external interference may originate from board noise, power supply, or reference noise.

[0018] Ideally, the common-mode amplification is zero, but in practical circuits, the common-mode amplification may be different from zero.

[0019] Importantly, the common-mode amplification is moderate so that the common-mode signal does not saturate the output (subsequent circuitry). Therefore, the common-mode amplification should preferably be less than 1; otherwise, it may eventually become too large when further differential modules are cascaded (e.g., in higher-order ΔΣ modulators).

[0020] When the circuit is well balanced, the common-mode rejection ratio (CMRR) is high, and why the common-mode amplification is zero is not so important. Good balance enables the circuit to resist common-mode signals at the input without introducing differential residues at the output.

[0021] In one embodiment, the common-mode amplification is very small to ensure that the common-mode voltage is not amplified from one modulator stage to subsequent modulator or integrator stages, thereby risking saturation of subsequent differential circuitry. In one embodiment, the common-mode amplification is one; and in other embodiments, the common-mode amplification is slightly less than one, for example, in the range of 0.9–1.

[0022] Figure 1The diagram illustrates the basic principle of a delta-sigma modulator (e.g., for use in hearing aids or hearing devices). At input 10, the delta-sigma modulator receives an analog input signal representing an audio signal picked up, for example, by means of an input transducer like a microphone. The analog input signal is directed via adder 11 to integrator 12, which integrates the signal received from adder 11, and further to quantizer 13. Quantizer 13 outputs a digitized signal based on the signal received from adder 11 and integrated in integrator 12. A reference signal and a clock signal control the sampling frequency or bit rate of the output signal. The signal from quantizer 13 to output 14 is fed back to adder 11 via a feedback loop and subtracted from the analog input signal. The feedback loop includes a 1-bit digital-to-analog converter 15 that ensures the feedback signal is presented to adder 11 as an analog signal.

[0023] Figure 2 A basic single-stage single-ended amplifier 20 with a first p-channel MOSFET transistor 21 and a second n-channel MOSFET transistor 22 is shown. The single-stage single-ended amplifier 20 is powered by a positive supply voltage V. dd and negative power supply voltage or ground V ss Power supply. The input signal supplied to the single-stage single-ended amplifier 20 is at the input terminal V. in The signal is received and the output provided by the single-stage single-ended amplifier 20 is at the output terminal V. out Upload.

[0024] Figure 2 The single-stage single-ended amplifier 20 shown has very high power efficiency. Furthermore, when a pair of single-stage single-ended amplifiers 20 are used in the integrator stage of the Δ-Σ modulator according to the invention, the single-stage single-ended amplifier 20 exhibits several advantages. Both transistors 21 and 22 contribute to transconductance. Therefore, the input reference voltage noise of the combined transistors 21 and 22 is ultimately lower than the noise from each of the individual transistors 21 and 22. This is an improvement compared to the commonly used differential amplifier topology where transistor noise is additive. Moreover, the nonlinearity in each individual transistor tends to cancel out the nonlinearity of the opposite transistor. The combined characteristics of the two transistors are more linear than those of a single transistor.

[0025] also, Figure 2The single-stage single-ended amplifier 20 shown has excellent input and output performance. The single-stage single-ended amplifier 20 operates as a push-pull amplifier, alternately supplying current to or drawing current from a connected load. Push-pull amplifiers are generally very efficient and can achieve high output power. When the amplifier input amplitude is large, the transconductance increases, thus reducing the settling time. The combined single-stage input and output stages have higher power efficiency compared to topologies with multiple gain stages. Furthermore, the single-stage amplifier is inherently stable in a closed loop. This allows the amplifier to be used without frequency compensation, thus achieving rapid settling. In a differential configuration, the power supply noise (e.g., at V) is significantly reduced. dd The above appears as a common mode and is rejected.

[0026] According to the present invention, the common-mode signal is fed back from the output to the input to facilitate control of the common-mode gain. This does not alter the important differential characteristics of the circuit, which will be explained in detail below.

[0027] Figure 3 An embodiment of a differential Δ-Σ modulator according to the present invention is schematically illustrated. The differential Δ-Σ modulator has two differential input terminals 30 and an integrator 49 including a pair of single-ended amplifiers 46, 47. The integrator 49 has a first switchable capacitor configuration 31 provided between the two differential input terminals 30 and the inputs of the pair of single-ended amplifiers 46, 47; and a second switchable capacitor configuration 32 provided between the inputs and outputs of the respective pair of single-ended amplifiers 46, 47. A sampling clock 50 is used to drive the two switchable capacitor configurations 31, 32 at a predetermined switching period. In one embodiment, the sampling clock 50 provides a sampling period consisting of two non-overlapping portions or time periods P1, P2.

[0028] In one embodiment, the second switchable capacitor configuration 32 includes a pair of output sampling capacitors C3 and C5 and a switch S. 16 S 17 ,like Figure 4 As shown, this is used to sample the corresponding outputs from a pair of single-ended amplifiers 46 and 47 during the first part P1 of the switching cycle. The second switchable capacitor configuration 32 also includes a common-mode capacitor C4 and a switch S. 26 S 27 Switch S 26 S 27 The common-mode capacitor C4 is charged in the second part P2 of the switching cycle using the average voltage of the low-pass filtered voltage sampled by a pair of output sampling capacitors C3 and C5. The voltage across the common-mode capacitor C4 represents the common-mode voltage used for the low-pass filtering of integrator 49.

[0029] In one embodiment, the second switchable capacitor configuration 32, during the second portion P2 of the switching cycle, is connected via a pair of capacitors C6, C7 and switch S. 23 S 21 S 25 Provide feedback paths to the corresponding inputs of the two single-ended amplifiers 46 and 47 (e.g., Figure 4 (As shown).

[0030] In one embodiment, the first switchable capacitor configuration 31 includes an input sampling capacitor C8 and a switch S. 12 S 14 ,like Figure 4 As shown, this is used to switch the signal from the differential input terminal V during the first part P1 of the switching cycle. in+ V in- (exist Figure 3 The input (referred to as 30) is sampled, and switch S 22 S 24 Used to transfer the sampled input from the input sampling capacitor C8 to the corresponding inputs of a pair of single-ended amplifiers 46 and 47 during the second part P2 of the switching cycle.

[0031] In one embodiment, the third switchable capacitor configuration includes a switch S 11 S 15 ,like Figure 4 As shown, switch S 11 S 15 Suitable for sampling the output signal from quantizer 48 during the first part P1 of the switching cycle using a pair of common-mode feedback capacitors C6 and C7. Switch S 21 S 25 It is suitable to connect the output from quantizer 48, sampled by a pair of common-mode feedback capacitors C6, C7, to the corresponding inputs of a pair of single-ended amplifiers 46, 47 during the second part P2 of the switching cycle.

[0032] In one embodiment, the differential Δ-Σ modulator further includes a quantizer 48 (operating as a comparator) that compares the outputs from a pair of single-ended amplifiers 46 and 47 and outputs a logic level based on the comparison. In the first part P1 of the switching cycle, two capacitors C6 and C7 ( Figure 4 and Figure 5a The output signal from quantizer 48 is sampled. In the second part P2 of the switching cycle, the first switchable capacitor configuration 31 connects a pair of capacitors C6, C7 to the corresponding inputs of a pair of single-ended amplifiers 46, 47.

[0033] refer to Figure 4 A differential Δ-Σ modulator 40 according to an embodiment of the present invention is shown. The differential Δ-Σ modulator 40 has a differential input Vin+ and V in- Following that is a differential integrator 49, marked with a dashed line and based on two single-ended amplifiers 46 and 47.

[0034] The first single-ended amplifier 46 is composed of a first inverting amplifier 41 and a capacitor C1, and the second single-ended amplifier 47 is composed of a second inverting amplifier 42 and a capacitor C2. The outputs from the two single-ended amplifiers 46 and 47 are fed to the input of comparator 43, and the single-ended output of comparator 43 is received at the D input of flip-flop 44. Comparator 43 and flip-flop 44 together constitute quantizer 48. The Q output from flip-flop 44 provides the output 45 of the Δ-Σ modulator. The Q output and the inverted Q output from flip-flop 44 are fed back to the inputs of the corresponding single-ended amplifiers 46 and 47 via corresponding feedback paths.

[0035] exist Figure 4 In the illustrated embodiment, the differential Δ-Σ modulator 40 according to the present invention includes a plurality of switches S 11 -S 17 and S 21 -S 27 Switch S 11 -S 17 and S 21 -S 27 Operates at the sampling frequency. The sampling period consists of two non-overlapping time intervals labeled P1 and P2. Switch S 11 -S 17 It is enabled (closed) during period P1 and subsequently disabled (opened) during period P2. Switch S 21 -S 27 It is deactivated (disconnected) in the P1 period and then activated (closed) in the P2 period.

[0036] Switches S11 and S15 belong to the feedback loop of the differential Δ-Σ modulator 40. Two single-ended amplifiers 46 and 47, and switch S... 12 -S 14 S 16 -S 17 and S 21 -S 27 The capacitors C3-C8 together form the integrator 49 of the differential Δ-Σ modulator 40.

[0037] Because the switch S is in time period P1 11 -S 17 Close the switch S 21 -S 27 When disconnected, capacitors C3 and C5 sample the output voltages of the two single-ended amplifiers 41 and 42 during time period P1 (e.g., Figure 5a(As shown). During time period P2, the two capacitors C3 and C5 are switched by switch S. 26 and S 27 This connection results in capacitor C4 being charged by the average voltage provided by capacitors C3 and C5 during period P2. The average voltage represents the common-mode voltage. The switching capacitor's function of charging another capacitor is equivalent to a low-pass filter. The low-pass filtered common-mode voltage is fed back to the inputs of amplifiers 41 and 42 via two sampling capacitors C6 and C7 (e.g., ...). Figure 5b (As shown).

[0038] At differential input V in+ and V in- The signal present above is sampled by capacitor C8 during time period P1 (e.g. Figure 5a As shown), and during the P2 period, it is fed as input to two single-ended amplifiers 46 and 47 (as shown). Figure 5b (As shown).

[0039] The proposed solution boasts very high power efficiency. It operates multiple switches S. 11 -S 17 and S 21 -S 27 The power consumption is practically negligible. Another significant advantage of the common-mode feedback circuit is that the switched capacitor noise of the second switchable capacitor configuration 32 only increases the common-mode noise and not the differential noise. This is important for the performance of the differential Δ-Σ modulator 40 using two single-ended amplifiers 46 and 47. The common-mode voltage gain is close to 1.

[0040] Figure 4 The illustration shows a first-order Δ-Σ modulator 40 according to an embodiment of the invention and used as an analog-to-digital converter. The differential integrator 49 has two inputs, one of which is a differential input V from the Δ-Σ modulator 40. in+ and V in- Another feedback comes from trigger 44 or quantizer 48.

[0041] To control the common-mode DC of the two single-ended amplifiers 46 and 47, feedback common-mode is required via at least one of the two integrator inputs 30. Capacitor C8 is used to pave the circuit at the two integrator inputs 30 (V... in+ and V in- The differential input voltage received at point () is sampled. The differential input voltage is independent of ground. Common-mode feedback enters via sampling caps C6 and C7.

[0042] The concept of this invention is generally applicable to any Δ-Σ analog-to-digital converter. For most high-performance converters, it is desirable to implement them differentially, which is why the power-saving solution of implementing the integrator as a simple single-ended amplifier according to the invention is very attractive.

[0043] Compared to a single-ended configuration, a differential Δ-Σ converter or modulator using a simple single-ended amplifier in the integrator stage will increase the dynamic range for the same power usage and make the converter more tolerant of noise from other circuitry on the same chip. The converter will also emit less noise to other circuitry.

[0044] exist Figure 6 In one embodiment of the invention shown, a differential Δ-Σ modulator 40, comprising an integrator 49 including a pair of single-ended amplifiers 46, 47, is included in a hearing aid device 60, such as a hearing aid. The Δ-Σ modulator 40 receives a differential signal directly from a microphone 61 having a differential output 62. The Δ-Σ modulator 40 transmits the output signal to a digital signal processor (DSP) 63 for processing the digital signal, so that the audio signal output by the hearing aid device 60 via a receiver or speaker 64 is modulated and amplified at frequencies within those portions of the audible frequency range of the user's hearing impairment.

Claims

1. A differential Δ-Σ modulator having an integrator (49) including a pair of single-ended amplifiers (46, 47), and the differential Δ-Σ modulator comprising: A sampling clock (50) drives a first switchable capacitor configuration (31) and a second switchable capacitor configuration (32) with a predetermined switching cycle; The second switchable capacitor configuration (32) is suitable for: In the first part (P1) of the switching cycle, the corresponding outputs from the pair of single-ended amplifiers (46, 47) are sampled on a pair of output sampling capacitors (C3, C5); and In the second part (P2) of the switching cycle, the common-mode capacitor (C4) is charged using the average voltage of the voltages sampled by the pair of output sampling capacitors (C3, C5); in The voltage across the common-mode capacitor (C4) represents the common-mode voltage used for the integrator (49); The quantizer (48) is adapted to compare the outputs from the pair of single-ended amplifiers (46, 47) and output a logic level according to the comparison; The first switchable capacitor configuration (31) is adapted in the first part of the switching cycle to sample the output signal from the quantizer (48) by means of a pair of common-mode feedback capacitors (C6, C7) in the first part (P1) of the switching cycle; and In the second part (P2) of the switching cycle, the pair of common-mode feedback capacitors (C6, C7) are connected to the corresponding inputs of the pair of single-ended amplifiers (46, 47).

2. The differential Δ-Σ modulator according to claim 1, wherein the second switchable capacitor configuration (32) is adapted during the second portion (P2) of the switching cycle to provide a feedback path to the respective inputs of the pair of single-ended amplifiers (46, 47) via a pair of common-mode feedback capacitors (C6, C7).

3. The differential Δ-Σ modulator according to claim 1, wherein the first switchable capacitor configuration (31) is adapted to: During the first part (P1) of the switching cycle, the input from a pair of differential input terminals (30) is sampled by means of an input sampling capacitor (C8); and During the second part (P2) of the switching cycle, the sampled input from the input sampling capacitor (C8) is transmitted to the corresponding input of the pair of single-ended amplifiers (46, 47).

4. The differential Δ-Σ modulator according to claim 3, wherein the second switchable capacitor configuration (32) in the second part (P2) of the switching cycle is adapted to provide a feedthrough path for the sampled input on the input sampling capacitor (C8) to the respective inputs of the pair of single-ended amplifiers (46, 47).

5. The differential Δ-Σ modulator according to claim 1, wherein the sampling clock (50) drive of the first switchable capacitor configuration (31) and the second switchable capacitor configuration (32) is adapted to provide a sampling period consisting of two non-overlapping time periods (P1, P2).

6. A hearing aid device having a microphone (61) providing a differential output (62) and a differential Δ-Σ modulator (40) according to claim 1 for transmitting an output signal for signal processing.

7. A method of operating a differential Δ-Σ modulator having an integrator, the integrator comprising a pair of single-ended amplifiers, and the method comprising: The first switchable capacitor configuration and the second switchable capacitor configuration are driven at a predetermined switching cycle; In the first part of the switching cycle, the corresponding outputs from the pair of single-ended amplifiers are sampled across a pair of output sampling capacitors; In the second part of the switching cycle, the common-mode capacitor is charged with the average voltage of the voltages sampled by the pair of output sampling capacitors, wherein the voltage across the common-mode capacitor represents the common-mode voltage used for the integrator; Compare the outputs from the pair of single-ended amplifiers and output a logic level based on the comparison; as well as In the first part of the switching cycle, the output signal from the quantizer is sampled by means of a pair of common-mode feedback capacitors; Furthermore, in the second part of the switching cycle, the pair of common-mode feedback capacitors are connected to the respective inputs of the pair of single-ended amplifiers.

8. The method of claim 7, further comprising: In the second part of the switching cycle, a feedback path is provided to the respective inputs of the pair of single-ended amplifiers via a pair of common-mode feedback capacitors.

9. The method of claim 7, further comprising, in a first portion of the switching cycle, sampling an input from a pair of differential input terminals on an input sampling capacitor; and in a second portion of the switching cycle, transmitting the sampled input from the input sampling capacitor to a corresponding input of the pair of single-ended amplifiers.

10. The method of claim 9, further comprising, in a second portion of the switching cycle, providing a feedthrough path for the sampled input on the input sampling capacitor to a corresponding input of the pair of single-ended amplifiers.

11. The method of claim 7, wherein the sampling period drive of the first switchable capacitor configuration and the second switchable capacitor configuration consists of two non-overlapping time periods.

12. A differential Δ-Σ modulator, the differential Δ-Σ modulator having two differential input terminals (30), and the differential Δ-Σ modulator further comprising: An integrator (49) comprising a pair of single-ended amplifiers (46, 47); A first switchable capacitor configuration (31) is provided between the two differential input terminals (30) and the inputs of the pair of single-ended amplifiers (46, 47); A second switchable capacitor configuration (32) is provided between the input and output of a corresponding pair of single-ended amplifiers (46, 47); as well as A sampling clock (50) is used to drive the first switchable capacitor configuration (31) and the second switchable capacitor configuration (32) at a predetermined switching period; A quantizer (48) compares the outputs from the pair of single-ended amplifiers (46, 47) and outputs a logic level based on the comparison; in A pair of common-mode feedback capacitors (C6, C7) samples the output signal from the quantizer (48) in the first part (P1) of the switching cycle, and wherein the first switchable capacitor configuration (31) connects the pair of common-mode feedback capacitors (C6, C7) to the respective inputs of the pair of single-ended amplifiers (46, 47) in the second part (P2) of the switching cycle.

13. The differential Δ-Σ modulator according to claim 12, wherein the second switchable capacitor configuration (32) samples the output from the pair of single-ended amplifiers (46, 47) by means of a pair of output sampling capacitors (C3, C5) in the first part (P1) of the switching cycle.

14. The differential Δ-Σ modulator according to claim 13, wherein the second switchable capacitor configuration (32) is adapted in the second part (P2) of the switching cycle to charge a common-mode capacitor (C4) that is charged with the average value of the voltage sampled by the pair of output sampling capacitors (C3, C5), wherein the voltage across the common-mode capacitor (C4) represents the common-mode voltage for the integrator (49).

15. The differential Δ-Σ modulator of claim 14, wherein the second switchable capacitor configuration (32) further provides a feedback path to the respective inputs of the pair of single-ended amplifiers (46, 47) via a pair of common-mode feedback capacitors (C6, C7) in the second portion (P2) of the switching cycle.

16. The differential Δ-Σ modulator according to claim 12, wherein the first switchable capacitor configuration (31) samples the input from the pair of differential input terminals (30) by means of an input sampling capacitor (C8) in the first part (P1) of the switching cycle.

17. The differential Δ-Σ modulator of claim 16, wherein the first switchable capacitor configuration (31) provides a feedthrough path for the sampled input value on the input sampling capacitor (C8) to the respective inputs of the pair of single-ended amplifiers (46, 47) in the second part (P2) of the switching cycle.

18. The differential Δ-Σ modulator of claim 12, wherein the sampling clock (50) provides a sampling period consisting of two non-overlapping time periods (P1, P2).

19. A hearing aid device having a microphone (61) providing a differential output (62) and a differential Δ-Σ modulator (40) according to claim 12 for transmitting an output signal for signal processing.

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