Scan driver and display device including the same

Abstract

The present application provides a scan driver and a display device including the same. The scan driver of the display device includes a driving circuit and a shielding circuit. The driving circuit includes a control part, a first output part, and a second output part. The control part outputs a first control signal and a second control signal in response to a clock signal and a carry signal. The first output part is connected to a first output terminal outputting a first scan signal and a first voltage terminal supplied with a first voltage, and operates in response to the first control signal. The second output part is connected to the first output terminal and a second voltage terminal supplied with a second voltage, and operates in response to the second control signal. The shielding circuit receives the first and second control signals, outputs a second scan signal to the second output terminal in response to the first and second control signals, and is connected to an input terminal supplied with a shielding signal to control a voltage level of the second scan signal according to the shielding signal.

Description

Technical Field

[0001] The present invention relates to a scan driver and a display device including the same, and more particularly to a scan driver capable of reducing power consumption and a display device including the scan driver. Background Technology

[0002] Organic light-emitting diodes (OLEDs) in display devices use organic light-emitting diodes (OLEDs) to generate light through the recombination of electrons and holes to display images. These OLEDs offer the advantages of fast response times and low power consumption.

[0003] The display device includes a display panel for displaying images, a scan driver for sequentially supplying scan signals to scan lines provided in the display panel, and a data driver for supplying data signals to data lines provided in the display panel.

[0004] In particular, the scan driver may include multiple stages that output scan signals to corresponding scan lines in synchronization with a predetermined clock. The scan driver repeats the operation of outputting scan signals sequentially from the first stage to the last stage for each frame at the same period. Summary of the Invention

[0005] The purpose of this invention is to provide a scan driver that can reduce power consumption and a display device including the same.

[0006] A scan driver according to a feature of the present invention includes a drive circuit and a shielding circuit. The drive circuit includes a control unit, a first output unit, and a second output unit. The control unit outputs a first control signal and a second control signal in response to a clock signal and a carry signal. The first output unit is connected to a first output terminal that outputs a first scan signal and a first voltage terminal that is supplied with a first voltage, and operates in response to the first control signal. The second output unit is connected to the first output terminal and a second voltage terminal that is supplied with a second voltage, and operates in response to the second control signal. The shielding circuit receives the first and second control signals, outputs a second scan signal to the second output terminal in response to the first and second control signals, and is connected to an input terminal that is supplied with a shielding signal to control the voltage level of the second scan signal according to the shielding signal.

[0007] A display device according to a feature of the present invention includes: a display panel including: a plurality of pixels respectively connected to a plurality of data lines, a plurality of compensation scan lines and a plurality of initialization scan lines; a data driver for driving the plurality of data lines; a scan driver for driving the plurality of compensation scan lines and the plurality of initialization scan lines; and a drive controller for controlling the data driver and the scan driver to display an image in the display panel.

[0008] The scan driver includes a drive stage that outputs a compensation scan signal to the corresponding compensation scan line in the compensation scan lines and an initialization scan signal to the corresponding initialization scan line in the initialization scan lines.

[0009] The drive stage includes a drive circuit and a shielding circuit. The drive circuit includes a control unit, a first output unit, and a second output unit. The control unit outputs a first control signal and a second control signal in response to a clock signal and a carry signal. The first output unit is connected to a first output terminal that outputs a first scan signal and a first voltage terminal that is supplied with a first voltage, and operates in response to the first control signal. The second output unit is connected to the first output terminal and a second voltage terminal that is supplied with a second voltage, and operates in response to the second control signal. The shielding circuit receives the first and second control signals, outputs a second scan signal to the second output terminal in response to the first and second control signals, and is connected to the input terminal that is supplied with a shielding signal to control the voltage level of the second scan signal according to the shielding signal.

[0010] (Invention Effects)

[0011] The display device according to the present invention can output a stable level scanning signal even if it includes a shielding circuit for shielding the output of the scanning signal.

[0012] In addition, since shielding circuits for shielding the output of the scanning signal are added to each driver stage, the size of the output section of each driver stage can be prevented from increasing. Attached Figure Description

[0013] Figure 1A This is a perspective view of a display device according to an embodiment of the present invention.

[0014] Figure 1B This is an exploded perspective view of a display device according to an embodiment of the present invention.

[0015] Figure 1C as well as Figure 1D It is along Figure 1B The cross-sectional view of the display device cut by the cutting line I-I' is shown.

[0016] Figure 2A This is a plan view showing a display device operating in normal frequency mode according to an embodiment of the present invention.

[0017] Figure 2B This is a plan view showing a display device operating in multi-frequency mode according to an embodiment of the present invention.

[0018] Figure 3A This is a diagram illustrating the operation of a display device in normal frequency mode according to an embodiment of the present invention.

[0019] Figure 3B This is a diagram illustrating the operation of a display device in multi-frequency mode according to an embodiment of the present invention.

[0020] Figure 4 This is a block diagram of a display device according to an embodiment of the present invention.

[0021] Figure 5 This is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0022] Figure 6A This is a block diagram of a scan driver according to an embodiment of the present invention.

[0023] Figure 6B This is a waveform diagram showing the initial scan signal and the compensation scan signal output from the scan driver in normal frequency mode and multi-frequency mode.

[0024] Figure 7A This is a circuit diagram illustrating the k-th driver stage in a driver stage according to an embodiment of the present invention.

[0025] Figures 7B to 7D It is shown Figure 7A The waveforms of the shielding signal, the first and second clock signals, the initialization scan signal, and the compensation scan signal are shown.

[0026] Figure 8A This is a circuit diagram illustrating the k-th driver stage in a driver stage according to an embodiment of the present invention.

[0027] Figure 8B It is shown Figure 8A The waveforms of the shielding signal, the first and second clock signals, the initialization scan signal, and the compensation scan signal are shown.

[0028] Figure 9 This is a circuit diagram illustrating the k-th driver stage in a driver stage according to an embodiment of the present invention.

[0029] Figure 10A This is a block diagram of a scan driver according to an embodiment of the present invention.

[0030] Figure 10B This is a waveform diagram showing the initial scan signal and the compensation scan signal output from the scan driver in normal frequency mode and multi-frequency mode.

[0031] Figure 11 This is a block diagram of a scan driver according to an embodiment of the present invention.

[0032] Figure 12A as well as Figure 12BThis is a perspective view of a display device according to an embodiment of the present invention.

[0033] (Explanation of reference numerals in the attached diagram)

[0034] DD: Display device; DP: Display panel

[0035] 300, 301, 302: Scan driver; DA: Display area

[0036] DA1: First display area; DA2: Second display area

[0037] MC: Shielding circuit; DC: Drive circuit

[0038] CC: Control Unit; OC1: First Output Unit

[0039] OC2: Second output section; MSC1: First shielding circuit

[0040] MSC2: Second shielding circuit; CS1: First control signal

[0041] CS2: Second control signal; MS, MS_a: Shielding signal Detailed Implementation

[0042] In this specification, when a constituent element (or region, layer, part, etc.) is referred to as being "on", "connected to", or "integrated with" another constituent element, it means that the constituent element can be directly configured / connected / integrated on the other constituent element, or that a third constituent element can be configured between them.

[0043] The same reference numerals refer to the same constituent elements. Furthermore, in the drawings, the thickness, scale, and dimensions of the constituent elements are enlarged for the purpose of effectively illustrating the technical content. "And / or" includes all combinations of the relevant constituent elements that can be defined.

[0044] The terms "first," "second," etc., can be used to describe multiple constituent elements, but the constituent elements described above are not limited by these terms. These terms are used only to distinguish one constituent element from another. For example, without departing from the scope of the invention, a first constituent element may be named a second constituent element, and similarly, a second constituent element may be named a first constituent element. Singular expressions include plural expressions unless explicitly stated otherwise in the context.

[0045] In addition, terms such as "below," "lower side," "above," and "upper side" are used to describe the relational relationships of the components shown in the accompanying drawings. These terms are relative concepts and are explained based on the directions indicated in the accompanying drawings.

[0046] Terms such as “including” or “having” should be understood as indicating the presence of features, numbers, steps, operations, constituent elements, components, or combinations thereof as described in the specification, and do not preclude the existence or additional possibilities of one or more other features, numbers, steps, operations, constituent elements, components, or combinations thereof.

[0047] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms such as those defined in commonly used dictionaries shall be interpreted as having the same meaning in the context of the relevant art, provided they are not interpreted as having an ideal or overly formal meaning, and are expressly defined herein.

[0048] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0049] Figure 1A This is a perspective view of a display device according to an embodiment of the present invention. Figure 1B This is an exploded perspective view of a display device according to an embodiment of the present invention. Figure 1C as well as Figure 1D It is along Figure 1B The cross-sectional view of the display device cut by the cutting line I-I' is shown.

[0050] Reference Figure 1A as well as Figure 1B The display device DD can be a device activated by an electrical signal. The display device DD can be used in electronic devices such as smartwatches, tablets, laptops, computers, and smart TVs.

[0051] The display device DD can display an image IM facing a third direction DR3 from each of the display surfaces IS parallel to the first direction DR1 and the second direction DR2. The display surface IS displaying the image IM can correspond to the front surface of the display device DD. The image IM can include not only moving images but also still images.

[0052] In this embodiment, the front (or top) and back (or bottom) of each component are defined based on the direction in which the image IM is displayed. The front and back may be opposite each other on a third-party direction DR3, with the normal direction of each front and back parallel to the third-party direction DR3.

[0053] The spacing between the front and back sides on the third-direction DR3 can correspond to the thickness of the display device DD on the third-direction DR3. On the other hand, the directions indicated by the first to third-direction DR1, DR2, DR3 can be converted to other directions as a relative concept.

[0054] The display device DD can sense external input applied from the outside. External input can include various forms of input provided from outside the display device DD. For example, external input can include not only contact caused by a part of the user's body such as a hand, but also external input applied when the user is close to or adjacent to the display device DD at a predetermined distance (e.g., hovering). In addition, external input can take various forms such as force, pressure, temperature, light, etc.

[0055] The display surface IS of the display device DD can be divided into a transmissive area TA and a border area BZA. The transmissive area TA can be the area where the image IM is displayed. The user identifies the image IM through the transmissive area TA. In this embodiment, the transmissive area TA is shown as a rectangular shape with a circled vertex. However, this is shown by way of example, and the transmissive area TA can have various shapes and is not limited to a particular embodiment.

[0056] The border region BZA is adjacent to the transmissive region TA. The border region BZA may have a predetermined color. The border region BZA may surround the transmissive region TA. Thus, the shape of the transmissive region TA can be substantially defined by the border region BZA. However, this is shown by way of example, and the border region BZA may also be configured to be adjacent to only one side of the transmissive region TA, or it may be omitted. The display device DD according to an embodiment of the present invention may include various embodiments and is not limited to one particular embodiment.

[0057] like Figure 1B As shown, the display device DD may include a display module DM and a window WM disposed on the display module DM. The display module DM may include a display panel DP and an input sensor ISP.

[0058] According to an embodiment of the present invention, the display panel DP can be a light-emitting display panel, and is not particularly limited. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel can contain organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel can include quantum dots and quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0059] Reference Figure 1C The input sensor ISP can be directly disposed on the display panel DP. According to one embodiment of the present invention, the input sensor ISP can be formed on the display panel DP through a continuous process. That is, when the input sensor ISP is directly disposed on the display panel DP, the adhesive film is not disposed between the input sensor ISP and the display panel DP. However, as... Figure 1DAs shown, an internal adhesive film I_AF can be configured between the input sensor ISP and the display panel DP. In this case, the input sensor ISP is not manufactured using a process continuous with the display panel DP, but rather using a separate process from the display panel DP, and then fixed to the display panel DP using the internal adhesive film I_AF.

[0060] The display panel (DP) generates an image, which is then input to the sensor (ISP) to obtain external coordinate information.

[0061] The window WM can be made of a transparent material capable of projecting an image IM. For example, it can be made of glass, sapphire, plastic, etc. Although the window WM is shown as a single layer, it is not limited to this and can include multiple layers. On the other hand, although not shown, the border area BZA of the aforementioned display device DD can substantially be provided as an area in which a material including a predetermined color is printed in a region of the window WM. As an example of the present invention, the window WM may include a light-shielding pattern WBM for defining the border area BZA. The light-shielding pattern WBM is a colored organic film, for example, formed by coating.

[0062] The window WM can be bonded to the display module DM via an adhesive film AF. As an example of the present invention, the adhesive film AF may include an optically clear adhesive film (OCA). However, the adhesive film AF is not limited to this and may include conventional adhesives or tackifiers. For example, the adhesive film AF may include an optically clear resin (OCR) or a pressure-sensitive adhesive film (PSA).

[0063] A reflection-preventing layer may also be disposed between the window WM and the display module DM. The reflection-preventing layer reduces the reflectivity of external light incident from the upper side of the window WM. According to an embodiment of the present invention, the reflection-preventing layer may include a phase retarder and a polarizer. The phase retarder may be a film-type or a liquid crystal coated type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film-type or a liquid crystal coated type. For example, the film-type may comprise a stretched synthetic resin film, and the liquid crystal coated type may comprise liquid crystals arranged in a predetermined pattern. The phase retarder and the polarizer may be implemented by a single polarizing film.

[0064] It is possible that the display module DM displays the image IM based on electrical signals and sends / receives information for external input. The display module DM can be defined as a display area DA and a non-display area NDA. The display area DA can be defined as the area from which the emitted image IM is emitted.

[0065] The non-display area NDA is adjacent to the display area DA. For example, the non-display area NDA may surround the display area DA. However, the non-display area NDA can be defined in various shapes and is not limited to a particular embodiment. According to one embodiment, the display area DA of the display module DM may correspond to at least a portion of the transmissive area TA.

[0066] The display module DM may also include a main circuit board (MCB), a flexible circuit film (FCB), and a driver chip (DIC). The main circuit board (MCB) can be connected to the flexible circuit film (FCB) and electrically connected to the display panel (DP). The main circuit board (MCB) may include multiple driving elements. The multiple driving elements may include circuitry for driving the display panel (DP). The flexible circuit film (FCB) is connected to the display panel (DP) and electrically connects the display panel (DP) and the main circuit board (MCB). The driver chip (DIC) may be mounted on the flexible circuit film (FCB).

[0067] The driver chip DIC may include driving elements for driving the pixels of the display panel DP, such as data driving circuitry. A flexible circuit film FCB according to an embodiment of the invention is shown as a single unit, but is not limited thereto; multiple units may be provided and connected to the display panel DP. Figure 1B The diagram illustrates a structure where the driver chip DIC is mounted on a flexible circuit film FCB, but the invention is not limited thereto. For example, the driver chip DIC can be directly mounted on the display panel DP. In this case, the portion of the display panel DP with the driver chip DIC mounted can be bent and positioned behind the display module DM.

[0068] The input sensor ISP can be electrically connected to the main circuit board MCB via a flexible circuit film FCB. However, embodiments of the present invention are not limited thereto. That is, the display module DM may further include a separate flexible circuit film for electrically connecting the input sensor ISP to the main circuit board MCB.

[0069] The display device DD also includes a housing EDC that houses the display module DM. The housing EDC can be combined with the window WM to define the appearance of the display device DD. The housing EDC protects the components housed within it by absorbing impacts from the outside and preventing foreign matter / moisture from penetrating into the display module DM. On the other hand, as an example of the present invention, the housing EDC can be provided in the form of incorporating multiple housing components.

[0070] According to one embodiment, the display device DD may further include: an electronic module including various functional modules for enabling the display module DM to operate; a power supply module for supplying power required for the overall operation of the display device DD; and a bracket that is combined with the display module DM and / or the housing EDC to divide the internal space of the display device DD, etc.

[0071] Figure 2A This is a plan view showing the screen of a display device operating in normal frequency mode. Figure 2B It is a plan view showing the screen of a display device operating in multi-frequency mode. Figure 3A This diagram illustrates the operation of a display device in normal frequency mode. Figure 3B This diagram illustrates the operation of a display device in multi-frequency mode.

[0072] Reference Figures 2A to 3B The display device DD can display images in either Normal Frequency Mode (NFM) or Multi-Frequency Mode (MFM). In Normal Frequency Mode (NFM), the display area DA of the display device DD is not divided into multiple display areas with different driving frequencies. That is, in Normal Frequency Mode (NFM), the display area DA operates at a single driving frequency, which can be defined as the normal frequency. For example, the normal frequency could be 60Hz. In Normal Frequency Mode (NFM), 60 images corresponding to frames F1 to F60 can be displayed in the display area DA of the display device DD within one second (1 sec).

[0073] In a multi-frequency mode MFM, the display area DA of the display device DD is divided into multiple display areas with different driving frequencies. As an example of the present invention, in a multi-frequency mode MFM, the display area DA may include a first display area DA1 and a second display area DA2. The first and second display areas DA1 and DA2 are arranged adjacent to each other in a first direction DR1. The driving frequency of the first display area DA1 can be a frequency higher than or equal to the normal frequency, and the driving frequency of the second display area DA2 can be a frequency lower than the normal frequency. For example, when the normal frequency is 60Hz, the driving frequency of the first display area DA1 can be 60Hz, 80Hz, 90Hz, 100Hz, 120Hz, etc., and the driving frequency of the second display area DA2 can be 1Hz, 20Hz, 30Hz, 40Hz, etc.

[0074] As an example of the present invention, the first display area DA1 may be an area displaying dynamic images that require high-speed driving (hereinafter referred to as the first image IM1), and the second display area DA2 may be an area displaying static images that do not require high-speed driving or text images with long change cycles (hereinafter referred to as the second image IM2). Therefore, when static images and dynamic images are displayed simultaneously on the screen of the display device DD, by making the display device DD operate in multi-frequency mode (MFM), the display quality of dynamic images can be improved while reducing overall power consumption.

[0075] Reference Figure 3A as well as Figure 3BIn multi-frequency mode (MFM), an image can be displayed in the display area DA of the display device DD during multiple driving frames (DF). Each driving frame (DF) may include a full frame (FF) where both the first display area DA1 and the second display area DA2 are driven, and a partial frame where only the first display area DA1 is driven. Each partial frame may have a shorter duration than the full frame (FF). The number of partial frames included in each driving frame (DF) may be the same or different. Each driving frame (DF) can be defined as the period from the start of the current full frame (FF) to the start of the next full frame (FF).

[0076] As an example of the present invention, during each driving frame DF, the first display area DA1 operates at 100Hz and the second display area DA2 operates at 1Hz. In this case, each driving frame DF may have a duration corresponding to 1 second (1 sec) and includes a full frame FF and 99 partial frames HF1 to HF99. Alternatively, during each driving frame DF, 100 first images IM1 corresponding to the full frame FF and the 99 partial frames HF1 to HF99 are displayed in the first display area DA1 of the display device DD, and a second image IM2 corresponding to the full frame FF is displayed in the second display area DA2.

[0077] exist Figure 3B For ease of explanation, as an example, a case is shown where the driving frequency of the first display area DA1 in the multi-frequency mode MFM is 100Hz and the driving frequency of the second display area DA2 is 1Hz, but the present invention is not limited to this. For example, the driving frequency of the first display area DA1 can be 100Hz, and the driving frequency of the second display area DA2 can be 20Hz. In this case, during each driving frame DF, five first images IM1 corresponding to a full frame FF and four partial frames are displayed in the first display area DA1 of the display device DD, and one second image IM2 corresponding to the full frame FF is displayed in the second display area DA2. Alternatively, the driving frequency of the first display area DA1 can be 90Hz, and the driving frequency of the second display area DA2 can be 30Hz. In this case, during each driving frame DF, three first images IM1 corresponding to a full frame FF and two partial frames are displayed in the first display area DA1 of the display device DD, and one second image IM2 corresponding to the full frame FF is displayed in the second display area DA2.

[0078] Figure 4 This is a block diagram of a display device according to an embodiment of the present invention. Figure 5 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0079] Reference Figure 4 as well as Figure 5 The display device DD includes a display panel DP, a panel driver, and a drive controller 100. As an example of the present invention, the panel driver includes a data driver 200, a scan driver 300, a light-emitting driver 350, and a voltage generator 400.

[0080] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 generates an image data signal DATA that converts the RGB data format to match the interface specifications of the data driver 200. The drive controller 100 outputs a scan control signal SCS and a data control signal DCS.

[0081] The data driver 200 receives a data control signal DCS and an image data signal DATA from the drive controller 100. The data driver 200 converts the image data signal DATA into a data signal and outputs the data signal to the plurality of data lines DL1-DLm described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0082] The scan driver 300 receives a scan control signal SCS from the drive controller 100. The scan driver 300 can output a scan signal to the scan line in response to the scan control signal SCS.

[0083] Voltage generator 400 generates the voltages required for the operation of display panel DP. In this embodiment, voltage generator 400 generates a first drive voltage ELVDD, a second drive voltage ELVSS, and an initialization voltage VINT.

[0084] The display panel DP includes initialization scan lines SIL1~SILn, compensation scan lines SCL1~SCLn, write scan lines SWL1~SWLn+1, light emission control lines EML1~EMLn, data lines DL1~DLm, and pixels PX. The initialization scan lines SIL1~SILn, compensation scan lines SCL1~SCLn, write scan lines SWL1~SWLn+1, light emission control lines EML1~EMLn, data lines DL1~DLm, and pixels PX can overlap with the display area DA. The initialization scan lines SIL1~SILn, compensation scan lines SCL1~SCLn, write scan lines SWL1~SWLn+1, and light emission control lines EML1~EMLn extend in the second direction DR2. The initialization scan lines SIL1~SILn, compensation scan lines SCL1~SCLn, write scan lines SWL1~SWLn+1, and light emission control lines EML1~EMLn are arranged spaced apart from each other in the first direction DR1. The data lines DL1 to DLm extend in the first direction DR1 and are arranged apart from each other in the second direction DR2.

[0085] Multiple pixels (PX) are electrically connected to the initialization scan lines SIL1-SILn, the compensation scan lines SCL1-SCLn, the write scan lines SWL1-SWLn+1, the emission control lines EML1-EMLn, and the data lines DL1-DLm. Each pixel (PX) can be electrically connected to three scan lines. For example, ... Figure 4 As shown, the pixels PX in the first row can be connected to the first initialization scan line SIL1, the first compensation scan line SCL1, and the first write scan line SWL1. Similarly, the pixels PX in the second row can be connected to the second initialization scan line SIL2, the second compensation scan line SCL2, and the second write scan line SWL2.

[0086] The scan driver 300 can be configured in the non-display area NDA of the display panel DP. The scan driver 300 receives a scan control signal SCS from the drive controller 100. Specifically, in response to the scan control signal SCS, the scan driver 300 outputs initialization scan signals to the initialization scan lines SIL1 to SILn, compensation scan signals to the compensation scan lines SCL1 to SCLn, and write scan signals to the write scan lines SWL1 to SWLn+1. The circuit configuration and operation of the scan driver 300 will be described in detail later.

[0087] The light-emitting driver 350 can output light-emitting control signals to the light-emitting control lines EML1 to EMLn. In another embodiment, the scan driver 300 can be connected to the light-emitting control lines EML1 to EMLn. In this case, the scan driver 300 can output light-emitting control signals to the light-emitting control lines EML1 to EMLn.

[0088] Each of the plurality of pixels PX includes a light-emitting diode ED and a pixel circuit section PXC for controlling the light emission of the light-emitting diode ED. The pixel circuit section PXC may include a plurality of transistors and capacitors. The scan driver 300 may include transistors formed using the same process as the pixel circuit section PXC.

[0089] Each of the multiple pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT from the voltage generator 400.

[0090] Figure 5 An example is shown in Figure 4The equivalent circuit diagram of pixel PXij among multiple pixels is shown. Since each of the multiple pixels has the same circuit structure, the circuit structure of pixel PXij will be described, and the specific description of the other pixels will be omitted. Pixel PXij is connected to the i-th data line DL1 to DLm (hereinafter referred to as the data line), the j-th initialization scan line SILj (hereinafter referred to as the initialization scan line) among the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj (hereinafter referred to as the compensation scan line) among the compensation scan lines SCL1 to SCLn, the j-th and j+1 write scan lines SWLj and SWLj+1 (hereinafter referred to as the first and second write scan lines) among the write scan lines SWL1 to SWLn+1, and the j-th light emission control line EMLj (hereinafter referred to as the light emission control line) among the light emission control lines EML1 to EMLn.

[0091] Pixel PXij includes a light-emitting diode (ED) and a pixel circuit section PXC. The pixel circuit section PXC includes first to seventh transistors T1 to T7 and a capacitor Cst. Each of the first to seventh transistors T1 to T7 can be a transistor having an LTPS (low-temperature polycrystalline silicon) semiconductor layer. A portion of the first to seventh transistors T1 to T7 can be P-type transistors, and the remainder can be N-type transistors. For example, the first, second, and fifth to seventh transistors T1, T2, and T5 to T7 can be P-type transistors, and the third and fourth transistors T3 and T4 can be N-type transistors with oxide semiconductor as the semiconductor layer. In one embodiment, at least one of the first to seventh transistors T1 to T7 can be an N-type transistor, and the rest can be P-type transistors. The configuration of the pixel circuit section PXC according to the present invention is not limited to... Figure 5 The example shown. Figure 5 The pixel circuit section PXC shown is only an example, and its configuration can be implemented by modification. For example, the first to seventh transistors T1 to T7 can all be P-type transistors or N-type transistors.

[0092] The initialization scan line SILj, the compensation scan line SCLj, the first and second write scan lines SWLj, SWLj+1, and the light emission control line EMLj can respectively transmit the j-th initialization scan signal SIj (hereinafter referred to as the initialization scan signal), the j-th compensation scan signal SCj (hereinafter referred to as the compensation scan signal), the j-th and j+1 write scan signals SWj, SWj+1 (hereinafter referred to as the first and second write scan signals), and the j-th light emission control signal EMj (hereinafter referred to as the light emission control signal) to the pixel PXij. The data line DL1 transmits the data signal Di to the pixel PXij. The data signal Di can have the same characteristics as the input to the display device DD (refer to...). Figure 4 The image signal RGB corresponds to the voltage level. The first to third driving voltage lines VL1, VL2, and VL3 can respectively transmit the first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT to the pixel PXij.

[0093] The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via the fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting diode ED via the sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can receive the data signal Di transmitted by the data line DL1 according to the switching operation of the second transistor T2 and supply a driving current Id to the light-emitting diode ED.

[0094] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the first write scan line SWLj. The second transistor T2 can transmit the data signal Di transmitted from the data line DLi to the first electrode of the first transistor T1 when the first write scan signal SWj received through the first write scan line SWLj is turned on.

[0095] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the compensation scan line SCLj. The third transistor T3 can be turned on according to the compensation scan signal SCj received through the compensation scan line SCLj, thereby connecting the gate electrode and the second electrode of the first transistor T1 to each other and causing the first transistor T1 to be diode connected.

[0096] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third voltage line VL3 to which the initialization voltage VINT is transmitted, and a gate electrode connected to the initialization scan line SILj. The fourth transistor T4 can be turned on according to the initialization scan signal SIj received through the initialization scan line SILj, thereby transmitting the initialization voltage VINT to the gate electrode of the first transistor T1 and performing initialization work to initialize the voltage of the gate electrode of the first transistor T1.

[0097] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the light-emitting control line EMLj.

[0098] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting diode ED, and a gate electrode connected to the light-emitting control line EMLj.

[0099] The fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on according to the light emission control signal EMj received through the light emission control line EMLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be transmitted to the light emission diode ED after being compensated by the first transistor T1 connected to the diode.

[0100] The seventh transistor T7 includes a first electrode connected to the second electrode of the fourth transistor T4, a second electrode connected to the second electrode of the sixth transistor T6, and a gate electrode connected to the second write scan line SWLj+1.

[0101] As described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end is connected to the first driving voltage line VL1. The cathode of the light-emitting diode ED can be connected to the second driving voltage line VL2, which transmits the second driving voltage ELVSS.

[0102] When a high-level initialization scan signal SIj is provided through the initialization scan line SILj, the fourth transistor T4 is turned on in response to the high-level initialization scan signal SIj. The initialization voltage VINT is transmitted to the gate electrode of the first transistor T1 through the turned-on fourth transistor T4, and the first transistor T1 is initialized by the initialization voltage VINT.

[0103] Next, when a high-level compensation scan signal SCj is supplied through the compensation scan line SCLj, the third transistor T3 is turned on. The first transistor T1 is connected to the turned-on third transistor T3 by a diode and is forward biased. Meanwhile, the second transistor T2 is turned on by a low-level first write scan signal SWj. Then, a compensation voltage (“Di-Vth”) that reduces the threshold voltage Vth of the first transistor T1 is applied to the gate electrode of the first transistor T1 in the data signal Di supplied from the data line DL1. That is, the potential of the gate electrode of the first transistor T1 can constitute the compensation voltage (“Di-Vth”).

[0104] It is possible that a first driving voltage ELVDD and a compensation voltage (“Di-Vth”) are applied across the capacitor Cst, and the capacitor Cst stores a charge corresponding to the voltage difference across its terminals.

[0105] On the other hand, the seventh transistor T7 is turned on by receiving a low-level second write scan signal SWj+1 through the second write scan line SWLj+1. Through the seventh transistor T7, a portion of the drive current Id can flow out as a bypass current Ibp.

[0106] Even if the minimum current flow of the first transistor T1, which displays a black image, is the drive current Id, the black image cannot be displayed properly if the light-emitting diode ED emits light. Therefore, according to an embodiment of the present invention, the seventh transistor T7 in pixel PXij can divert a portion of the minimum current of the first transistor T1 as a bypass current Ibp to a current path other than the current path on the side of the light-emitting diode ED. Here, the minimum current of the first transistor T1 refers to the current under the condition that the first transistor T1 is turned off because its gate-source voltage is less than the threshold voltage. The minimum drive current (e.g., a current of less than 10 pA) under such a condition that the first transistor T1 is turned off is transmitted to the light-emitting diode ED, resulting in an image with black brightness. It can be considered that when the minimum drive current for displaying a black image flows, the effect of the detour transmission of the bypass current Ibp is large; conversely, when a large drive current flows for displaying a regular image or an image such as a white image, the effect of the bypass current Ibp is almost non-existent. Therefore, when the drive current for displaying a black image flows, the light-emitting current Ied of the light-emitting diode ED is reduced to the extent that the bypass current Ibp flowing out from the drive current Id through the seventh transistor T7, so that the current is minimized to accurately represent the black image. Thus, the seventh transistor T7 can be used to achieve a correct black brightness image and improve contrast.

[0107] Next, the light emission control signal EMj supplied from the light emission control line EMLj changes from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 are turned on by the low-level light emission control signal EMj. Then, a drive current Id is generated based on the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and this drive current Id is supplied to the light emission diode ED through the sixth transistor T6, resulting in a light emission current Ied flowing in the light emission diode ED.

[0108] Figure 6A This is a block diagram of a scan driver according to an embodiment of the present invention. Figure 6B This is a waveform diagram showing the initial scan signal and the compensation scan signal output from the scan driver in normal frequency mode and multi-frequency mode.

[0109] Reference Figure 6A The scan driver 300 includes drive stages ST0 to STn. Each of the drive stages ST0 to STn... Figure 4 The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and a mask signal MS. Each of the drive stages ST0-STn further receives a first voltage VGH and a second voltage VGL. The first voltage VGH and the second voltage VGL can be obtained from... Figure 4 The voltage generator 400 shown is provided.

[0110] The shielding signal MS can be a signal used to shield the scan signal (e.g., the initialization scan signal) supplied to the second display area DA2 to a predetermined level. As an example of the present invention, the shielding signal MS can be provided to each of the drive stages ST0 to STn.

[0111] In one embodiment, each of the drive stages ST0 to STn may have a first output terminal OUT1 that outputs a corresponding compensation scan signal and a second output terminal OUT2 that outputs a corresponding initialization scan signal.

[0112] A corresponding compensation scan line is connected to the first output terminal OUT1 of each of the driver stages ST1 to STn in the driver stages ST0 to STn. The compensation scan signals SC1 to SCn in the compensation scan signals SC0 to SCn are respectively provided to the compensation scan lines SCL1 to SCLn. Specifically, the first output terminal OUT1 of the first driver stage ST1 in the driver stages ST1 to STn is connected to the corresponding first compensation scan line SCL1, thereby supplying the first compensation scan signal SC1 to the first compensation scan line SCL1.

[0113] The second output terminal OUT2 of the driver stages ST0 to STn-1 in the driver stages ST0 to STn-1 can be connected to a corresponding initialization scan line. The initialization scan signals SI1-SIn output from the second output terminal OUT2 of the driver stages ST0 to STn-1 are respectively provided to the initialization scan lines SIL1 to SILn. Specifically, the second output terminal OUT2 of the dummy driver stage ST0 in the driver stages ST0 to STn-1 is connected to the corresponding first initialization scan line SIL1, thereby supplying the first initialization scan signal SI1 to the first initialization scan line SIL1. In addition, the second output terminal OUT2 of the first driver stage ST1 in the driver stages ST0 to STn-1 is connected to the corresponding second initialization scan line SIL2, thereby supplying the second initialization scan signal SI2 to the second initialization scan line SIL2.

[0114] Here, the first to the kth initialization scan lines SIL1 to SILk of the n initialization scan lines SIL1 to SILn are configured in the first display area DA1, and the (k+1)th to the nth initialization scan lines SILk+1 to SILn of the n initialization scan lines SIL1 to SILn are configured in the second display area DA2. Here, n and k are integers greater than or equal to 1, and n is greater than k. The first to the kth compensation scan lines SCL1 to SCLn of the n compensation scan lines SCL1 to SCLn are configured in the first display area DA1, and the (k+1)th to the nth compensation scan lines SCLk+1 to SCLn of the n compensation scan lines SCL1 to SCLn are configured in the second display area DA2.

[0115] Figure 6A Not shown in the middle Figure 4 The write scan lines SWL1 to SWLn+1 are shown. Driver stages ST1 to STn can be connected to the corresponding write scan lines, but the invention is not limited thereto. That is, in addition to driver stages ST1 to STn, the scan driver 300 may also include driver stages for providing write scan signals to write scan lines SWL1 to SWLn+1 respectively.

[0116] The dummy driver ST0 in driver stages ST0 to STn can receive the start signal FLM as a carry signal. Each driver stage ST1 to STn receives a carry signal from the previous driver stage. For example, the first driver stage ST1 receives a carry signal from the dummy driver stage ST0, and the second driver stage ST2 receives a carry signal from the first driver stage ST1. As an example of the present invention, the carry signal input to the first driver stage ST1 can be the first initialization scan signal SI1 output from the dummy driver stage ST0, and the carry signal input to the second driver stage ST2 can be the second initialization scan signal SI2 output from the first driver stage ST1. That is, the first to nth driver stages ST1 to STn in driver stages ST0 to STn can receive the initialization scan signal output from the adjacent previous driver stage as a carry signal. However, the present invention is not limited to this. In one embodiment, driver stages ST1 to STn can receive the initialization scan signal output from any one of the previous driver stages as a carry signal.

[0117] Reference Figure 6A as well as Figure 6B In normal frequency mode NFM, the shielding signal MS remains at the first level (e.g., high level). Here, the first level can be the same as the level of the first voltage VGH.

[0118] In normal frequency mode NFM, during each frame F1, F2, and F3, the scan driver 300 can output sequentially activated compensation scan signals SC1 to SCn and initialization scan signals SI1 to SIn. As an example of the present invention, each of the compensation scan signals SC1 to SCn may have a high level during the activation period and a low level during the deactivation period. Alternatively, each of the initialization scan signals SI1 to SIn may have a high level during the activation period and a low level during the deactivation period. Optionally, each of the compensation scan signals SC1 to SCn may have a low level during the activation period and a high level during the deactivation period. Alternatively, each of the initialization scan signals SI1 to SIn may have a low level during the activation period and a high level during the deactivation period.

[0119] For ease of explanation, the mode in which each of the compensation scan signals SC1-SCn and the initialization scan signals SI1-SIn has a high level during the activation period and a low level during the deactivation period is defined as a normally low mode. Conversely, the mode in which each of the compensation scan signals SC1-SCn and the initialization scan signals SI1-SIn has a low level during the activation period and a high level during the deactivation period is defined as a normally high mode. Hereinafter, Figures 6A to 7DThe explanation is based on the normal low-mode operation. Figure 8A as well as Figure 8B The explanation is based on the operating mode of the constant high-altitude mode.

[0120] In multi-frequency mode MFM, the driving frame DF includes the full frame FF and some frames HF1 and HF2. Figure 6B Only two partial frames, HF1 and HF2, included in the driving frame DF are shown. However, the number of partial frames HF1 and HF2 included in the driving frame DF can vary depending on the driving frequency of the first display area DA1.

[0121] In multi-frequency mode MFM, the shielding signal MS can remain at the first level throughout the entire frame FF. That is, the shielding signal MS can maintain the first level in the same way as in normal frequency mode NFM during the entire frame FF.

[0122] In multi-frequency mode (MFM), when the full frame (FF) ends and the first partial frame (HF1) begins, the shielding signal MS can be synchronized with the start time of the second display area (DA2) driven at a low frequency and change from a first level to a second level (e.g., a low level). Here, the second level can be the same as the level of the second voltage VGL.

[0123] When the second display area DA2 begins at the pixel row connected to the (k+1)th initialization scan line SILk+1 and the (k+1)th compensation scan line SCLk+1, the masking signal MS can change from a first level to a second level before the activation period of the kth compensation scan signal SCk. That is, the time point t1 at which the masking signal MS changes from the first level to the second level can coincide with or precede the activation time point t2 of the kth compensation scan signal SCk.

[0124] like Figure 6B As shown, in the normally low mode, the first level of the shielding signal MS can be a high level, and the second level can be a low level lower than the first level. However, in the normally high mode, the first level of the shielding signal MS can be a low level, and the second level can be a high level higher than the first level.

[0125] The (k+1)th initialization scan signal SIk+1 output from the k-th driver stage STk can be shielded by the shielding signal MS. That is, the k-th compensation scan signal SCk output from the first output terminal OUT1 of the k-th driver stage STk is activated, while the (k+1)th initialization scan signal SIk+1 output from the second output terminal OUT2 of the k-th driver stage STk is not activated by the shielding signal MS. In addition, the (k+1)th driver stage STk+1, which receives the (k+1)th initialization scan signal SIk+1 as a carry signal and remains in the deactivated state, cannot activate the (k+2)th initialization scan signal SIk+2 and the (k+1)th compensation scan signal SCk+1. Therefore, the initialization scan lines SILk+1 to SILn and the compensation scan lines SCLk+1 to SCLn configured in the second display area DA2 during the first partial frame period HF1 remain in the deactivated state.

[0126] The masking signal MS can remain at the second level until the start of the next partial frame HF2 (i.e., referred to as the second partial frame). When the second partial frame HF2 begins, the masking signal MS changes to the first level. The masking signal MS can change from the first level to the second level synchronously with the start time of the second display area DA2 during the second partial frame period HF2.

[0127] During each of the partial frames HF1 and HF2, as the level of the shielding signal MS changes synchronously with the start time of the second display area DA2, the initialization scan lines SILk+1 to SILn and the compensation scan lines SCLk+1 to SCLn configured in the second display area DA2 can be kept in a deactivated state. The width of the period during which the shielding signal MS has the second level (i.e., referred to as the second level period) can vary according to the size of the second display area DA2. That is, if the proportion occupied by the second display area DA2 in the display area DA increases, the proportion occupied by the second level period of the shielding signal MS in each of the partial frames HF1 and HF2 can also increase.

[0128] As described above, the shielding signal MS can shield a portion of the initialization scan signals SIk+1 to SIn output from the driver stages ST0 to STn, which are connected to the second display area DA2, into a deactivated state in the multi-frequency mode MFM. Figure 7A An example is shown of one of the drive stages STk to STn where the shielding signal MS is provided (i.e., the kth drive stage).

[0129] Figure 6AEach of the driver levels ST0 to STn shown may include the same circuit configuration as the k-th driver level STk. Hereinafter, the k-th driver level STk will be described in detail, and descriptions of the other driver levels will be omitted. For ease of explanation, the k-th driver level STk will be referred to as driver level STk below.

[0130] Figure 7A This is a circuit diagram illustrating the k-th driver stage in a driver stage according to an embodiment of the present invention. Figures 7B to 7D It is shown Figure 7A The waveforms of the shielding signal, the first and second clock signals, the initialization scan signal, and the compensation scan signal are shown.

[0131] Reference Figure 7A The drive stage STk includes a drive circuit DC, a shielding circuit MC, first to fifth input terminals IN1, IN2, IN3, IN4, first and second voltage terminals V1, V2, and first and second output terminals OUT1, OUT2.

[0132] The driving circuit DC includes a control unit CC, a first output unit OC1, and a second output unit OC2. The control unit CC can output a first control signal CS1 and a second control signal CS2 in response to clock signals CLK1, CLK2, and a carry signal CRk-1. The first output unit OC1 is connected between the first output terminal OUT1 and the first voltage terminal V1, and operates in response to the first control signal CS1. The second output unit OC2 is connected between the first output terminal OUT1 and the second voltage terminal V2, and operates in response to the second control signal CS2. The driving stage STk outputs the k-th compensation scan signal SCk through the first output terminal OUT1. As an example of the present invention, a first voltage VGH is applied to the first voltage terminal V1, and a second voltage VGL is applied to the second voltage terminal V2. Here, the second voltage VGL can have a lower voltage level than the first voltage VGH. Therefore, the k-th compensation scan signal SCk can have the same voltage level as the first voltage VGH during the activation period and the same voltage level as the second voltage VGL during the deactivation period.

[0133] The control unit CC includes drive transistors DT1-DT10 and drive capacitors C1, C2, and C3. The control unit CC receives a first clock signal CLK1, a second clock signal CLK2, and a carry signal CRk-1 through the first to third input terminals IN1-IN3, respectively. The control unit CC receives a first voltage VGH and a second voltage VGL through the first voltage terminal V1 and the second voltage terminal V2, respectively. The carry signal CRk-1 received through the third input terminal IN3 can be the k-th initialization scan signal SIk output from the previous drive stage. Figure 6A (as shown in the image).

[0134] Figure 6A In the driving stages ST0 to STn shown, for a portion of the driving stages (e.g., the odd-numbered driving stages), each of the driving stages receives a first clock signal CLK1 at its first input terminal IN1 and a second clock signal CLK2 at its second input terminal IN2. Conversely, in the driving stages ST0 to STn, for a portion of the driving stages (e.g., the even-numbered driving stages), each of the driving stages receives a second clock signal CLK2 at its first input terminal IN1 and a first clock signal CLK1 at its second input terminal IN2.

[0135] The first driving transistor DT1 is connected between the third input terminal IN3 and the first control node CN1, and includes a gate electrode connected to the first input terminal IN1. The second driving transistor DT2 is connected between the first voltage terminal V1 and the second control node CN2, and includes a gate electrode connected to the third control node NC3. The third driving transistor DT3 is connected between the second control node CN2 and the second input terminal IN2, and includes a gate electrode connected to the first control node CN1.

[0136] A fourth driving transistor DT4 is connected between the third control node CN3 and the first input terminal IN1, and includes a gate electrode connected to the second input terminal IN2. As an example of the invention, multiple fourth driving transistors DT4 can be provided, and these multiple fourth transistors DT4 can be connected in series between the third control node CN3 and the first input terminal IN1. A fifth driving transistor DT5 is connected between the third control node CN3 and the second voltage terminal V2, and includes a gate electrode connected to the first input terminal IN1. A sixth driving transistor DT6 is connected between the first voltage terminal V1 and the fourth control node CN4, and includes a gate electrode connected to the second input terminal IN2. A seventh driving transistor DT7 is connected between the fourth control node CN4 and the second input terminal IN2, and includes a gate electrode connected to the fifth control node CN5.

[0137] The first driving capacitor C1 is connected between the first node N1 and the first voltage terminal V1. The second driving capacitor C2 is connected between the fourth control node CN4 and the fifth control node CN5. The third driving capacitor C3 is connected between the first control node CN1 and the second control node CN2.

[0138] The eighth driving transistor DT8 is connected between the first voltage terminal V1 and the first node N1, and includes a gate electrode connected to the second input terminal IN2. The ninth driving transistor DT9 is connected between the third control node CN3 and the fifth control node CN5, and includes a gate electrode connected to the second voltage terminal V2. The tenth driving transistor DT10 is connected between the second input terminal IN2 and the second node N2, and includes a gate electrode connected to the second voltage terminal V2.

[0139] In response to the carry signal CRk-1 and the first and second clock signals CLK1 and CLK2, the control unit CC outputs a first control signal CS1 for controlling the first output unit OC1 through the first node N1, and outputs a second control signal CS2 for controlling the second output unit OC2 through the second node N2. Figure 7A The diagram shows a control unit CC comprising 10 driving transistors DT1 to DT10 and 3 driving capacitors C1, C2, and C3, but the circuit configuration of the control unit CC is not limited to this. That is, various modifications can be made to the number and connection relationship of the driving transistors and driving capacitors included in the control unit CC.

[0140] The first output section OC1 includes a first output transistor OT1, and the second output section OC2 includes a second output transistor OT2. The first output transistor OT1 is connected between a first voltage terminal V1 and a first output terminal OUT1, and includes a gate electrode connected to a first node N1. The second output transistor OT2 is connected between a second voltage terminal V2 and a first output terminal OUT1, and includes a gate electrode connected to a second node N2.

[0141] Reference Figure 7A as well as Figure 7B The first output unit OC1 operates in response to the first control signal CS1. During the activation period of the first control signal CS1, the first output transistor OT1 is turned on, and the first voltage VGH is provided to the first output terminal OUT1 through the turned-on first output transistor OT1, thereby activating the k-th compensation scan signal SCk to the first voltage VGH. The second output unit OC2 operates in response to the second control signal CS2. The second control signal CS2 is activated during the deactivation period of the first control signal CS1, causing the second output transistor OT2 to turn on. The second voltage VGL is provided to the first output terminal OUT1 through the turned-on second output transistor OT2, thereby deactivating the k-th compensation scan signal SCk to the second voltage VGL. Figure 7BIn this process, the k-th compensation scan signal SCk operates in a normally low mode. As an example of the present invention, since each of the first and second output transistors OT1 and OT2 includes a PMOS transistor, each of the first and second control signals CS1 and CS2 can have a low level (e.g., the same voltage level as the second voltage VGL) during the activation period and a high level (e.g., the same voltage level as the first voltage VGH) during the deactivation period.

[0142] Reference Figure 6A , Figure 6B , Figure 7A as well as Figure 7B The shielding circuit MC includes a first shielding circuit MSC1 and a second shielding circuit MSC2. The first shielding circuit MSC1 includes a first shielding transistor MT1, and the second shielding circuit MSC2 includes a second shielding transistor MT2. The first shielding transistor MT1 is connected between the fourth input terminal IN4 and the second output terminal OUT2, and includes a gate electrode connected to the first node N1. The second shielding transistor MT2 is connected between the second output terminal OUT2 and the second voltage terminal V2, and includes a gate electrode connected to the second node N2. A first control signal CS1 output from the first node N1 of the control unit CC is provided to the first shielding circuit MSC1, and a second control signal CS2 output from the second node N2 of the control unit CC is provided to the second shielding circuit MSC2.

[0143] According to the present invention, the first and second shielding circuits MSC1 and MSC2 are not directly connected to the first output terminal OUT1. Therefore, even if a shielding circuit MC is added to the drive stage STk, the k-th compensation scan signal SCk and the (k+1)-th initialization scan signal SIk+1 can still be stably output through the first and second output terminals OUT1 and OUT2.

[0144] According to the present invention, the first and second shielding circuits MSC1 and MSC2 receive the first and second control signals CS1 and CS2 directly from the control unit CC without passing through the first output terminal OUT1. Therefore, compared with the structure in which the first and second shielding circuits MSC1 and MSC2 are directly connected to the first output terminal OUT1, the size of each of the shielding circuit MC and the first and second output units OC1 and OC2 can be reduced.

[0145] The first shielding circuit MSC1 stops (or shields) the output of the (k+1)th initialization scan signal SIk+1 in response to the first control signal CS1. Since the first shielding circuit MSC1 operates in the same manner as the first output section OC1 in response to the first control signal CS1, it can be turned on simultaneously with the first output section OC1. Specifically, during the activation period of the first control signal CS1, the first shielding transistor MT1 is turned on, and the shielding signal MS is applied to the second output terminal OUT2 through the turned-on first shielding transistor MT1. When the shielding signal MS has a first level MG1, the (k+1)th initialization scan signal SIk+1, which is activated to the first level MG1, can be output to the second output terminal OUT2. Since the shielding signal MS has the first level MG1 and is deactivated during the entire frame FF, the (k+1)th initialization scan signal SIk+1 can be activated simultaneously with the kth compensation scan signal SCk during the entire frame FF.

[0146] From the start of each partial frame HF1, HF2 to the first time point t1, the shielding signal MS can maintain a first level MG1. At the first time point t1, the shielding signal MS can change from the first level MG1 to a second level MG2. That is, in each partial frame HF1, HF2, the shielding signal MS can include a deactivation period corresponding to the period when the first display area DA1 is driven, maintaining the first level MG1, and an activation period corresponding to the period when the second display area DA2 is driven, maintaining the second level MG2. When the area from the region configured with the (k+1)th initial scan line SILk+1 to the region configured with the nth initial scan line SILn is defined as the second display area DA2, the shielding signal MS can change to the second level MG2 before the time point t2 (hereinafter, the second time point) when the kth compensation scan signal SCk is activated. The first time point t1 can be the same as or earlier than the second time point t2.

[0147] If the shielding signal MS has a second level MG2, then even if the shielding signal MS is applied to the second output terminal OUT2 through the conducting first shielding transistor MT1, the (k+1)th initialization scan signal SIk+1 cannot be activated. As an example of the present invention, the first level MG1 of the shielding signal MS may be the same as the level of the first voltage VGH, and the second level MG2 may be the same as the level of the second voltage VGL. Therefore, during the activation period when the shielding signal MS remains at the second level MG2, even if the shielding signal MS is applied to the second output terminal OUT2 through the conducting first shielding transistor MT1, the (k+1)th initialization scan signal SIk+1 remains at the second voltage VGL. That is, even if the first shielding circuit MSC1 and the first output section OC1 are simultaneously turned on in response to the first control signal CS1, the kth compensation scan signal SCk output through the first output terminal OUT1 is activated, while the (k+1)th initialization scan signal SIk+1 output through the second output terminal OUT2 remains deactivated due to the shielding signal MS having the second level MG2. Therefore, the (k+1)th initialization scan signal SIk+1 during each partial frame HF1 and HF2 can be shielded by the first shielding circuit MSC1.

[0148] The second shielding circuit MSC2 operates in response to the second control signal CS2. Specifically, the second shielding transistor MT2 can be turned on during the activation period of the second control signal CS2, and the (k+1)th initialization scan signal SIk+1 is maintained at the second voltage VGL through the turned-on second shielding transistor MT2. In particular, the second control signal CS2 can be activated during the deactivation period of the first control signal CS1. Therefore, the second shielding circuit MSC2 can be turned on during the period when the first shielding circuit MSC1 is off, thus maintaining the (k+1)th initialization scan signal SIk+1 in a deactivated state. Subsequently, if the second control signal CS2 is deactivated and the first control signal CS1 is activated, the first shielding circuit MSC1 outputs the shielding signal MS to the second output terminal OUT2 in response to the first control signal CS1.

[0149] Since the shielding signal MS changes to the second level MG2 at the first time point t1 of each frame HF1 and HF2, even if the first shielding circuit MSC1 is activated in response to the first control signal CS1, the (k+1)th initialization scan signal SIk+1 can remain in the deactivated state.

[0150] Reference Figure 7CAt the first time point t1, the shielding signal MS can be changed to the second level MG2. As an example of the present invention, the second level MG2 can be a voltage level different from the second voltage VGL. Specifically, the second level MG2 can be the same as the level of the compensation voltage VGC1, which is higher than the second voltage VGL. For example, when the second voltage VGL is -8V, the compensation voltage VGC1 can be -6V. If the potential of the first node N1 connected to the gate electrode of the first shielding transistor MT1 is the same as the potential of the source electrode of the first shielding transistor MT1, it is possible that the first and second shielding transistors MT1 and MT2 are simultaneously turned off. Then, the (k+1)th initialization scan signal SIk+1 can have a floating state. When the second level MG2 of the shielding signal MS is higher than the level of the second voltage VGL, the potential of the first node N1 connected to the gate electrode of the first shielding transistor MT1 becomes lower than the potential of the source electrode of the first shielding transistor MT1. At this time, the first shielding transistor MT1 can be turned on. Therefore, the situation where the first and second shielding transistors MT1 and MT2 are simultaneously disconnected can be avoided, which prevents the (k+1)th initialization scan signal SIk+1 from being in a floating state.

[0151] Reference Figure 7D Each of the first and second clock signals CKL1 and CLK2 can have: a high-level period with a third level; and a low-level period with a fourth level, thereby oscillating. As an example of the present invention, the third level may be the same as the level of the first voltage VGH, and the fourth level may be the same as the level of the second voltage VGL.

[0152] At the first time point t1, the shielding signal MS can be changed to the second level MG2. As an example of the present invention, the second level MG2 can be the same as the level of the second voltage VGL. After the first time point t1, the second clock signal CLK2, which determines the potential of the first node N1, can drop to a level corresponding to the second compensation voltage VGC2 during the low-level period. That is, if the second clock signal CLK2 has the same voltage level as the second voltage VGL during the low-level period before the first time point t1, then after the first time point t1, the second clock signal CLK2 can have a voltage level corresponding to the second compensation voltage VGC2, which is lower than the second voltage VGL. As an example of the present invention, the second voltage VGL can be -8V, and the second compensation voltage VGC2 can be -10V.

[0153] After the first time point t1, even if the second level MG2 of the shielding signal MS remains at the second voltage VGL, the potential of the first node N1 becomes lower than the potential of the source electrode of the first shielding transistor MT1 through the second clock signal CLK2. At this time, the first shielding transistor MT1 can be turned on. Therefore, the situation where the first and second shielding transistors MT1 and MT2 are simultaneously turned off can be avoided, and as a result, the (k+1)th initialization scan signal SIk+1 can be prevented from being in a floating state.

[0154] Figure 8A This is a circuit diagram illustrating the k-th driver stage in a driver stage according to an embodiment of the present invention. Figure 8B It is shown Figure 8A The waveforms of the shielding signal, the first and second clock signals, the initialization scan signal, and the compensation scan signal are shown. However, in Figure 8A as well as Figure 8B In the explanation, regarding and Figure 7A as well as Figure 7B The same constituent elements shown are denoted by the same reference numerals in the accompanying drawings. To avoid repetition, specific descriptions of the same constituent elements will be omitted.

[0155] Reference Figure 8A as well as Figure 8B The driver stage STk_a includes a driver circuit DC, a shielding circuit MC, first to fourth input terminals IN1, IN2, IN3, IN4, first and second voltage terminals V1, V2, and first and second output terminals OUT1, OUT2.

[0156] The driving circuit DC includes a control unit CC, a first output unit OC1, and a second output unit OC2. The control unit CC can output a first control signal CS1 and a second control signal CS2 in response to clock signals CLK1, CLK2, and a carry signal CRk-1. The first output unit OC1 is connected between the first output terminal OUT1 and the first voltage terminal V1, which outputs the k-th compensation scan signal SCk, and operates in response to the first control signal CS1. The second output unit OC2 is connected between the first output terminal OUT1 and the second voltage terminal V2, and operates in response to the second control signal CS2. As an example of the present invention, a first voltage VGH is applied to the first voltage terminal V1, and a second voltage VGL is applied to the second voltage terminal V2. Here, the second voltage VGL can have a lower voltage level than the first voltage VGH. Therefore, the k-th compensation scan signal SCk can have the same voltage level as the second voltage VGL during the activation period and the same voltage level as the first voltage VGH during the deactivation period. Figure 8B In this mode, the carry signal CRk-1 and the k-th compensation scan signal SCk operate in constant high mode.

[0157] As an example of the present invention, since each of the first and second output transistors OT1 and OT2 includes a PMOS transistor, each of the first and second control signals CS1 and CS2 can have a low level during the activation period (e.g., the same voltage level as the second voltage VGL) and a high level during the deactivation period (e.g., the same voltage level as the first voltage VGH).

[0158] Due to the configuration of each of the control unit CC, the first output unit OC1, and the second output unit OC2, and Figure 7A The control unit CC, the first output unit OC1, and the second output unit OC2 shown are all identical in configuration, so detailed descriptions are omitted.

[0159] Reference Figure 8A as well as Figure 8B The shielding circuit MC includes a first shielding circuit MSC1 and a second shielding circuit MSC2. The first shielding circuit MSC1 includes a first shielding transistor MT1, and the second shielding circuit MSC2 includes a second shielding transistor MT2. The first shielding transistor MT1 is connected between a first voltage terminal V1 and a second output terminal OUT2, and includes a gate electrode connected to a first node N1. The second shielding transistor MT2 is connected between the second output terminal OUT2 and a fourth input terminal IN4, and includes a gate electrode connected to a second node N2.

[0160] The second shielding circuit MSC2 stops (or shields) the output of the (k+1)th initialization scan signal SIk+1 in response to the second control signal CS2. Specifically, the second shielding circuit MSC2 outputs the shielding signal MS_a, which is input through the fourth input terminal IN4, to the second output terminal OUT2 in response to the second control signal CS2. Since the second shielding circuit MSC2 operates in the same manner as the second output unit OC2 in response to the second control signal CS2, they can be turned on simultaneously.

[0161] During full-frame FF, the shielding signal MS_a can have a first level MG1. As an example of the present invention, the first level MG1 can be the same as the level of the second voltage VGL. Therefore, the second shielding circuit MSC2, which is turned on simultaneously with the second output OC2, can output the shielding signal MS_a with the first level MG1 as the (k+1)th initialization scan signal SIk+1 in response to the second control signal CS2. During full-frame FF, the k-th compensation scan signal SCk and the (k+1)th initialization scan signal SIk+1 output from the k-th driver stage STk can be activated simultaneously.

[0162] On the other hand, from the start of each partial frame HF1, HF2 to the first time point t1, the shielding signal MS_a can maintain the first level MG1. At the first time point t1, the shielding signal MS_a can change from the first level MG1 to the second level MG2. As an example of the present invention, the second level MG2 can be the same as the level of the first voltage VGH. That is, even if the second shielding circuit MSC2 and the second output unit OC2 are simultaneously turned on in response to the second control signal CS2, the k-th compensation scan signal SCk output through the first output terminal OUT1 is activated, while the (k+1)-th initialization scan signal SIk+1 output through the second output terminal OUT2 remains deactivated by the shielding signal MS_a with the second level MG2. Therefore, the (k+1)-th initialization scan signal SIk+1 can be shielded by the second shielding circuit MSC2 during each partial frame HF1, HF2.

[0163] The first shielding circuit MSC1 operates in response to the first control signal CS1. Specifically, the first shielding transistor MT1 may be turned on during the activation period of the first control signal CS1, and the (k+1)th initialization scan signal SIk+1 may be maintained at the first voltage VGH through the turned-on first shielding transistor MT1. In particular, the second control signal CS2 may be deactivated during the activation period of the first control signal CS1. Therefore, the first shielding circuit MSC1 may be turned on during the period when the second shielding circuit MSC2 is off, thereby maintaining the (k+1)th initialization scan signal SIk+1 in a deactivated state. Subsequently, if the first control signal CS1 is deactivated and the second control signal CS2 is activated, the second shielding circuit MSC2 responds to the second control signal CS2 by outputting the shielding signal MS_a to the second output terminal OUT2.

[0164] Since the shielding signal MS_a changes from the first level MG1 to the second level MG2 at the first time point t1 of each frame HF1 and HF2, even if the second shielding circuit MSC2 is activated in response to the second control signal CS2, the k+1th initialization scan signal SIk+1 can remain in the deactivated state.

[0165] Figure 9 This is a circuit diagram illustrating the k-th driver stage in a driver stage according to an embodiment of the present invention. However, in Figure 9 In the explanation, regarding and Figure 7A The same constituent elements shown are denoted by the same reference numerals in the accompanying drawings. To avoid repetition, specific descriptions of the same constituent elements will be omitted.

[0166] Reference Figure 9The driver stage STk_b includes a driver circuit DC, a shielding circuit MC, first to fifth input terminals IN1, IN2, IN3, IN4, IN5, first and second voltage terminals V1, V2, and first and second output terminals OUT1, OUT2. The driver stage STk_b can output the k-th compensation scan signal SCk and the (k+1)-th initialization scan signal SIk+1 in either a normally low mode or a normally high mode.

[0167] A first voltage VGH is applied to the first voltage terminal V1, and a second voltage VGL is applied to the second voltage terminal V2. Here, the second voltage VGL may have a lower voltage level than the first voltage VGH. Specifically, in a normally low mode, the k-th compensation scan signal SCk may have the same voltage level as the first voltage VGH during the activation period and the same voltage level as the second voltage VGL during the deactivation period. Alternatively, in a normally high mode, the k-th compensation scan signal SCk may have the same voltage level as the second voltage VGL during the activation period and the same voltage level as the first voltage VGH during the deactivation period.

[0168] The first shielding circuit MSC1 includes a first shielding transistor MT1, and the second shielding circuit MSC2 includes a second shielding transistor MT2. The first shielding transistor MT1 is connected between the fourth input terminal IN4 and the second output terminal OUT2, and operates in response to a first control signal CS1. The second shielding transistor MT2 is connected between the second output terminal OUT2 and the fifth input terminal IN5, and operates in response to a second control signal CS2.

[0169] The first shielding circuit MSC1, in response to the first control signal CS1, outputs the first shielding signal MS_b1, input through the fourth input terminal IN4, to the second output terminal OUT2. The second shielding circuit MSC2, in response to the second control signal CS2, outputs the second shielding signal MS_b2, input through the fifth input terminal IN5, to the second output terminal OUT2. As an example of the present invention, in the normally low mode, the first level MG1 of the first shielding signal MS_b1 (refer to...) Figure 7B The second level MG2 of the first shielding signal MS_b1 has the same voltage level as the first voltage VGH (refer to...). Figure 7B It has the same voltage level as the second voltage VGL. This could be, in constant high mode, the first level MG1 of the first shielding signal MS_b1 (refer to...). Figure 8B The second level MG2 of the first shielding signal MS_b1 has the same voltage level as the second voltage VGL (refer to...). Figure 8B It has the same voltage level as the first voltage VGH.

[0170] Therefore, according to Figure 9 The driver stage STk_b can output the k-th compensation scan signal SCk and the (k+1)-th initialization scan signal SIk+1 in either constant low or constant high mode. The output of the (k+1)-th initialization scan signal SIk+1 can be masked in either constant low or constant high mode.

[0171] Figure 10A This is a block diagram of a scan driver according to an embodiment of the present invention. Figure 10B This is a waveform diagram showing the initial scan signal and the compensation scan signal output from the scan driver in normal frequency mode and multi-frequency mode. However, in Figure 10A as well as Figure 10B In the explanation, regarding and Figure 6A as well as Figure 6B The same constituent elements shown are denoted by the same reference numerals in the accompanying drawings. To avoid repetition, specific descriptions of the same constituent elements will be omitted.

[0172] Reference Figure 10A as well as Figure 10B According to an embodiment of the present invention, the scan driver 301 includes drive stages ST0 to STn. Each drive stage ST0 to STn includes first to fourth input terminals IN1, IN2, IN3, IN4, first and second voltage terminals V1, V2, and first and second output terminals OUT1, OUT2.

[0173] A first voltage VGH may be supplied to the fourth input terminal IN4 of the drive stage (hereinafter, normal stage) that supplies initialization scan signals SI1 to SIk to the initialization scan lines SIL1 to SILk configured in the first display area DA1. A shielding signal MS may be supplied to the fourth input terminal IN4 of the drive stage (hereinafter, shielding stage) that supplies initialization scan signals SIk+1 to SIn to the initialization scan lines SILk+1 to SILn configured in the second display area DA2.

[0174] When the position and size of the second display area DA2 in the display area DA of the display device DD change, the number of normal levels of the shielding signal MS with the first voltage VGH applied to the fourth input terminal IN4 can also change accordingly.

[0175] Figure 10A The diagram illustrates a structure where the fourth input terminal IN4 of the normal stage is separated from the first voltage terminal V1, but the invention is not limited thereto. For example, when in a display device DD (refer to...) Figure 4 The display area DA (refer to) Figure 4When the position of the second display area DA2 is fixed, the fourth input terminal IN4 of the normal stage can be integrated with the first voltage terminal V1. At this time, the shielding circuit of the normal stage can be connected between the first voltage terminal V1 and the second voltage terminal V2.

[0176] The shielding signal MS is provided to the shielding stages ST0 to STn in the drive stages. In the normal frequency mode NFM, the shielding signal MS is maintained at a first level (e.g., high level). Here, the first level can be the same as the level of the first voltage VGH.

[0177] In normal frequency mode NFM, during each frame F1, F2, and F3, the scan driver 301 can output sequentially activated compensation scan signals SC1 to SCn and initialization scan signals SI1 to SIn. As an example of the present invention, each of the compensation scan signals SC1 to SCn may have a high level during the activation period and a low level during the deactivation period. Alternatively, each of the initialization scan signals SI1 to SIn may have a high level during the activation period and a low level during the deactivation period.

[0178] In multi-frequency mode MFM, the driving frame DF includes the full frame FF and some frames HF1, HF2, HF3, and HF4. Figure 10B Only four partial frames HF1, HF2, HF3, and HF4 included in the driving frame DF are shown, but the number of partial frames HF1, HF2, HF3, and HF4 included in the driving frame DF can vary depending on the driving frequency of the first display area DA1.

[0179] In multi-frequency mode MFM, the shielding signal MS can remain at the first level throughout the entire frame FF. That is, the shielding signal MS can maintain the first level in the same way as in normal frequency mode NFM during the entire frame FF.

[0180] In Multi-Frequency Mode (MFM), if the full frame (FF) ends and the first partial frame (HF1) begins, the shielding signal MS can change from a first level to a second level (e.g., a low level) at the start time t1 of the first partial frame (HF1). Here, the second level can be the same as the level of the second voltage VGL. Since the shielding signal MS is only supplied to the shielding level, it can remain at the second level during partial frames HF1, HF2, HF3, and HF4. At the end of partial frames HF1, HF2, HF3, and HF4 and the start of the next full frame, the shielding signal MS can change to the first level.

[0181] During frames HF1 to HF4, while the shielding signal MS maintains its second level, the initialization scan lines SILk+1 to SILn and the compensation scan lines SCLk+1 to SCLn configured in the second display area DA2 can be kept in an inactive state. As described above, the shielding signal MS can shield the initialization scan signals SIk+1 to SIn output from the shielding level of the initialization scan lines SILk+1 to SILn connected to the second display area DA2 in the multi-frequency mode MFM from the driver stages ST0 to STn to an inactive state.

[0182] Figure 11 This is a block diagram of a scan driver according to an embodiment of the present invention.

[0183] Reference Figure 11 According to an embodiment of the present invention, the scan driver 302 includes drive stages ST0 to STn. Each drive stage ST0 to STn includes first to fourth input terminals IN1, IN2, IN3, IN4, first and second voltage terminals V1, V2, and first and second output terminals OUT1, OUT2.

[0184] A first voltage VGH may be supplied to the fourth input terminal IN4 of the drive stage (hereinafter, normal stage) that supplies initialization scan signals SI1 to SIk to the initialization scan lines SIL1 to SILk configured in the first display area DA1. The drive stage (hereinafter, shielding stage) that supplies initialization scan signals SIk+1 to SIn to the initialization scan lines SILk+1 to SILn configured in the second display area DA2 may include a first shielding stage STk to STk+2 and a second shielding stage.

[0185] The first shielding levels STk to STk+2 are drive levels configured adjacent to the boundaries of the first and second display areas DA1 and DA2. The second shielding level is the remaining drive levels in the shielding levels other than the first shielding levels STk to STk+2.

[0186] A first voltage VGH can be applied to the fourth input terminal IN4 of the normal stage and the second shielding stage. A shielding signal MS can be supplied to the fourth input terminal IN4 of the first shielding stage STk to STk+2.

[0187] Figure 11 The diagram illustrates a structure where the fourth input terminal IN4 of each of the normal stage and the second shielding stage is separated from the first voltage terminal V1, but the invention is not limited thereto. For example, when in a display device DD (refer to...) Figure 4 The display area DA (refer to) Figure 4When the position of the second display area DA2 is fixed, the fourth input terminal IN4 of each of the normal stage and the second shielding stage can be integrated with the first voltage terminal V1. At this time, the shielding circuit of each of the normal stage and the second shielding stage can be connected between the first voltage terminal V1 and the second voltage terminal V2.

[0188] The shielding signal MS is provided to the first shielding stages STk to STk+2 in the drive stages ST0 to STn. The shielding signal MS can have the same characteristics as... Figure 10B The waveform of the shielding signal shown is the same.

[0189] Figure 11 The number of first shielding levels STk to STk+2 to which the shielding signal MS is applied is shown as three, but the present invention is not limited thereto. The number of first shielding levels STk to STk+2 to which the shielding signal MS is applied can be set in various ways according to the performance of the scan driver 302 and the driving method, etc.

[0190] Figure 12A This is a perspective view showing the unfolded state of a display device according to an embodiment of the present invention. Figure 12B It is shown Figure 12A A perspective view of the display device in its folded state.

[0191] Figure 12A as well as Figure 12B The illustration shows a display device F_DD as a mobile phone. However, the invention is not limited thereto. The display device F_DD may include a tablet PC, smartphone, personal digital assistant (PDA), portable multimedia player (PMP), game console, watch-type electronic device, etc. The invention can be used in small and medium-sized electronic devices, including large electronic devices such as televisions or external billboards, personal computers, laptops, kiosks, car navigation devices, cameras, etc. These are provided by way of example only, and it is obvious that they can be used in other electronic devices without departing from the concept of the invention.

[0192] The display device F_DD includes a display area DA and a non-display area NDA. The display device F_DD can display images through the display area DA. When the display device F_DD is in its unfolded state, the display area DA can include a plane defined by a first direction DR1 and a second direction DR2. The non-display area NDA surrounds the display area DA.

[0193] The display area DA may include a first non-folded area NFA1, a folded area FA, and a second non-folded area NFA2. The folded area FA may be bent with reference to a folding axis FX extending along the second direction DR2.

[0194] When the display device F_DD is folded, the first non-folded area NFA1 and the second non-folded area NFA2 can face each other. In this case, the display area DA may not be exposed to the outside, which can be referred to as the in-folding state. Optionally, when the display device F_DD is folded, the first non-folded area NFA1 and the second non-folded area NFA2 can be opposite each other. In this case, the display area DA can be exposed to the outside, which can be referred to as the out-folding state.

[0195] The display device F_DD can perform either inward folding or outward folding. Optionally, the display device F_DD can perform both inward folding and outward folding. In this case, the folding area FA of the display device F_DD can be both inward folding and outward folding. Alternatively, a portion of the display device F_DD can be inward folding, and another portion can be outward folding.

[0196] Figure 12A as well as Figure 12B The example shows a folded region FA and two non-folded regions NFA1 and NFA2, but the number of folded and non-folded regions is not limited thereto. For example, the display device F_DD may include more than two non-folded regions and multiple folded regions configured between adjacent non-folded regions.

[0197] Figure 12A as well as Figure 12B The illustration shows the folding axis FX parallel to the minor axis of the display device F_DD, but the invention is not limited thereto. For example, the folding axis FX can also be parallel to the major axis of the display device F_DD, for example, extending along a direction parallel to the first direction DR1. In this case, the first non-folding region NFA1, the folding region FA, and the second non-folding region NFA2 can be arranged sequentially along the second direction DR2.

[0198] The display area DA of the display device F_DD may include multiple display areas DA1 and DA2. Figure 12A The example shows two display areas DA1 and DA2, but the number of display areas DA1 and DA2 included in display area DA is not limited to this.

[0199] Multiple display areas DA1 and DA2 may include a first display area DA1 and a second display area DA2. For example, the first display area DA1 may be the area displaying a first image IM1, and the second display area DA2 may be the area displaying a second image IM2. For example, the first image IM1 may be a dynamic image, and the second image IM2 may be a static image or a text image with a long change period.

[0200] According to one embodiment, the display device F_DD can drive the entire first display area DA1 and the second display area DA2 at a normal frequency during normal frequency mode. Alternatively, according to one embodiment, the display device F_DD can drive the first display area DA1, which displays a first image IM1, at a higher driving frequency than the normal frequency during multi-frequency mode, and drive the second display area DA2, which displays a second image IM2, at a lower driving frequency than the normal frequency. The display device F_DD can improve the display quality of dynamic images by increasing the driving frequency of the first display area DA1. The display device DD can reduce power consumption by decreasing the driving frequency of the second display area DA2.

[0201] The dimensions of each of the first display area DA1 and the second display area DA2 can be preset and can be changed by an application. In one embodiment, the first display area DA1 may correspond to the first non-folding area NFA1, and the second display area DA2 may correspond to the second non-folding area NFA2. Alternatively, a portion of the folding area FA may correspond to the first display area DA1, and another portion of the folding area FA may correspond to the second display area DA2.

[0202] In one embodiment, the first display area DA1 may correspond to a portion of the first non-foldable area NFA1, and the second display area DA2 may correspond to another portion of the first non-foldable area NFA1, the foldable area FA, and the second non-foldable area NFA2. That is, the area of ​​the first display area DA1 may be larger than the area of ​​the second display area DA2.

[0203] In one embodiment, the first display area DA1 may correspond to a portion of the first non-foldable area NFA1, the foldable area FA, and the second non-foldable area NFA2, and the second display area DA2 may be another portion of the second non-foldable area NFA2. That is, the area of ​​the second display area DA2 may be larger than the area of ​​the first display area DA1.

[0204] like Figure 12B As shown, when the folded area FA is folded, the first display area DA1 corresponds to the first non-folded area NFA1, and the second display area DA2 corresponds to the folded area FA and the second non-folded area NFA2.

[0205] Figure 12A as well as Figure 12B A foldable display device F_DD is shown, but the invention is not limited thereto. For example, the invention can also be applied to rollable display devices, etc.

[0206] The above description refers to embodiments; however, those skilled in the art will understand that various modifications and alterations can be made to the present invention without departing from the spirit and scope of the invention as set forth in the appended claims. Furthermore, the embodiments disclosed in this invention are not intended to limit the technical concept of the invention, and should be interpreted as including all technical concepts within the appended claims and their equivalents within the scope of the invention.

Claims

1. A scan driver which drives a display panel including a plurality of pixels connected to a plurality of compensation scan lines and a plurality of initialization scan lines, respectively, wherein, The scan driver includes: The driving circuit includes: a control unit that outputs a first control signal and a second control signal in response to a clock signal and a carry signal; a first output unit connected to a first output terminal that outputs a compensation scan signal to a corresponding compensation scan line in the compensation scan lines and a first voltage terminal that is supplied with a first voltage, and operates in response to the first control signal; and a second output unit connected to the first output terminal and a second voltage terminal that is supplied with a second voltage, and operates in response to the second control signal; and A shielding circuit receives the first control signal and the second control signal, and in response to the first control signal and the second control signal, outputs an initialization scan signal to a second output terminal connected to the corresponding initialization scan line in the initialization scan line. It is also connected to an input terminal supplied with a shielding signal to control the voltage level of the initialization scan signal according to the shielding signal. In the normal frequency mode, the shielding signal has a first level and is deactivated. In the multi-frequency mode, the shielding signal includes a deactivation period with the first level and an activation period with the second level.

2. The scan driver according to claim 1, wherein, The shielding circuit is connected between the first voltage terminal and one of the second voltage terminals and the input terminal.

3. The scan driver according to claim 2, wherein, The shielding circuit includes: A first shielding circuit is connected between the input terminal and the second output terminal, and transmits the shielding signal to the second output terminal in response to the first control signal; and The second shielding circuit is connected between the second output terminal and the second voltage terminal, and transmits the second voltage to the second output terminal in response to the second control signal.

4. The scan driver according to claim 3, wherein, The first shielding circuit includes: The first shielded transistor includes: a first electrode for receiving the first control signal; a second electrode connected to the input terminal; and a third electrode connected to the second output terminal. The second shielding circuit includes: The second shielded transistor includes: a first electrode for receiving the second control signal; a second electrode connected to the second voltage terminal; and a third electrode connected to the second output terminal.

5. The scan driver according to claim 4, wherein, The first output unit includes: The first output transistor includes: a first electrode for receiving the first control signal; a second electrode connected to the first voltage terminal; and a third electrode connected to the first output terminal. The second output section includes: The second output transistor includes: a first electrode for receiving the second control signal; a second electrode connected to the second voltage terminal; and a third electrode connected to the first output terminal.

6. The scan driver according to claim 1, wherein, The first level is the same as the level of the first voltage. The second level is the same as the level of the second voltage.

7. The scan driver according to claim 6, wherein, The clock signal has the following characteristics: The first time period has a third level; and the second time period has a fourth level.

8. The scan driver according to claim 7, wherein, In the normal frequency mode, the fourth voltage level is the same as the level of the second voltage. In the multi-frequency mode, the fourth level is lower than the level of the second voltage during the deactivation period of the shielding signal.

9. The scan driver according to claim 1, wherein, The first level is the same as the level of the first voltage. The second voltage level is lower than the first voltage level but higher than the second voltage level.

10. The scan driver according to claim 2, wherein, The shielding circuit includes: A first shielding circuit is connected between the first voltage terminal and the second output terminal, and transmits the first voltage to the second output terminal in response to the first control signal; and A second shielding circuit is connected between the input terminal and the second output terminal, and transmits the shielding signal to the second output terminal in response to the second control signal.

11. The scan driver according to claim 10, wherein, The first voltage level is the same as the second voltage level. The second voltage level is the same as the first voltage level.

12. The scan driver according to claim 1, wherein, The input terminals include: The first input terminal is supplied with the first shielding signal from the shielding signals; and The second input terminal is supplied with the second shielding signal from the shielding signals.

13. The scan driver according to claim 12, wherein, The shielding circuit includes: A first shielding circuit is connected between the first input terminal and the second output terminal, and transmits the first shielding signal to the second output terminal in response to the first control signal; and The second shielding circuit is connected between the second input terminal and the second output terminal, and transmits the second shielding signal to the second output terminal in response to the second control signal.

14. The scan driver according to claim 13, wherein, In the normal frequency mode, the first shielding signal has the same first level as the first voltage and is deactivated. In the multi-frequency mode, the first shielding signal has: a deactivation period, having the first level; And during the activation period, a second level having the same level as the second voltage. In both the normal frequency mode and the multi-frequency mode, the second shielding signal maintains the second level.

15. The scan driver according to claim 13, wherein, In the normal frequency mode, the second shielding signal has a first level that is the same as the level of the second voltage and is deactivated. In the multi-frequency mode, the second shielding signal has: a deactivation period, having the first level; And during the activation period, a second voltage level has the same level as the first voltage. In both the normal frequency mode and the multi-frequency mode, the first shielding signal maintains the second level.

16. A display device comprising: The display device includes: The display panel includes: multiple pixels, which are respectively connected to multiple data lines, multiple compensation scan lines and multiple initialization scan lines; A data driver drives the multiple data lines; A scan driver drives the plurality of compensated scan lines and the plurality of initialization scan lines; and The drive controller controls the data driver and the scan driver to display the image on the display panel. The scan driver includes a drive stage that outputs a compensation scan signal to the corresponding compensation scan line in the compensation scan lines and an initialization scan signal to the corresponding initialization scan line in the initialization scan lines. The driver level includes: The driving circuit includes: a control unit that outputs a first control signal and a second control signal in response to a clock signal and a carry signal; a first output unit connected to a first output terminal that outputs the compensated scan signal and a first voltage terminal that is supplied with a first voltage, and operating in response to the first control signal; and a second output unit connected to the first output terminal and a second voltage terminal that is supplied with a second voltage, and operating in response to the second control signal; and The shielding circuit receives the first control signal and the second control signal, and in response to the first control signal and the second control signal, outputs the initialization scan signal to the second output terminal. It is also connected to the input terminal supplied with the shielding signal to control the voltage level of the initialization scan signal according to the shielding signal. In the normal frequency mode, the shielding signal has a first level and is deactivated. In the multi-frequency mode, the shielding signal includes a deactivation period with the first level and an activation period with the second level.

17. The display device according to claim 16, wherein, The shielding circuit includes: The first shielded transistor includes: a first electrode for receiving the first control signal; a second electrode connected to the input terminal; and a third electrode connected to the second output terminal; and The second shielded transistor includes a first electrode for receiving the second control signal; a second electrode connected to the second voltage terminal; and a third electrode connected to the second output terminal. In the normal frequency mode, the shielding signal has a first level that is the same as the first voltage level and is deactivated. In the multi-frequency mode, the shielding signal has: a deactivation period having the first level; and an activation period having a second level having the same level as the second voltage.

18. The display device according to claim 17, wherein, The first output unit includes: The first output transistor includes: a first electrode for receiving the first control signal; a second electrode connected to the first voltage terminal; and a third electrode connected to the first output terminal. The second output section includes: The second output transistor includes: a first electrode for receiving the second control signal; a second electrode connected to the second voltage terminal; and a third electrode connected to the first output terminal.

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