Time-based combining of block families of memory devices

Abstract

This application relates to time-based combining of block families of a memory device. An example memory subsystem includes a memory device; and a processing device operably coupled to the memory device. The processing device is configured to determine that a first block family of a plurality of block families of the memory device and a second block family of the plurality of block families meet a proximity condition; determine whether the first block family and the second block family satisfy a time-based combining criterion corresponding to the proximity condition; and in response to determining that the first block family and the second block family satisfy the time-based combining criterion, merge the first block family and the second block family.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems and, more specifically, to time-based combining for block families of a memory device. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. SUMMARY

[0003] One aspect of the present disclosure relates to a system comprising: a memory device; and a processing device operably coupled to the memory device, the processing device to perform operations comprising: determining that a first block family of a plurality of block families of the memory device and a second block family of the plurality of block families meet a proximity condition; determining whether the first block family and the second block family satisfy a time-based combining criterion corresponding to the proximity condition; and in response to determining that the first block family and the second block family satisfy the time-based combining criterion, merging the first block family and the second block family.

[0004] Another aspect of the present disclosure relates to a method comprising: determining that a first block family of a plurality of block families of a memory device and a second block family of the plurality of block families meet a proximity condition; determining whether the first block family and the second block family satisfy a time-based combining criterion; in response to determining that the first block family and the second block family satisfy the time-based combining criterion, determining whether the first block family and the second block family satisfy a voltage-based combining criterion; and in response to determining that the first block family and the second block family satisfy the voltage-based combining criterion, merging the first block family and the second block family.

[0005] Yet another aspect of the present disclosure relates to a non-transitory computer- readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: determine that a first block family of a plurality of block families of a memory device and a second block family of the plurality of block families meet a proximity condition; determine whether the first block family and the second block family satisfy a time-based combining criterion corresponding to the proximity condition; and in response to determining that the first block family and the second block family satisfy the time-based combining criterion, merge the first block family and the second block family. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which:

[0007] Figure 1 An example computing system including a memory sub-system is shown in accordance with some embodiments of the present disclosure.

[0008] Figure 2 A time-voltage shift due to slow charge loss exhibited by a three-level memory cell is schematically shown in accordance with some embodiments of the present disclosure.

[0009] Figure 3 An example plot showing dependence of threshold voltage shift on post-program time (i.e., the time period elapsed from when the block was programmed) is depicted in accordance with some embodiments of the present disclosure.

[0010] Figure 4 A set of predefined threshold voltage shift intervals in accordance with embodiments of the present disclosure is schematically shown.

[0011] Figure 5 Block family management operations implemented by a block family manager component of a memory sub-system controller operated in accordance with embodiments of the present disclosure are schematically shown.

[0012] Figure 6 Selecting a block family for calibration in accordance with embodiments of the present disclosure is schematically shown.

[0013] Figure 7 Example metadata maintained by a memory sub-system controller to associate blocks and / or partitions with block families in accordance with embodiments of the present disclosure is schematically shown.

[0014] Figure 8 A sequence diagram depicting a sequence of events flow of an example method 800 for combining two block families when conforming to a time-based combination criterion is shown in accordance with one or more aspects of the present disclosure.

[0015] Figure 9 is a flow diagram of an example method of performing block family combination in a memory sub-system according to a time-based combination criterion and a voltage-based combination criterion in accordance with some embodiments of the present disclosure.

[0016] Figure 10 is a flow diagram of an example method of performing block family combination in a memory sub-system according to a time-based combination criterion in accordance with some embodiments of the present disclosure.

[0017] Figure 11 is a flow diagram of an example method of performing block family combination in a memory sub-system according to a time-based combination criterion or a voltage-based combination criterion in accordance with some embodiments of the present disclosure.

[0018] Figure 12 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0019] Embodiments of the present disclosure relate to block family combination management of block families of a memory device. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with Figure 1 A host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0020] The memory sub-system can utilize one or more memory devices (including any combination of different types of non-volatile memory devices and / or volatile memory devices) to store data provided by the host system. In some embodiments, the non-volatile memory devices can be provided by a not-and (NAND) type flash memory device. Examples of non-volatile memory devices are described below in connection with Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. The planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical intervals. Each block is composed of a set of pages. Each page is composed of a set of memory cells (“cells”). A cell is an electronic circuit that stores information.

[0021] Data operations can be performed by the memory sub-system. The data operations can be host initiated operations. For example, a host system can initiate data operations (e.g., writes, reads, erases, etc.) on the memory sub-system. The host system can send access requests (e.g., write commands, read commands) to the memory sub-system in order to store data on the memory devices at the memory sub-system and to read data from the memory devices on the memory sub-system. The data to be read or written is referred to hereinafter as “host data” as specified by the host request. The host request can include logical address information (e.g., logical block addresses (LBAs), name spaces) for the host data, which is a location associated with the host data by the host system. The logical address information (e.g., LBAs, name spaces) can be part of metadata for the host data. The metadata can also include error handling data (e.g., ECC codewords, parity codes), data versions (e.g., to distinguish an age of written data), valid bitmap (whose LBAs or logical transfer units contain valid data), etc.

[0022] A memory device comprises multiple memory cells, each of which may store one or more bits of information, depending on the type of memory cell. A memory cell can be programmed (written to) by applying a voltage to it, causing charge to be held by the memory cell, thus allowing modulation of the voltage distribution generated by the memory cell. Furthermore, precise control of the amount of charge stored in a memory cell allows the establishment of multiple threshold voltage levels corresponding to different logic levels, thereby effectively allowing a single memory cell to store multiple bits of information: with 2... n A memory cell operating at different threshold voltage levels can store n bits of information. In this document, "threshold voltage" refers to the voltage level that defines the boundary between two adjacent voltage distributions corresponding to two logic levels. Therefore, a read operation can be performed by comparing the measured voltage exhibited by the memory cell with one or more reference voltage levels to distinguish between two logic levels for a single-level cell and multiple logic levels for a multi-level cell.

[0023] Due to a phenomenon known as slow charge loss, the threshold voltage of a memory cell changes in a timely manner as the cell's charge degrades; this is called "time voltage shift" (because charge degradation causes the voltage distribution to shift along the voltage axis towards a lower voltage level). The threshold voltage changes rapidly at first (immediately after the memory cell is programmed), and then slows down approximately logarithmically with respect to the time elapsed since the cell programming event. Therefore, failure to mitigate the time voltage shift caused by slow charge loss can lead to an increased bit error rate during read operations.

[0024] However, various common implementations fail to adequately address time-voltage shift or employ inefficient strategies that result in high bit error rates and / or other drawbacks. Embodiments of this disclosure address these and other shortcomings by implementing a memory subsystem using a block-family-based error avoidance strategy, thereby significantly improving the bit error rate exhibited by the memory subsystem. According to embodiments of this disclosure, time-voltage shift is selectively tracked for programmed blocks grouped by block families, and an appropriate voltage offset based on the block affiliation of a particular block family is applied to a base read level to perform a read operation. Here, "block family" refers to a group of blocks that have been programmed within a specified time window and a specified temperature window. Since the elapsed time and temperature after programming are major factors affecting time-voltage shift, it is presumed that all blocks and / or partitions within a single block family exhibit similar threshold voltage distributions in the memory cell, and therefore, the same voltage offset will be required to be applied to the base read level for the read operation. "Base read level" herein refers to the initial threshold voltage level exhibited by the memory cell immediately following programming. In some implementations, the base read level may be stored in the metadata of the memory device.

[0025] Block families can be created asynchronously with respect to block programming events. In an illustrative example, a new block family can be created whenever a specified period of time (e.g., a predetermined number of minutes) has elapsed since the creation of the last block family or the reference temperature of the memory unit has changed by more than a specified threshold. The memory sub-system controller can maintain an identifier of the active block family that is associated with the blocks while they are being programmed.

[0026] The memory sub-system controller can periodically perform a calibration process in order to associate each die of each block family with one of a predefined threshold voltage offset interval that is in turn associated with a voltage offset to be applied for read operations. The associations of blocks with block families and of block families and dies with threshold voltage offset intervals can be stored in respective metadata tables maintained by the memory sub-system controller.

[0027] More specifically, the present disclosure addresses the ability to combine block families according to a time-based combination criterion by combining two block families when a predefined period of time has elapsed from the start of the older block family of the two adjacent block families in order to efficiently manage the number of block families within the memory sub-system while avoiding the overhead of a scan process.

[0028] According to embodiments of the present disclosure, the start time and the end time of each block family within the memory sub-system can be recorded to determine whether any two block families are adjacent in time. The start time refers to the time at which a block family is created and assigned as the current block family in the system, and the end time refers to the time at which the block family is no longer the current block family in the system. In an implementation, two block families can be marked as adjacent in time when the difference between the end time of one block family and the start time of the other block family is equal to or less than a predetermined period of time. When two block families are determined to be adjacent in time, the two adjacent block families in time can be combined after a period of time has elapsed from the opening of the older block family of the two adjacent block families (e.g., a multiple of the predetermined period of time used to determine whether black families are adjacent in time). Combining two block families can refer to merging the blocks of the first block family into the second block family and then deleting the first block family.

[0029] In some embodiments, the memory sub-system can have a plurality of threshold voltage offset intervals for classifying block families based on their threshold voltage offsets. A threshold voltage offset interval defines a set of threshold voltage offsets that are to be applied to a base voltage read level in order to perform read operations on blocks in a block family associated with the interval. Each threshold voltage offset interval within the memory sub-system can have a separate time-multiple for determining when to consolidate block families within each threshold voltage offset interval, such that the time-multiple within each interval can be adjusted based on the threshold voltage offset associated with the interval. In one embodiment, two adjacent block families can be combined when a time-based criterion is met (e.g., a time-multiple of a predetermined time period has elapsed from the start of the first block family) without further scanning or verification. In another embodiment, a voltage-based criterion can be determined prior to combining two adjacent block families after a time-based criterion is met. The voltage-based criterion can be a determination of whether a data state metric of one block family is within a predetermined variance of a data state metric of another block family. The data state metric of a block family can be indicative of a temporal voltage shift (TVS) of blocks associated with the block family. If two adjacent block families meet the voltage-based criterion, the two adjacent block families can be combined.

[0030] In yet another embodiment, block families assigned to a new threshold voltage offset interval can be combined according to a time-based combination criterion. On the other hand, block families assigned to an old threshold voltage offset interval can be combined according to a voltage-based combination criterion. Additionally, one or more time-multiples within the memory sub-system 110 can be adjusted based on a temperature of the memory devices of the memory sub-system to accommodate different rates of threshold voltage convergence at higher temperatures, as explained in more detail below.

[0031] Accordingly, advantages of systems and methods implemented in accordance with some embodiments of the disclosure include, but are not limited to, improving bit error rate in read operations by maintaining metadata tracking groups of blocks (block families) that are assumed to exhibit similar voltage distributions. Additionally, the present disclosure enables merging block families together based on proximity in time of a start of a block family and an end of another block family without performing expensive scanning operations, thereby minimizing any additional overhead on the memory sub-system, as described in more detail below.

[0032] Figure 1 An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the disclosure is shown. The memory sub-system 110 can include media such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such.

[0033] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include a solid state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a Secure Digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMM).

[0034] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked consumer device), or such computing device that includes a memory and a processing device (e.g., a processor).

[0035] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 One example of a host system 120 coupled to one memory sub-system 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0036] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, e.g., to write data to the memory sub-system 110 and to read data from the memory sub-system 110.

[0037] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), an open NAND flash interface (ONFI), double data rate (DDR), low power double data rate (LPDDR), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access the memory components (e.g., the memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is shown as an example. In general, a host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0038] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0039] Some examples of non-volatile memory devices (e.g., the memory devices 130) include negative-and (NAND) type flash memories and in-place writeable memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-gridded data access arrays. Additionally, in contrast to many flash-based memories, cross-point non-volatile memories can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0040] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit of data per cell. Other types of memory cells, for example, multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs), can store multiple bits of data per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination of such arrays of memory cells. In some embodiments, a particular memory device can include an SLC portion of memory cells, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to a logical unit of the memory device for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0041] While non-volatile memory devices such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory devices 130 can be based on any other type of non-volatile memory such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non- (NOR) flash memory, as well as electrically erasable programmable read-only memory (EEPROM).

[0042] The memory sub-system controller 115 (controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0043] The memory sub-system controller 115 can include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0044] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although the local memory 119 is illustrated as being internal to the memory sub-system controller 115, in some embodiments, the local memory 119 can be external to the memory sub-system controller 115. Figure 1 In some embodiments, the memory sub-system 110 can include a memory controller 115 to control operation of the memory sub-system 110. In other embodiments, the memory sub-system 110 can not include a memory controller 115, and can rely on external control (e.g., by an external host or by an external processor or controller separate from the memory sub-system).

[0045] Generally, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., a logical block address (LBA), a namespace) and a physical address (e.g., a physical block address) associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory devices 130, as well as convert responses associated with the memory devices 130 into information for the host system 120.

[0046] In some implementations, the memory sub-system 110 can use a striping scheme, according to which each data payload (e.g., user data) is spread across multiple dies of the memory devices 130 (e.g., NAND-type flash memory devices) such that the payload is distributed across a subset of dies, while one or more remaining dies are used to store error correction information (e.g., parity bits). Accordingly, a set of blocks distributed across a set of dies of a memory device using a striping scheme is referred to herein as a “superblock.”

[0047] The memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive and decode addresses from the controller 115 to access the memory devices 130.

[0048] In some embodiments, the memory devices 130 include a local media controller 135 that operates in conjunction with the memory sub-system controller 115 to perform operations on one or more memory cells of the memory devices 130. An external controller (e.g., the memory sub-system controller 115) can externally manage the memory devices 130 (e.g., perform media management operations on the memory devices 130). In some embodiments, the memory devices 130 are managed memory devices that are original memory devices combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0049] According to embodiments of the present disclosure, the memory sub-system 110 includes a block family combination component 113 that can be used to implement techniques for combining block families within the memory sub-system 110 primarily based on time-based criteria. In some embodiments, the block family combination component 113 can record a start time and an end time for each block family within the memory sub-system 110. The start time can be a time at which a block family is created and assigned as a current block family in the system, and the end time is a time at which the block family is no longer a current block family in the system. In implementation, when the block family combination component 113 determines that a difference between an end time of one block family and a start time of another block family is equal to or less than a predetermined time period (e.g., 1 hour), the block family combination component 113 can determine that the two block families are adjacent. In certain implementations, to determine that two block families are adjacent, the block family combination component 113 further determines that the two block families are assigned to a same threshold voltage offset interval. The threshold voltage offset interval defines a set of threshold voltage offsets that are to be applied to a base voltage read level in order to perform read operations on blocks of a corresponding block family.

[0050] After determining that two block families are adjacent, the block family combination component 113 can determine that the two adjacent block families can be combined when a second time period that is a particular multiple of the time period has elapsed. As an example, when an opening of an older block family of the two adjacent block families has elapsed for 24 hours (e.g., the multiple of time is 24), the block family combination component 113 can determine that the two adjacent block families can be combined. Combining the two block families can refer to merging blocks of a first block family into a second block family and then deleting the first block family.

[0051] In certain implementations, each threshold voltage offset bin within the memory sub-system can have a separate time multiplier for determining when to combine the family of blocks assigned to the respective threshold voltage offset bin, such that the time multiplier for each bin can be adjusted based on the threshold voltage offset associated with the bin, as explained in greater detail below. In this case, the two family of blocks assigned to the first threshold voltage offset bin (e.g., A and B) can be combined based on the time multiplier associated with the first threshold voltage offset bin, while the two family of blocks assigned to the second threshold voltage offset bin (e.g., C and D) can be combined based on the time multiplier associated with the second threshold voltage offset bin.

[0052] In one implementation, the family of blocks combining component 113 can combine two adjacent families of blocks when the second time period has elapsed without further scanning or verification. In another implementation, when the family of blocks combining component 113 determines that the second time period has elapsed, the family of blocks combining component 113 can make an additional determination to find out whether the two adjacent families of blocks meet a voltage-based criterion before combining the two families of blocks. As an example, the voltage-based criterion can be a determination of whether the data state metric of one family of blocks is within a predetermined variance of the data state metric of another family of blocks. The data state metric of a family of blocks can be indicative of the temporal voltage shift (TVS) of the blocks associated with the family of blocks. In this case, if the two adjacent families of blocks meet the voltage-based criterion, the family of blocks combining component 113 can combine the two adjacent families of blocks.

[0053] In yet another implementation, the block family combination component 113 can use a time-based combination criterion for new threshold voltage offset intervals (i.e., intervals associated with threshold voltage offsets corresponding to post-program times shorter than a threshold) and a voltage-based combination criterion for old threshold voltage offset intervals (i.e., intervals associated with threshold voltage offsets corresponding to post-program times longer than a threshold). When a given block family has a short post-program time, the threshold voltage offset associated with the block family can change more frequently, so measuring data states to determine a voltage-based criterion can be inaccurate and / or expensive to perform. On the other hand, when a block family has a long post-program time, the threshold voltage offset associated with the block family can change less frequently, so measuring data states to determine a voltage-based criterion for this block family can be more accurate and / or less expensive than the former case. Thus, to combine two block families, the block family combination component 113 can utilize a time-based combination criterion for new threshold voltage offset intervals (e.g., a particular time period associated with a start time of one of the two block families and an end time of the other block family). Similarly, the block family combination component 113 can use a voltage-based combination criterion for old threshold voltage offset intervals (e.g., by measuring and comparing data state metrics for each block family), as explained in more detail below.

[0054] In some implementations, the block family combination component 113 can adjust one or more time multipliers within the memory sub-system 110 based on a temperature of the memory devices 130-140. As an example, when a memory device 130 is kept at a high temperature, the convergence of threshold voltages associated with blocks of the memory device 130 can occur at a faster rate than at normal / lower temperatures. Thus, upon detecting a high temperature of the memory device 130, the block family combination component 113 can shorten one or more time multipliers associated with the memory device 130 to reflect the faster convergence of threshold voltages.

[0055] Figure 2 Time voltage shifts due to slow charge loss exhibited by three-level memory cells are shown. While Figure 2 The illustrative example of FIG. 1 utilizes three-level cells, but the same observations can be made, and thus, the same remedies can be applied to single-level cells and any memory cells having multiple levels.

[0056] A memory cell can be programmed (written to) by applying a voltage (e.g., a program voltage) to the memory cell, resulting in a charge stored by the memory cell. Precise control of the amount of charge stored by the memory cell allows the memory cell to have multiple threshold voltage levels corresponding to different logic levels, thus effectively allowing a single memory cell to store multiple bits of information. In 2n A memory cell capable of operating at n different threshold voltage levels is capable of storing n bits of information.

[0057] Each of graphs 210 and 230 shows a programmed voltage distribution 220A-420N (also referred to herein as a "program distribution" or "voltage distribution" or "distribution" or "level") of memory cells programmed with a corresponding write level (which can be assumed to be at the midpoint of the program distribution) to encode a corresponding logic level. Program distributions 220A to 220N can illustrate a range of threshold voltages (e.g., a normal distribution of threshold voltages) for memory cells programmed with a corresponding write level (e.g., program voltage). To distinguish between adjacent program distributions (corresponding to two different logic levels), a read threshold voltage level is defined (shown by the vertical dashed line) such that any measured voltage below the read threshold level is associated with one of the pair of adjacent program distributions, while any measured voltage greater than or equal to the read threshold level is associated with the other program distribution of the pair of adjacent distributions.

[0058] In graph 210, eight states of memory cells are shown below the corresponding program distributions (except for the state labeled ER, which is the erased state, for which no distribution is shown). Each state corresponds to a certain logic level. Read threshold voltage levels are labeled Va-Vh. As shown, any measured voltage below Va is associated with the ER state. States labeled P1, P2, P3, P4, P5, P6, and P7 correspond to distributions 22A-220N, respectively.

[0059] Time after program (TAP) will refer herein to the time from when a cell has been written and is the primary driver of time voltage shift (TVS). TVS captures SCL as well as other charge loss mechanisms. TAP can be estimated (e.g., inferred from data state metrics) or directly measured (e.g., from controller clock). A cell, block, page, block family, etc. is new (or relatively new) if it has a (relatively) small TAP and old (or relatively old) if it has a (relatively) large TAP. A time slice is the duration between two TAP points during which measurements can be made (e.g., X to Y minutes or hours after program to perform a reference calibration). A time slice can be referenced by its center point.

[0060] As can be seen from example graphs 210 and 230, which respectively reflect the time after programming (TAP) 0 (immediately following programming) and T hours TAP (where T is the number of hours), the programming distribution changes over time primarily due to slow charge loss. To reduce the read bit error rate, the corresponding read threshold voltage is adjusted to compensate for the shift in the programming distribution, which is shown by the vertical dashed line. In various embodiments of this disclosure, the time voltage shift is selectively tracked for the die group based on measurements performed at one or more representative dies of the die group. Based on measurements of the time voltage shift and operating temperature of the die group's dies, which are characteristic of the die group, the read threshold voltage offset for reading the memory cells of the die group's dies is updated and applied to the base read threshold level to perform a read operation.

[0061] Figure 3 A graph 300 illustrates the dependence of the threshold voltage offset 310 on the programming time 320 (i.e., the time elapsed since the block was programmed). (As shown in the graph 300) Figure 3 The diagram illustrates how blocks in a memory device are grouped into families 330A-330N, such that each family contains one or more blocks programmed within a specified time and temperature window. As described above, since the elapsed time and temperature after programming are the primary factors affecting the time-voltage shift, it is presumed that all blocks and / or partitions within a single family 310 exhibit similar threshold voltage distributions in the memory cells and therefore will require the same voltage offset for read operations.

[0062] Block families can be created asynchronously relative to block programming events. In the illustrative example, whenever a specified time period (e.g., a predetermined number of minutes) has elapsed since the creation of the last block family, or whenever the reference temperature of a memory cell (which is updated at specified time intervals) has changed by more than a specified threshold since the creation of the current block family, then... Figure 1 The memory subsystem controller 115 can create new block families.

[0063] The newly created block families can be associated with interval 0. Then, the memory subsystem controller can periodically perform a calibration process to ensure that each die in each block family is offset from a predefined threshold voltage interval (within...). Figure 3 In the illustrative example, one of the intervals (0 to 7) is associated with the voltage offset to be applied to the read operation. The association between blocks and block families, as well as between block families and dies, and the threshold voltage offset intervals can be stored in the corresponding metadata tables maintained by the memory subsystem controller.

[0064] Figure 4 A set of predefined threshold voltage offset intervals (intervals 0 to 9) are schematically illustrated according to embodiments of the present disclosure. Figure 4Illustratively, the threshold voltage offset plot can be subdivided into a plurality of threshold voltage offset intervals, such that each interval corresponds to a predetermined range of threshold voltage offsets. Although Figure 4 The illustrative example defines ten intervals, but in other implementations various other numbers of intervals can be used (e.g., 64 intervals). Based on a periodically performed calibration procedure, the memory sub-system controller associates each die of each block family with a certain threshold voltage offset interval that defines a set of threshold voltage offsets to be applied to a base voltage read level in order to perform read operations, as described in greater detail herein below.

[0065] Figure 5 Illustratively, block family management operations implemented by a block family manager component of a memory sub-system controller operating in accordance with embodiments of the present disclosure are shown. As Figure 5 Illustratively, the block family manager 510 can maintain in a memory variable an identifier 520 of an active block family that is associated with one or more blocks of a cursor 530A-530K as the cursor is programmed. A "cursor" herein is to be broadly interpreted to refer to a location on a memory device to which data is written.

[0066] The memory sub-system controller can utilize a power-on minute (POM) clock to track a creation time of a block family. In some implementations, in addition to the POM clock, a less accurate clock that continues to run when the controller is in various low power states can be utilized, such that upon the controller waking up from a low power state, the POM clock is updated based on the less accurate clock.

[0067] Accordingly, upon initialization of each block family, a current time 540 is stored in a memory variable as a block family start time 550. When the blocks are programmed, the current time 540 is compared to the block family start time 550. In response to detecting that the difference between the current time 540 and the block family start time 550 is greater than or equal to a specified time period (e.g., a predetermined number of minutes), the memory variable storing the active block family identifier 520 is updated to store a next block family number (e.g., a next sequential integer number), and the memory variable storing the block family start time 550 is updated to store the current time 540.

[0068] The block family manager 510 can further periodically compute a difference between the high temperature 560 and the low temperature 570. In response to determining that the difference between the high temperature 560 and the low temperature 570 is higher than or equal to a specified temperature threshold, the block family manager 510 can create a new active block family: the memory variable storing the active block family identifier 520 is updated to store the next block family number (e.g., the next sequential integer number), the memory variable storing the block family start time 550 is updated to store the current time 540, and the high temperature 560 and low temperature 570 variables are updated to store the values of the current temperatures of the selected dies of the memory device.

[0069] The block family manager 510 can further periodically compute a difference between the high temperature 560 and the low temperature 570. In response to determining that the difference between the high temperature 560 and the low temperature 570 is higher than or equal to a specified temperature threshold, the block family manager 510 can create a new active block family: the memory variable storing the active block family identifier 520 is updated to store the next block family number (e.g., the next sequential integer number), the memory variable storing the block family start time 550 is updated to store the current time 540, and the high temperature 560 and low temperature 570 variables are updated to store the values of the current temperatures of the selected dies of the memory device.

[0070] In programming a block, the memory sub-system controller associates the block with the currently active block family. The association of each block with the corresponding block family is reflected by the block family metadata 580, as described below with reference to Figure 7 Described in greater detail.

[0071] As described herein above, based on the periodically performed calibration procedure, the memory sub-system controller associates each die of each block family with a certain threshold voltage offset interval, the threshold voltage offset interval defining a set of threshold voltage offsets to be applied to a base voltage read level in order to perform a read operation. The calibration procedure involves performing read operations with different threshold voltage offsets with respect to a specified number of randomly selected blocks within the block family being calibrated, and picking the threshold voltage offset that minimizes the error rate of the read operations.

[0072] Figure 6 Selecting block families for calibration according to embodiments of the disclosure is schematically illustrated. As Figure 6 It is schematically illustrated that the memory sub-system controller can limit the calibration operations to the oldest block family in each interval (e.g., block family 610 in interval 0 and block family 620 in interval 1), which is the oldest block family, to drift to the next interval before any other block family of the current interval due to slow charge loss.

[0073] Figure 7An instance metadata maintained by a memory sub-system controller to associate blocks and / or partitions with block families according to embodiments of the present disclosure is illustratively shown. As Figure 7 As illustratively shown, the memory sub-system controller can maintain a super block table 710, a family table 720, and an offset table 730.

[0074] Each record of the super block table 710 specifies a block family associated with a specified super block and partition combination. In some embodiments, the super block table record can further contain a time and temperature value associated with the specified super block and partition combination.

[0075] The family table 720 is indexed by block family number, such that each record of the family table 720 specifies, for the block family to which the record's index refers, a set of threshold voltage offset intervals associated with the respective dies of the block family. In other words, each record of the family table 720 contains a vector, each element of which specifies a threshold voltage offset interval associated with the die to which the vector element's index refers. The threshold voltage offset intervals associated with a block family die can be determined by a calibration process, as described in greater detail herein above.

[0076] Finally, the offset table 730 is indexed by interval number. Each record of the offset table 730 specifies a set of threshold voltage offsets (e.g., for TLC, MLC, and / or SLC) associated with the threshold voltage offset interval.

[0077] When two block families are combined, e.g., by merging the blocks of a first block family into a second block family followed by deleting the first block family, the metadata tables 710-730 can be updated as a result of combining the two block families. For example, the super block table 710 can be updated to reflect that the super block and partition combination of the first block family should be associated with the second block family. Similarly, the family table 720 can be updated to delete the record associated with the first block family from the family table 720.

[0078] The metadata tables 710-730 can be stored on the one or more memory devices 130 of Figure 1 In some embodiments, at least a portion of the metadata tables can be cached in a local memory 119 of the memory sub-system controller 115 of Figure 1

[0079] ​In operation, upon receiving a read command, the memory sub-system controller determines a physical address corresponding to a logical block address (LBA) specified by the read command. The metadata table traversal is performed with physical address components such as a physical block number and a die identifier: first, the superblock table 710 is used to identify a block family identifier corresponding to the physical block number; next, the block family identifier is used as an index to the family table 720 in order to determine a threshold voltage offset interval associated with the block family and die; finally, the identified threshold voltage offset interval is used as an index to the offset table 730 in order to determine a threshold voltage offset corresponding to the interval. The memory sub-system controller can then superimpose the identified threshold voltage offset to a base voltage read level in order to perform the requested read operation.

[0080] In Figure 7 In the illustrative example, the superblock table 710 maps partition 0 of superblock 0 to block family 4, which is used as an index to the family table 720 in order to determine that die 0 is mapped to interval 3. The latter value is used as an index to the offset table in order to determine the threshold voltage offset value for interval 3.

[0081] Figure 8 A sequence diagram depicting an event flow for an example method 800 for combining two block families when a time-based combination criterion is met, in accordance with one or more aspects of the present disclosure. The method 800 can be performed by processing logic that includes hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processor to simulate the hardware), or a combination thereof. In some embodiments, the method 800 is performed by the block family combination component 113 of Figure 1

[0082] The method 800 begins at operation 810. At operation 810, the processing logic starts a new block family BF 1 at time TO, allocating BF 1 with blocks programmed between TO and the time at which BF 1 ends. The processing logic can further record the time TO at which BF 1 starts in order to utilize TO when calculating a time-based combination criterion for combining BF 1 with another block family, as explained in greater detail herein.

[0083] ​At operation 811, the processing logic ends BF 1 at time Tl by determining that another block family can be the current active block family in the memory sub-system. In an implementation, BF 1 can end upon determining that a predetermined duration of the current active block family has elapsed since TO. At operation 812, the processing logic starts a new block family, BF 2, at time T2 by assigning BF 2 as the current active block family in the memory sub-system. In one example, BF 2 can be the block family that immediately follows BF 1 as the current active block family. In another example, BF 2 can be the block family that starts at some point in time after BF 1 ends but not necessarily immediately after BF 1 as the current active block family.

[0084] At operation 814, the processing logic ends BF 2 at time T3 by determining that a third block family can be the current active block family in the memory sub-system. The processing logic can further record time T3 as the end time of BF 2 in order to utilize T3 in calculating a time-based combination criterion for combining BF 1 and BF 2. In an implementation, the processing logic can determine a time period between T3, at which BF 2 ends, and TO, at which BF 1 starts. If the determined time period is equal to or less than a predetermined number of minutes (e.g., 60 minutes), the processing logic can determine that BF 1 and BF 2 are adjacent block families and can combine the two block families after a particular time-based criterion has elapsed since BF 2 ends. In an example, the time-based criterion can be a multiple of the determined time period of T3-T0. In this case, the processing logic can determine that since BF 1 and BF 2 are adjacent block families, the threshold voltages of the two block families are likely to converge to similar values after a particular time period, which can be calculated based on the difference between the start time and the stop time of adjacent block families.

[0085] At operation 818, the processing logic can determine a multiple of time has elapsed since T3 at time T4, and then the processing logic can combine BF 1 and BF 2. In an implementation, the processing logic can combine the two block families by merging the blocks of BF 1 into BF 2 (e.g., by assigning the blocks of BF 1 to BF 2) and then deleting BF 1 from the block family metadata table of the memory sub-system controller.

[0086] Figure 9is a flowchart of an example method of performing block family combination in a memory sub-system according to time-based combination criteria and voltage-based combination criteria according to some embodiments of the present disclosure. The method 900 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 900 is performed by the block family combination component 113 of FIG. 1. Figure 1 Although illustrated in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, it is to be understood that the illustrated embodiments are merely examples, and that the illustrated operations can be performed in a different order, and / or concurrently with each other. Additionally, one or more operations can be omitted in some embodiments. Thus, not all of the operations illustrated in any of the embodiments are required, and other processing flows are possible.

[0087] At operation 910, the processing logic determines a time Tl at which the block family BF 1 starts and a time T2 at which the block family BF 2 ends. In an implementation, the processing logic can determine that BF 1 and BF 2 are adjacent when the difference between the end time of BF 2 and the start time of BF 1 is equal to or less than a predetermined time period (e.g., 1 hour).

[0088] Thus, at operation 930, the processing logic determines whether the difference between T2 and Tl meets a proximity threshold (e.g., 1 hour) to determine whether the two block families are adjacent. At operation 940, the processing logic determines that BF 2 and BF 1 are adjacent because (T2-Tl) meets the proximity condition. The processing logic can then mark BF 1 and BF 2 as adjacent block families, for example, in a metadata table of the memory sub-system.

[0089] At operation 950, assuming that BF 1 and BF 2 are adjacent, the processing logic can determine whether a particular multiple of the time (T2-Tl) has elapsed since Tl (the start of BF 1). In an implementation, the processing logic can determine that BF 1 and BF 2 meet the time-based combination criteria when a multiple (e.g., 24) of the difference between T2 and Tl has elapsed, as explained in greater detail above.

[0090] At operation 955, the processing logic can further determine whether the voltage-based combination criteria are met by determining that the time-based combination criteria have elapsed. In one embodiment, meeting the voltage-based criteria can be achieved by determining whether the data state metric of BF 1 is within a predetermined variance of the data state metric of BF 2. The data state metric of a block family can indicate a time-voltage shift (TVS) of the blocks associated with the block family. For example, if the average threshold voltage of BF 1 differs from the average threshold voltage of BF 2 by 3 units of digital-to-analog conversion (DAC), then BF 1 and BF 2 meet the voltage-based combination criteria.

[0091] At operation 960, when the processing logic determines that BF 1 and BF 2 meet the voltage-based combination criteria, the processing logic can combine BF 1 and BF 2, e.g., by merging the blocks of BF 1 into BF 2 and then deleting BF 1, as explained in greater detail herein.

[0092] Figure 10 is a flow diagram of an example method of performing block family combination in a memory sub-system according to time-based combination criteria according to some embodiments of the present disclosure. The method 1000 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 1000 is performed by the block family combination component 113 of FIG. 1. Figure 1 is a flow diagram of an example method of performing block family combination in a memory sub-system according to time-based combination criteria according to some embodiments of the present disclosure. The method 1000 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 1000 is performed by the block family combination component 113 of FIG. 1.

[0093] At operation 1010, the processing logic determines that two block families in a group of block families within a memory device meet a proximity condition. In an embodiment, the proximity condition can be determining that a difference between a start time of one block family and an end time of another block family does not exceed a predetermined time period (e.g., 1 hour), as explained in greater detail herein.

[0094] At operation 1020, based on determining that the two block families meet the proximity condition, the processing logic determines that the two block families are adjacent and thus can be combined when the time-based combination criteria are met. In an embodiment, the processing logic can determine that the two block families can be combined when a second time period has elapsed since the start of the first block family. For example, the second time period can be a multiple of the predetermined time period (e.g., 24 hours).

[0095] At operation 1030, upon determining that the time-based combination criteria has been satisfied (e.g., 24 hours have passed since the first chunk family began), the processing logic can determine that the two chunk families can be combined. In embodiments, the processing logic can merge the first chunk family and the second chunk family by assigning the chunks of the first chunk family to the second chunk family and then deleting the first chunk family, as explained in greater detail above.

[0096] Figure 11 is a flow diagram of an example method of performing chunk family combination in a memory sub-system according to time-based combination criteria or voltage-based combination criteria according to some embodiments of the present disclosure. The method 1100 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a computing device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 1100 is performed by the chunk family combination component 113 of FIG. 1. Figure 1 is a flow diagram of an example method of performing chunk family combination in a memory sub-system according to time-based combination criteria or voltage-based combination criteria according to some embodiments of the present disclosure. The method 1100 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a computing device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 1100 is performed by the chunk family combination component 113 of FIG. 1.

[0097] At operation 1110, the processing logic determines that two chunk families, BF 1 and BF 2, of threshold voltage bin 1 of the memory device meet a proximity condition. In embodiments, the proximity condition can be a determination that a difference between a start time of BF 1 and an end time of BF 2 does not exceed a predetermined time period (e.g., 1 hour), as explained in greater detail herein.

[0098] At operation 1120, the processing logic determines whether Bin 1 meets the age criteria. In certain embodiments, the age of a threshold voltage offset interval is determined based on the post-program time value associated with the threshold voltage offset interval. Thus, the age criteria for Bin 1 can be a determination of whether the post-program time associated with Bin 1 exceeds a threshold. When the post-program time for a given threshold voltage offset interval is short, the frequency of changes in the threshold voltage offset associated with the interval can be high, and thus measuring data states to determine the voltage-based criteria for the block family assigned to the interval can be inaccurate and / or expensive to perform. On the other hand, when the post-program time for an interval is long, the frequency of changes in the threshold voltage offset associated with the interval can be low, and thus measuring data states to determine the voltage-based criteria for the block family assigned to the interval can be more accurate and / or less expensive than when the post-program time is short. Thus, the processing logic can use a time-based combination criteria to combine block families assigned to new intervals, and a voltage-based combination criteria to combine block families assigned to old intervals.

[0099] Thus, at operation 1130, when the processing logic determines that the age of interval 1 is below a threshold (i.e., a new interval), the process can determine whether BF 1 and BF 2 meet a time-based combination criteria, e.g., a certain time period has elapsed associated with the start time of BF 1 and the end time of BF 2, to combine BF 1 and BF 2. At operation 1160, if BF 1 and BF 2 meet the time-based combination criteria, the processing logic can merge BF 1 and BF 2, as explained in greater detail above.

[0100] On the other hand, at operation 1140, when the processing logic determines that the age of Bin 1 is not below a threshold (i.e., an old interval), the process can determine whether BF 1 and BF 2 meet a voltage-based combination criteria, e.g., by measuring and comparing data state metrics of BF 1 and BF 2, in order to combine BF 1 and BF 2. At operation 1160, if BF 1 and BF 2 meet the voltage-based combination criteria, the processing logic can merge BF 1 and BF 2, as explained in greater detail above.

[0101] Figure 12 An example machine is shown in FIG. 12, in which an instance of the machine can execute a set of instructions that are arranged to result in machine operations, in accordance with any one or more of the methods discussed herein. In some embodiments, the computer system 1200 corresponds to a host system (e.g., host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to the host system 120 of FIG. 1). Figure 1 An example machine is shown in FIG. 12, in which an instance of the machine can execute a set of instructions that are arranged to result in machine operations, in accordance with any one or more of the methods discussed herein. In some embodiments, the computer system 1200 corresponds to a host system (e.g., host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to the host system 120 of FIG. 1). Figure 1 An example machine is shown in FIG. 12, in which an instance of the machine can execute a set of instructions that are arranged to result in machine operations, in accordance with any one or more of the methods discussed herein. In some embodiments, the computer system 1200 corresponds to a host system (e.g., host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to the host system 120 of FIG. 1). Figure 1The machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet, for example, by a wired (e.g., LAN) or wireless (e.g., cellular) connection, as

[0102] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions (sequentially or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0103] The example computer system 1200 includes a processing device 1202, a main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1218, which communicate with each other via a bus 1230.

[0104] Processing device 1202 represents one or more general -purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 1202 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 1202 is configured to execute instructions 1226 for performing the operations and steps discussed herein. The computer system 1200 can further include a network interface device 1208 to communicate over the network 1220.

[0105] The data storage system 1218 can include a machine-readable storage medium 1224 (also known as a computer-readable medium) on which is stored one or more sets of instructions 1226 or software embodying any one or more of the methodologies or functions described herein. The instructions 1226 can also reside, completely or at least partially, within the main memory 1204 and / or within the processing device 1202 during execution thereof by the computer system 1200, the main memory 1204 and the processing device 1202 also constituting machine-readable storage media. The machine-readable storage medium 1224, data storage system 1218, and / or main memory 1204 can correspond to memory subsystem 110 of FIG. 1. Figure 1

[0106] In one embodiment, the instructions 1226 include instructions to implement functionality corresponding to the block family combination component 113 of FIG. 1. Figure 1 While the machine-readable storage medium 1224 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "computer-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0107] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These

[0108] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0109] ​The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0110] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0111] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0112] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A memory system comprising: Memory devices; as well as A processing device operatively coupled to the memory device, the processing device being configured to perform operations including: Determine that a first block family and a second block family of a plurality of block families of the memory device meet a proximity condition, wherein the first block family is associated with a first set of voltage offsets applied to a first plurality of blocks of the first block family, and wherein the second block family is associated with a second set of voltage offsets applied to a second plurality of blocks of the second block family; Determine whether the first block family and the second block family meet a time-based combination criterion, wherein the time-based combination criterion is based on a multiple of the time period elapsed since the start of the first block family, wherein the multiple is adjusted based on the temperature of the memory device; as well as In response to determining that the first block family and the second block family satisfy the time-based combination criterion, the first block family and the second block family are merged.

2. The memory system of claim 1, wherein the proximity condition includes a time period between the time at which the first block family begins and the time at which the second block family ends.

3. The memory system of claim 2, wherein the multiplier is adjusted based on the voltage offset within a threshold voltage offset range.

4. The memory system of claim 1, wherein the first block family and the second block family are assigned to a first threshold voltage offset interval.

5. The memory system of claim 4, wherein the operation further comprises: Determine that the third and fourth blocks meet the proximity condition; In response to determining that the third and fourth blocks are assigned to the second threshold voltage offset interval, it is determined whether the third and fourth blocks satisfy a second time-based combination criterion; and In response to determining that the third block family and the fourth block family satisfy the second time-based combination criterion, the third block family and the fourth block family are merged.

6. The memory system of claim 4, wherein the operation further comprises: Determine that the third and fourth blocks meet the proximity condition; In response to determining that the third and fourth blocks are assigned to a second threshold voltage offset interval, it is determined whether the third and fourth blocks satisfy a voltage-based combination criterion, wherein the second threshold voltage offset interval corresponds to a certain post-programming time, the post-programming time being longer than the second post-programming time corresponding to the first threshold voltage offset interval; as well as In response to determining that the third and fourth blocks satisfy the voltage-based combination criterion, the third and fourth blocks are merged.

7. The memory system of claim 1, wherein the operation further comprises: The time-based combination criterion is updated after a change in the temperature of the memory device is detected.

8. A method for operating a memory device, comprising: Determine that a first block family and a second block family of a plurality of block families of the memory device meet a proximity condition, wherein the first block family is associated with a first set of voltage offsets applied to a first plurality of blocks of the first block family, and wherein the second block family is associated with a second set of voltage offsets applied to a second plurality of blocks of the second block family; Determine whether the first block family and the second block family meet a time-based combination criterion, wherein the time-based combination criterion is based on a multiple of the time period elapsed since the start of the first block family, wherein the multiple is adjusted based on the voltage offset associated with the threshold voltage offset range; In response to determining that the first block family and the second block family satisfy the time-based combination criterion, it is determined whether the first block family and the second block family satisfy the voltage-based combination criterion; and In response to determining that the first block family and the second block family satisfy the voltage-based combination criterion, the first block family and the second block family are merged.

9. The method of claim 8, wherein the proximity condition includes a time period between the time at which the first block family begins and the time at which the second block family ends.

10. The method of claim 8, wherein the multiplier is adjusted based on the temperature of the memory device.

11. The method of claim 8, wherein the first block family and the second block family are assigned to the threshold voltage offset interval.

12. The method of claim 11, further comprising: Determine that the third and fourth blocks meet the proximity condition; In response to determining that the third and fourth blocks are assigned to a second threshold voltage offset interval, it is determined whether the third and fourth blocks satisfy a second time-based combination criterion associated with the second threshold voltage offset interval; and In response to determining that the third and fourth blocks satisfy the second time-based combination criterion and the voltage-based combination criterion, the third and fourth blocks are merged.

13. The method of claim 8, wherein the voltage-based combination criterion is based on a data state metric for each of the plurality of blocks.

14. The method of claim 8, further comprising: The time-based combination criterion is updated after a change in the temperature of the memory device is detected.

15. A non-transitory computer-readable storage medium including instructions that, when executed by a processing means, cause the processing means to perform the following operations: Determine that the first block family and the second block family of the plurality of block families of the memory device meet the proximity condition; Determine whether the first block family and the second block family satisfy the time-based combination criterion corresponding to the proximity condition; In response to determining that the first block family and the second block family satisfy the time-based combination criterion, the first block family and the second block family are merged, wherein the first block family and the second block family are assigned to a first threshold voltage offset interval, and wherein the first threshold voltage offset interval defines a voltage offset to be applied for a read operation, the voltage offset being the same for all block families associated with the first threshold voltage offset interval; Determine that the third and fourth blocks meet the proximity condition; In response to determining that the third and fourth blocks are assigned to a second threshold voltage offset interval, it is determined whether the third and fourth blocks satisfy a voltage-based combination criterion, wherein the second threshold voltage offset interval corresponds to a second post-programming time, which is longer than a first post-programming time corresponding to the first threshold voltage offset interval; and In response to determining that the third and fourth blocks satisfy the voltage-based combination criterion, the third and fourth blocks are merged.

16. The non-transitory computer-readable storage medium of claim 15, wherein the proximity condition includes a time period between the start time of the first block family and the end time of the second block family.

17. The non-transitory computer-readable storage medium of claim 16, wherein the time-based combination criterion includes a multiple of the time period.

18. The non-transitory computer-readable storage medium of claim 15, wherein the processing apparatus further performs the following operations: In response to determining that the third and fourth blocks are assigned to the second threshold voltage offset interval, it is determined whether the third and fourth blocks satisfy a second time-based combination criterion; and In response to determining that the third block family and the fourth block family satisfy the second time-based combination criterion, the third block family and the fourth block family are merged.

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