Semiconductor devices and methods

Abstract

This application provides semiconductor devices and methods. Embodiments include a semiconductor device comprising a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions located on the substrate and disposed between the plurality of fin structures. The device further includes a plurality of gate structures located on the plurality of isolation regions. The device also includes a plurality of epitaxial structures located on the plurality of first fin structures. The device further includes a plurality of contact structures located on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures, and the plurality of contact structures are elements of one or more resonators.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more specifically to semiconductor devices and methods. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by the following steps: sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit elements and assemblies thereon.

[0003] The semiconductor industry is constantly increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to one aspect of this application, a semiconductor device is provided, comprising: a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures; a plurality of isolation regions located on the substrate and disposed between the plurality of fin structures; a plurality of gate structures located on the plurality of isolation regions; a plurality of epitaxial structures located on the plurality of first fin structures; and a plurality of contact structures located on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures, and the plurality of contact structures are elements of one or more resonators.

[0005] According to another aspect of this application, a semiconductor device is provided, comprising: a substrate having a first surface and a second surface; an isolation structure located above the first surface of the substrate; a plurality of gate structures located above the isolation structure; a resonator including a plurality of first fin structures, at least one epitaxial structure, and a contact structure, the plurality of first fin structures being located on the first surface of the substrate, the at least one epitaxial structure being located on the first fin structure, and the contact structure being located on the at least one epitaxial structure; and at least one second fin structure being located on the first surface of the substrate, and the at least one second fin structure being disposed between two of the plurality of first fin structures, the at least one second fin structure having no epitaxial structure.

[0006] According to another aspect of this application, a method for fabricating a semiconductor device is provided, comprising: forming a plurality of fin structures extending from a substrate, the fin structures having a plurality of first fin structures and a plurality of second fin structures; forming a plurality of isolation regions located on the substrate and disposed between the plurality of fin structures; forming a plurality of gate structures on the plurality of isolation regions; growing a plurality of epitaxial structures on the plurality of first fin structures, the plurality of second fin structures having no epitaxial structures; and forming a plurality of contact structures on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures, and the plurality of contact structures are elements of one or more resonators. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a FinFET according to some embodiments is illustrated in a 3D view.

[0009] Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17 This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22 , Figure 23 , Figure 24 and Figure 25 Top views and cross-sectional views of various configurations of semiconductor devices according to some embodiments are illustrated.

[0011] Figure 26 and Figure 27 The illustration shows top views of various configurations of semiconductor devices according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] In addition, for ease of description, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to describe the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0014] Before detailing the illustrated embodiments, certain advantageous features and aspects of embodiments of this disclosure will be summarized. In general, this disclosure discloses a device and a method for fabricating a resonator using a fin structure, which can be used as a frequency source in a circuit. In some embodiments, the frequency generated by the device is determined by the fin material and the fin spacing. The device design allows for better integration of this structure into complementary metal-oxide-semiconductor (CMOS) process flows. The disclosed embodiments allow the device to generate more than one frequency in a single structure, while also simplifying the process and eliminating the need for special packaging.

[0015] The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0016] Figure 1 An example of a FinFET according to some embodiments is illustrated in a three-dimensional view. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fin 52 protrudes above and from between adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may be used to refer only to the semiconductor substrate or may be used to refer to the semiconductor substrate including the isolation regions. Furthermore, although the fin 52 is illustrated as a single, continuous material with respect to the substrate 50, the fin 52 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 52 refers to the portion extending between adjacent isolation regions 56.

[0017] The gate dielectric layer 92 runs along the sidewall of the fin 52 and is located above the top surface of the fin 52, and the gate electrode 94 is located above the gate dielectric layer 92. Source / drain regions 82 are arranged on opposite sides of the fin 52 (relative to the gate dielectric layer 92 and the gate electrode 94). Figure 1 The reference cross sections used in the following figures are further illustrated. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction perpendicular to, for example, the direction of the current between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 52 and in the direction of the current between, for example, the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, the following figures refer to these reference cross sections.

[0018] Some embodiments discussed herein are discussed in the context of FinFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs, nanostructured (e.g., nanosheets, nanowires, gate-around-the-loop, etc.) field-effect transistors (NSFETs), etc.

[0019] Figures 2 to 17 This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6 and Figure 7 The diagram shows Figure 1 The figure shows a reference cross-section AA, but multiple fins / FinFETs are also shown. Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A It is along Figure 1 The reference cross-section AA shown in the diagram is illustrated in the middle, and Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 14C , Figure 15B and Figure 16B It is along Figure 1 The diagram in the middle is similar to the cross-section of BB, but it shows multiple fins / FinFETs. Figure 10C , Figure 10D , Figure 10E and Figure 17 It is along Figure 1 The reference cross-section CC shown in the figure is illustrated, but multiple fins / FinFETs are also shown.

[0020] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate (typically a silicon or glass substrate). Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium indium arsenide; or combinations thereof.

[0021] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor or an n-type FinFET. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor or a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P (as illustrated by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-type region 50N and the p-type region 50P.

[0022] exist Figure 3A and Figure 3B In this embodiment, fins 52 are formed in the substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. Etching can be anisotropic.

[0023] The fin can be patterned using any suitable method. For example, the fin 52 can be patterned using one or more photolithography processes, including dual patterning or multi-patterning processes. Typically, dual patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin. In some embodiments, a mask (or other layer) may be retained on the fin 52.

[0024] like Figure 3B As illustrated, substrate 50 has device regions 50N / P (e.g., the regions containing n-type region 50N and p-type region 50P) and resonator device regions 50R. Device regions 50N / P can be regions used to form logic devices, memory devices, input / output devices, etc. Resonator device regions 50R can be used to form resonator devices. Device regions 50N / P can be physically separated from resonator device regions 50R (as illustrated by separator 53), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between these two regions. Although resonator device regions 50R are not shown in each step, device regions 50N / P and resonator device regions 50R are formed simultaneously using the same process.

[0025] like Figure 3BAs illustrated in the diagram, some fins in the resonator device region 50R can be removed by a fin-cutting process. In some embodiments, the fin-cutting process includes masking the fins 52 that are desired to be retained, while etching the exposed fins 52. In some embodiments, masking can be achieved using photoresist and / or other masks (not shown). For example, a photoresist can be formed over the fins 52 and patterned to expose the fins to be removed. An etching process can then be performed to remove the exposed fins 52. Etching can be any acceptable etching process, such as RIE, NBE, or combinations thereof. Etching can be anisotropic or isotropic. After etching, the photoresist can be removed.

[0026] exist Figure 4 In this embodiment, an insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., depositing a CVD-based material in a remote plasma system and post-curing it to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 50 and the fins 52. Subsequently, a filler material, such as those discussed above, may be formed over the liner.

[0027] exist Figure 5 In this process, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back processes, or combinations thereof, can be used. The planarization process exposes the fin 52 such that, after the planarization process is completed, the fin 52 is flush with the top surface of the insulating material 54. In embodiments where the mask remains on the fin 52, the planarization process may expose or remove the mask such that, after the planarization process is completed, the top surface of the mask or the top surface of the fin 52 is flush with the top surface of the insulating material 54, respectively.

[0028] exist Figure 6In this design, insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The insulating material 54 is recessed such that the upper portions of fins 52 in the n-type region 50N and p-type region 50P protrude between adjacent STI regions 56. Furthermore, the top surface of the STI region 56 can have a flat surface (as illustrated), a convex surface, a recessed surface (e.g., a depression), or a combination thereof. The top surface of the STI region 56 can be formed as flat, convex, and / or recessed by appropriate etching. The STI region 56 can be recessed using acceptable etching processes, such as etching processes selectively targeting the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than the material of the fins 52). For example, oxide removal can be used, employing, for example, dilute hydrofluoric acid (dHF).

[0029] about Figures 2 to 6 The described process is merely one example of how fin 52 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a trench can be etched through the dielectric layer to expose the underlying substrate 50. Homoethelic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoethelic structure protrudes from the dielectric layer to form the fin. Furthermore, in some embodiments, heteroethelic structures can be used for the fin 52. For example, Figure 5 The fin 52 can be recessed, and a material different from the fin 52 can be epitaxially grown over the recessed fin 52. In such an embodiment, the fin 52 includes a recessed material and an epitaxial growth material disposed over the recessed material. In a further embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and a trench can be etched through the dielectric layer to form a trench. A heteroepitaxial structure can then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxial growth material can be in-situ doped during growth, which can avoid prior and / or subsequent implantation, although in-situ doping and implantation doping can be used together.

[0030] Furthermore, it may be advantageous to epitaxially grow a material different from that in the p-type region 50P (e.g., PMOS region) in the n-type region 50N (e.g., NMOS region). In various embodiments, the upper portion of the fin 52 may be made of silicon-germanium (Si). x Ge 1-x(where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0031] Further in Figure 6 In this process, suitable wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N and an N-well may be formed in the p-type region 50P. In some embodiments, either a P-well or an N-well may be formed in both the n-type region 50N and the p-type region 50P.

[0032] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using photoresist and / or other masks (not shown). For example, photoresist can be formed over the fins 52 and STI regions 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using a spin-coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted in the region, with a concentration equal to or less than 10. 18 cm -3 For example, in about 10 16 cm -3 Peace Treaty 10 18 cm -3 Between. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0033] After implantation into the p-type region 50P, a photoresist is formed over the fins 52 and STI regions 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted in the region, with a concentration equal to or less than 10. 18 cm -3 For example, in about 10 16 cm -3 Peace Treaty 1018 cm -3 Between. After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0034] After implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, although in-situ doping and implantation doping can be used together.

[0035] exist Figure 7 In this process, a dummy dielectric layer 60 is formed on fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 can be deposited over the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 can be deposited over the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, polysilicon-germanium (polysilicon-germanium), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 62 can be made of other materials that have high etch selectivity for etching isolation regions (e.g., STI region 56) and / or the dummy dielectric layer 60. The mask layer 64 may comprise one or more layers, such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 60 is shown to cover only the fin 52. In some embodiments, the dummy dielectric layer 60 may be deposited such that it covers the STI region 56, extends over the STI region, and extends between the dummy gate layer 62 and the STI region 56.

[0036] Figures 8A to 16B The illustrations depict various additional steps in the fabrication of the device in the embodiment. Figures 8A to 16B The illustration shows the characteristics of either the n-type region 50N or the p-type region 50P. For example, Figures 8A to 16B The structure shown in the diagram is applicable to both n-type region 50N and p-type region 50P. The structural differences between n-type region 50N and p-type region 50P (if any) are described in the accompanying text description for each diagram.

[0037] exist Figure 8A and Figure 8BIn this process, acceptable photolithography and etching techniques can be used to process mask layer 64 (see...). Figure 7 The mask 74 is patterned to form a dummy gate layer 62. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using an acceptable etching technique for forming the dummy gates 72. The dummy gates 72 cover the corresponding channel regions 58 of the fins 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gates 72 may also have a length direction that is substantially perpendicular to the length direction of the corresponding fin 52.

[0038] Further in Figure 8A and Figure 8B In this process, the gate sealing spacer 80 can be formed on the exposed surfaces of the dummy gate 72, mask 74, and / or fin 52. The gate sealing spacer 80 can be formed by thermal oxidation or deposition followed by anisotropic etching. The gate sealing spacer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc.

[0039] After forming the gate sealing spacer 80, implantation can be performed for the lightly doped source / drain (LDD) region (not explicitly shown). In embodiments with different device types, similar to the above... Figure 6 The implantation discussed earlier can involve forming a mask, such as a photoresist, over the n-type region 50N, exposing the p-type region 50P, and implanting an impurity of an appropriate type (e.g., p-type) into the exposed fins 52 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain regions can have approximately 10... 15 cm -3 To about 10 19 cm -3 The concentration of impurities. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0040] exist Figure 9A and Figure 9B In this process, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0041] It should be noted that the above disclosure provides a general description of the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or more spacers can be used, different step sequences can be used (e.g., the gate seal spacer 80 may not be etched before forming the gate spacer 86, resulting in an "L-shaped" gate seal spacer), spacers can be formed and removed, and so on. Furthermore, different structures and steps can be used to form n-type and p-type devices. For example, the LDD region for an n-type device can be formed before forming the gate seal spacer 80, while the LDD region for a p-type device can be formed after forming the gate seal spacer 80.

[0042] exist Figure 10A and Figure 10B In the fin 52, epitaxial source / drain regions 82 are formed. The epitaxial source / drain regions 82 are formed in the fin 52 such that each dummy gate 72 is disposed between a corresponding pair of adjacent epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fin 52 and may also penetrate the fin 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 82 do not short-circuit the subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain regions 82 can be selected to apply stress in the corresponding channel region 58, thereby improving performance.

[0043] The epitaxial source / drain region 82 in the n-type region 50N can be formed by the following steps: masking the p-type region 50P and etching the source / drain region of the fin 52 in the n-type region 50N to form a groove in the fin 52. Then, the epitaxial source / drain region 82 in the n-type region 50N is epitaxially grown in the groove. The epitaxial source / drain region 82 can include any acceptable material, such as materials suitable for n-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the n-type region 50N can include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 82 in the n-type region 50N can have a surface protruding from the corresponding surface of the fin 52 and can have a small facet.

[0044] The epitaxial source / drain region 82 in the p-type region 50P can be formed by the following steps: masking the n-type region 50N and etching the source / drain region of the fin 52 in the p-type region 50P to form a groove in the fin 52. Then, the epitaxial source / drain region 82 in the p-type region 50P is epitaxially grown in the groove. The epitaxial source / drain region 82 can include any acceptable material, such as materials suitable for p-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region 50P can include a material for applying compressive strain in the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 82 in the p-type region 50P can have a surface protruding from the corresponding surface of the fin 52 and can have a small facet.

[0045] The epitaxial source / drain regions 82 and / or fins 52 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a density between approximately 10⁻⁶. 19 cm -3 With about 10 21 cm -3 The impurity concentrations between the two. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0046] Due to the epitaxial process used to form the epitaxial source / drain regions 82 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions has small planes that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, these small planes cause adjacent source / drain regions 82 of the same FinFET to merge, such as... Figure 10D As illustrated. In other embodiments, adjacent source / drain regions 82 remain separated after the epitaxial process is completed, as shown in the figure. Figure 10C and Figure 10E As shown in the diagram. Figure 10C and Figure 10D In the embodiment illustrated in the figure, the gate spacer 86 is formed as part of a sidewall covering the fin 52 extending over the STI region 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacer 86 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 56.

[0047] exist Figure 11A and Figure 11B In the middle, the first interlayer dielectric (ILD) 88 is deposited in Figure 10A and Figure 10BAbove the structure shown in the diagram. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain region 82, mask 74, and gate spacer 86. CESL 87 may include a dielectric material having a lower etch rate than the material of the overlying first ILD 88, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0048] exist Figure 12A and Figure 12B In this process, a planarization process, such as CMP, can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 over the dummy gate 72, and may remove portions of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, gate sealing spacers 80, gate spacers 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0049] exist Figure 13A and Figure 13BIn this process, the dummy gate 72 and mask 74 (if present) are removed in one or more etching steps to form a recess 90. A portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, while the dummy dielectric layer 60 remains and is exposed in the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., a core logic region) and remains in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 72 while barely etching the first ILD 88 or gate spacer 86. Each recess 90 exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is arranged between an adjacent pair of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 can be used as an etch stop layer when the dummy gate 72 is etched. The dummy dielectric layer 60 can then be selectively removed after the dummy gate 72 has been removed.

[0050] exist Figure 14A and Figure 14B In this process, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 14C The diagram shows Figure 14B A detailed view of region 89. A gate dielectric layer 92 is deposited in the recess 90, for example, on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 comprises one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxides, metal silicates, etc. For example, in some embodiments, the gate dielectric layer 92 comprises a silicon oxide interface layer formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 92 may include a dielectric layer with a k value greater than about 7.0. Methods for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy gate dielectric 60 is retained in the recess 90, the gate dielectric layer 92 comprises the material of the dummy gate dielectric 60 (e.g., SiO2).

[0051] Gate electrodes 94 are deposited over the gate dielectric layer 92 and fill the remaining portion of the trench 90. Gate electrodes 94 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although... Figure 14BThe diagram illustrates a single-layer gate electrode 94, but the gate electrode 94 may include any number of liner layers 94A, any number of work function tuning layers 94B, and filler material 94C, such as... Figure 14C As illustrated, after filling the trench 90, a planarization process, such as CMP, can be performed to remove excess material from the gate dielectric layer 92 and gate electrode 94, which lie above the top surface of the ILD 88. The remaining material of the gate electrode 94 and gate dielectric layer 92 thus forms the alternative gate of the resulting FinFET. The gate electrode 94 and gate dielectric layer 92 can be collectively referred to as the “gate stack”. The gate and gate stack can extend along the sidewalls of the channel region 58 of the fin 52.

[0052] The formation of the gate dielectric layer 92 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed by different processes, such that the gate dielectric layer 92 can be made of different materials, and / or the gate electrode 94 in each region can be formed by different processes, such that the gate electrode 94 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0053] exist Figure 15A and Figure 15B In this configuration, a gate mask 96 is formed over a gate stack (including a gate dielectric layer 92 and a corresponding gate electrode 94), and the gate mask may be disposed between opposing portions of the gate spacers 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack such that a groove is formed directly over the gate stack and between opposing portions of the gate spacers 86. The gate mask 96, comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), fills the groove, and then a planarization process is performed to remove excess dielectric material extending over the first ILD 88. The gate mask 96 is optional and may be omitted in some embodiments. In such embodiments, the gate stack may remain flush with the top surface of the first ILD 88.

[0054] In addition, such as Figure 15A and Figure 15BAs illustrated, a second ILD 108 is deposited above a first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. The gate contact 110 is subsequently formed. Figure 16A and Figure 16B It penetrates the second ILD 108 and the gate mask 96 (if present) to contact the top surface of the recessed gate electrode 94.

[0055] exist Figure 16A and Figure 16B In some embodiments, gate contact 110 and source / drain contact 112 are formed through the second ILD 108 and the first ILD 88. An opening for the source / drain contact 112 is formed through the first ILD 88 and the second ILD 108, and an opening for the gate contact 110 is formed through the second ILD 108 and the gate mask 96 (if present). Acceptable photolithography and etching techniques can be used to form the openings. A liner (not shown) and conductive material are formed in the openings; the liner may be, for example, a diffusion barrier layer, an adhesive layer, etc. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the surface of the ILD 108. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 110 in the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is substantially and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is substantially and electrically coupled to the gate electrode 106. The source / drain contact 112 and the gate contact 110 can be formed in different processes or in the same process. Although the source / drain contact 112 and the gate contact 110 are shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 112 and the gate contact 110 can be formed in a different cross-section, which avoids short circuits in the contacts.

[0056] Figure 17 The illustration is similar to Figure 3B and Figure 10C A cross-sectional view and illustration of the cross-section. Figure 16A and Figure 16B Further processing of the structure. In Figure 17In this configuration, a third ILD 114 is deposited above the second ILD 108. In some embodiments, the third ILD 108 is similar to the second ILD 108 and will not be described again here. Vias 116 and metallization patterns 118 are formed in the third ILD 114 and are electrically connected to the source / drain contacts 112. Vias 116 and metallization patterns 118 are formed, for example, by an inlay process. Figure 17 As illustrated in the diagram, for regions 50N / P and 50R, the ILD, vias, and metallization patterns are formed identically. This design allows for complete integration of this structure into the CMOS process flow.

[0057] Figures 18A to 25 Top views and cross-sectional views of various configurations of semiconductor devices according to some embodiments are illustrated.

[0058] Figure 18A A top view of a semiconductor device 210 according to some embodiments of the present disclosure is illustrated. Figure 18B The illustration shows a semiconductor device 210 along some embodiments of the present disclosure. Figure 18A Cross-sectional view of cross-section line 18B-18B in the diagram. Figure 18C The illustration shows a semiconductor device 210 along some embodiments of the present disclosure. Figure 18A Cross-sectional view of section line 18C-18C in the diagram. (Reference) Figures 18A to 18C The semiconductor device 210 includes a substrate 50, a plurality of fin structures 52, an isolation region 56, a plurality of gate structures 94, a plurality of epitaxial structures 82 (sometimes referred to as source / drain structures 82), and a plurality of contact structures 112. These structures have been described previously and will not be repeated here. Details similar to those of the foregoing embodiments regarding this embodiment will not be repeated here.

[0059] In some embodiments, the fin structure 52 has a plurality of first fin structures 52A and a plurality of second fin structures 52B. In some embodiments, the plurality of first fin structures 52A and the plurality of second fin structures 52B are arranged in an alternating pattern, wherein at least one second fin structure 52B separates the first fin structures 52A from each other. Each first fin structure 52A has an epitaxial structure 82 formed thereon, and each second fin structure 52B does not have an epitaxial structure 82 formed thereon. In some embodiments, the second fin structure 52B separates and isolates the epitaxial structure 82 on the first fin structure 52A and may be referred to as an isolation fin structure 52B. In some embodiments, each epitaxial structure 82 has at least one contact structure 112 formed thereon. Each contact structure 112 is electrically connected to at least one epitaxial structure 82. According to some embodiments of the present disclosure, the semiconductor device 210 includes a plurality of resonators 217. In the illustrated embodiment, each epitaxial structure 82 is located only on a single first fin structure 52A, although in other embodiments, the epitaxial structures 82 may be combined and formed on a plurality of first fin structures 52A (see, for example...). Figure 19A and Figure 19B The epitaxial structure 82 is located between adjacent gate structures 94, wherein the gate structures 94 extend in a direction perpendicular to the fin structure 52. The gate structure 94 may be an alternative gate structure 94 or a pseudo gate structure 72 as described above.

[0060] In some embodiments, at least one second fin structure 52B is arranged between two first fin structures 52A. In some embodiments, four second fin structures 52B are arranged between two first fin structures 52A. In some embodiments, the output frequency of the resonator 217 can be determined by the number of first fin structures 52A, the material composition of the first fin structures 52A, and the number of second fin structures 52B between the first fin structures 52A.

[0061] exist Figures 18A to 21B In the embodiments illustrated, the output frequency of the resonator 217 can be configured by the number of first fin structures 52A and second fin structures 52B under a single merged epitaxial structure 82. Furthermore, in these embodiments, the material composition of the first fin structure 52A can be configured to tune the output frequency of the resonator 217. Figures 18A-18C In one embodiment, the resonator 217 is configured such that each epitaxial structure is located on a single first fin structure 52A and each first fin structure 52A is separated by four second fin structures 52B.

[0062] Figure 19A A top view of a semiconductor device 212 according to some embodiments is illustrated, and Figure 19B The illustration shows a semiconductor device 212 along some embodiments. Figure 19AThe cross-sectional view is shown in the cross-sectional line 19B-19B. Details similar to those in the previous embodiments will not be repeated here.

[0063] exist Figures 19A-19B In one embodiment, the resonator 217 is configured such that each epitaxial structure is located on two adjacent first fin structures 52A and each pair of first fin structures 52A is separated by a single second fin structure 52B. Epitaxial structures 82 are located between adjacent gate structures 94, wherein the gate structures 94 extend in a direction perpendicular to the fin structures 52. The gate structures 94 may be alternative gate structures 94 or pseudo-gate structures 72 as described above.

[0064] Figure 20A A top view of a semiconductor device 214 according to some embodiments is illustrated, and Figure 20B The illustration shows a semiconductor device 214 along some embodiments. Figure 20A The cross-sectional view is shown by cross-sectional lines 20B-20B. Details similar to those in the previous embodiments will not be repeated here.

[0065] exist Figures 20A-20B In one embodiment, the resonator 217 is configured such that each epitaxial structure is located on two adjacent first fin structures 52A and each pair of first fin structures 52A is separated by three second fin structures 52B. Epitaxial structures 82 are located between adjacent gate structures 94, wherein the gate structures 94 extend in a direction perpendicular to the fin structures 52. The gate structures 94 may be alternative gate structures 94 or pseudo-gate structures 72 as described above.

[0066] Figure 21A A top view of a semiconductor device 216 according to some embodiments is illustrated, and Figure 21B The illustration shows a semiconductor device 216 along some embodiments. Figure 21A The cross-sectional view is shown by cross-sectional lines 21B-21B. Details similar to those in the previous embodiments will not be repeated here.

[0067] exist Figures 21A-21B In one embodiment, the resonator 217 is configured such that each epitaxial structure is located on three adjacent first fin structures 52A and each group of first fin structures 52A is separated by four second fin structures 52B. Epitaxial structures 82 are located between adjacent gate structures 94, wherein the gate structures 94 extend in a direction perpendicular to the fin structures 52. The gate structures 94 may be alternative gate structures 94 or pseudo-gate structures 72 as described above.

[0068] In various configurations of the resonator 217, the output frequency of the resonator 217 can be configured by the number of first fin structures 52A and second fin structures 52B under a single merged epitaxial structure 82. Furthermore, in these embodiments, the material composition of the first fin structure 52A can be configured to tune the output frequency of the resonator 217.

[0069] Figure 22 A cross-sectional view of a semiconductor device 220 according to some embodiments is illustrated. In this embodiment, the semiconductor device 220 has fin structures 52 grouped together, such that multiple fin spacings exist in the semiconductor device 220. For example, a group of first or second fin structures 52A or 52B may have an internal distance D2, while each fin group is separated from its adjacent fin group by a distance D1. Details similar to those of the foregoing embodiments regarding this embodiment will not be repeated here.

[0070] exist Figure 22 In some embodiments, the resonator 217 is configured such that each epitaxial structure is located on a set of two adjacent first fin structures 52A and each set of first fin structures 52A is separated by two sets of second fin structures 52B. In some embodiments, each first fin structure 52A within a set of first fin structures 52A is separated by a distance D2. In some embodiments, each second fin structure 52B within a set of second fin structures 52B is separated by a distance D2. In some embodiments, the distance D2 is in the range of 1 nm to 200 nm. In some embodiments, each set of first fin structures 52A is separated from the nearest fin group (first or second fin) by a distance D1. In some embodiments, the distance D1 is in the range of 1 nm to 200 nm. In some embodiments, D1 is different from D2. In some embodiments, D1 is less than D2, while in other embodiments, D1 is greater than D2.

[0071] In various configurations of the resonator 217, the output frequency of the resonator 217 can be configured by the number of first fin structures 52A under a single combined epitaxial structure 82, the distance D2, the distance D1, the ratio of D1 to D2, or a combination thereof.

[0072] Figure 23 A cross-sectional view of a semiconductor device 222 according to some embodiments is illustrated. This embodiment is similar to... Figure 22 The embodiment further includes multiple internal fin spacings and multiple external structures 82 connected to a single contact structure 112. Details similar to those of the foregoing embodiments regarding this embodiment will not be repeated here.

[0073] exist Figure 23In an embodiment, the resonator 217 is configured such that each epitaxial structure is located on a set of three adjacent first fin structures 52A. At least two of the first fin structures 52A in the set are separated by a distance D2. In addition, at least two of the first fin structures 52A are separated by a distance D3, which is different from D2. In some embodiments, the distance D3 is in the range from 1 nm to 200 nm. In some embodiments, D3 is different from D2. In some embodiments, D2 is less than D3, while in other embodiments, D2 is greater than D3.

[0074] In some embodiments, at least one of the first fin structures 52A in the set is separated from the nearest second fin structure 52B by a distance D4. In some embodiments, the distance D4 is in the range from 1 nm to 200 nm. In some embodiments, D1 is different from D4. In some embodiments, D1 is less than D4, while in other embodiments, D1 is greater than D4.

[0075] In various configurations of the resonator 217, the output frequency of the resonator 217 can be configured by the number of first fin structures 52A under a single merged epitaxial structure 82, the number of epitaxial structures 82 under a single contact structure 112, the distance D2, the distance D1, the distance D3, the distance D4, the ratio of D1 to D2, the ratio of D3 to D2, the ratio of D1 to D4, or a combination thereof.

[0076] Figure 24 and 25 FIG. illustrates a cross-sectional view of semiconductor devices 224 and 226 according to some embodiments. This embodiment is similar to Figure 22 the embodiment and further includes fin structures having a gradient material composition. Details similar to those of the foregoing embodiments with respect to this embodiment are not repeated herein.

[0077] In Figure 24 and Figure 25 the embodiment, at least one of the first fin structures 52A has a gradient concentration material composition. In some embodiments, at least one of the first fin structures 52A has a gradient compound semiconductor material composition. In some embodiments, at least one of the first fin structures 52A has a gradient composition of SiGe material and can be Si 1-x Ge x material composition, where 0 < x < 1. In Figure 24 , when going from the top to the bottom of at least one of the first fin structures 52A, the x value increases. In some embodiments, the x value increases from 0.01 to 0.99. In Figure 25 , when going from the top to the bottom of at least one of the first fin structures 52A, the x value decreases. In some embodiments, the x value decreases from 0.99 to 0.01.

[0078] In various configurations of the resonator 217, the output frequency of the resonator 217 can be configured by the number of first fin structures 52A under a single merged epitaxial structure 82, the number of epitaxial structures 82 under a single contact structure 112, the gradient concentration of the material of at least one first fin structure 52A, the direction of the gradient concentration of the material of at least one first fin structure 52A, or a combination thereof.

[0079] Figure 26 and 27 A top view of an example circuit configuration for operating resonator 217 to generate an output frequency is illustrated. In each example, the external contact structure 112 (e.g., located at...) Figure 26 and Figure 27 The top and bottom contact structures 112 (as seen in the top view) are alternately coupled to different input voltages Vin. In some embodiments, the input voltage Vin is an alternating current (AC) signal. For example, in one embodiment, one half of the outer contact structure 112 is coupled to positive Vin (e.g., +1 / 2 Vin), while the other half is coupled to negative Vin (e.g., -1 / 2 Vin). In each example, one or more of the gate structures are coupled to the gate voltage Vg. Figure 26 In this configuration, the left sides of a pair of internal contact structures 112 are coupled together to form an output signal (e.g., an output frequency), and the right sides of the pair of internal contact structures are coupled to a low voltage, such as ground. Figure 26 In one embodiment, each extensional structure 82 and contact structure 112 is located on a plurality of first fin structures 52A, and there are a plurality of second fin structures 52B between each group of first fin structures 52A.

[0080] Figure 27 It is the minimum resonator configuration. Figure 27 In this configuration, a pair of internal contact structures 112 are coupled together to form an output signal (e.g., output frequency). Figure 27 In one embodiment, there is no second fin structure 52B between each first fin structure 52A and each extension structure 82 is located on only a single first fin structure 52A.

[0081] exist Figure 26 and 27 In both cases, the input signal Vin and the gate voltage Vg vibrate within the fin structure based on the resonance of the fin structure. In some embodiments, this vibration causes a change in capacitance and carrier movement within the fin, generating a high-frequency sensing current. In some embodiments, the resonant frequency of the fin structure is related to material properties (e.g., Young's modulus, mass density, geometry, etc., or combinations thereof).

[0082] As an example, the gate structure 94, the first fin structure 52A, and the gate dielectric between them create a capacitor. Therefore, when a gate voltage Vg is applied to the gate, electrostatic forces can squeeze the dielectric, and consequently squeeze the first fin structure 52A. A series of regular voltage pulses, representing the gate voltage Vg, can generate periodic pulses in the fin structure 52A. By spacing a series of first fin structures 52A and second fin structures 52B in various configurations and connecting them all to the gate structure 94, the resonator 217 can resonate at a wide range of frequencies from megahertz to gigahertz.

[0083] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructured (e.g., nanosheets, nanowires, gate-around, etc.) field-effect transistors (NSFETs). In NSFET embodiments, a nanostructure formed by a stack of alternating layers of patterned channel layers and sacrificial layers replaces the fins. The dummy gate stack and source / drain regions can be formed in a manner similar to the embodiments described above. After removing the dummy gate stack, the sacrificial layer in the channel region can be partially or completely removed. An alternative gate structure can be formed in a manner similar to the embodiments described above, which can partially or completely fill the opening left by removing the sacrificial layer, and can partially or completely surround the channel layer in the channel region of the NSFET device. An ILD and contacts contacting the alternative gate structure and source / drain regions can be formed in a manner similar to the embodiments described above. Nanostructured devices can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0084] The embodiments disclosed herein offer advantages. The disclosed devices and methods include using fin structures to fabricate resonators that can be used as frequency sources in circuits. In some embodiments, the frequency generated by the device is determined by the fin material and fin spacing. Device designs allow for better integration of this structure into complementary metal-oxide-semiconductor (CMOS) process flows. The disclosed embodiments allow the device to generate more than one frequency in a single structure, while also simplifying the process and eliminating the need for special packaging.

[0085] The embodiment includes a semiconductor device comprising a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions located on the substrate and disposed between the plurality of fin structures. The device further includes a plurality of gate structures located on the plurality of isolation regions. The device also includes a plurality of epitaxial structures located on the plurality of first fin structures. The device further includes a plurality of contact structures located on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures, and the plurality of contact structures are elements of one or more resonators.

[0086] Embodiments may include one or more of the following features. In a semiconductor device, one or more resonators include a contact structure, an epitaxial structure, and a first fin structure. At least one of a plurality of second fin structures is arranged between two of the plurality of first fin structures. A plurality of second fin structures are arranged between two of the plurality of first fin structures. One or more resonators include a contact structure, a plurality of epitaxial structures, and a plurality of first fin structures. At least one of a plurality of gate structures extends between the plurality of epitaxial structures, the plurality of first fin structures and the plurality of second fin structures are arranged in an alternating pattern, and at least one of the plurality of second fin structures separates two of the plurality of first fin structures. Each first fin structure includes a gradient material composition from the top of the first fin structure to the bottom of the first fin structure. One of the plurality of first fin structures has a first sidewall facing a first direction and a second sidewall facing a second direction opposite to the first direction, the first sidewall being spaced a first distance from the nearest fin structure in the first direction, and the second sidewall being spaced a second distance from the nearest fin structure in the second direction, the second distance being different from the first distance. The nearest fin structure in the first direction is the first fin structure, and the nearest fin structure in the second direction is the second fin structure.

[0087] An embodiment includes a semiconductor device comprising a substrate having a first surface and a second surface. The semiconductor device further includes an isolation structure located above the first surface of the substrate. The device also includes a plurality of gate structures located above the isolation structure. The device further includes a resonator comprising a plurality of first fin structures, at least one epitaxial structure, and a contact structure, wherein the plurality of first fin structures are located on the first surface of the substrate, the at least one epitaxial structure is located on the first fin structures, and the contact structure is located on the at least one epitaxial structure. The device also includes at least one second fin structure located on the first surface of the substrate, and the at least one second fin structure is disposed between two of the plurality of first fin structures, the at least one second fin structure having no epitaxial structure.

[0088] Embodiments may include one or more of the following features. In a semiconductor device, the output frequency of a resonator is based on the pitch of a first fin structure and the material composition of the first fin structure. A plurality of second fin structures are disposed between two first fin structures in the first fin structures, where there are no first fin structures between the two first fin structures. Each first fin structure includes a compound semiconductor material. Each first fin structure includes a gradient material composition from the top to the bottom of the first fin structure. One of the plurality of first fin structures has a first sidewall facing a first direction and a second sidewall facing a second direction, the second direction being opposite to the first direction, the first sidewall being separated from the nearest fin structure in the first direction by a first distance, and the second sidewall being separated from the nearest fin structure in the second direction by a second distance, the second distance being different from the first distance.

[0089] Embodiments include a method that includes forming a plurality of fin structures extending from a substrate, the fin structures having a plurality of first fin structures and a plurality of second fin structures. The method further includes forming a plurality of isolation regions located on the substrate and disposed between the plurality of fin structures. The method further includes forming a plurality of gate structures on the isolation regions. The method further includes growing a plurality of epitaxial structures on the plurality of first fin structures, the plurality of second fin structures not having epitaxial structures. The method further includes forming a plurality of contact structures on the plurality of epitaxial structures, where the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures, and the plurality of contact structures are elements of one or more resonators.

[0090] Embodiments may include one or more of the following features. In the method, the material of at least one first fin structure is Si 1-x Ge x , 0 < x < 1. From the top to the bottom of at least one first fin structure, the value of x increases. From the top to the bottom of at least one first fin structure, the value of x decreases. A plurality of second fin structures are disposed between two first fin structures in the first fin structures, where there are no first fin structures between the two first fin structures.

[0091] Some examples are provided below.

[0092] Example 1. A semiconductor device, comprising:

[0093] a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures;

[0094] a plurality of isolation regions located on the substrate and disposed between the plurality of fin structures;

[0095] a plurality of gate structures located on the plurality of isolation regions;

[0096] Multiple extensional structures are located on the multiple first fin structures; and

[0097] Multiple contact structures are located on the multiple epitaxial structures, wherein the multiple first fin structures, the multiple gate structures, the multiple epitaxial structures and the multiple contact structures are elements of one or more resonators.

[0098] Example 2. A semiconductor device as described in Example 1, wherein one of the one or more resonators includes a contact structure, an epitaxial structure, and a first fin structure.

[0099] Example 3. A semiconductor device as described in Example 1, wherein one of the one or more resonators includes a contact structure, a plurality of epitaxial structures, and a plurality of first fin structures.

[0100] Example 4. A semiconductor device as described in Example 2, wherein at least one of the plurality of second fin structures is arranged between two of the plurality of first fin structures.

[0101] Example 5. A semiconductor device as described in Example 4, wherein a plurality of second fin structures are arranged between two of the plurality of first fin structures.

[0102] Example 6. A semiconductor device as described in Example 1, wherein at least one of the plurality of gate structures extends between the plurality of epitaxial structures, the plurality of second fin structures and the plurality of first fin structures are arranged in an alternating pattern, and at least one of the plurality of second fin structures separates two of the plurality of first fin structures.

[0103] Example 7. A semiconductor device as described in Example 1, wherein each first fin structure includes a gradient material composition from the top of the first fin structure to the bottom of the first fin structure.

[0104] Example 8. A semiconductor device as described in Example 1, wherein one of the plurality of first fin structures has a first sidewall facing a first direction and a second sidewall facing a second direction opposite to the first direction, the first sidewall being separated from the nearest fin structure in the first direction by a first distance, and the second sidewall being separated from the nearest fin structure in the second direction by a second distance, the second distance being different from the first distance.

[0105] Example 9. A semiconductor device as described in Example 8, wherein the nearest fin structure in the first direction is a first fin structure, and wherein the nearest fin structure in the second direction is a second fin structure.

[0106] Example 10. A semiconductor device, comprising:

[0107] The substrate has a first surface and a second surface;

[0108] An isolation structure is located above the first surface of the substrate;

[0109] Multiple gate structures are located above the isolation structure;

[0110] A resonator includes a plurality of first fin structures, at least one epitaxial structure, and a contact structure, wherein the plurality of first fin structures are located on a first surface of the substrate, the at least one epitaxial structure is located on the first fin structures, and the contact structure is located on the at least one epitaxial structure; and

[0111] At least one second fin structure is located on the first surface of the substrate, and the at least one second fin structure is arranged between two of the plurality of first fin structures, the at least one second fin structure having no epitaxial structure.

[0112] Example 11. A semiconductor device as described in Example 10, wherein the output frequency of the resonator is based on the spacing of the first fin structure and the material composition of the first fin structure.

[0113] Example 12. A semiconductor device as described in Example 10, wherein a plurality of second fin structures are arranged between two first fin structures in the first fin structure, wherein there is no first fin structure between two first fin structures.

[0114] Example 13. A semiconductor device as described in Example 10, wherein each first fin structure comprises a compound semiconductor material.

[0115] Example 14. A semiconductor device as described in Example 10, wherein each first fin structure includes a gradient material composition from the top of the first fin structure to the bottom of the first fin structure.

[0116] Example 15. A semiconductor device as described in Example 10, wherein one of the plurality of first fin structures has a first sidewall facing a first direction and a second sidewall facing a second direction opposite to the first direction, the first sidewall being separated from the nearest fin structure in the first direction by a first distance, and the second sidewall being separated from the nearest fin structure in the second direction by a second distance, the second distance being different from the first distance.

[0117] Example 16. A method for fabricating a semiconductor device, comprising:

[0118] Multiple fin structures extending from the substrate are formed, the fin structures having multiple first fin structures and multiple second fin structures;

[0119] Multiple isolation regions are formed, the multiple isolation regions being located on the substrate and arranged between the multiple fin structures;

[0120] Multiple gate structures are formed on the multiple isolation regions;

[0121] Multiple epitaxial structures are grown on the plurality of first fin structures, and the plurality of second fin structures have no epitaxial structures; and

[0122] Multiple contact structures are formed on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures and the plurality of contact structures are elements of one or more resonators.

[0123] Example 17. The method as described in Example 16, wherein the material of at least one first fin structure is Si. 1-x Ge x 0 <x<1。

[0124] Example 18. The method as described in Example 17, wherein the x value increases from the top of the at least one first fin structure to the bottom of the at least one first fin structure.

[0125] Example 19. The method as described in Example 17, wherein the x value decreases from the top of the at least one first fin structure to the bottom of the at least one first fin structure.

[0126] Example 20. The method as described in Example 16, wherein a plurality of second fin structures are arranged between two first fin structures in the first fin structure, wherein there is no first fin structure between the two first fin structures.

[0127] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: Multiple fin structures extending from a substrate, the multiple fin structures having multiple first fin structures and multiple second fin structures; Multiple isolation regions are located on the substrate and arranged between the multiple fin structures; Multiple gate structures are located on the multiple isolation regions; Multiple extensional structures are located on the multiple first fin structures, while the multiple second fin structures have no extensional structures; as well as Multiple contact structures are located on the multiple epitaxial structures, wherein the multiple first fin structures, the multiple gate structures, the multiple epitaxial structures and the multiple contact structures are elements of one or more resonators.

2. The semiconductor device of claim 1, wherein one of the one or more resonators comprises a contact structure, an epitaxial structure, and a first fin structure.

3. The semiconductor device of claim 1, wherein one of the one or more resonators comprises a contact structure, a plurality of epitaxial structures and a plurality of first fin structures.

4. The semiconductor device of claim 2, wherein at least one of the plurality of second fin structures is arranged between two of the plurality of first fin structures.

5. The semiconductor device of claim 4, wherein a plurality of second fin structures are arranged between two of the plurality of first fin structures.

6. The semiconductor device of claim 1, wherein at least one of the plurality of gate structures extends between the plurality of epitaxial structures, the plurality of second fin structures and the plurality of first fin structures are arranged in an alternating pattern, and at least one of the plurality of second fin structures separates two of the plurality of first fin structures.

7. The semiconductor device of claim 1, wherein each first fin structure includes a gradient material composition from the top of the first fin structure to the bottom of the first fin structure.

8. The semiconductor device of claim 1, wherein one of the plurality of first fin structures has a first sidewall facing a first direction and a second sidewall facing a second direction opposite to the first direction, the first sidewall being separated from the nearest fin structure in the first direction by a first distance, and the second sidewall being separated from the nearest fin structure in the second direction by a second distance, the second distance being different from the first distance.

9. The semiconductor device of claim 8, wherein the nearest fin structure in the first direction is a first fin structure, and wherein the nearest fin structure in the second direction is a second fin structure.

10. A semiconductor device, comprising: The substrate has a first surface and a second surface; An isolation structure is located above the first surface of the substrate; Multiple gate structures are located above the isolation structure; A resonator includes a plurality of first fin structures, at least one epitaxial structure, and a contact structure, wherein the plurality of first fin structures are located on a first surface of the substrate, the at least one epitaxial structure is located on the first fin structures, and the contact structure is located on the at least one epitaxial structure. as well as At least one second fin structure is located on the first surface of the substrate, and the at least one second fin structure is disposed between two of the plurality of first fin structures, the at least one second fin structure having no epitaxial structure, and the isolation structure is disposed between the plurality of fin structures including the plurality of first fin structures and the at least one second fin structure.

11. The semiconductor device of claim 10, wherein the output frequency of the resonator is based on the spacing of the first fin structure and the material composition of the first fin structure.

12. The semiconductor device of claim 10, wherein a plurality of second fin structures are arranged between two first fin structures in the first fin structure, wherein there is no first fin structure between two first fin structures.

13. The semiconductor device of claim 10, wherein each first fin structure comprises a compound semiconductor material.

14. The semiconductor device of claim 10, wherein each first fin structure includes a gradient material composition from the top of the first fin structure to the bottom of the first fin structure.

15. The semiconductor device of claim 10, wherein one of the plurality of first fin structures has a first sidewall facing a first direction and a second sidewall facing a second direction opposite to the first direction, the first sidewall being separated from the nearest fin structure in the first direction by a first distance, and the second sidewall being separated from the nearest fin structure in the second direction by a second distance, the second distance being different from the first distance.

16. A method for fabricating a semiconductor device, comprising: Multiple fin structures extending from the substrate are formed, the fin structures having multiple first fin structures and multiple second fin structures; Multiple isolation regions are formed, the multiple isolation regions being located on the substrate and arranged between the multiple fin structures; Multiple gate structures are formed on the multiple isolation regions; Multiple epitaxial structures are grown on the plurality of first fin structures, while the plurality of second fin structures have no epitaxial structures. as well as Multiple contact structures are formed on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures and the plurality of contact structures are elements of one or more resonators.

17. The method of claim 16, wherein the material of at least one first fin structure is Si 1-x Ge x , 0 < x < 1.

18. The method of claim 17, wherein the x value increases from the top of the at least one first fin structure to the bottom of the at least one first fin structure.

19. The method of claim 17, wherein the x value decreases from the top of the at least one first fin structure to the bottom of the at least one first fin structure.

20. The method of claim 16, wherein a plurality of second fin structures are arranged between two first fin structures in the first fin structure, wherein there is no first fin structure between the two first fin structures.

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