Semiconductor facility layout simulation method, computer system, and computer readable medium

Abstract

The present application relates to a kind of semiconductor facility layout simulation method, computer system and non-transitory computer readable medium.In computer system, the computer system includes processor and memory, the memory stores the program code executable by processor;Wherein, the processor executes the following steps: by first layout method or second layout method, the facility arranged in semiconductor FAB is laid out, and according to layout method, the result is simulated, and the simulation result is compared by various parameters.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0158155, filed with the Korean Intellectual Property Office on November 23, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to a method for simulating the layout of semiconductor facilities, a computer system, and a non-transitory computer-readable medium. Background Technology

[0004] In related technologies, semiconductor facility layout is done manually, and yield calculations are performed using manual preparation and derivation methods, making it difficult to analyze yield variation trends. Furthermore, when calculating yield by adding new facility types beyond existing ones, it is difficult to calculate yield without applicable simulation tools. Summary of the Invention

[0005] This invention aims to provide a system capable of providing, comparing, and analyzing simulation results based on semiconductor facility layout methods.

[0006] The problems to be solved by this invention are not limited to those described above. Those skilled in the art will clearly understand from this specification and the accompanying drawings any problems not mentioned.

[0007] An exemplary embodiment of the present invention provides a computer system including a processor and a memory storing program code executable by the processor.

[0008] The processor can perform the following steps: lay out the facilities set in the semiconductor FAB using a first layout method or a second layout method, and simulate the results according to the layout method; and compare the simulation results using various parameters.

[0009] In an exemplary implementation, the processor can perform a simulation by receiving the size of a facility set in a semiconductor FAB, processing time, transmission time, etc.

[0010] In an exemplary implementation, the processor can perform a simulation by receiving the dimensions of a semiconductor FAB.

[0011] In an exemplary implementation, the processor may compare the daily or hourly output of the facility located in the semiconductor FAB.

[0012] In an exemplary implementation, the processor can compare the production volume with the space and price of the semiconductor FAB.

[0013] In an exemplary embodiment, the processor may compare the daily or hourly output of the transmission or processing modules in a facility located in a semiconductor FAB during a down situation.

[0014] In an exemplary implementation, the processor can perform visual datalizing of daily or hourly output using charts or tables based on changes in processing time.

[0015] In an exemplary embodiment, the first layout method may be a method of arranging facilities on both sides facing each other in a semiconductor FAB and inserting channels between the facilities, and the second layout method may be a method of arranging the facilities in a zigzag pattern in a semiconductor FAB without space.

[0016] Another exemplary embodiment of the present invention provides a non-transitory computer-readable medium for storing program code that can be executed by a processor.

[0017] Another exemplary embodiment of the present invention provides a method for performing semiconductor facility layout simulation using a computer system.

[0018] The method may include the following steps: determining the layout method of the facility set up in the semiconductor FAB; inputting the size, processing time, transfer time, etc. of the facility set up in the semiconductor FAB; performing a simulation based on the input values; and visualizing and displaying the results of the simulation.

[0019] In an exemplary implementation, in determining the layout method of facilities disposed in a semiconductor FAB, either a first layout method or a second layout method may be determined, wherein the first layout method is to arrange facilities on both sides of the semiconductor FAB facing each other and inserting channels between the facilities, and the second layout method is to arrange facilities in the semiconductor FAB in a zigzag pattern without space.

[0020] In an exemplary implementation, when inputting the dimensions, processing time, and transmission time of the facility set in the semiconductor FAB, the dimensions of the semiconductor FAB can be entered together.

[0021] In an exemplary implementation, visualization of the execution results may involve visualizing and displaying the results of the daily or hourly output of the facility set up in the semiconductor FAB.

[0022] In an exemplary implementation, visualization of the results can be achieved by visualizing and displaying the results of the yield versus the space and price ratio of semiconductor FABs.

[0023] In an exemplary implementation, visualization of the results may involve visualizing and displaying the results of the transfer or processing modules in the facility located in the semiconductor FAB in a shutdown state, or the daily or hourly output of the facility.

[0024] According to the present invention, efficiency can be analyzed based on the facility layout method in semiconductors.

[0025] The effects of this invention are not limited to those described above. Those skilled in the art will clearly understand any effects not mentioned from this specification and the accompanying drawings. Attached Figure Description

[0026] Figure 1 A block diagram of a computer system capable of performing semiconductor facility layout simulation according to an exemplary embodiment of the present invention is shown.

[0027] Figure 2A and Figure 2B These are figures used to describe a semiconductor facility layout method according to an exemplary embodiment of the present invention.

[0028] Figures 3 to 8 This is a diagram illustrating the results of a simulation performed by a computer system or non-transitory computer-readable medium capable of performing semiconductor facility layout simulation, according to an exemplary embodiment of the present invention.

[0029] Figure 9 This is a flowchart illustrating a semiconductor facility layout simulation method according to an exemplary embodiment of the present invention. Detailed Implementation

[0030] In the following description, exemplary embodiments of the invention will be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments of the invention. However, the invention may be implemented differently and is not limited to the following embodiments. In the following description of the invention, detailed descriptions of known functions and configurations incorporated herein are omitted to avoid obscuring the subject matter of the invention. Furthermore, throughout the drawings, the same reference numerals are used for components having similar functions and effects.

[0031] Unless explicitly stated otherwise, the word "include" and variations such as "includes" or "including" shall be construed as implying the inclusion of the stated element but not excluding any other element. It should be understood that the terms "include" and "have" are intended to indicate the presence or combination thereof of the features, quantities, steps, operations, constituent elements and components described in the specification, and do not exclude the prior presence or addition of one or more other features, quantities, steps, operations, constituent elements and components, or combinations thereof.

[0032] The singular expressions used in this article include plural expressions unless they have a clearly contradictory meaning in the context. Therefore, the shape, size, etc. of the elements in the figure may be exaggerated for the sake of clarity.

[0033] Figure 1 A block diagram of a computer system capable of performing semiconductor facility layout simulation according to an exemplary embodiment of the present invention is shown.

[0034] The simulation method described below can be executed by a computer device. The computer device may include at least one of a computer, workstation, server, desktop PC, netbook, smartphone, tablet PC, mobile phone, video phone, e-book reader, PDA, PMP, MP3 player, medical device, electronic device, and wearable device. Furthermore, the computer device can be implemented in a centralized data storage environment or in a distributed data storage environment.

[0035] Figure 1 This is a block diagram used to describe a simulation device according to some exemplary embodiments of the present invention. Figure 1 It shows the method for performing use Figure 3 Exemplary computing devices or non-transitory computer-readable media of the simulation methods described in 9.

[0036] Reference Figure 1 According to some exemplary embodiments of the present invention, the simulation device 1 may include a processor 10, a memory 20, a display 30, an interface unit 40, a bus 50, etc.

[0037] Various components, such as processor 10, memory 20, display 30, and interface unit 40, can be connected to and communicate with each other (i.e., control message transmission and data transmission) via bus 50.

[0038] Processor 10 may include one or more of a central processing unit, an application processor, and a communication processor (CP). Processor 10 may perform operations or data processing, such as control and / or communication for at least one other component of a computing device or a non-transitory computer-readable medium.

[0039] Memory 20 may include volatile memory (e.g., DRAM, SRAM, or SDRAM) and / or non-volatile memory (e.g., one-time programmable ROM (OTPROM), PROM, EPROM, EEPROM, mask ROM, flash ROM, flash memory, PRAM, RRAM, MRAM, hard disk drive, or solid state drive (SSD)). Memory 20 may include internal memory and / or external memory. Memory 20 may store, for example, instructions or data related to at least one other component of the electronic device. Furthermore, memory 20 may store software and / or programs. These programs may include, for example, kernels, middleware, application programming interfaces (APIs), and / or applications (or "applications"). At least a portion of the kernel, middleware, or API may be referred to as an operating system.

[0040] Memory 20 stores instructions for executing the simulation method described below.

[0041] On the other hand, a non-transitory computer-readable medium can be provided, which stores a program that sequentially executes a simulation method according to some exemplary embodiments of the present invention. A non-transitory computer-readable medium refers to a medium in which data is stored semi-permanently and is readable by a computer, rather than a medium in which data is temporarily stored, such as registers, caches, memories, etc. Specifically, the various applications or programs described above can be stored and provided in non-transitory computer-readable media, such as CDs, DVDs, hard disks, Blu-ray discs, USB drives, memory cards, or ROMs.

[0042] Display 30 may include, for example, a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic light-emitting diode (OLED) display, a microelectronic machine system (MEMS) display, or an electronic paper display. Display 30 may display various content to the user, such as text, images, videos, icons, and / or symbols. Display 30 may include a touchscreen and may receive touch, gesture, proximity, or hover input, for example, using an electronic pen or a part of the user's body.

[0043] Interface unit 40 allows the computing device to communicate with external systems via a network. Here, the network includes both wired and wireless methods. Specifically, wireless communication may include, for example, LTE, LTE-A (LTE-Advanced), CDMA (Code Division Multiple Access), WCDMA (Wideband CDMA), Universal Mobile Telecommunications System (UMTS), Wireless Broadband (WiBro), or Global System for Mobile Communications (GSM). Alternatively, wireless communication may include at least one of Wireless Fidelity (WiFi), Light Fidelity (LiFi), Bluetooth, Bluetooth Low Energy (BLE), Zigbee, Near Field Communication (NFC), Magnetic Secure Transmission, Radio Frequency (RF), or Body Area Network (BAN). Alternatively, wireless communication may include GNSS. GNSS can be, for example, the Global Positioning System (GPS), the Global Navigation Satellite System (GLONASS), the BeiDou Navigation Satellite System (hereinafter referred to as "BeiDou"), or Galileo, as well as the European Global Navigation Satellite System. Wired communication can include at least one of the following: Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI), RS-232, Power Line Communication or Plain Old Telephone Service (POTS), and computer networks (such as Local Area Networks (LANs) or Wide Area Networks (WANs)).

[0044] The memory 20 according to an exemplary embodiment of the present invention may include a simulation unit 21 and a comparison unit 22. According to the present invention, the simulation unit 21 may lay out facilities disposed in a semiconductor FAB using a first layout method or a second layout method, and simulate the results according to the layout method. According to the present invention, the comparison unit 22 may compare and visualize the results simulated by the simulation unit 21 using various parameters.

[0045] The semiconductor facility layout simulation according to the present invention has the following effects: by executing a layout method for a semiconductor facility of a predetermined size, and by applying values ​​such as the size and processing time of the layout semiconductor facility directly input by the user to perform the simulation, productivity can be confirmed based on various conditions of the layout method or facility.

[0046] The simulation unit 21 according to the present invention can perform simulation by receiving various values. According to an exemplary embodiment, the simulation unit 21 can receive values ​​such as the size of a facility disposed in a semiconductor FAB, processing time, and transmission time to perform simulation. According to another exemplary embodiment, the simulation unit 21 can perform simulation by receiving the size of the semiconductor FAB.

[0047] According to the present invention, the simulation unit 21 can lay out the facility and perform a simulation by selecting either a first layout method or a second layout method. According to another exemplary embodiment of the present invention, the simulation unit 21 can perform a simulation according to each of the first and second layout methods, and transmit the simulation results according to each layout method to a comparison unit to compare the results of each parameter. The details of the first and second layout methods will be described below using FIG2.

[0048] According to the present invention, the comparison unit 22 can compare and visualize the simulation results of the simulation unit 21 using various parameters. The parameters used in the comparison unit 22 to compare the simulation results can be the wafer production per day (WPD) of the facility located in the semiconductor FAB. The parameters used in the comparison unit 22 to compare the simulation results can also be the unit per equipment hour (UPEH) of the facility located in the semiconductor FAB.

[0049] According to another exemplary embodiment of the present invention, the parameters for comparing simulation results in comparison unit 22 may be the wafer production to space and price (WPPS) ratio of semiconductor FAB.

[0050] That is, according to the present invention, the comparison unit 22 compares the yield results of various layout structures simulated by the simulation unit 21, thereby determining the optimal layout structure.

[0051] According to another exemplary embodiment of the present invention, the comparison unit 22 can compare the daily or hourly output of the transmission module or processing module installed in the semiconductor facility during a shutdown state. When assuming a shutdown of the transmission module or processing module in the semiconductor facility, the simulation unit 21 can input the number of wafers lost during the shutdown state, and the comparison unit 22 can output the output reflecting the input number of lost wafers, and compare the output outputs in a visual form.

[0052] Furthermore, according to the present invention, the comparison unit 22 has the following effect: it displays the results of various production parameters in graph or table form according to the changes in processing time, so as to visually digitize the production parameter results. As a result, it is more convenient for users to compare.

[0053] The processing methods of the simulation unit 21 and the comparison unit 22 described above can be stored in the memory 20, which stores program code executable by the processor 10.

[0054] The semiconductor facility layout simulation method according to the present invention, which uses actual simulation results, will be described in more detail below.

[0055] Figure 2A and 2B These are figures used to describe a semiconductor facility layout method according to an exemplary embodiment of the present invention.

[0056] Figure 2A The first layout method is shown, and Figure 2B The second layout method is shown.

[0057] The first layout method refers to arranging facilities on both sides facing each other in a semiconductor FAB, and inserting passages between the facilities. The second layout method refers to arranging facilities in a sawtooth pattern in a semiconductor FAB, without any space constraints.

[0058] Figure 2A It shows the traditional layout method, while Figure 2B This illustrates a newly proposed layout method in this invention. According to... Figure 2A Traditional layout methods follow general facility layout practices. It can be confirmed that facilities are arranged horizontally facing each other on both sides, with passageways for pedestrians. (See reference...) Figure 2B It can be confirmed that the facilities are based on EFEM, which do not face each other on both sides, but are instead compressed in a layout with no space. According to Figure 2B In one exemplary implementation, the facility can be laid out in a sawtooth pattern.

[0059] Since the number of semiconductor facilities deployed varies depending on the layout of the facilities within the limited space of the FAB, as well as variations in facility throughput and space efficiency, throughput varies depending on the chosen layout method, necessitating a comparison of throughput. Therefore, in this invention, two layout methods are selected to compare and analyze the throughput under each layout method.

[0060] According to the present invention, simultaneous comparison of two layout methods is possible. Therefore, each layout method can be compared and analyzed. According to the present invention, each facility layout method is simulated by inputting various parameters (such as the number of processing modules for each facility type within the limited space of the FAB, processing time, etc.), thereby determining the output and space efficiency according to each layout method through simulation.

[0061] Figures 3 to 8 This is a diagram illustrating the results of a simulation performed by a computer system or non-transitory computer-readable medium capable of performing semiconductor facility layout simulation, according to an exemplary embodiment of the present invention.

[0062] From Figures 3 to 8 The abbreviations for the simulation results have the following meanings.

[0063] UPEH refers to the output per unit of time of a single piece of equipment. WPD refers to the daily wafer production. WPPS refers to the daily wafer production, in relation to space and price. The price ratio sets the price of a specific facility as a reference of 1 and writes the price of the remaining facilities as the ratio. According to an exemplary implementation, the price ratio can be displayed as 0.98 in 98% of cases, while in 150% of cases, the price ratio can be displayed as 1.5.

[0064] according to Figure 3 For each PM, it has the effect of confirming the output per unit time (UPEH) and daily wafer production (WPD) for each machine. According to Figure 3 The result could be the result of either the first layout method or the second layout method. Figure 3 The table shows the wafer yield that users can obtain based on the configured layout method. Figure 3 It can automatically calculate and compare the daily wafer production (WPD) and the production per unit time (UPEH) of a semiconductor facility by receiving data such as the size, processing time, and transmission time of each facility type.

[0065] according to Figure 4 For each PM, it has the effect of confirming wafer yield, price, and space ratio (WPPS). Figure 4 It has the effect of calculating WPPS values ​​by inputting various values ​​(such as chamber size, price ratio, system size, etc.) and confirming the calculated WPPS values ​​in tabular form.

[0066] Reference Figure 5 The unit output per hour (UPEH), daily wafer production (WPD), unit output per equipment hour per processing module (UPEH per PM), and daily wafer production per processing module (WPD per PM) can be displayed graphically based on each processing time. This results in the ability to verify output trends based on processing time. Furthermore, the visualized data can be analyzed. According to an exemplary implementation, specific values ​​can be confirmed by representing them in tabular form. In tabular form, the data on item values ​​can be compared and analyzed based on changes in processing time.

[0067] Reference Figure 5 This example illustrates a scenario where output is confirmed only within the corresponding facility model selected based on a specific facility model. In such an example, trends in MUPEH / WPD and UPEH / WPD per 1 PM can be analyzed based on variations in the processing time of the selected facility model.

[0068] Reference Figure 6 This illustrates an example of confirming yield changes for each PM based on yield selection. Figure 6 This allows us to select a facility model based on the output per unit time (UPEH per PM) of each processing module. In this example scenario, the selection criteria for each facility model can be compared and analyzed based on variations in processing time for the selected output.

[0069] Reference Figure 7 This shows an example of a scenario where the transfer module (TM) is shut down.

[0070] Reference Figure 7 During normal progress and TM downtime of 1 to 23 hours, the trend of UPEH / WPD value can be analyzed based on the changes in processing time in the selected facility model.

[0071] Reference Figure 8 The illustration shows an example of a processing module (PM) shutdown scenario. In the event of a PM shutdown, the number of wafers to be lost can be selected and entered.

[0072] Reference Figure 8 During normal operation and when the selected number of PMs is down for 1 to 23 hours, the trend of UPEH / WPD value can be analyzed based on the changes in processing time in the selected facility model.

[0073] According to the present invention, facility layout can be simulated using various methods based on the number of processing modules, processing time, etc., for each facility type in a specific space of the semiconductor FAB, thereby determining the output, space, and price efficiency for each layout method through simulation. Furthermore, during TM or PM shutdowns, the shutdown time and the number of shutdown modules are received, and the results can also be used to analyze output variations.

[0074] According to the semiconductor facility layout simulation system of the present invention, the layout method can be used as an image to support preview. Furthermore, it can support viewing the maximum number of PMs and PM chambers in the layout, changing the size of each space or facility type, and performing simulations under various conditions.

[0075] According to an exemplary implementation, by simultaneously comparing when a specific number of PMs are arranged in a specific FAB space and when the maximum number of PMs is arranged in a specific FAB space, designers can easily determine productivity based on the space layout to help determine space efficiency based on the layout.

[0076] According to the present invention, the daily wafer production output (WPD), the output per unit time (UPEH) of a single equipment, and the daily and hourly output can be automatically calculated for each PM. Furthermore, according to the present invention, the output of different facility types can be compared. Furthermore, when determining the comparison results, processing time, transmission time, etc., can be changed and controlled.

[0077] Figure 9 This is a flowchart illustrating a semiconductor facility layout simulation method according to an exemplary embodiment of the present invention.

[0078] according to Figure 9 The method for performing semiconductor facility layout simulation using the semiconductor facility layout simulation system according to the present invention can determine the layout method of the facilities set up in the semiconductor FAB. The determined layout method can be a first layout method as a linear layout method or a second layout method as a zigzag layout method. After determining the layout method, values ​​such as the size, processing time, and transfer time of the facilities set up in the semiconductor FAB can be input. The size of the semiconductor FAB can also be input at this time. Subsequently, the simulation can be performed by simultaneously considering the input values ​​and the layout method. The results of the simulation can then be visualized and displayed. The daily or hourly output of the facilities set up in the semiconductor FAB can then be visualized and displayed. According to another exemplary embodiment, the comparison results of the semiconductor FAB's output with space and price ratios can also be visualized and displayed. According to yet another exemplary embodiment, the daily or hourly output of the facility can be visualized and displayed when the transfer module or processing module in the semiconductor facility is down.

[0079] According to the present invention, by proposing a system and method capable of imaging or comparing facilities of each facility type arranged in two layout methods in a specific semiconductor FAB space, and by confirming the efficiency based on each layout method and condition of the facility, a suitable layout method can be easily determined.

[0080] It should be understood that exemplary embodiments are provided to aid in understanding the invention, and the scope of the invention is not limited, with various modifications of the invention included within its scope. The accompanying drawings provided in this invention are merely illustrative of the best exemplary embodiments. The scope of protection of this invention should be determined by the technical concept of the appended claims, and it should be understood that the scope of protection of this invention is not limited to the literal disclosure in the appended claims, and the technical value is substantially affected by the equivalent scope of the invention.

Claims

1. A computer system, the computer system comprising: processor; as well as The memory stores program code executable by the processor. The processor performs the following steps: Multiple facilities in a semiconductor FAB are laid out using a first layout method or a second layout method, and a first result and a second result are simulated according to the first layout method and the second layout method, respectively; and The first and second results from the simulation were compared using various parameters. The first layout method is a method of arranging the plurality of facilities on both sides facing each other in the semiconductor FAB and inserting channels between the facilities, and the second layout method is a method of arranging the plurality of facilities in the semiconductor FAB in a zigzag pattern without space. The processor performs simulations of the first layout method and the second layout method by receiving the dimensions, processing time, and transmission time of the plurality of facilities disposed in the semiconductor FAB. The processor further performs the simulation of the first layout method and the second layout method by receiving the dimensions of the semiconductor FAB. The processor uses the daily or hourly output of the plurality of facilities located in the semiconductor FAB to compare the first result and the second result; The processor further uses the daily or hourly output of the plurality of facilities in the semiconductor FAB, in a shutdown state, to compare the first result and the second result.

2. The computer system according to claim 1, wherein, The processor also uses the production volume to compare the space and price ratio of the semiconductor FAB to the first result and the second result.

3. The computer system according to claim 1 or 2, wherein, The processor performs visual data visualization of daily or hourly output using charts or tables based on changes in processing time.

4. A non-transitory computer-readable medium for storing processor-executable program code, wherein, The processor performs the following steps: Multiple facilities in a semiconductor FAB are laid out using a first layout method or a second layout method, and a first result and a second result are simulated according to the first layout method and the second layout method, respectively. as well as The first and second results of the simulation were compared using various parameters; The first layout method is a method of arranging multiple facilities on both sides facing each other in the semiconductor FAB and inserting channels between the facilities, and the second layout method is a method of arranging the multiple facilities in the semiconductor FAB in a zigzag pattern without space. The processor performs the simulation of the first layout method and the second layout method by receiving the dimensions, processing time, and transmission time of the plurality of facilities set in the semiconductor FAB; The processor further performs the simulation of the first layout method and the second layout method by receiving the dimensions of the semiconductor FAB. The processor uses the daily or hourly output of the plurality of facilities located in the semiconductor FAB to compare the first result and the second result. The processor further uses the daily or hourly output of the plurality of facilities in the semiconductor FAB, in a shutdown state, to compare the first result and the second result.

5. The non-transitory computer-readable medium according to claim 4, wherein, The processor also uses the production volume to compare the space and price ratio of the semiconductor FAB to the first result and the second result.

6. The non-transitory computer-readable medium according to claim 4 or 5, wherein, The processor performs visual data visualization of daily or hourly output using charts or tables based on changes in processing time.

7. A semiconductor facility layout simulation method using a computer system according to claim 1 to perform semiconductor facility layout simulation, the semiconductor facility layout simulation method comprising the following steps: Determine the layout method for multiple facilities set up in the semiconductor FAB; Input the dimensions, processing time, and transfer time of the plurality of facilities set in the semiconductor FAB; Perform a simulation based on the input value; and Visualize and display the results of the simulation.

8. The semiconductor facility layout simulation method according to claim 7, wherein, In the method of determining the layout of the plurality of facilities disposed in the semiconductor FAB, either a first layout method or a second layout method is determined, wherein the first layout method arranges the plurality of facilities on both sides facing each other in the semiconductor FAB and inserts channels between the facilities, and the second layout method arranges the plurality of facilities in the semiconductor FAB in a zigzag pattern without space.

9. The semiconductor facility layout simulation method according to claim 8, wherein, When inputting the dimensions, processing time, and transfer time of the plurality of facilities set in the semiconductor FAB, the dimensions of the semiconductor FAB are also input.

10. The semiconductor facility layout simulation method according to claim 9, wherein, The visualization of the results of the execution involves visualizing and displaying the daily or hourly output of the multiple facilities set up in the semiconductor FAB.

11. The semiconductor facility layout simulation method according to claim 10, wherein, The visualization of the results involves visualizing and displaying the output relative to the spatial and price ratio of the semiconductor FAB.

12. The semiconductor facility layout simulation method according to claim 11, wherein, The visualization of the results of the execution is to visualize and display the daily or hourly output of the transmission or processing modules in the plurality of facilities set up in the semiconductor FAB in a shutdown state.

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