Non-volatile memory devices and integration schemes with metal-insulator-metal (MIM) capacitors in a substrate

Abstract

The present invention relates to non-volatile memory devices and integration schemes with metal-insulator-metal (MIM) capacitors in a substrate. A non-volatile memory device is provided. The non-volatile memory device includes a floating gate disposed over a first active region, where the first active region is located in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor can be disposed laterally adjacent to the floating gate, where a portion of the metal-insulator-metal capacitor is located in the active layer. A contact pillar can connect a first electrode of the metal-insulator-metal capacitor to the floating gate.

Description

Technical Field

[0001] The disclosed embodiments generally relate to non-volatile memory devices, and more specifically to non-volatile memory devices and integration schemes having metal-insulator-metal (MIM) capacitors in a substrate. Background Technology

[0002] Even when power is off, non-volatile memory devices retain the stored data. Examples of non-volatile memory devices include electrically erasable programmable read-only memory (EEPROM) and flash EEPROM. In a typical flash memory architecture, a floating gate is used to store charge. The floating gate can be arranged above an active region such as a p-well. The source region can be formed in the p-well adjacent to a first side of the floating gate, and the drain region can be formed in the p-well adjacent to a second side of the floating gate (opposite to the first side). A metal-insulator-metal capacitor can be used to bias the floating gate. The metal-insulator-metal capacitor is located in a back-end process (BEOL) layer above the floating gate. The term "back-end process" can refer to a part of semiconductor processing that forms conductive lines for transmitting power and signals between devices such as transistors and semiconductor chip interfaces.

[0003] Due to space constraints in the back-end process layer, the coupling ratio between non-volatile memory devices and the metal-insulator-metal capacitors in the back-end process layer above the floating gate is insufficient. This problem is further exacerbated at advanced technology nodes as the feature size of non-volatile memory devices shrinks. Low coupling ratios result in higher programming and erasing voltages and shorter device lifetimes. Therefore, overcoming these challenges is necessary. Summary of the Invention

[0004] In one aspect of this disclosure, a non-volatile memory device is provided. The non-volatile memory device includes a floating gate disposed over a first active region, wherein the first active region may be disposed in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be disposed laterally adjacent to the floating gate, wherein a portion of the MIM capacitor may be located in the active layer. Contact posts may connect a first electrode of the MIM capacitor to the floating gate.

[0005] In another aspect of this disclosure, a non-volatile memory device array is provided. The non-volatile memory device array includes a first active region and a second active region disposed in an active layer of a substrate. A first isolation region and a second isolation region adjacent to the first isolation region may be disposed between the first active region and the second active region. A first floating gate array may be disposed above the first active region, and a second floating gate array may be disposed above the second active region. A metal-insulator-metal capacitor may be disposed laterally adjacent to the floating gates, wherein the lower portion of the metal-insulator-metal capacitor may be disposed in the first isolation region of the active layer and in a first dielectric layer of the substrate, and contact posts may connect a first electrode of the metal-insulator-metal capacitor to each floating gate.

[0006] In another aspect of this disclosure, a method for manufacturing a non-volatile memory device is provided. The method includes disposing a floating gate over a first active region, wherein the first active region may be disposed in an active layer of a substrate. Contact pillars may be disposed over the floating gate. A metal-insulator-metal capacitor may be disposed laterally adjacent to the floating gate, wherein a portion of the metal-insulator-metal capacitor may be disposed in the active layer, and a first electrode of the metal-insulator-metal capacitor may be connected to the floating gate via the contact pillars.

[0007] Many advantages can be obtained from the embodiments described below. The embodiments provide a non-volatile memory device with a high coupling ratio. The second electrode of a metal-insulator-metal capacitor can be connected to an input terminal. The term "coupling ratio" can refer to the voltage transfer capability from the metal-insulator-metal capacitor to the floating gate. The lower portion of the metal-insulator-metal capacitor can be disposed in a first isolation region. The upper portion of the first isolation region can be surrounded by a second isolation region adjacent to the first active region, thereby forming a compact non-volatile memory device. The second isolation region can be a shallow trench isolation region. An extension of the metal-insulator-metal capacitor can be disposed on an inter-metal dielectric (IMD) layer above the floating gate, resulting in a high capacitance value and a high coupling ratio. The metal-insulator-metal capacitor can extend across the length of at least the active region, providing a high coupling ratio for the non-volatile memory device. The lower portion of the metal-insulator-metal capacitor can be separated from the base layer of the substrate by a portion of the first dielectric layer. Therefore, the metal-insulator-metal capacitor is electrically insulated from the base layer of the substrate, resulting in stable device operation. Attached Figure Description

[0008] The disclosed embodiments will be better understood by reading the following detailed description taken in conjunction with the accompanying drawings:

[0009] Figure 1 A is a top view of a non-volatile memory device array according to an embodiment of the present disclosure.

[0010] Figure 1 B is a section taken along the cross-section A-A' according to an embodiment of this disclosure. Figure 1 A is a cross-sectional view of the non-volatile memory device array shown in Figure A.

[0011] Figures 2 to 7 Some embodiments according to this disclosure are shown. Figure 1 The manufacturing process flow for the non-volatile memory device array shown in B.

[0012] For simplicity and clarity, the accompanying drawings illustrate general construction methods, and specific descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of embodiments of the described device. Furthermore, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding embodiments of the device. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements. Detailed Implementation

[0013] The following detailed description is exemplary in nature and is not intended to limit the devices or their applications and uses. Furthermore, it is not intended to be bound by the foregoing background of these devices or any theory set forth in the following detailed description.

[0014] Figure 1 A is a top view of a non-volatile memory device array 100 according to an embodiment of the present disclosure. (See reference...) Figure 1A non-volatile memory device array 100 is provided. The non-volatile memory device array 100 may include a first active region 102a and a second active region 102b. A first floating gate array 112a may be disposed over the first active region 102a, and a second floating gate array 112b may be disposed over the second active region 102b. A first doped region 106 may be disposed in the first active region 102a and the second active region 102b and adjacent to a first side 116 of the first floating gate array 112a and the second floating gate array 112b, respectively. A second doped region 110 may be disposed in the first active region 102a and the second active region 102b and adjacent to a second side 118 of the first floating gate array 112a and the second floating gate array 112b, respectively. The first side 116 of the floating gates 112a and 112b may be opposite to the second side 118. For example, the first doped region 106 can be the source, the second doped region 110 can be the drain, and the floating gate 112a or 112b can be the charge storage region of a non-volatile memory transistor. The term "floating gate" can refer to a gate electrode that is electrically isolated from the input terminal and can be capacitively coupled to the input terminal. During a read operation, no DC current flows from the input terminal to the floating gate.

[0015] Contact 114 can be disposed above the first doped region 106 and contact 124 can be disposed above the second doped region 110 for connection to an external input terminal. A metal-insulator-metal (MIM) capacitor 108 can be disposed laterally adjacent to floating gates 112a and 112b, whereby the lower portion of the MIM capacitor 108 can be disposed in the substrate. For simplicity, Figure 1 A substrate is not shown in A. The extension of the metal-insulator-metal capacitor 108 is depicted as a dashed outline. The extension of the metal-insulator-metal capacitor 108 may at least partially overlap with a portion of the first active region 102a and the second active region 102b, as well as the first floating gate array 112a and the second floating gate array 112b. In one embodiment, the metal-insulator-metal capacitor 108 may extend across at least a portion of the length of the first active region 102a and the second active region 102b, thereby providing a non-volatile memory device array 100 with a high coupling ratio. In another embodiment, the metal-insulator-metal capacitor 108 may extend beyond the length of the first active region 102a and the second active region 102b. Contact posts 120a and 120b may connect the first electrode 122 of the metal-insulator-metal capacitor 108 to the first floating gate array 112a and the second floating gate array 112b, respectively. Contact 150 can couple the second electrode 128 of the metal-insulator-metal capacitor 108 to an external input terminal.

[0016] Figure 1B is a section taken along the cross-section A-A' according to an embodiment of this disclosure. Figure 1 A is a cross-sectional view of the non-volatile memory device array 100 shown in Figure A. (Reference) Figure 1 B. The first active region 102a and the second active region 102b may be located in the active layer 158 of the substrate 178. The first isolation region 152a and the second isolation region 156a may be located in the active layer 158 of the substrate 178 between the first active region 102a and the second active region 102b. In one embodiment, the first isolation region 152a may extend to the first dielectric layer 160 of the substrate 178. In another embodiment, the first isolation region 152a may extend to the upper portion of the first dielectric layer 160. The lower portion of the metal-insulator-metal capacitor 108 may be located in the first isolation region 152a. In one embodiment, the lower portion of the capacitor 108 may extend vertically within the thickness of the active layer 158. In another embodiment, the lower portion of the capacitor 108 may extend vertically below the active layer 158 into the first dielectric layer 160 of the substrate 178, and in one embodiment, extends into the upper portion of the first dielectric layer 160 of the substrate 178.

[0017] A first isolation region 152a may surround the lower portion of a metal-insulator-metal capacitor 108. In one embodiment, the first isolation region 152a may surround the side and bottom surfaces of the lower portion of the metal-insulator-metal capacitor 108. In an alternative embodiment, the first isolation region 152a may surround the side surfaces of the lower portion of the metal-insulator-metal capacitor 108, and the bottom surface of the metal-insulator-metal capacitor 108 may contact the first dielectric layer 160 of the substrate 178. A second isolation region 156a may be adjacent to the upper portion of the first isolation region 152a. In one embodiment, the second isolation region 156a may partially surround the upper portion of the first isolation region 152a. In another embodiment, the second isolation region 156a may completely surround the upper portion of the first isolation region 152a. The first isolation region 152a may be deep trench isolation (DTI) and the second isolation region 156a may be shallow trench isolation (STI). The first isolation region 152a may be located within the second isolation region 156a. The lower portion of the metal-insulator-metal capacitor 108 does not occupy additional lateral space because it is located within the first isolation region 152a. In one embodiment, the first isolation region 152a and the second isolation region 156a may be located between the lower portion of the metal-insulator-metal capacitor 108 and the first active region 102a below the first floating gate array 112a and the second active region 102b below the second floating gate array 112b.

[0018] Isolation regions 152 and 156 may be laterally adjacent to the first active region 102a or the second active region 102b. Isolation region 156 may be adjacent to the upper portion of isolation region 152. Isolation region 156 may be a shallow trench isolation and isolation region 152 may be a deep trench isolation. In an alternative embodiment, the lower portion of the metal-insulator-metal capacitor 108 may be disposed in isolation region 152.

[0019] Substrate 178 may include a base layer 162, a first dielectric layer 160 over the base layer 162, and an active layer 158 over the first dielectric layer 160. In one embodiment, the base layer 162 may be made of a suitable semiconductor material (e.g., silicon). In one embodiment, the first dielectric layer 160 may be made of a suitable dielectric material (e.g., silicon dioxide). In one embodiment, the active layer 158 may be made of a suitable semiconductor material (e.g., silicon). In one embodiment, substrate 178 may be a silicon-on-insulator (SOI) substrate. In a preferred embodiment, a portion of the lower part of the first dielectric layer 160 and a portion of the first isolation region 152 may be located between the metal-insulator-metal capacitor 108 and the base layer 162 of substrate 178 to electrically insulate the metal-insulator-metal capacitor 108 from the base layer 162 of substrate, thereby ensuring stable device operation. In an alternative embodiment, the lower part of the first dielectric layer 160 may be located between the metal-insulator-metal capacitor 108 and the base layer 162 of substrate 178. In another embodiment, a portion of the first isolation region 152a may be located between the metal-insulator-metal capacitor 108 and the base layer 162 of the substrate 178.

[0020] An interlayer dielectric (ILD) layer 166a may be disposed on the substrate 178. The upper portion of the metal-insulator-metal (MIM) capacitor 108 may extend vertically within the interlayer dielectric layer 166a above the substrate 178. An intermetallic dielectric (IMD) layer 166b may be disposed on the interlayer dielectric layer 166a. The extended portion of the upper portion of the metal-insulator-metal capacitor 108 may extend laterally within the intermetallic dielectric layer 166b above the interlayer dielectric layer 166a, and at least partially overlap laterally with the first floating gate array 112a and the second floating gate array 112b.

[0021] The first electrode 122 of the metal-insulator-metal capacitor 108 can be disposed on the side and bottom surfaces of the metal-insulator-metal capacitor 108. For example, the first electrode 122 can be conformally formed at least on the side and bottom surfaces of the opening 104 through the first isolation region 152a and the interlayer dielectric layer 166a. A dielectric layer 126 can be disposed over the first electrode 122 of the metal-insulator-metal capacitor 108. In a preferred embodiment, the dielectric layer 126 can be made of a high dielectric constant (high k) dielectric layer. The term "high dielectric constant dielectric layer" can refer to a dielectric material layer with a dielectric constant greater than 20. In an alternative embodiment, the dielectric layer 126 can be made of silicon dioxide or silicon nitride (Si3N4). The second electrode 128 of the metal-insulator-metal capacitor 108 can be disposed over the high dielectric constant dielectric layer 126. Contact post 120a can connect the first electrode 122 of the metal-insulator-metal capacitor 108 to the first floating gate array 112a. Contact post 120b can connect the first electrode 122 of the metal-insulator-metal capacitor 108 to the second floating gate array 112b.

[0022] Table 1

[0023]

[0024] Table 1 shows the uses Figure 1 A and Figure 1 A set of exemplary bias conditions for the non-volatile memory device array 100 shown in B. Programming can be performed via hot carrier injection. For example, during programming, a voltage of approximately 12V can be applied to the metal-insulator-metal capacitor 108. 0V can be applied to the first doped region 106 or source of the selected non-volatile memory transistor. A voltage of approximately 12V can be applied to the second doped region 110 or drain of the selected non-volatile memory transistor. 0V can be applied to the substrate 178 through the base region 162. The programming conditions create a strong vertical orientation electric field in the channel region between the first doped region 106 and the second doped region 110 of the selected non-volatile memory transistor, resulting in the injection of hot electrons into the edge portions of the floating gate 112a or 112b of the selected non-volatile memory transistor near the second doped region 110. The term "hot electron" can refer to electrons that acquire high kinetic energy due to the strong electric field.

[0025] Erasure can be performed via hot hole injection. During erasure, for example, 0V can be applied to the metal-insulator-metal capacitor 108. A voltage of approximately 0V can be applied to the first doped region 106 and the substrate 178 via the base region 162. A voltage of approximately 18V can be applied to the second doped region 110. Hot holes can be generated in the channel region between the first doped region 106 and the second doped region 110 and injected into the floating gates 112a and 112b to recombine with electrons stored in the floating gates 112a and 112b. The non-volatile memory device array 100 can be erased simultaneously. The term "hot hole" can refer to a hole that acquires high kinetic energy due to a strong electric field.

[0026] During a read operation, a voltage of approximately 2.5V can be applied to the metal-insulator-metal capacitor 108 of the selected non-volatile memory transistor. A voltage of approximately 1V can be applied to the second doped region 110 or the drain of the selected non-volatile memory transistor. 0V can be applied to the first doped region 106 or the source and substrate 178 through the base region 162. Depending on the threshold voltage of the selected non-volatile memory transistor, a current can be detected at the second doped region 110. For example, the threshold voltage of the selected non-volatile memory transistor is low after erasure, and a current can be detected at the second doped region 110. A programming operation can result in a high threshold voltage of the selected non-volatile memory transistor, and a small or negligible current can be detected at the second doped region 110.

[0027] Figures 2 to 7 Some embodiments according to this disclosure are shown. Figure 1 The manufacturing process flow of the non-volatile memory device array 100 shown in B. Figure 2 This is a cross-sectional view of a non-volatile memory device array 100 partially completed according to an embodiment of the present disclosure. Reference Figure 2 A substrate 178 may be provided. The substrate 178 may include a base layer 162, a first dielectric layer 160 disposed on the base layer 162, and an active layer 158 disposed on the first dielectric layer 160. A first isolation region 152a and a second isolation region 156a may be disposed in the substrate 178. The second isolation region 156a may be adjacent to the upper portion of the first isolation region 152a. A first active region 102a and a second active region 102b may be formed adjacent to the second isolation region 156a. Isolation regions 152 and 156 may be disposed in the substrate 178, adjacent to either the first active region 102a or the second active region 102b. The second isolation region 156a and isolation region 156 may thereby define the areas of the first active region 102a and the second active region 102b. In one embodiment, the first active region 102a and the second active region 102b may be p-type doped to form p-well regions.

[0028] The formation of the second isolation region 156a and isolation region 156 may include forming openings in the active layer 158 by conventional photolithography processes followed by wet or dry etching processes. Conventional photolithography processes may include depositing a photoresist layer over the active layer 158, followed by exposure and development to form a photoresist pattern. A portion of the active layer 158 not covered by the photoresist pattern may be removed using wet or dry etching processes, thereby forming openings in the active layer 158. The photoresist layer may then be removed. Suitable dielectric materials, such as borosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), or any other suitable dielectric material, may be deposited within the openings in the active layer 158 using suitable deposition processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any other suitable deposition process. A suitable planarization process, such as chemical mechanical polishing (CMP), can be used to remove a portion of the borosilicate glass layer from the top surface of the active layer 158, leaving another portion of the borosilicate glass layer in the opening in the active layer 158, thereby forming the second isolation region 156a and the isolation region 156.

[0029] The formation of the first isolation region 152a and isolation region 152 may include forming openings in a portion of the second isolation region 156a and isolation region 156, active layer 158, and first dielectric layer 160 by conventional photolithography processes followed by wet or dry etching. A suitable dielectric material layer, such as a high-density plasma (HDP) silicon dioxide layer or any other suitable dielectric material layer, may be deposited in the openings using a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable deposition process. A suitable planarization process, such as chemical mechanical polishing, may be used to remove a portion of the silicon dioxide layer from the top surface of the second isolation region 156a and isolation region 156 and active layer 158, leaving another portion of the silicon dioxide layer in the openings in the second isolation region 156a and isolation region 156, active layer 158, and first dielectric layer 160, thereby forming the first isolation region 152a and isolation region 152, respectively.

[0030] Figure 3 This is a cross-sectional view of a partially completed non-volatile memory device array 100 after forming a first floating gate array 112a and a second floating gate array 112b, spacer structures 172a and 172b, gate dielectric layers 170a and 170b, and an etch stop layer 176, according to embodiments of the present disclosure. (See also...) Figure 3A suitable dielectric material layer, such as a silicon dioxide layer, can be deposited over the active layer 158, the first active region 102a, the second active region 102b, the first isolation region 152a, and the second isolation region 156a using a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable deposition process. A doped polysilicon layer can be deposited over the silicon dioxide layer using a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable deposition process. In one embodiment, the polysilicon layer may be n-type doped. The doped polysilicon layer and the silicon dioxide layer below the doped polysilicon layer can be patterned using conventional photolithography processes and subsequent wet or dry etching to leave a portion of the doped polysilicon layer and silicon dioxide layer over the first active region 102a, thereby forming the first floating gate array 112a and the gate dielectric layer 170a below the first floating gate array 112a, respectively. Similarly, a wet or dry etching process following conventional photolithography can be used to pattern the doped polysilicon layer and the silicon dioxide layer beneath it, leaving a portion of the doped polysilicon layer and silicon dioxide layer over the second active region 102b, thereby forming the second floating gate array 112b and the gate dielectric layer 170b beneath it. A suitable dielectric material layer, such as a silicon dioxide layer, a silicon nitride (Si3N4) layer, or a silicon oxynitride (SiON) layer, can be deposited over the first floating gate array 112a and the second floating gate array 112b using a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable deposition process. Anisotropic etching can be used to pattern the silicon dioxide layer, leaving a portion of it on the sidewalls of the first floating gate array 112a and the second floating gate array 112b, thereby forming spacer structures 172a and 172b, respectively. An etch stop layer 176 can be formed by depositing a suitable dielectric material layer, such as a silicon nitride layer, over the active layer 158, the first isolation region 152a, the second isolation region 156a, the isolation structures 152 and 156, the spacer structures 172a and 172b, the first floating gate array 112a, and the second floating gate array 112b using a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable deposition process. The term "anisotropic etching" can refer to an etching process that is inherently directional.

[0031] Figure 4This is a cross-sectional view of a partially completed non-volatile memory device array 100 after the formation of the interlayer dielectric layer 166a and contact pillars 120a and 120b according to embodiments of the present disclosure. The interlayer dielectric layer 166a can be formed by depositing a suitable dielectric material layer, such as a silicon dioxide layer, a high-density plasma (HDP) undoped silicate glass (USG) layer, a tetraethyl orthosilicate (TEOS) layer, or any other suitable dielectric material layer, over the etch stop layer 176 using a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable deposition process. Openings can be formed in the interlayer dielectric layer 166a and the etch stop layer 176 to expose portions of the first floating gate array 112a and the second floating gate array 112b. The openings can be formed by conventional photolithography processes followed by wet or dry etching. A suitable conductive material layer, such as a tungsten (W) layer, can be deposited in the openings using a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable deposition process. A suitable planarization process, such as chemical mechanical planarization, can be used to remove a portion of the tungsten layer from the top surface of the interlayer dielectric layer 166a, leaving another portion of the tungsten layer in the opening, thereby forming contact posts 120a over the first floating gate array 112a and contact posts 120b over the second floating gate array 112b.

[0032] Figure 5 This is a cross-sectional view of a partially completed non-volatile memory device array 100 after an opening 104 has been formed in a portion of the interlayer dielectric layer 166a, the etch stop layer 176, and the first isolation region 152a, according to an embodiment of the present disclosure. Reference Figure 5 The opening 104 can be formed by conventional photolithography processes followed by wet or dry etching. The opening 104 can be formed in an interlayer dielectric layer 166a and an etch stop layer 176 located between the first floating gate array 112a and the second floating gate array 112b. In one embodiment, the opening 104 can extend to a portion of a first isolation region 152a between the first active region 102a and the second active region 102b. The first isolation region 152a can be laterally displaced relative to the first floating gate array 112a and the second floating gate array 112b. In a preferred embodiment, a portion of the first isolation region 152a can be disposed above the side and bottom surfaces of the opening 104. In an alternative embodiment, the opening 104 can extend to the bottom surface of the first isolation region 152a to expose a portion of the first dielectric layer 160 at the bottom surface of the opening 104.

[0033] Figure 6This is a cross-sectional view of a non-volatile memory device array 100 partially completed after the formation of conductive material layer 132, dielectric layer 136, and conductive material layer 138, according to embodiments of the present disclosure. (See also...) Figure 6 A suitable conductive material layer, such as a titanium nitride (TiN) layer, a titanium (Ti) layer, or any other suitable conductive material layer, can be deposited on the interlayer dielectric layer 166a, the contact pillars 120a above the first floating gate array 112a, the contact pillars 120b above the second floating gate array 112b, and the side and bottom surfaces of the opening 104, to form a conductive material layer 132. A suitable high-dielectric-constant dielectric material layer, such as a hafnium oxide (HfO2) layer, a silicon nitride (Si3N4) layer, an aluminum oxide (Al2O3) layer, a tantalum oxide (Ta2O5) layer, a zirconium oxide (ZrO2) layer, a hafnium silicate (HfSiO4) layer, or any other suitable high-dielectric-constant dielectric material layer, can be deposited on the conductive material layer 132 to form a dielectric layer 136. A suitable conductive material layer, such as a tungsten (W) layer, an aluminum (Al) layer, or any other suitable conductive material layer, can be deposited on top of the dielectric layer 136 and fill the opening 104 to form a conductive material layer 138. The deposition process of the conductive material layer 132, the dielectric layer 136, and the conductive material layer 138 can be achieved by a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable deposition process.

[0034] Figure 7 This is a cross-sectional view of a non-volatile memory device array 100 partially completed after the formation of the first electrode 122, the dielectric layer 126, and the second electrode 128, according to an embodiment of the present disclosure. Reference Figure 7 The conductive layer 138 can be patterned to form the second electrode 128 of the metal-insulator-metal capacitor 108. A suitable patterning process, such as photolithography, can be used to leave a portion of the conductive layer 138 in the opening 104 in the interlayer dielectric layer 166a and at least partially above the top surface of the interlayer dielectric layer 166a. The dielectric layer 136 can also be patterned simultaneously with or separately from the conductive layer 138 to form the dielectric layer 126. Similarly, the conductive layer 132 can be patterned simultaneously with or separately from the conductive layer 138 and the dielectric layer 136 to form the first electrode 122 of the metal-insulator-metal capacitor 108. In one example, the patterning of the conductive layer 138, the dielectric layer 136, and the conductive layer 132 can be achieved by conventional photolithography processes followed by wet or dry etching processes.

[0035] Figure 7 The non-volatile memory device array 100 is further processed to form Figure 1 The final device is shown in B. Return to reference. Figure 1 Figure B shows a cross-sectional view of a non-volatile memory device array 100 after the formation of a metallization layer 168 and an intermetallic dielectric (IMD) layer 166b, according to an embodiment of the present disclosure. The metallization layer 168 can be formed by a conventional stripping process. For example, a photoresist layer can be deposited over the top surface of the intermetallic dielectric layer 166a and the second electrode 128 of the metal-insulator-metal capacitor 108. Openings can be formed in the photoresist layer by exposure and development to expose the second electrode 128 of the metal-insulator-metal capacitor 108. A suitable conductive material layer, such as a copper (Cu) layer, an aluminum (Al) layer, or any other suitable conductive material layer, can be deposited in the openings by a suitable deposition process, such as electroplating, chemical vapor deposition, physical vapor deposition, or any other suitable deposition process. The photoresist layer can be removed to leave a portion of a copper layer over the second electrode 128 of the metal-insulator-metal capacitor 108, thereby forming the metallization layer 168. A suitable dielectric material, such as silicon dioxide, undoped silicate glass (USG), fluorinated silicate glass (FSG), tetraethyl orthosilicate (TEOS), or any other suitable dielectric material, can be deposited on the interlayer dielectric layer 166a and the metallization layer 168 to form the intermetallic dielectric layer 166b.

[0036] The terms “first,” “second,” “third,” etc. (if any) used in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a particular order or chronological sequence. It should be understood that such terms are interchangeable where appropriate so that embodiments of the devices described herein can operate, for example, in an order different from that shown or otherwise described herein. The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “above,” “below,” etc. (if any) used in the specification and claims are for descriptive purposes and are not necessarily used to describe permanent relative positions. It should be understood that such terms are interchangeable where appropriate so that embodiments of the devices described herein can operate, for example, in an orientation different from that shown or otherwise described herein. Similarly, if the method described herein comprises a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed; certain steps may be omitted and / or other specific steps not described herein may be added to the method. Furthermore, the terms “comprising,” “including,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device that includes a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or not inherent to those processes, methods, articles, or devices.

[0037] Although several exemplary embodiments have been given in the above detailed description of the device, it should be understood that many variations exist. It should also be understood that the embodiments are merely examples and are not intended to limit the scope, applicability, size, or configuration of the device in any way. Rather, the above detailed description will provide a convenient guide for those skilled in the art to implement exemplary embodiments of the device, and it will be understood that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments and the methods of manufacturing thereof without departing from the scope of this disclosure set forth in the appended claims.

Claims

1. A non-volatile memory device, comprising: A floating gate located above a first active region, wherein the first active region is located in an active layer of a substrate; A metal-insulator-metal (MIM) capacitor laterally adjacent to the floating gate, wherein a portion of the metal-insulator-metal capacitor is located in the active layer; as well as The first electrode of the metal-insulator-metal capacitor is connected to the contact post of the floating gate. The substrate includes a first dielectric layer located beneath the active layer, and the lower portion of the metal-insulator-metal capacitor extends vertically into the first dielectric layer. The metal-insulator-metal capacitor extends across at least a portion of the length of the first active region.

2. The non-volatile memory device of claim 1, wherein the lower portion of the metal-insulator-metal capacitor extends into the upper portion of the first dielectric layer in the substrate.

3. The non-volatile memory device of claim 1, wherein the upper portion of the metal-insulator-metal capacitor extends vertically in an interlayer dielectric (ILD) layer above the substrate.

4. The non-volatile memory device of claim 3, wherein the upper portion of the metal-insulator-metal capacitor further comprises: The extension portion extending laterally in the intermetallic dielectric (IMD) layer above the interlayer dielectric layer.

5. The non-volatile memory device of claim 4, wherein the extension portion at least partially overlaps laterally with the floating gate.

6. The non-volatile memory device according to claim 1, further comprising: A first isolation region is located in the substrate, which surrounds the lower part of the metal-insulator-metal capacitor.

7. The non-volatile memory device according to claim 6, further comprising: A second isolation region located in the active layer of the substrate, wherein the second isolation region is adjacent to the upper part of the first isolation region.

8. The non-volatile memory device of claim 7, wherein the first isolation region and the second isolation region are located between the lower portion of the metal-insulator-metal capacitor and the first active region below the floating gate.

9. The non-volatile memory device of claim 1, wherein the first electrode of the metal-insulator-metal capacitor is conformally fitted to the side surface and bottom surface of the metal-insulator-metal capacitor.

10. An array of non-volatile memory devices, comprising: The first active region and the second active region are located in the active layer of the substrate; The first isolation zone and the second isolation zone adjacent to the first isolation zone are located between the first active zone and the second active zone; A first floating gate array located above the first active region and a second floating gate array located above the second active region; A metal-insulator-metal capacitor laterally adjacent to the first floating gate array and the second floating gate array, wherein the lower portion of the metal-insulator-metal capacitor is located in the first dielectric layer in the substrate and in the first isolation region in the active layer; The first electrode of the metal-insulator-metal capacitor is connected to the contact post of each floating gate. The metal-insulator-metal capacitor extends across at least a portion of the length of the first active region and the second active region.

11. The non-volatile memory device array of claim 10, wherein the substrate comprises the first dielectric layer and the active layer located above the first dielectric layer.

12. The non-volatile memory device array of claim 11, wherein the lower portion of the metal-insulator-metal capacitor extends vertically in the upper portion of the first dielectric layer and the active layer in the substrate.

13. The non-volatile memory device array of claim 12, wherein the upper portion of the metal-insulator-metal capacitor extends vertically in an interlayer dielectric (ILD) layer above the substrate.

14. The non-volatile memory device array of claim 13, wherein the upper portion of the metal-insulator-metal capacitor further comprises: An extension portion that extends laterally in the inter-metal dielectric (IMD) layer above the inter-layer dielectric layer and at least partially overlaps laterally with the first floating gate array and the second floating gate array.

15. A method for manufacturing a non-volatile memory device, comprising: A floating gate is disposed above a first active region, wherein the first active region is located in the active layer of the substrate; A contact post is provided above the floating gate; as well as A metal-insulator-metal capacitor is disposed laterally adjacent to the floating gate, wherein a portion of the metal-insulator-metal capacitor is located in the active layer, and the first electrode of the metal-insulator-metal capacitor is connected to the floating gate via the contact post. The provision of a floating gate above the first active region further includes the provision of a substrate comprising a first dielectric layer and an active layer located above the first dielectric layer, wherein the lower portion of the metal-insulator-metal capacitor extends vertically to the first dielectric layer, and The metal-insulator-metal capacitor extends across at least a portion of the length of the first active region.

16. The method of claim 15, wherein providing a floating gate over the first active region further comprises: A first isolation region and a second isolation region adjacent to the first isolation region are formed in the substrate; Forming the first active region adjacent to the second isolation region; The floating gate is formed above the first active region.

17. The method of claim 16, wherein providing contact posts above the floating gate further comprises: An interlayer dielectric layer is disposed on the floating gate and the substrate; as well as Contact pillars are formed in the interlayer dielectric layer above the floating gate.

18. The method of claim 17, wherein providing a metal-insulator-metal capacitor laterally adjacent to the floating gate further comprises: An opening is formed in the interlayer dielectric layer and the first isolation region, wherein the opening is laterally adjacent to the floating gate; A first conductive layer is formed on the interlayer dielectric layer, the contact post above the floating gate, and the sidewalls and bottom surface of the opening; A high dielectric constant layer is formed on top of the first conductive layer; A second conductive layer is formed on the high dielectric constant dielectric layer, thereby filling the openings in the interlayer dielectric layer and the first isolation region; The second conductive layer is patterned to form the second electrode of the metal-insulator-metal capacitor; The high dielectric constant layer is patterned to form the high dielectric constant layer of the metal-insulator-metal capacitor; as well as The first conductive layer is patterned to form the first electrode of the metal-insulator-metal capacitor on the interlayer dielectric layer, the contact post above the floating gate, and the sidewall and bottom surface of the opening.

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